[u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Roger Quadros]

Hi,

This series adds driver model support for rawnand: omap_gpmc
and omap_elm drivers.

This will enable the driver to be used on K2/K3 platforms as well.

cheers,
-roger

Roger Quadros (14):
  mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
  mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
  mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
  mtd: rawnand: omap_gpmc: Optimize NAND reads
  mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
  mtd: rawnand: nand_base: Allow base driver to be used in SPL without
    nand_bbt
  mtd: rawnand: nand_spl_loaders: Fix cast type build warning
  mtd: rawnand: omap_gpmc: Reduce .bss usage
  dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
  mtd: rawnand: omap_gpmc: support u-boot driver model
  mtd: rawnand: omap_gpmc: Add SPL NAND support
  mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
  dt-bindings: mtd: Add ti,elm DT binding documentation
  mtd: rawnand: omap_elm: u-boot driver model support

 doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
 .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
 drivers/mtd/nand/raw/Kconfig                  |  11 +-
 drivers/mtd/nand/raw/Makefile                 |   2 +-
 drivers/mtd/nand/raw/nand_base.c              |  18 +-
 drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
 drivers/mtd/nand/raw/omap_elm.c               |  33 +-
 .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
 drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
 9 files changed, 637 insertions(+), 136 deletions(-)
 create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
 create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
 rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)

-- 
2.17.1

[u-boot][PATCH 01/14] mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h

[Roger Quadros]

We want to get rid of <asm/arch/mem.h> so don't
enforce it for new platforms.

This also means GPMC_MAX CS doesn't have to be defined
by platform code.

Define it locally here for now.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/omap_gpmc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 8b9ff4de18..7e9ccf7878 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -8,7 +8,11 @@
 #include <log.h>
 #include <asm/io.h>
 #include <linux/errno.h>
+
+#ifdef CONFIG_ARCH_OMAP2PLUS
 #include <asm/arch/mem.h>
+#endif
+
 #include <linux/mtd/omap_gpmc.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/rawnand.h>
@@ -17,6 +21,10 @@
 #include <nand.h>
 #include <linux/mtd/omap_elm.h>
 
+#ifndef GPMC_MAX_CS
+#define GPMC_MAX_CS	4
+#endif
+
 #define BADBLOCK_MARKER_LENGTH	2
 #define SECTOR_BYTES		512
 #define ECCCLEAR		(0x1 << 8)
-- 
2.17.1

[u-boot][PATCH 02/14] mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms

[Roger Quadros]

The GPMC module is present on some K2 and K3 SoCs.
Enable building GPMC NAND driver for K2/K3 platforms.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index ce67d1abde..bc5cabdfc2 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -189,7 +189,7 @@ config NAND_LPC32XX_SLC
 
 config NAND_OMAP_GPMC
 	bool "Support OMAP GPMC NAND controller"
-	depends on ARCH_OMAP2PLUS
+	depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
 	help
 	  Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
 	  GPMC controller is used for parallel NAND flash devices, and can
-- 
2.17.1

[u-boot][PATCH 03/14] mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms

[Roger Quadros]

Pointer size cannot be assumed to be 32-bit, so use
use uintptr_t instead of uint32_t.

Fixes the below build warning on 64-bit builds.

drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
  head = ((uint32_t) buf) % 4;

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/omap_gpmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 7e9ccf7878..d62c3e6fce 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -438,14 +438,14 @@ static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
 static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int ret;
-	uint32_t head, tail;
+	uintptr_t head, tail;
 	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/*
 	 * If the destination buffer is unaligned, start with reading
 	 * the overlap byte-wise.
 	 */
-	head = ((uint32_t) buf) % 4;
+	head = ((uintptr_t)buf) % 4;
 	if (head) {
 		omap_nand_read(mtd, buf, head);
 		buf += head;
-- 
2.17.1

[u-boot][PATCH 04/14] mtd: rawnand: omap_gpmc: Optimize NAND reads

[Roger Quadros]

Rename omap_nand_read() to omap_nand_read_buf() to reflect
actual behaviour.

Use FIFO read address instead of raw read address for reads.

The GPMC automatically converts 32-bit/16-bit reads to NAND
device specific reads (8/16 bit). Use the largest possible
read granularity size for more efficient reads.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++--------------
 1 file changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index d62c3e6fce..b36fe762b3 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -55,6 +55,7 @@ struct omap_nand_info {
 	enum omap_ecc ecc_scheme;
 	uint8_t cs;
 	uint8_t ws;		/* wait status pin (0,1) */
+	void __iomem *fifo;
 };
 
 /* We are wasting a bit of memory but al least we are safe */
@@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 	return 0;
 }
 
+static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
+	u32 alignment = ((uintptr_t)buf | len) & 3;
+
+	if (alignment & 1)
+		readsb(info->fifo, buf, len);
+	else if (alignment & 3)
+		readsw(info->fifo, buf, len >> 1);
+	else
+		readsl(info->fifo, buf, len >> 2);
+}
+
 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
 
 #define PREFETCH_CONFIG1_CS_SHIFT	24
@@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
 		cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
 
 		for (i = 0; i < cnt / 4; i++) {
-			*buf++ = readl(CONFIG_SYS_NAND_BASE);
+			*buf++ = readl(info->fifo);
 			len -= 4;
 		}
 	} while (len);
@@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
 	return 0;
 }
 
-static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-
-	if (chip->options & NAND_BUSWIDTH_16)
-		nand_read_buf16(mtd, buf, len);
-	else
-		nand_read_buf(mtd, buf, len);
-}
-
 static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int ret;
@@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 	 */
 	head = ((uintptr_t)buf) % 4;
 	if (head) {
-		omap_nand_read(mtd, buf, head);
+		omap_nand_read_buf(mtd, buf, head);
 		buf += head;
 		len -= head;
 	}
@@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 	ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
 	if (ret < 0) {
 		/* fallback in case the prefetch engine is busy */
-		omap_nand_read(mtd, buf, len);
+		omap_nand_read_buf(mtd, buf, len);
 	} else if (tail) {
 		buf += len - tail;
-		omap_nand_read(mtd, buf, tail);
+		omap_nand_read_buf(mtd, buf, tail);
 	}
 }
 #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
@@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand)
 	int32_t gpmc_config = 0;
 	int cs = cs_next++;
 	int err = 0;
+	struct omap_nand_info *info;
+
 	/*
 	 * xloader/Uboot's gpmc configuration would have configured GPMC for
 	 * nand type of memory. The following logic scans and latches on to the
@@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand)
 
 	nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 	nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
-	omap_nand_info[cs].control = NULL;
-	omap_nand_info[cs].cs = cs;
-	omap_nand_info[cs].ws = wscfg[cs];
+
+	info = &omap_nand_info[cs];
+	info->control = NULL;
+	info->cs = cs;
+	info->ws = wscfg[cs];
+	info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE;
 	nand_set_controller_data(nand, &omap_nand_info[cs]);
 	nand->cmd_ctrl	= omap_nand_hwcontrol;
 	nand->options	|= NAND_NO_PADDING | NAND_CACHEPRG;
@@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand)
 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
 	nand->read_buf = omap_nand_read_prefetch;
 #else
-	if (nand->options & NAND_BUSWIDTH_16)
-		nand->read_buf = nand_read_buf16;
-	else
-		nand->read_buf = nand_read_buf;
+	nand->read_buf = omap_nand_read_buf;
 #endif
 
 	nand->dev_ready = omap_dev_ready;
-- 
2.17.1

[u-boot][PATCH 05/14] mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction

[Roger Quadros]

The BCH detection hardware can generate ECC bytes for multiple
sectors in one go. Use that feature.

correct() only corrects one sector at a time so we need to call it
repeatedly for each sector.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/omap_gpmc.c | 325 +++++++++++++++++++++----------
 1 file changed, 223 insertions(+), 102 deletions(-)

diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index b36fe762b3..b5ad66ad49 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -27,6 +27,9 @@
 
 #define BADBLOCK_MARKER_LENGTH	2
 #define SECTOR_BYTES		512
+#define ECCSIZE0_SHIFT		12
+#define ECCSIZE1_SHIFT		22
+#define ECC1RESULTSIZE		0x1
 #define ECCCLEAR		(0x1 << 8)
 #define ECCRESULTREG1		(0x1 << 0)
 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
@@ -187,72 +190,35 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 __maybe_unused
 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 {
-	struct nand_chip	*nand	= mtd_to_nand(mtd);
-	struct omap_nand_info	*info	= nand_get_controller_data(nand);
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(nand);
 	unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
-	unsigned int ecc_algo = 0;
-	unsigned int bch_type = 0;
-	unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
-	u32 ecc_size_config_val = 0;
-	u32 ecc_config_val = 0;
-	int cs = info->cs;
+	u32 val;
 
-	/* configure GPMC for specific ecc-scheme */
-	switch (info->ecc_scheme) {
-	case OMAP_ECC_HAM1_CODE_SW:
-		return;
-	case OMAP_ECC_HAM1_CODE_HW:
-		ecc_algo = 0x0;
-		bch_type = 0x0;
-		bch_wrapmode = 0x00;
-		eccsize0 = 0xFF;
-		eccsize1 = 0xFF;
+	/* Clear ecc and enable bits */
+	writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+	/* program ecc and result sizes */
+	val = ((((nand->ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
+			ECC1RESULTSIZE);
+	writel(val, &gpmc_cfg->ecc_size_config);
+
+	switch (mode) {
+	case NAND_ECC_READ:
+	case NAND_ECC_WRITE:
+		writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 		break;
-	case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
-	case OMAP_ECC_BCH8_CODE_HW:
-		ecc_algo = 0x1;
-		bch_type = 0x1;
-		if (mode == NAND_ECC_WRITE) {
-			bch_wrapmode = 0x01;
-			eccsize0 = 0;  /* extra bits in nibbles per sector */
-			eccsize1 = 28; /* OOB bits in nibbles per sector */
-		} else {
-			bch_wrapmode = 0x01;
-			eccsize0 = 26; /* ECC bits in nibbles per sector */
-			eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
-		}
-		break;
-	case OMAP_ECC_BCH16_CODE_HW:
-		ecc_algo = 0x1;
-		bch_type = 0x2;
-		if (mode == NAND_ECC_WRITE) {
-			bch_wrapmode = 0x01;
-			eccsize0 = 0;  /* extra bits in nibbles per sector */
-			eccsize1 = 52; /* OOB bits in nibbles per sector */
-		} else {
-			bch_wrapmode = 0x01;
-			eccsize0 = 52; /* ECC bits in nibbles per sector */
-			eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
-		}
+	case NAND_ECC_READSYN:
+		writel(ECCCLEAR, &gpmc_cfg->ecc_control);
 		break;
 	default:
-		return;
+		printf("%s: error: unrecognized Mode[%d]!\n", __func__, mode);
+		break;
 	}
-	/* Clear ecc and enable bits */
-	writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-	/* Configure ecc size for BCH */
-	ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
-	writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
-
-	/* Configure device details for BCH engine */
-	ecc_config_val = ((ecc_algo << 16)	| /* HAM1 | BCHx */
-			(bch_type << 12)	| /* BCH4/BCH8/BCH16 */
-			(bch_wrapmode << 8)	| /* wrap mode */
-			(dev_width << 7)	| /* bus width */
-			(0x0 << 4)		| /* number of sectors */
-			(cs <<  1)		| /* ECC CS */
-			(0x1));			  /* enable ECC */
-	writel(ecc_config_val, &gpmc_cfg->ecc_config);
+
+	/* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
+	val = (dev_width << 7) | (info->cs << 1) | (0x1);
+	writel(val, &gpmc_cfg->ecc_config);
 }
 
 /*
@@ -271,6 +237,124 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
  */
 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 				uint8_t *ecc_code)
+{
+	u32 val;
+
+	val = readl(&gpmc_cfg->ecc1_result);
+	ecc_code[0] = val & 0xFF;
+	ecc_code[1] = (val >> 16) & 0xFF;
+	ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
+
+	return 0;
+}
+
+/* GPMC ecc engine settings for read */
+#define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
+#define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
+#define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
+#define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
+#define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
+
+/* GPMC ecc engine settings for write */
+#define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
+#define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
+#define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
+
+/**
+ * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ *
+ * When using BCH with SW correction (i.e. no ELM), sector size is set
+ * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
+ * for both reading and writing with:
+ * eccsize0 = 0  (no additional protected byte in spare area)
+ * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
+ */
+static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd,
+						 int mode)
+{
+	unsigned int bch_type;
+	unsigned int dev_width, nsectors;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
+	u32 val, wr_mode;
+	unsigned int ecc_size1, ecc_size0;
+
+	/* GPMC configurations for calculating ECC */
+	switch (info->ecc_scheme) {
+	case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
+		bch_type = 1;
+		nsectors = 1;
+		wr_mode   = BCH_WRAPMODE_6;
+		ecc_size0 = BCH_ECC_SIZE0;
+		ecc_size1 = BCH_ECC_SIZE1;
+		break;
+	case OMAP_ECC_BCH8_CODE_HW:
+		bch_type = 1;
+		nsectors = chip->ecc.steps;
+		if (mode == NAND_ECC_READ) {
+			wr_mode   = BCH_WRAPMODE_1;
+			ecc_size0 = BCH8R_ECC_SIZE0;
+			ecc_size1 = BCH8R_ECC_SIZE1;
+		} else {
+			wr_mode   = BCH_WRAPMODE_6;
+			ecc_size0 = BCH_ECC_SIZE0;
+			ecc_size1 = BCH_ECC_SIZE1;
+		}
+		break;
+	case OMAP_ECC_BCH16_CODE_HW:
+		bch_type = 0x2;
+		nsectors = chip->ecc.steps;
+		if (mode == NAND_ECC_READ) {
+			wr_mode   = 0x01;
+			ecc_size0 = 52; /* ECC bits in nibbles per sector */
+			ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
+		} else {
+			wr_mode   = 0x01;
+			ecc_size0 = 0;  /* extra bits in nibbles per sector */
+			ecc_size1 = 52; /* OOB bits in nibbles per sector */
+		}
+		break;
+	default:
+		return;
+	}
+
+	writel(ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+	/* Configure ecc size for BCH */
+	val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
+	writel(val, &gpmc_cfg->ecc_size_config);
+
+	dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
+
+	/* BCH configuration */
+	val = ((1			<< 16) | /* enable BCH */
+	       (bch_type		<< 12) | /* BCH4/BCH8/BCH16 */
+	       (wr_mode			<<  8) | /* wrap mode */
+	       (dev_width		<<  7) | /* bus width */
+	       (((nsectors - 1) & 0x7)	<<  4) | /* number of sectors */
+	       (info->cs		<<  1) | /* ECC CS */
+	       (0x1));				 /* enable ECC */
+
+	writel(val, &gpmc_cfg->ecc_config);
+
+	/* Clear ecc and enable bits */
+	writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+}
+
+/**
+ * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
+ * @mtd:        MTD device structure
+ * @dat:        The pointer to data on which ecc is computed
+ * @ecc_code:   The ecc_code buffer
+ * @sector:     The sector number (for a multi sector page)
+ *
+ * Support calculating of BCH4/8/16 ECC vectors for one sector
+ * within a page. Sector number is in @sector.
+ */
+static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
+				   u8 *ecc_code, int sector)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct omap_nand_info *info = nand_get_controller_data(chip);
@@ -279,17 +363,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 	int8_t i = 0, j;
 
 	switch (info->ecc_scheme) {
-	case OMAP_ECC_HAM1_CODE_HW:
-		val = readl(&gpmc_cfg->ecc1_result);
-		ecc_code[0] = val & 0xFF;
-		ecc_code[1] = (val >> 16) & 0xFF;
-		ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
-		break;
 #ifdef CONFIG_BCH
 	case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 #endif
 	case OMAP_ECC_BCH8_CODE_HW:
-		ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
+		ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3];
 		val = readl(ptr);
 		ecc_code[i++] = (val >>  0) & 0xFF;
 		ptr--;
@@ -301,23 +379,24 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 			ecc_code[i++] = (val >>  0) & 0xFF;
 			ptr--;
 		}
+
 		break;
 	case OMAP_ECC_BCH16_CODE_HW:
-		val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
+		val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]);
 		ecc_code[i++] = (val >>  8) & 0xFF;
 		ecc_code[i++] = (val >>  0) & 0xFF;
-		val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
+		val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]);
 		ecc_code[i++] = (val >> 24) & 0xFF;
 		ecc_code[i++] = (val >> 16) & 0xFF;
 		ecc_code[i++] = (val >>  8) & 0xFF;
 		ecc_code[i++] = (val >>  0) & 0xFF;
-		val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
+		val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]);
 		ecc_code[i++] = (val >> 24) & 0xFF;
 		ecc_code[i++] = (val >> 16) & 0xFF;
 		ecc_code[i++] = (val >>  8) & 0xFF;
 		ecc_code[i++] = (val >>  0) & 0xFF;
 		for (j = 3; j >= 0; j--) {
-			val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
+			val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j]
 									);
 			ecc_code[i++] = (val >> 24) & 0xFF;
 			ecc_code[i++] = (val >> 16) & 0xFF;
@@ -330,18 +409,18 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 	}
 	/* ECC scheme specific syndrome customizations */
 	switch (info->ecc_scheme) {
-	case OMAP_ECC_HAM1_CODE_HW:
-		break;
 #ifdef CONFIG_BCH
 	case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
-
+		/* Add constant polynomial to remainder, so that
+		 * ECC of blank pages results in 0x0 on reading back
+		 */
 		for (i = 0; i < chip->ecc.bytes; i++)
-			*(ecc_code + i) = *(ecc_code + i) ^
-						bch8_polynomial[i];
+			ecc_code[i] ^= bch8_polynomial[i];
 		break;
 #endif
 	case OMAP_ECC_BCH8_CODE_HW:
-		ecc_code[chip->ecc.bytes - 1] = 0x00;
+		/* Set 14th ECC byte as 0x0 for ROM compatibility */
+		ecc_code[chip->ecc.bytes - 1] = 0x0;
 		break;
 	case OMAP_ECC_BCH16_CODE_HW:
 		break;
@@ -351,6 +430,22 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 	return 0;
 }
 
+/**
+ * omap_calculate_ecc_bch - ECC generator for 1 sector
+ * @mtd:        MTD device structure
+ * @dat:	The pointer to data on which ecc is computed
+ * @ecc_code:	The ecc_code buffer
+ *
+ * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
+ * when SW based correction is required as ECC is required for one sector
+ * at a time.
+ */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd,
+				  const u_char *dat, u_char *ecc_calc)
+{
+	return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0);
+}
+
 static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
@@ -475,6 +570,35 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
 
 #ifdef CONFIG_NAND_OMAP_ELM
+
+/**
+ * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
+ * @mtd:	MTD device structure
+ * @dat:	The pointer to data on which ecc is computed
+ * @ecc_code:	The ecc_code buffer
+ *
+ * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
+ */
+static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
+					const u_char *dat, u_char *ecc_calc)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	int eccbytes = chip->ecc.bytes;
+	unsigned long nsectors;
+	int i, ret;
+
+	nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
+	for (i = 0; i < nsectors; i++) {
+		ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);
+		if (ret)
+			return ret;
+
+		ecc_calc += eccbytes;
+	}
+
+	return 0;
+}
+
 /*
  * omap_reverse_list - re-orders list elements in reverse order [internal]
  * @list:	pointer to start of list
@@ -627,52 +751,49 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
+	int ecctotal = chip->ecc.total;
 	int eccsteps = chip->ecc.steps;
 	uint8_t *p = buf;
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
 	uint8_t *ecc_code = chip->buffers->ecccode;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
 	uint8_t *oob = chip->oob_poi;
-	uint32_t data_pos;
 	uint32_t oob_pos;
 
-	data_pos = 0;
 	/* oob area start */
 	oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
 	oob += chip->ecc.layout->eccpos[0];
 
-	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
-				oob += eccbytes) {
-		chip->ecc.hwctl(mtd, NAND_ECC_READ);
-		/* read data */
-		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
-		chip->read_buf(mtd, p, eccsize);
-
-		/* read respective ecc from oob area */
-		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
-		chip->read_buf(mtd, oob, eccbytes);
-		/* read syndrome */
-		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
-
-		data_pos += eccsize;
-		oob_pos += eccbytes;
-	}
+	/* Enable ECC engine */
+	chip->ecc.hwctl(mtd, NAND_ECC_READ);
+
+	/* read entire page */
+	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);
+	chip->read_buf(mtd, buf, mtd->writesize);
+
+	/* read all ecc bytes from oob area */
+	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
+	chip->read_buf(mtd, oob, ecctotal);
+
+	/* Calculate ecc bytes */
+	omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc);
 
 	for (i = 0; i < chip->ecc.total; i++)
 		ecc_code[i] = chip->oob_poi[eccpos[i]];
 
+	/* error detect & correct */
 	eccsteps = chip->ecc.steps;
 	p = buf;
 
 	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		int stat;
-
 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 		if (stat < 0)
 			mtd->ecc_stats.failed++;
 		else
 			mtd->ecc_stats.corrected += stat;
 	}
+
 	return 0;
 }
 #endif /* CONFIG_NAND_OMAP_ELM */
@@ -820,9 +941,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
 		nand->ecc.strength	= 8;
 		nand->ecc.size		= SECTOR_BYTES;
 		nand->ecc.bytes		= 13;
-		nand->ecc.hwctl		= omap_enable_hwecc;
+		nand->ecc.hwctl		= omap_enable_hwecc_bch;
 		nand->ecc.correct	= omap_correct_data_bch_sw;
-		nand->ecc.calculate	= omap_calculate_ecc;
+		nand->ecc.calculate	= omap_calculate_ecc_bch;
 		/* define ecc-layout */
 		ecclayout->eccbytes	= nand->ecc.bytes * eccsteps;
 		ecclayout->eccpos[0]	= BADBLOCK_MARKER_LENGTH;
@@ -861,9 +982,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
 		nand->ecc.strength	= 8;
 		nand->ecc.size		= SECTOR_BYTES;
 		nand->ecc.bytes		= 14;
-		nand->ecc.hwctl		= omap_enable_hwecc;
+		nand->ecc.hwctl		= omap_enable_hwecc_bch;
 		nand->ecc.correct	= omap_correct_data_bch;
-		nand->ecc.calculate	= omap_calculate_ecc;
+		nand->ecc.calculate	= omap_calculate_ecc_bch;
 		nand->ecc.read_page	= omap_read_page_bch;
 		/* define ecc-layout */
 		ecclayout->eccbytes	= nand->ecc.bytes * eccsteps;
@@ -894,9 +1015,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
 		nand->ecc.size		= SECTOR_BYTES;
 		nand->ecc.bytes		= 26;
 		nand->ecc.strength	= 16;
-		nand->ecc.hwctl		= omap_enable_hwecc;
+		nand->ecc.hwctl		= omap_enable_hwecc_bch;
 		nand->ecc.correct	= omap_correct_data_bch;
-		nand->ecc.calculate	= omap_calculate_ecc;
+		nand->ecc.calculate	= omap_calculate_ecc_bch;
 		nand->ecc.read_page	= omap_read_page_bch;
 		/* define ecc-layout */
 		ecclayout->eccbytes	= nand->ecc.bytes * eccsteps;
-- 
2.17.1

[u-boot][PATCH 06/14] mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt

[Roger Quadros]

nand_bbt.c is not being built with the nand_base driver during SPL
build. This results in build failures if we try to access any nand_bbt
related functions.

Don't use any nand_bbt functions for SPL build.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/nand_base.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 4b09a11288..826ae633ce 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -447,7 +447,10 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
-	int res, ret = 0;
+	int ret = 0;
+#ifndef CONFIG_SPL_BUILD
+	int res;
+#endif
 
 	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
 		struct erase_info einfo;
@@ -465,12 +468,14 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 		nand_release_device(mtd);
 	}
 
+#ifndef CONFIG_SPL_BUILD
 	/* Mark block bad in BBT */
 	if (chip->bbt) {
 		res = nand_markbad_bbt(mtd, ofs);
 		if (!ret)
 			ret = res;
 	}
+#endif
 
 	if (!ret)
 		mtd->ecc_stats.badblocks++;
@@ -517,7 +522,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
 	if (!chip->bbt)
 		return 0;
 	/* Return info from the table */
+#ifndef CONFIG_SPL_BUILD
 	return nand_isreserved_bbt(mtd, ofs);
+#else
+	return 0;
+#endif
 }
 
 /**
@@ -543,7 +552,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
 		return chip->block_bad(mtd, ofs);
 
 	/* Return info from the table */
+#ifndef CONFIG_SPL_BUILD
 	return nand_isbad_bbt(mtd, ofs, allowbbt);
+#else
+	return 0;
+#endif
 }
 
 /**
@@ -3752,8 +3765,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
 		chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
 	if (!chip->read_buf || chip->read_buf == nand_read_buf)
 		chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
+
+#ifndef CONFIG_SPL_BUILD
 	if (!chip->scan_bbt)
 		chip->scan_bbt = nand_default_bbt;
+#endif
 
 	if (!chip->controller) {
 		chip->controller = &chip->hwcontrol;
-- 
2.17.1

[u-boot][PATCH 07/14] mtd: rawnand: nand_spl_loaders: Fix cast type build warning

[Roger Quadros]

Fixes the below build warning on 64-bit platforms.

drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
      dst = (void *)((int)dst - page_offset);

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c
index 4befc75c04..156b44d835 100644
--- a/drivers/mtd/nand/raw/nand_spl_loaders.c
+++ b/drivers/mtd/nand/raw/nand_spl_loaders.c
@@ -23,7 +23,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 				if (unlikely(page_offset)) {
 					memmove(dst, dst + page_offset,
 						CONFIG_SYS_NAND_PAGE_SIZE);
-					dst = (void *)((int)dst - page_offset);
+					dst = (void *)(dst - page_offset);
 					page_offset = 0;
 				}
 				dst += CONFIG_SYS_NAND_PAGE_SIZE;
-- 
2.17.1

[u-boot][PATCH 08/14] mtd: rawnand: omap_gpmc: Reduce .bss usage

[Roger Quadros]

Allocate omap_ecclayout on the heap as we have
limited .bss space on AM64 R5 SPL configuration.

Reduces .bss usage by 2984 bytes.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/omap_gpmc.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index b5ad66ad49..e772a914c8 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -40,7 +40,6 @@ static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
 				0x97, 0x79, 0xe5, 0x24, 0xb5};
 #endif
 static uint8_t cs_next;
-static __maybe_unused struct nand_ecclayout omap_ecclayout;
 
 #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
@@ -874,7 +873,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 static int omap_select_ecc_scheme(struct nand_chip *nand,
 	enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 	struct omap_nand_info	*info		= nand_get_controller_data(nand);
-	struct nand_ecclayout	*ecclayout	= &omap_ecclayout;
+	struct nand_ecclayout	*ecclayout	= nand->ecc.layout;
 	int eccsteps = pagesize / SECTOR_BYTES;
 	int i;
 
@@ -1167,7 +1166,9 @@ int board_nand_init(struct nand_chip *nand)
 	nand->cmd_ctrl	= omap_nand_hwcontrol;
 	nand->options	|= NAND_NO_PADDING | NAND_CACHEPRG;
 	nand->chip_delay = 100;
-	nand->ecc.layout = &omap_ecclayout;
+	nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL);
+	if (!nand->ecc.layout)
+		return -ENOMEM;
 
 	/* configure driver and controller based on NAND device bus-width */
 	gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
-- 
2.17.1

[u-boot][PATCH 09/14] dt-bindings: mtd: Add ti, gpmc-nand DT binding documentation

[Roger Quadros]

Add DT binding documentation for the TI GPMC NAND controller.
This is picked up from the Linux Kernel.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 .../mtd/ti,gpmc-nand.yaml                     | 129 ++++++++++++++++++
 1 file changed, 129 insertions(+)
 create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml

diff --git a/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml b/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
new file mode 100644
index 0000000000..4ac198814b
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments GPMC NAND Flash controller.
+
+maintainers:
+  - Tony Lindgren <tony@atomide.com>
+  - Roger Quadros <rogerq@kernel.org>
+
+description:
+  GPMC NAND controller/Flash is represented as a child of the
+  GPMC controller node.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - ti,am64-nand
+          - ti,omap2-nand
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Interrupt for fifoevent
+      - description: Interrupt for termcount
+
+  "#address-cells": true
+
+  "#size-cells": true
+
+  ti,nand-ecc-opt:
+    description: Desired ECC algorithm
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [sw, ham1, bch4, bch8, bch16]
+
+  ti,nand-xfer-type:
+    description: Data transfer method between controller and chip.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
+    default: prefetch-polled
+
+  ti,elm-id:
+    description:
+      phandle to the ELM (Error Location Module).
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  nand-bus-width:
+    description:
+      Bus width to the NAND chip
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [8, 16]
+    default: 8
+
+  rb-gpios:
+    description:
+      GPIO connection to R/B signal from NAND chip
+    maxItems: 1
+
+patternProperties:
+  "@[0-9a-f]+$":
+    $ref: "/schemas/mtd/partitions/partition.yaml"
+
+allOf:
+  - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"
+
+required:
+  - compatible
+  - reg
+  - ti,nand-ecc-opt
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/gpio/gpio.h>
+
+    gpmc: memory-controller@50000000 {
+      compatible = "ti,am3352-gpmc";
+      dmas = <&edma 52 0>;
+      dma-names = "rxtx";
+      clocks = <&l3s_gclk>;
+      clock-names = "fck";
+      reg = <0x50000000 0x2000>;
+      interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+      gpmc,num-cs = <7>;
+      gpmc,num-waitpins = <2>;
+      #address-cells = <2>;
+      #size-cells = <1>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      gpio-controller;
+      #gpio-cells = <2>;
+
+      ranges = <0 0 0x08000000 0x01000000>;   /* CS0 space. Min partition = 16MB */
+      nand@0,0 {
+        compatible = "ti,omap2-nand";
+        reg = <0 0 4>;          /* device IO registers */
+        interrupt-parent = <&gpmc>;
+        interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                     <1 IRQ_TYPE_NONE>; /* termcount */
+        ti,nand-xfer-type = "prefetch-dma";
+        ti,nand-ecc-opt = "bch16";
+        ti,elm-id = <&elm>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        /* NAND generic properties */
+        nand-bus-width = <8>;
+        rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
+
+        /* GPMC properties*/
+        gpmc,device-width = <1>;
+
+        partition@0 {
+          label = "NAND.SPL";
+          reg = <0x00000000 0x00040000>;
+        };
+        partition@1 {
+          label = "NAND.SPL.backup1";
+          reg = <0x00040000 0x00040000>;
+        };
+      };
+    };
-- 
2.17.1

[u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model

[Roger Quadros]

Adds driver model support.

We need to be able to self initialize the NAND controller/chip
at probe and so enable CONFIG_SYS_NAND_SELF_INIT.

Doing so requires nand_register() API which is provided by nand.c
and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT.
But nand.c also provides nand_init() so we need to get rid of nand_init()
in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/Kconfig     |  1 +
 drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++-
 2 files changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index bc5cabdfc2..1d23144ce4 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC
 config NAND_OMAP_GPMC
 	bool "Support OMAP GPMC NAND controller"
 	depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
+	select SYS_NAND_SELF_INIT if ARCH_K3
 	help
 	  Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
 	  GPMC controller is used for parallel NAND flash devices, and can
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index e772a914c8..7192ca9e5a 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <log.h>
 #include <asm/io.h>
+#include <dm/uclass.h>
 #include <linux/errno.h>
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
  *   nand_scan about special functionality. See the defines for further
  *   explanation
  */
-int board_nand_init(struct nand_chip *nand)
+int gpmc_nand_init(struct nand_chip *nand)
 {
 	int32_t gpmc_config = 0;
 	int cs = cs_next++;
@@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
 
 	return 0;
 }
+
+static struct nand_chip *nand_chip;	/* First NAND chip for SPL use only */
+
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
+
+static int gpmc_nand_probe(struct udevice *dev)
+{
+	struct nand_chip *nand = dev_get_priv(dev);
+	struct mtd_info *mtd = nand_to_mtd(nand);
+	int ret;
+
+	gpmc_nand_init(nand);
+
+	ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
+	if (ret)
+		return ret;
+
+	ret = nand_register(0, mtd);
+	if (ret)
+		return ret;
+
+	if (!nand_chip)
+		nand_chip = nand;
+
+	return 0;
+}
+
+static const struct udevice_id gpmc_nand_ids[] = {
+	{ .compatible = "ti,am64-nand" },
+	{ .compatible = "ti,omap2-nand" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpmc_nand) = {
+	.name           = "gpmc-nand",
+	.id             = UCLASS_MTD,
+	.of_match       = gpmc_nand_ids,
+	.probe          = gpmc_nand_probe,
+	.priv_auto	= sizeof(struct nand_chip),
+};
+
+void board_nand_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_DRIVER_GET(gpmc_nand), &dev);
+	if (ret && ret != -ENODEV)
+		pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);
+}
+#endif /* CONFIG_SYS_NAND_SELF_INIT */
-- 
2.17.1

[u-boot][PATCH 11/14] mtd: rawnand: omap_gpmc: Add SPL NAND support

[Roger Quadros]

Enables SPL NAND support for ARCH_K3 by enabling
SPL_NAND_INIT and SPL_SYS_NAND_SELF_INIT.

Legacy OMAP2plus platforms still rely on SPL_NAND_AM33XX_BCH
instead.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/Kconfig     |  5 ++++
 drivers/mtd/nand/raw/Makefile    |  2 +-
 drivers/mtd/nand/raw/omap_gpmc.c | 40 ++++++++++++++++++++++++++++++++
 3 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 1d23144ce4..b803759166 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -26,6 +26,9 @@ config TPL_SYS_NAND_SELF_INIT
 config TPL_NAND_INIT
 	bool
 
+config SPL_NAND_INIT
+	bool
+
 config SYS_NAND_DRIVER_ECC_LAYOUT
 	bool "Omit standard ECC layouts to save space"
 	help
@@ -191,6 +194,8 @@ config NAND_OMAP_GPMC
 	bool "Support OMAP GPMC NAND controller"
 	depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
 	select SYS_NAND_SELF_INIT if ARCH_K3
+	select SPL_NAND_INIT if ARCH_K3
+	select SPL_SYS_NAND_SELF_INIT if ARCH_K3
 	help
 	  Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
 	  GPMC controller is used for parallel NAND flash devices, and can
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index a398aa9d88..6fe33d2485 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \
 				nand_macronix.o nand_micron.o \
 				nand_samsung.o nand_toshiba.o
 obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o
-obj-$(CONFIG_TPL_NAND_INIT) += nand.o
+obj-$(CONFIG_$(SPL_TPL_)NAND_INIT) += nand.o
 ifeq ($(CONFIG_SPL_ENV_SUPPORT),y)
 obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o
 endif
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 7192ca9e5a..79b14ce297 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -1254,3 +1254,43 @@ void board_nand_init(void)
 		pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);
 }
 #endif /* CONFIG_SYS_NAND_SELF_INIT */
+
+#if defined(CONFIG_SPL_NAND_INIT)
+
+/* nand_init() is provided by nand.c */
+
+/* Unselect after operation */
+void nand_deselect(void)
+{
+	struct mtd_info *mtd = nand_to_mtd(nand_chip);
+
+	if (nand_chip->select_chip)
+		nand_chip->select_chip(mtd, -1);
+}
+
+static int nand_is_bad_block(int block)
+{
+	struct mtd_info *mtd = nand_to_mtd(nand_chip);
+
+	loff_t ofs = block * CONFIG_SYS_NAND_BLOCK_SIZE;
+
+	return nand_chip->block_bad(mtd, ofs);
+}
+
+static int nand_read_page(int block, int page, uchar *dst)
+{
+	int page_addr = block * CONFIG_SYS_NAND_PAGE_COUNT + page;
+	loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE;
+	int ret;
+	size_t len = CONFIG_SYS_NAND_PAGE_SIZE;
+	struct mtd_info *mtd = nand_to_mtd(nand_chip);
+
+	ret = nand_read(mtd, ofs, &len, dst);
+	if (ret)
+		printf("nand_read failed %d\n", ret);
+
+	return ret;
+}
+
+#include "nand_spl_loaders.c"
+#endif /* CONFIG_SPL_NAND_INIT */
-- 
2.17.1

[u-boot][PATCH 12/14] mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC

[Roger Quadros]

The symbol is required for NAND support in SPL when using
OMAP_GPMC driver.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index b803759166..95fe27c283 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -566,7 +566,8 @@ config SYS_NAND_ONFI_DETECTION
 config SYS_NAND_PAGE_COUNT
 	hex "NAND chip page count"
 	depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
-		SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
+		SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \
+		NAND_OMAP_GPMC)
 	help
 	  Number of pages in the NAND chip.
 
-- 
2.17.1

[u-boot][PATCH 13/14] dt-bindings: mtd: Add ti, elm DT binding documentation

[Roger Quadros]

Adds DT binding documentation for the TI Error Location Module.
This is picked up from the Linux Kernel.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 doc/device-tree-bindings/mtd/ti,elm.yaml | 72 ++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml

diff --git a/doc/device-tree-bindings/mtd/ti,elm.yaml b/doc/device-tree-bindings/mtd/ti,elm.yaml
new file mode 100644
index 0000000000..87128c0045
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/ti,elm.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ti,elm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments Error Location Module (ELM).
+
+maintainers:
+  - Roger Quadros <rogerq@kernel.org>
+
+description:
+  ELM module is used together with GPMC and NAND Flash to detect
+  errors and the location of the error based on BCH algorithms
+  so they can be corrected if possible.
+
+properties:
+  compatible:
+    enum:
+      - ti,am3352-elm
+      - ti,am64-elm
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: Functional clock.
+
+  clock-names:
+    items:
+      - const: fck
+
+  power-domains:
+    maxItems: 1
+
+  ti,hwmods:
+    description:
+      Name of the HWMOD associated with ELM. This is for legacy
+      platforms only.
+    $ref: /schemas/types.yaml#/definitions/string
+    deprecated: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,am64-elm
+    then:
+      required:
+        - clocks
+        - clock-names
+        - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    elm: ecc@0 {
+        compatible = "ti,am3352-elm";
+        reg = <0x0 0x2000>;
+        interrupts = <4>;
+    };
-- 
2.17.1

[u-boot][PATCH 14/14] mtd: rawnand: omap_elm: u-boot driver model support

[Roger Quadros]

Support u-boot driver model. We still retain
support legacy way of doing things if ELM_BASE
is defined in <asm/arch/hardware.h>

We could completely get rid of that if all
platforms defining ELM_BASE get rid of that definition
and enable CONFIG_SYS_NAND_SELF_INIT and are verified
to work.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/omap_elm.c               | 33 ++++++++++++++++++-
 .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |  6 ++++
 drivers/mtd/nand/raw/omap_gpmc.c              | 12 ++++++-
 3 files changed, 49 insertions(+), 2 deletions(-)
 rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)

diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c
index 35c6dd1f1b..7f4721f617 100644
--- a/drivers/mtd/nand/raw/omap_elm.c
+++ b/drivers/mtd/nand/raw/omap_elm.c
@@ -15,9 +15,14 @@
 #include <common.h>
 #include <asm/io.h>
 #include <linux/errno.h>
-#include <linux/mtd/omap_elm.h>
 #include <asm/arch/hardware.h>
 
+#include <dm.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+#include "omap_elm.h"
+
 #define DRIVER_NAME		"omap-elm"
 #define ELM_DEFAULT_POLY (0)
 
@@ -180,6 +185,7 @@ void elm_reset(void)
 		;
 }
 
+#ifdef ELM_BASE
 /**
  * elm_init - Initialize ELM module
  *
@@ -191,3 +197,28 @@ void elm_init(void)
 	elm_cfg = (struct elm *)ELM_BASE;
 	elm_reset();
 }
+#endif
+
+static int elm_probe(struct udevice *dev)
+{
+	struct resource res;
+
+	dev_read_resource(dev, 0, &res);
+	elm_cfg = devm_ioremap(dev, res.start, resource_size(&res));
+	elm_reset();
+
+	return 0;
+}
+
+static const struct udevice_id elm_ids[] = {
+	{ .compatible = "ti,am3352-elm" },
+	{ .compatible = "ti,am64-elm" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpmc_elm) = {
+	.name           = DRIVER_NAME,
+	.id             = UCLASS_MTD,
+	.of_match       = elm_ids,
+	.probe          = elm_probe,
+};
diff --git a/include/linux/mtd/omap_elm.h b/drivers/mtd/nand/raw/omap_elm.h
similarity index 97%
rename from include/linux/mtd/omap_elm.h
rename to drivers/mtd/nand/raw/omap_elm.h
index f3db00d55d..a7f7bacb15 100644
--- a/include/linux/mtd/omap_elm.h
+++ b/drivers/mtd/nand/raw/omap_elm.h
@@ -74,6 +74,12 @@ int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
 		u32 *error_locations);
 int elm_config(enum bch_level level);
 void elm_reset(void);
+#ifdef ELM_BASE
 void elm_init(void);
+#else
+static inline void elm_init(void)
+{
+}
+#endif
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_ELM_H */
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 79b14ce297..68f8d48e87 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -20,7 +20,8 @@
 #include <linux/bch.h>
 #include <linux/compiler.h>
 #include <nand.h>
-#include <linux/mtd/omap_elm.h>
+
+#include "omap_elm.h"
 
 #ifndef GPMC_MAX_CS
 #define GPMC_MAX_CS	4
@@ -1248,6 +1249,15 @@ void board_nand_init(void)
 	struct udevice *dev;
 	int ret;
 
+#ifdef CONFIG_NAND_OMAP_ELM
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_DRIVER_GET(gpmc_elm), &dev);
+	if (ret && ret != -ENODEV) {
+		pr_err("%s: Failed to get ELM device: %d\n", __func__, ret);
+		return;
+	}
+#endif
+
 	ret = uclass_get_device_by_driver(UCLASS_MTD,
 					  DM_DRIVER_GET(gpmc_nand), &dev);
 	if (ret && ret != -ENODEV)
-- 
2.17.1

Re: [u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model

[Adam Ford]

On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros <rogerq@kernel.org> wrote:
>
> Adds driver model support.
>
> We need to be able to self initialize the NAND controller/chip
> at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
>
> Doing so requires nand_register() API which is provided by nand.c
> and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT.
> But nand.c also provides nand_init() so we need to get rid of nand_init()
> in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/Kconfig     |  1 +
>  drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++-
>  2 files changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
> index bc5cabdfc2..1d23144ce4 100644
> --- a/drivers/mtd/nand/raw/Kconfig
> +++ b/drivers/mtd/nand/raw/Kconfig
> @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC
>  config NAND_OMAP_GPMC
>         bool "Support OMAP GPMC NAND controller"
>         depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
> +       select SYS_NAND_SELF_INIT if ARCH_K3

I have a question about this down below.

>         help
>           Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
>           GPMC controller is used for parallel NAND flash devices, and can
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> index e772a914c8..7192ca9e5a 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -7,6 +7,7 @@
>  #include <common.h>
>  #include <log.h>
>  #include <asm/io.h>
> +#include <dm/uclass.h>
>  #include <linux/errno.h>
>
>  #ifdef CONFIG_ARCH_OMAP2PLUS
> @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
>   *   nand_scan about special functionality. See the defines for further
>   *   explanation
>   */
> -int board_nand_init(struct nand_chip *nand)
> +int gpmc_nand_init(struct nand_chip *nand)
>  {
>         int32_t gpmc_config = 0;
>         int cs = cs_next++;
> @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
>
>         return 0;
>  }
> +
> +static struct nand_chip *nand_chip;    /* First NAND chip for SPL use only */
> +
> +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
> +
> +static int gpmc_nand_probe(struct udevice *dev)
> +{
> +       struct nand_chip *nand = dev_get_priv(dev);
> +       struct mtd_info *mtd = nand_to_mtd(nand);
> +       int ret;
> +
> +       gpmc_nand_init(nand);
> +
> +       ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
> +       if (ret)
> +               return ret;
> +
> +       ret = nand_register(0, mtd);
> +       if (ret)
> +               return ret;
> +
> +       if (!nand_chip)
> +               nand_chip = nand;
> +
> +       return 0;
> +}
> +
> +static const struct udevice_id gpmc_nand_ids[] = {
> +       { .compatible = "ti,am64-nand" },
> +       { .compatible = "ti,omap2-nand" },

The gpmc_nand_ids reference to omap2, but it's encapsulated inside the
SYS_NAND_SELF_INIT ifdef which appears to only be set if K3.  Should
this code be expected to work on OMAP2?  I don't think K3 is set for
OMAP2+.  If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is
selected?

I have a DM3730 that I can test with this.  Do you have a repo I can
point to to test?  If not, I'll pull the series from patchwork, but I
need to know what branch to use as a starting point.

thanks,

adam

> +       { }
> +};
> +
> +U_BOOT_DRIVER(gpmc_nand) = {
> +       .name           = "gpmc-nand",
> +       .id             = UCLASS_MTD,
> +       .of_match       = gpmc_nand_ids,
> +       .probe          = gpmc_nand_probe,
> +       .priv_auto      = sizeof(struct nand_chip),
> +};
> +
> +void board_nand_init(void)
> +{
> +       struct udevice *dev;
> +       int ret;
> +
> +       ret = uclass_get_device_by_driver(UCLASS_MTD,
> +                                         DM_DRIVER_GET(gpmc_nand), &dev);
> +       if (ret && ret != -ENODEV)
> +               pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);
> +}
> +#endif /* CONFIG_SYS_NAND_SELF_INIT */
> --
> 2.17.1
>

Re: [u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model

[Roger Quadros]

Hi Adam,

On 11/10/2022 18:01, Adam Ford wrote:
> On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros <rogerq@kernel.org> wrote:
>>
>> Adds driver model support.
>>
>> We need to be able to self initialize the NAND controller/chip
>> at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
>>
>> Doing so requires nand_register() API which is provided by nand.c
>> and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT.
>> But nand.c also provides nand_init() so we need to get rid of nand_init()
>> in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
>>
>> Signed-off-by: Roger Quadros <rogerq@kernel.org>
>> ---
>>  drivers/mtd/nand/raw/Kconfig     |  1 +
>>  drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++-
>>  2 files changed, 55 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index bc5cabdfc2..1d23144ce4 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC
>>  config NAND_OMAP_GPMC
>>         bool "Support OMAP GPMC NAND controller"
>>         depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
>> +       select SYS_NAND_SELF_INIT if ARCH_K3
> 
> I have a question about this down below.
> 
>>         help
>>           Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
>>           GPMC controller is used for parallel NAND flash devices, and can
>> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
>> index e772a914c8..7192ca9e5a 100644
>> --- a/drivers/mtd/nand/raw/omap_gpmc.c
>> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
>> @@ -7,6 +7,7 @@
>>  #include <common.h>
>>  #include <log.h>
>>  #include <asm/io.h>
>> +#include <dm/uclass.h>
>>  #include <linux/errno.h>
>>
>>  #ifdef CONFIG_ARCH_OMAP2PLUS
>> @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
>>   *   nand_scan about special functionality. See the defines for further
>>   *   explanation
>>   */
>> -int board_nand_init(struct nand_chip *nand)
>> +int gpmc_nand_init(struct nand_chip *nand)
>>  {
>>         int32_t gpmc_config = 0;
>>         int cs = cs_next++;
>> @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
>>
>>         return 0;
>>  }
>> +
>> +static struct nand_chip *nand_chip;    /* First NAND chip for SPL use only */
>> +
>> +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
>> +
>> +static int gpmc_nand_probe(struct udevice *dev)
>> +{
>> +       struct nand_chip *nand = dev_get_priv(dev);
>> +       struct mtd_info *mtd = nand_to_mtd(nand);
>> +       int ret;
>> +
>> +       gpmc_nand_init(nand);
>> +
>> +       ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
>> +       if (ret)
>> +               return ret;
>> +
>> +       ret = nand_register(0, mtd);
>> +       if (ret)
>> +               return ret;
>> +
>> +       if (!nand_chip)
>> +               nand_chip = nand;
>> +
>> +       return 0;
>> +}
>> +
>> +static const struct udevice_id gpmc_nand_ids[] = {
>> +       { .compatible = "ti,am64-nand" },
>> +       { .compatible = "ti,omap2-nand" },
> 
> The gpmc_nand_ids reference to omap2, but it's encapsulated inside the
> SYS_NAND_SELF_INIT ifdef which appears to only be set if K3.  Should
> this code be expected to work on OMAP2?  I don't think K3 is set for
> OMAP2+.  If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is
> selected?

We want to eventually get this working using driver model and SYS_NAND_SELF_INIT
for OMAP2 as well but just that I didn't work on it yet or test it.

One challenge is that OMAP2 boards tend to either select nand_spl_simple.c
or am335x_spl_bch.c for NAND support at SPL.

We will need to figure out if it is possible to use CONFIG_SPL_NAND_INIT
and this driver instead.
One issue might be that everything doesn't fit in resources available at SPL?

> 
> I have a DM3730 that I can test with this.  Do you have a repo I can

That would be great. Thanks!

> point to to test?  If not, I'll pull the series from patchwork, but I
> need to know what branch to use as a starting point.

You can use this Repo as reference.
https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-test

It has a few patches on top consisting of device tree and u-boot configuration
for AM64 platform. You can ignore the last 2 patches as they are only for a
workaround on early AM64 boards.

If you hit any hurdles, we can discuss how to resolve.

> 
> thanks,
> 
> adam
> 
>> +       { }
>> +};
>> +
>> +U_BOOT_DRIVER(gpmc_nand) = {
>> +       .name           = "gpmc-nand",
>> +       .id             = UCLASS_MTD,
>> +       .of_match       = gpmc_nand_ids,
>> +       .probe          = gpmc_nand_probe,
>> +       .priv_auto      = sizeof(struct nand_chip),
>> +};
>> +
>> +void board_nand_init(void)
>> +{
>> +       struct udevice *dev;
>> +       int ret;
>> +
>> +       ret = uclass_get_device_by_driver(UCLASS_MTD,
>> +                                         DM_DRIVER_GET(gpmc_nand), &dev);
>> +       if (ret && ret != -ENODEV)
>> +               pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);
>> +}
>> +#endif /* CONFIG_SYS_NAND_SELF_INIT */
>> --
>> 2.17.1
>>

cheers,
-roger

Re: [u-boot][PATCH 01/14] mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h

[Michael Nazzareno Trimarchi]

Hi

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> We want to get rid of <asm/arch/mem.h> so don't
> enforce it for new platforms.
>
> This also means GPMC_MAX CS doesn't have to be defined
> by platform code.
>
> Define it locally here for now.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/omap_gpmc.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> index 8b9ff4de18..7e9ccf7878 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -8,7 +8,11 @@
>  #include <log.h>
>  #include <asm/io.h>
>  #include <linux/errno.h>
> +
> +#ifdef CONFIG_ARCH_OMAP2PLUS
>  #include <asm/arch/mem.h>
> +#endif
> +
>  #include <linux/mtd/omap_gpmc.h>
>  #include <linux/mtd/nand_ecc.h>
>  #include <linux/mtd/rawnand.h>
> @@ -17,6 +21,10 @@
>  #include <nand.h>
>  #include <linux/mtd/omap_elm.h>
>
> +#ifndef GPMC_MAX_CS
> +#define GPMC_MAX_CS    4
> +#endif
> +

Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>

>  #define BADBLOCK_MARKER_LENGTH 2
>  #define SECTOR_BYTES           512
>  #define ECCCLEAR               (0x1 << 8)
> --
> 2.17.1
>


-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model

[Adam Ford]

On Wed, Oct 12, 2022 at 1:22 AM Roger Quadros <rogerq@kernel.org> wrote:
>
> Hi Adam,
>
> On 11/10/2022 18:01, Adam Ford wrote:
> > On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros <rogerq@kernel.org> wrote:
> >>
> >> Adds driver model support.
> >>
> >> We need to be able to self initialize the NAND controller/chip
> >> at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
> >>
> >> Doing so requires nand_register() API which is provided by nand.c
> >> and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT.
> >> But nand.c also provides nand_init() so we need to get rid of nand_init()
> >> in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
> >>
> >> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> >> ---
> >>  drivers/mtd/nand/raw/Kconfig     |  1 +
> >>  drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++-
> >>  2 files changed, 55 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
> >> index bc5cabdfc2..1d23144ce4 100644
> >> --- a/drivers/mtd/nand/raw/Kconfig
> >> +++ b/drivers/mtd/nand/raw/Kconfig
> >> @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC
> >>  config NAND_OMAP_GPMC
> >>         bool "Support OMAP GPMC NAND controller"
> >>         depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
> >> +       select SYS_NAND_SELF_INIT if ARCH_K3
> >
> > I have a question about this down below.
> >
> >>         help
> >>           Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
> >>           GPMC controller is used for parallel NAND flash devices, and can
> >> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> >> index e772a914c8..7192ca9e5a 100644
> >> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> >> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> >> @@ -7,6 +7,7 @@
> >>  #include <common.h>
> >>  #include <log.h>
> >>  #include <asm/io.h>
> >> +#include <dm/uclass.h>
> >>  #include <linux/errno.h>
> >>
> >>  #ifdef CONFIG_ARCH_OMAP2PLUS
> >> @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
> >>   *   nand_scan about special functionality. See the defines for further
> >>   *   explanation
> >>   */
> >> -int board_nand_init(struct nand_chip *nand)
> >> +int gpmc_nand_init(struct nand_chip *nand)
> >>  {
> >>         int32_t gpmc_config = 0;
> >>         int cs = cs_next++;
> >> @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
> >>
> >>         return 0;
> >>  }
> >> +
> >> +static struct nand_chip *nand_chip;    /* First NAND chip for SPL use only */
> >> +
> >> +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
> >> +
> >> +static int gpmc_nand_probe(struct udevice *dev)
> >> +{
> >> +       struct nand_chip *nand = dev_get_priv(dev);
> >> +       struct mtd_info *mtd = nand_to_mtd(nand);
> >> +       int ret;
> >> +
> >> +       gpmc_nand_init(nand);
> >> +
> >> +       ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
> >> +       if (ret)
> >> +               return ret;
> >> +
> >> +       ret = nand_register(0, mtd);
> >> +       if (ret)
> >> +               return ret;
> >> +
> >> +       if (!nand_chip)
> >> +               nand_chip = nand;
> >> +
> >> +       return 0;
> >> +}
> >> +
> >> +static const struct udevice_id gpmc_nand_ids[] = {
> >> +       { .compatible = "ti,am64-nand" },
> >> +       { .compatible = "ti,omap2-nand" },
> >
> > The gpmc_nand_ids reference to omap2, but it's encapsulated inside the
> > SYS_NAND_SELF_INIT ifdef which appears to only be set if K3.  Should
> > this code be expected to work on OMAP2?  I don't think K3 is set for
> > OMAP2+.  If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is
> > selected?
>
> We want to eventually get this working using driver model and SYS_NAND_SELF_INIT
> for OMAP2 as well but just that I didn't work on it yet or test it.
>
> One challenge is that OMAP2 boards tend to either select nand_spl_simple.c
> or am335x_spl_bch.c for NAND support at SPL.
>
> We will need to figure out if it is possible to use CONFIG_SPL_NAND_INIT
> and this driver instead.
> One issue might be that everything doesn't fit in resources available at SPL?

On my board the GPMC runs more than just NAND.  I am hoping to get the
GPMC driver working in U-Boot first then in SPL (assuming it fits).  I
have LTO enabled on my DM3730, so I am hoping it might help make some
room.  I am hoping that once the NAND is working that the GPMC driver
can be used in U-Boot to handle the configuration of the bus for
handling Ethernet, so some of the quirks and manual board file
configuration can be removed.
>
> >
> > I have a DM3730 that I can test with this.  Do you have a repo I can
>
> That would be great. Thanks!
>
> > point to to test?  If not, I'll pull the series from patchwork, but I
> > need to know what branch to use as a starting point.
>
> You can use this Repo as reference.
> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-test
>

Thanks!

> It has a few patches on top consisting of device tree and u-boot configuration
> for AM64 platform. You can ignore the last 2 patches as they are only for a
> workaround on early AM64 boards.
>
> If you hit any hurdles, we can discuss how to resolve.

I'll just pull in the branch and build for my DM3730 then start
enabling and disabling stuff.  I haven't checked how big SPL is, but
SPL keeps growing instead of shrinking.  OF_PLATDATA might be an
option if it doesn't fit in SPL, but I was hoping to avoid that.

adam
>
> >
> > thanks,
> >
> > adam
> >
> >> +       { }
> >> +};
> >> +
> >> +U_BOOT_DRIVER(gpmc_nand) = {
> >> +       .name           = "gpmc-nand",
> >> +       .id             = UCLASS_MTD,
> >> +       .of_match       = gpmc_nand_ids,
> >> +       .probe          = gpmc_nand_probe,
> >> +       .priv_auto      = sizeof(struct nand_chip),
> >> +};
> >> +
> >> +void board_nand_init(void)
> >> +{
> >> +       struct udevice *dev;
> >> +       int ret;
> >> +
> >> +       ret = uclass_get_device_by_driver(UCLASS_MTD,
> >> +                                         DM_DRIVER_GET(gpmc_nand), &dev);
> >> +       if (ret && ret != -ENODEV)
> >> +               pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);
> >> +}
> >> +#endif /* CONFIG_SYS_NAND_SELF_INIT */
> >> --
> >> 2.17.1
> >>
>
> cheers,
> -roger

Re: [u-boot][PATCH 02/14] mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms

[Michael Nazzareno Trimarchi]

Hi

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> The GPMC module is present on some K2 and K3 SoCs.
> Enable building GPMC NAND driver for K2/K3 platforms.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
> index ce67d1abde..bc5cabdfc2 100644
> --- a/drivers/mtd/nand/raw/Kconfig
> +++ b/drivers/mtd/nand/raw/Kconfig
> @@ -189,7 +189,7 @@ config NAND_LPC32XX_SLC
>
>  config NAND_OMAP_GPMC
>         bool "Support OMAP GPMC NAND controller"
> -       depends on ARCH_OMAP2PLUS
> +       depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
>         help
>           Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
>           GPMC controller is used for parallel NAND flash devices, and can
> --
> 2.17.1
>

Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>

-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model

[Ladislav Michl]

Hi Adam,

On Wed, Oct 12, 2022 at 06:42:22AM -0500, Adam Ford wrote:
[snip]
> On my board the GPMC runs more than just NAND.  I am hoping to get the
> GPMC driver working in U-Boot first then in SPL (assuming it fits).  I
> have LTO enabled on my DM3730, so I am hoping it might help make some
> room.  I am hoping that once the NAND is working that the GPMC driver
> can be used in U-Boot to handle the configuration of the bus for
> handling Ethernet, so some of the quirks and manual board file
> configuration can be removed.

Any estimate on that? I moved IGEP to use DM for ethernet, but for reasons
you mentioned quirk in DT is still there. Reposting that patch would
currently add one more quirk into codebase, so I'd better avoid that.

Thank you,
	L.

Re: [u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model

[Adam Ford]

On Wed, Oct 12, 2022 at 6:57 AM Ladislav Michl <oss-lists@triops.cz> wrote:
>
> Hi Adam,
>
> On Wed, Oct 12, 2022 at 06:42:22AM -0500, Adam Ford wrote:
> [snip]
> > On my board the GPMC runs more than just NAND.  I am hoping to get the
> > GPMC driver working in U-Boot first then in SPL (assuming it fits).  I
> > have LTO enabled on my DM3730, so I am hoping it might help make some
> > room.  I am hoping that once the NAND is working that the GPMC driver
> > can be used in U-Boot to handle the configuration of the bus for
> > handling Ethernet, so some of the quirks and manual board file
> > configuration can be removed.
>
> Any estimate on that? I moved IGEP to use DM for ethernet, but for reasons
> you mentioned quirk in DT is still there. Reposting that patch would
> currently add one more quirk into codebase, so I'd better avoid that.

I won't know until I have a chance to sit down and try out the code
framework that's proposed.  I'll be doing it as a side project, so I
can't guarantee speed, but since Roger is trying to get NAND working,
my work will start there with the hope of evolving it to do more as I
get time.

adam
>
> Thank you,
>         L.

Re: [u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model

[Adam Ford]

On Wed, Oct 12, 2022 at 6:42 AM Adam Ford <aford173@gmail.com> wrote:
>
> On Wed, Oct 12, 2022 at 1:22 AM Roger Quadros <rogerq@kernel.org> wrote:
> >
> > Hi Adam,
> >
> > On 11/10/2022 18:01, Adam Ford wrote:
> > > On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros <rogerq@kernel.org> wrote:
> > >>
> > >> Adds driver model support.
> > >>
> > >> We need to be able to self initialize the NAND controller/chip
> > >> at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
> > >>
> > >> Doing so requires nand_register() API which is provided by nand.c
> > >> and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT.
> > >> But nand.c also provides nand_init() so we need to get rid of nand_init()
> > >> in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
> > >>
> > >> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> > >> ---
> > >>  drivers/mtd/nand/raw/Kconfig     |  1 +
> > >>  drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++-
> > >>  2 files changed, 55 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
> > >> index bc5cabdfc2..1d23144ce4 100644
> > >> --- a/drivers/mtd/nand/raw/Kconfig
> > >> +++ b/drivers/mtd/nand/raw/Kconfig
> > >> @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC
> > >>  config NAND_OMAP_GPMC
> > >>         bool "Support OMAP GPMC NAND controller"
> > >>         depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
> > >> +       select SYS_NAND_SELF_INIT if ARCH_K3
> > >
> > > I have a question about this down below.
> > >
> > >>         help
> > >>           Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
> > >>           GPMC controller is used for parallel NAND flash devices, and can
> > >> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> > >> index e772a914c8..7192ca9e5a 100644
> > >> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> > >> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> > >> @@ -7,6 +7,7 @@
> > >>  #include <common.h>
> > >>  #include <log.h>
> > >>  #include <asm/io.h>
> > >> +#include <dm/uclass.h>
> > >>  #include <linux/errno.h>
> > >>
> > >>  #ifdef CONFIG_ARCH_OMAP2PLUS
> > >> @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
> > >>   *   nand_scan about special functionality. See the defines for further
> > >>   *   explanation
> > >>   */
> > >> -int board_nand_init(struct nand_chip *nand)
> > >> +int gpmc_nand_init(struct nand_chip *nand)
> > >>  {
> > >>         int32_t gpmc_config = 0;
> > >>         int cs = cs_next++;
> > >> @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
> > >>
> > >>         return 0;
> > >>  }
> > >> +
> > >> +static struct nand_chip *nand_chip;    /* First NAND chip for SPL use only */
> > >> +
> > >> +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
> > >> +
> > >> +static int gpmc_nand_probe(struct udevice *dev)
> > >> +{
> > >> +       struct nand_chip *nand = dev_get_priv(dev);
> > >> +       struct mtd_info *mtd = nand_to_mtd(nand);
> > >> +       int ret;
> > >> +
> > >> +       gpmc_nand_init(nand);
> > >> +
> > >> +       ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
> > >> +       if (ret)
> > >> +               return ret;
> > >> +
> > >> +       ret = nand_register(0, mtd);
> > >> +       if (ret)
> > >> +               return ret;
> > >> +
> > >> +       if (!nand_chip)
> > >> +               nand_chip = nand;
> > >> +
> > >> +       return 0;
> > >> +}
> > >> +
> > >> +static const struct udevice_id gpmc_nand_ids[] = {
> > >> +       { .compatible = "ti,am64-nand" },
> > >> +       { .compatible = "ti,omap2-nand" },
> > >
> > > The gpmc_nand_ids reference to omap2, but it's encapsulated inside the
> > > SYS_NAND_SELF_INIT ifdef which appears to only be set if K3.  Should
> > > this code be expected to work on OMAP2?  I don't think K3 is set for
> > > OMAP2+.  If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is
> > > selected?
> >
> > We want to eventually get this working using driver model and SYS_NAND_SELF_INIT
> > for OMAP2 as well but just that I didn't work on it yet or test it.
> >
> > One challenge is that OMAP2 boards tend to either select nand_spl_simple.c
> > or am335x_spl_bch.c for NAND support at SPL.
> >
> > We will need to figure out if it is possible to use CONFIG_SPL_NAND_INIT
> > and this driver instead.
> > One issue might be that everything doesn't fit in resources available at SPL?
>
> On my board the GPMC runs more than just NAND.  I am hoping to get the
> GPMC driver working in U-Boot first then in SPL (assuming it fits).  I
> have LTO enabled on my DM3730, so I am hoping it might help make some
> room.  I am hoping that once the NAND is working that the GPMC driver
> can be used in U-Boot to handle the configuration of the bus for
> handling Ethernet, so some of the quirks and manual board file
> configuration can be removed.
> >
> > >
> > > I have a DM3730 that I can test with this.  Do you have a repo I can
> >
> > That would be great. Thanks!

I haven't spend a lot of time, but here is what I have so far:

U-Boot 2022.10-rc4-gf499f45d18-dirty (Oct 13 2022 - 05:33:33 -0500)

OMAP3630/3730-GP ES1.2, CPU-OPP2, L3-200MHz, Max CPU Clock 1 GHz
Model: LogicPD Zoom DM3730 Torpedo + Wireless Development Kit
DRAM:  256 MiB
Error binding driver 'gpmc-nand': -96
Some drivers failed to bind
Error binding driver 'ti-gpmc': -96
Some drivers failed to bind
Error binding driver 'simple_bus': -96
Some drivers failed to bind
initcall sequence 8ffde84c failed at call 8011705d (err=-96)
### ERROR ### Please RESET the board ###

There was a small conflict with arch/arm/mach-omap2/mem-common.c
 where I needed to remove a reference to gpmc_cfg to let it compile.

+#ifndef CONFIG_TI_GPMC
 const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
+#endif

After that, I had to enable CONFIG_CLK and CONFIG_CLK_TI_GATE, but I
am not sure it's sufficient.  I haven't had enough time to check to
see if the OMAP3 clock drivers are fully supported in U-Boot or not.
I am guessing they'll need to be functional enough to fetch the fck so
the GPMC controller knows how fast it's running to properly calculate
the timings.

Do you have any suggestions on what I should do to diagnose the -96
errors on all the GPMC sub-nodes?

adam
> >
> > > point to to test?  If not, I'll pull the series from patchwork, but I
> > > need to know what branch to use as a starting point.
> >
> > You can use this Repo as reference.
> > https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-test
> >
>
> Thanks!
>
> > It has a few patches on top consisting of device tree and u-boot configuration
> > for AM64 platform. You can ignore the last 2 patches as they are only for a
> > workaround on early AM64 boards.
> >
> > If you hit any hurdles, we can discuss how to resolve.
>
> I'll just pull in the branch and build for my DM3730 then start
> enabling and disabling stuff.  I haven't checked how big SPL is, but
> SPL keeps growing instead of shrinking.  OF_PLATDATA might be an
> option if it doesn't fit in SPL, but I was hoping to avoid that.
>
> adam
> >
> > >
> > > thanks,
> > >
> > > adam
> > >
> > >> +       { }
> > >> +};
> > >> +
> > >> +U_BOOT_DRIVER(gpmc_nand) = {
> > >> +       .name           = "gpmc-nand",
> > >> +       .id             = UCLASS_MTD,
> > >> +       .of_match       = gpmc_nand_ids,
> > >> +       .probe          = gpmc_nand_probe,
> > >> +       .priv_auto      = sizeof(struct nand_chip),
> > >> +};
> > >> +
> > >> +void board_nand_init(void)
> > >> +{
> > >> +       struct udevice *dev;
> > >> +       int ret;
> > >> +
> > >> +       ret = uclass_get_device_by_driver(UCLASS_MTD,
> > >> +                                         DM_DRIVER_GET(gpmc_nand), &dev);
> > >> +       if (ret && ret != -ENODEV)
> > >> +               pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);
> > >> +}
> > >> +#endif /* CONFIG_SYS_NAND_SELF_INIT */
> > >> --
> > >> 2.17.1
> > >>
> >
> > cheers,
> > -roger

Re: [u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model

[Roger Quadros]

On 13/10/2022 14:17, Adam Ford wrote:
> On Wed, Oct 12, 2022 at 6:42 AM Adam Ford <aford173@gmail.com> wrote:
>>
>> On Wed, Oct 12, 2022 at 1:22 AM Roger Quadros <rogerq@kernel.org> wrote:
>>>
>>> Hi Adam,
>>>
>>> On 11/10/2022 18:01, Adam Ford wrote:
>>>> On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>
>>>>> Adds driver model support.
>>>>>
>>>>> We need to be able to self initialize the NAND controller/chip
>>>>> at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
>>>>>
>>>>> Doing so requires nand_register() API which is provided by nand.c
>>>>> and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT.
>>>>> But nand.c also provides nand_init() so we need to get rid of nand_init()
>>>>> in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
>>>>>
>>>>> Signed-off-by: Roger Quadros <rogerq@kernel.org>
>>>>> ---
>>>>>  drivers/mtd/nand/raw/Kconfig     |  1 +
>>>>>  drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++-
>>>>>  2 files changed, 55 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>>>>> index bc5cabdfc2..1d23144ce4 100644
>>>>> --- a/drivers/mtd/nand/raw/Kconfig
>>>>> +++ b/drivers/mtd/nand/raw/Kconfig
>>>>> @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC
>>>>>  config NAND_OMAP_GPMC
>>>>>         bool "Support OMAP GPMC NAND controller"
>>>>>         depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
>>>>> +       select SYS_NAND_SELF_INIT if ARCH_K3
>>>>
>>>> I have a question about this down below.
>>>>
>>>>>         help
>>>>>           Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
>>>>>           GPMC controller is used for parallel NAND flash devices, and can
>>>>> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
>>>>> index e772a914c8..7192ca9e5a 100644
>>>>> --- a/drivers/mtd/nand/raw/omap_gpmc.c
>>>>> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
>>>>> @@ -7,6 +7,7 @@
>>>>>  #include <common.h>
>>>>>  #include <log.h>
>>>>>  #include <asm/io.h>
>>>>> +#include <dm/uclass.h>
>>>>>  #include <linux/errno.h>
>>>>>
>>>>>  #ifdef CONFIG_ARCH_OMAP2PLUS
>>>>> @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
>>>>>   *   nand_scan about special functionality. See the defines for further
>>>>>   *   explanation
>>>>>   */
>>>>> -int board_nand_init(struct nand_chip *nand)
>>>>> +int gpmc_nand_init(struct nand_chip *nand)
>>>>>  {
>>>>>         int32_t gpmc_config = 0;
>>>>>         int cs = cs_next++;
>>>>> @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
>>>>>
>>>>>         return 0;
>>>>>  }
>>>>> +
>>>>> +static struct nand_chip *nand_chip;    /* First NAND chip for SPL use only */
>>>>> +
>>>>> +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
>>>>> +
>>>>> +static int gpmc_nand_probe(struct udevice *dev)
>>>>> +{
>>>>> +       struct nand_chip *nand = dev_get_priv(dev);
>>>>> +       struct mtd_info *mtd = nand_to_mtd(nand);
>>>>> +       int ret;
>>>>> +
>>>>> +       gpmc_nand_init(nand);
>>>>> +
>>>>> +       ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
>>>>> +       if (ret)
>>>>> +               return ret;
>>>>> +
>>>>> +       ret = nand_register(0, mtd);
>>>>> +       if (ret)
>>>>> +               return ret;
>>>>> +
>>>>> +       if (!nand_chip)
>>>>> +               nand_chip = nand;
>>>>> +
>>>>> +       return 0;
>>>>> +}
>>>>> +
>>>>> +static const struct udevice_id gpmc_nand_ids[] = {
>>>>> +       { .compatible = "ti,am64-nand" },
>>>>> +       { .compatible = "ti,omap2-nand" },
>>>>
>>>> The gpmc_nand_ids reference to omap2, but it's encapsulated inside the
>>>> SYS_NAND_SELF_INIT ifdef which appears to only be set if K3.  Should
>>>> this code be expected to work on OMAP2?  I don't think K3 is set for
>>>> OMAP2+.  If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is
>>>> selected?
>>>
>>> We want to eventually get this working using driver model and SYS_NAND_SELF_INIT
>>> for OMAP2 as well but just that I didn't work on it yet or test it.
>>>
>>> One challenge is that OMAP2 boards tend to either select nand_spl_simple.c
>>> or am335x_spl_bch.c for NAND support at SPL.
>>>
>>> We will need to figure out if it is possible to use CONFIG_SPL_NAND_INIT
>>> and this driver instead.
>>> One issue might be that everything doesn't fit in resources available at SPL?
>>
>> On my board the GPMC runs more than just NAND.  I am hoping to get the
>> GPMC driver working in U-Boot first then in SPL (assuming it fits).  I
>> have LTO enabled on my DM3730, so I am hoping it might help make some
>> room.  I am hoping that once the NAND is working that the GPMC driver
>> can be used in U-Boot to handle the configuration of the bus for
>> handling Ethernet, so some of the quirks and manual board file
>> configuration can be removed.
>>>
>>>>
>>>> I have a DM3730 that I can test with this.  Do you have a repo I can
>>>
>>> That would be great. Thanks!
> 
> I haven't spend a lot of time, but here is what I have so far:
> 
> U-Boot 2022.10-rc4-gf499f45d18-dirty (Oct 13 2022 - 05:33:33 -0500)
> 
> OMAP3630/3730-GP ES1.2, CPU-OPP2, L3-200MHz, Max CPU Clock 1 GHz
> Model: LogicPD Zoom DM3730 Torpedo + Wireless Development Kit
> DRAM:  256 MiB
> Error binding driver 'gpmc-nand': -96
> Some drivers failed to bind
> Error binding driver 'ti-gpmc': -96
> Some drivers failed to bind
> Error binding driver 'simple_bus': -96
> Some drivers failed to bind
> initcall sequence 8ffde84c failed at call 8011705d (err=-96)
> ### ERROR ### Please RESET the board ###
> 
> There was a small conflict with arch/arm/mach-omap2/mem-common.c
>  where I needed to remove a reference to gpmc_cfg to let it compile.
> 
> +#ifndef CONFIG_TI_GPMC
>  const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
> +#endif

OK. But eventually we don't want to include mem-common.c
when TI_GPMC driver is enabled.

> 
> After that, I had to enable CONFIG_CLK and CONFIG_CLK_TI_GATE, but I
> am not sure it's sufficient.  I haven't had enough time to check to
> see if the OMAP3 clock drivers are fully supported in U-Boot or not.

Tom could answer this question.

> I am guessing they'll need to be functional enough to fetch the fck so
> the GPMC controller knows how fast it's running to properly calculate
> the timings.

Even if fck is not available we could assume a default value for now so
driver can proceed.

> 
> Do you have any suggestions on what I should do to diagnose the -96
> errors on all the GPMC sub-nodes?

-96 is EPFNOSUPPORT and it seems to be coming from uclass_add()

Did you enable CONFIG_DM_MEMORY and CONFIG_DM_MTD?

If that doesn't work then try to add some prints in device_bind_common() to see where it fails.

Please see this patch to see what all I had to enable to get NAND working on AM64
https://github.com/rogerq/u-boot/commit/f831875b6551588f7c83314d5770e2b73b18bc37

The following 2 patches might also be helpful to get NAND to work
https://github.com/rogerq/u-boot/commit/2c64a620e2a65eef3bbe3aa1e74488daea9e019d

https://github.com/rogerq/u-boot/commit/50d7ed49bc4737cccecc5ce2e3f2c3b17d540a5f

> 
> adam
>>>
>>>> point to to test?  If not, I'll pull the series from patchwork, but I
>>>> need to know what branch to use as a starting point.
>>>
>>> You can use this Repo as reference.
>>> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-test
>>>
>>
>> Thanks!
>>
>>> It has a few patches on top consisting of device tree and u-boot configuration
>>> for AM64 platform. You can ignore the last 2 patches as they are only for a
>>> workaround on early AM64 boards.
>>>
>>> If you hit any hurdles, we can discuss how to resolve.
>>
>> I'll just pull in the branch and build for my DM3730 then start
>> enabling and disabling stuff.  I haven't checked how big SPL is, but
>> SPL keeps growing instead of shrinking.  OF_PLATDATA might be an
>> option if it doesn't fit in SPL, but I was hoping to avoid that.
>>
>> adam
>>>
>>>>
>>>> thanks,
>>>>
>>>> adam
>>>>
>>>>> +       { }
>>>>> +};
>>>>> +
>>>>> +U_BOOT_DRIVER(gpmc_nand) = {
>>>>> +       .name           = "gpmc-nand",
>>>>> +       .id             = UCLASS_MTD,
>>>>> +       .of_match       = gpmc_nand_ids,
>>>>> +       .probe          = gpmc_nand_probe,
>>>>> +       .priv_auto      = sizeof(struct nand_chip),
>>>>> +};
>>>>> +
>>>>> +void board_nand_init(void)
>>>>> +{
>>>>> +       struct udevice *dev;
>>>>> +       int ret;
>>>>> +
>>>>> +       ret = uclass_get_device_by_driver(UCLASS_MTD,
>>>>> +                                         DM_DRIVER_GET(gpmc_nand), &dev);
>>>>> +       if (ret && ret != -ENODEV)
>>>>> +               pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);
>>>>> +}
>>>>> +#endif /* CONFIG_SYS_NAND_SELF_INIT */
>>>>> --
>>>>> 2.17.1
>>>>>
>>>
>>> cheers,
>>> -roger

cheers,
-roger

Re: [u-boot][PATCH 03/14] mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms

[Michael Nazzareno Trimarchi]

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Pointer size cannot be assumed to be 32-bit, so use
> use uintptr_t instead of uint32_t.
>
> Fixes the below build warning on 64-bit builds.
>
> drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
>   head = ((uint32_t) buf) % 4;
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/omap_gpmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> index 7e9ccf7878..d62c3e6fce 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -438,14 +438,14 @@ static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
>  static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>  {
>         int ret;
> -       uint32_t head, tail;
> +       uintptr_t head, tail;
>         struct nand_chip *chip = mtd_to_nand(mtd);
>
>         /*
>          * If the destination buffer is unaligned, start with reading
>          * the overlap byte-wise.
>          */
> -       head = ((uint32_t) buf) % 4;
> +       head = ((uintptr_t)buf) % 4;
>         if (head) {
>                 omap_nand_read(mtd, buf, head);
>                 buf += head;
> --
> 2.17.1
>

Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>

Michael

-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 04/14] mtd: rawnand: omap_gpmc: Optimize NAND reads

[Michael Nazzareno Trimarchi]

Hi

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Rename omap_nand_read() to omap_nand_read_buf() to reflect
> actual behaviour.
>
> Use FIFO read address instead of raw read address for reads.
>
> The GPMC automatically converts 32-bit/16-bit reads to NAND
> device specific reads (8/16 bit). Use the largest possible
> read granularity size for more efficient reads.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++--------------
>  1 file changed, 28 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> index d62c3e6fce..b36fe762b3 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -55,6 +55,7 @@ struct omap_nand_info {
>         enum omap_ecc ecc_scheme;
>         uint8_t cs;
>         uint8_t ws;             /* wait status pin (0,1) */
> +       void __iomem *fifo;
>  };
>
>  /* We are wasting a bit of memory but al least we are safe */
> @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>         return 0;
>  }
>
> +static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> +       struct nand_chip *chip = mtd_to_nand(mtd);
> +       struct omap_nand_info *info = nand_get_controller_data(chip);
> +       u32 alignment = ((uintptr_t)buf | len) & 3;
> +
> +       if (alignment & 1)
> +               readsb(info->fifo, buf, len);
> +       else if (alignment & 3)
> +               readsw(info->fifo, buf, len >> 1);
> +       else
> +               readsl(info->fifo, buf, len >> 2);
> +}
> +
>  #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
>
>  #define PREFETCH_CONFIG1_CS_SHIFT      24
> @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
>                 cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
>
>                 for (i = 0; i < cnt / 4; i++) {
> -                       *buf++ = readl(CONFIG_SYS_NAND_BASE);
> +                       *buf++ = readl(info->fifo);
>                         len -= 4;
>                 }
>         } while (len);
> @@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
>         return 0;
>  }
>
> -static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
> -{
> -       struct nand_chip *chip = mtd_to_nand(mtd);
> -
> -       if (chip->options & NAND_BUSWIDTH_16)
> -               nand_read_buf16(mtd, buf, len);
> -       else
> -               nand_read_buf(mtd, buf, len);
> -}
> -
>  static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>  {
>         int ret;
> @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>          */
>         head = ((uintptr_t)buf) % 4;
>         if (head) {
> -               omap_nand_read(mtd, buf, head);
> +               omap_nand_read_buf(mtd, buf, head);
>                 buf += head;
>                 len -= head;
>         }
> @@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>         ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
>         if (ret < 0) {
>                 /* fallback in case the prefetch engine is busy */
> -               omap_nand_read(mtd, buf, len);
> +               omap_nand_read_buf(mtd, buf, len);
>         } else if (tail) {
>                 buf += len - tail;
> -               omap_nand_read(mtd, buf, tail);
> +               omap_nand_read_buf(mtd, buf, tail);
>         }
>  }
>  #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
> @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand)
>         int32_t gpmc_config = 0;
>         int cs = cs_next++;
>         int err = 0;
> +       struct omap_nand_info *info;
> +
>         /*
>          * xloader/Uboot's gpmc configuration would have configured GPMC for
>          * nand type of memory. The following logic scans and latches on to the
> @@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand)
>
>         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
>         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
> -       omap_nand_info[cs].control = NULL;
> -       omap_nand_info[cs].cs = cs;
> -       omap_nand_info[cs].ws = wscfg[cs];
> +
> +       info = &omap_nand_info[cs];
> +       info->control = NULL;
> +       info->cs = cs;
> +       info->ws = wscfg[cs];
> +       info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE;
>         nand_set_controller_data(nand, &omap_nand_info[cs]);
>         nand->cmd_ctrl  = omap_nand_hwcontrol;
>         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
> @@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand)
>  #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
>         nand->read_buf = omap_nand_read_prefetch;
>  #else
> -       if (nand->options & NAND_BUSWIDTH_16)
> -               nand->read_buf = nand_read_buf16;
> -       else
> -               nand->read_buf = nand_read_buf;
> +       nand->read_buf = omap_nand_read_buf;
>  #endif
>
>         nand->dev_ready = omap_dev_ready;
> --
> 2.17.1
>

Is possible for you to split in use of fifo and optimize read/alignment

Otherwise

Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>


-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 04/14] mtd: rawnand: omap_gpmc: Optimize NAND reads

[Roger Quadros]

Hi Michael,

On 15/10/2022 10:24, Michael Nazzareno Trimarchi wrote:
> Hi
> 
> On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>>
>> Rename omap_nand_read() to omap_nand_read_buf() to reflect
>> actual behaviour.
>>
>> Use FIFO read address instead of raw read address for reads.
>>
>> The GPMC automatically converts 32-bit/16-bit reads to NAND
>> device specific reads (8/16 bit). Use the largest possible
>> read granularity size for more efficient reads.
>>
>> Signed-off-by: Roger Quadros <rogerq@kernel.org>
>> ---
>>  drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++--------------
>>  1 file changed, 28 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
>> index d62c3e6fce..b36fe762b3 100644
>> --- a/drivers/mtd/nand/raw/omap_gpmc.c
>> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
>> @@ -55,6 +55,7 @@ struct omap_nand_info {
>>         enum omap_ecc ecc_scheme;
>>         uint8_t cs;
>>         uint8_t ws;             /* wait status pin (0,1) */
>> +       void __iomem *fifo;
>>  };
>>
>>  /* We are wasting a bit of memory but al least we are safe */
>> @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>>         return 0;
>>  }
>>
>> +static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>> +{
>> +       struct nand_chip *chip = mtd_to_nand(mtd);
>> +       struct omap_nand_info *info = nand_get_controller_data(chip);
>> +       u32 alignment = ((uintptr_t)buf | len) & 3;
>> +
>> +       if (alignment & 1)
>> +               readsb(info->fifo, buf, len);
>> +       else if (alignment & 3)
>> +               readsw(info->fifo, buf, len >> 1);
>> +       else
>> +               readsl(info->fifo, buf, len >> 2);
>> +}
>> +
>>  #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
>>
>>  #define PREFETCH_CONFIG1_CS_SHIFT      24
>> @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
>>                 cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
>>
>>                 for (i = 0; i < cnt / 4; i++) {
>> -                       *buf++ = readl(CONFIG_SYS_NAND_BASE);
>> +                       *buf++ = readl(info->fifo);
>>                         len -= 4;
>>                 }
>>         } while (len);
>> @@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
>>         return 0;
>>  }
>>
>> -static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
>> -{
>> -       struct nand_chip *chip = mtd_to_nand(mtd);
>> -
>> -       if (chip->options & NAND_BUSWIDTH_16)
>> -               nand_read_buf16(mtd, buf, len);
>> -       else
>> -               nand_read_buf(mtd, buf, len);
>> -}
>> -
>>  static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>>  {
>>         int ret;
>> @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>>          */
>>         head = ((uintptr_t)buf) % 4;
>>         if (head) {
>> -               omap_nand_read(mtd, buf, head);
>> +               omap_nand_read_buf(mtd, buf, head);
>>                 buf += head;
>>                 len -= head;
>>         }
>> @@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>>         ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
>>         if (ret < 0) {
>>                 /* fallback in case the prefetch engine is busy */
>> -               omap_nand_read(mtd, buf, len);
>> +               omap_nand_read_buf(mtd, buf, len);
>>         } else if (tail) {
>>                 buf += len - tail;
>> -               omap_nand_read(mtd, buf, tail);
>> +               omap_nand_read_buf(mtd, buf, tail);
>>         }
>>  }
>>  #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
>> @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand)
>>         int32_t gpmc_config = 0;
>>         int cs = cs_next++;
>>         int err = 0;
>> +       struct omap_nand_info *info;
>> +
>>         /*
>>          * xloader/Uboot's gpmc configuration would have configured GPMC for
>>          * nand type of memory. The following logic scans and latches on to the
>> @@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand)
>>
>>         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
>>         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
>> -       omap_nand_info[cs].control = NULL;
>> -       omap_nand_info[cs].cs = cs;
>> -       omap_nand_info[cs].ws = wscfg[cs];
>> +
>> +       info = &omap_nand_info[cs];
>> +       info->control = NULL;
>> +       info->cs = cs;
>> +       info->ws = wscfg[cs];
>> +       info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE;
>>         nand_set_controller_data(nand, &omap_nand_info[cs]);
>>         nand->cmd_ctrl  = omap_nand_hwcontrol;
>>         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
>> @@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand)
>>  #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
>>         nand->read_buf = omap_nand_read_prefetch;
>>  #else
>> -       if (nand->options & NAND_BUSWIDTH_16)
>> -               nand->read_buf = nand_read_buf16;
>> -       else
>> -               nand->read_buf = nand_read_buf;
>> +       nand->read_buf = omap_nand_read_buf;
>>  #endif
>>
>>         nand->dev_ready = omap_dev_ready;
>> --
>> 2.17.1
>>
> 
> Is possible for you to split in use of fifo and optimize read/alignment

Sure, I'll remember to do that when I re-spin this series.

> 
> Otherwise
> 
> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
> 
> 
Thanks!

--
cheers,
-roger

Re: [u-boot][PATCH 04/14] mtd: rawnand: omap_gpmc: Optimize NAND reads

[Michael Nazzareno Trimarchi]

Hi Roger

On Sat, Oct 15, 2022 at 3:29 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Hi Michael,
>
> On 15/10/2022 10:24, Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>
> >> Rename omap_nand_read() to omap_nand_read_buf() to reflect
> >> actual behaviour.
> >>
> >> Use FIFO read address instead of raw read address for reads.
> >>
> >> The GPMC automatically converts 32-bit/16-bit reads to NAND
> >> device specific reads (8/16 bit). Use the largest possible
> >> read granularity size for more efficient reads.
> >>
> >> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> >> ---
> >>  drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++--------------
> >>  1 file changed, 28 insertions(+), 21 deletions(-)
> >>
> >> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> >> index d62c3e6fce..b36fe762b3 100644
> >> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> >> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> >> @@ -55,6 +55,7 @@ struct omap_nand_info {
> >>         enum omap_ecc ecc_scheme;
> >>         uint8_t cs;
> >>         uint8_t ws;             /* wait status pin (0,1) */
> >> +       void __iomem *fifo;
> >>  };
> >>
> >>  /* We are wasting a bit of memory but al least we are safe */
> >> @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
> >>         return 0;
> >>  }
> >>
> >> +static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> >> +{
> >> +       struct nand_chip *chip = mtd_to_nand(mtd);
> >> +       struct omap_nand_info *info = nand_get_controller_data(chip);
> >> +       u32 alignment = ((uintptr_t)buf | len) & 3;
> >> +
> >> +       if (alignment & 1)
> >> +               readsb(info->fifo, buf, len);
> >> +       else if (alignment & 3)
> >> +               readsw(info->fifo, buf, len >> 1);
> >> +       else
> >> +               readsl(info->fifo, buf, len >> 2);
> >> +}
> >> +

Can you optimize more I think here.You can consider the disaligment
portion and then read at max len. You read more
than the actual lens but I think it should not be a big problem. In
case of SPL you can use byte read and then can reduce
the code size here

Michael

> >>  #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
> >>
> >>  #define PREFETCH_CONFIG1_CS_SHIFT      24
> >> @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
> >>                 cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
> >>
> >>                 for (i = 0; i < cnt / 4; i++) {
> >> -                       *buf++ = readl(CONFIG_SYS_NAND_BASE);
> >> +                       *buf++ = readl(info->fifo);
> >>                         len -= 4;
> >>                 }
> >>         } while (len);
> >> @@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
> >>         return 0;
> >>  }
> >>
> >> -static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
> >> -{
> >> -       struct nand_chip *chip = mtd_to_nand(mtd);
> >> -
> >> -       if (chip->options & NAND_BUSWIDTH_16)
> >> -               nand_read_buf16(mtd, buf, len);
> >> -       else
> >> -               nand_read_buf(mtd, buf, len);
> >> -}
> >> -
> >>  static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
> >>  {
> >>         int ret;
> >> @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
> >>          */
> >>         head = ((uintptr_t)buf) % 4;
> >>         if (head) {
> >> -               omap_nand_read(mtd, buf, head);
> >> +               omap_nand_read_buf(mtd, buf, head);
> >>                 buf += head;
> >>                 len -= head;
> >>         }
> >> @@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
> >>         ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
> >>         if (ret < 0) {
> >>                 /* fallback in case the prefetch engine is busy */
> >> -               omap_nand_read(mtd, buf, len);
> >> +               omap_nand_read_buf(mtd, buf, len);
> >>         } else if (tail) {
> >>                 buf += len - tail;
> >> -               omap_nand_read(mtd, buf, tail);
> >> +               omap_nand_read_buf(mtd, buf, tail);
> >>         }
> >>  }
> >>  #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
> >> @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand)
> >>         int32_t gpmc_config = 0;
> >>         int cs = cs_next++;
> >>         int err = 0;
> >> +       struct omap_nand_info *info;
> >> +
> >>         /*
> >>          * xloader/Uboot's gpmc configuration would have configured GPMC for
> >>          * nand type of memory. The following logic scans and latches on to the
> >> @@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand)
> >>
> >>         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
> >>         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
> >> -       omap_nand_info[cs].control = NULL;
> >> -       omap_nand_info[cs].cs = cs;
> >> -       omap_nand_info[cs].ws = wscfg[cs];
> >> +
> >> +       info = &omap_nand_info[cs];
> >> +       info->control = NULL;
> >> +       info->cs = cs;
> >> +       info->ws = wscfg[cs];
> >> +       info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE;
> >>         nand_set_controller_data(nand, &omap_nand_info[cs]);
> >>         nand->cmd_ctrl  = omap_nand_hwcontrol;
> >>         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
> >> @@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand)
> >>  #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
> >>         nand->read_buf = omap_nand_read_prefetch;
> >>  #else
> >> -       if (nand->options & NAND_BUSWIDTH_16)
> >> -               nand->read_buf = nand_read_buf16;
> >> -       else
> >> -               nand->read_buf = nand_read_buf;
> >> +       nand->read_buf = omap_nand_read_buf;
> >>  #endif
> >>
> >>         nand->dev_ready = omap_dev_ready;
> >> --
> >> 2.17.1
> >>
> >
> > Is possible for you to split in use of fifo and optimize read/alignment
>
> Sure, I'll remember to do that when I re-spin this series.
>
> >
> > Otherwise
> >
> > Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
> >
> >
> Thanks!
>
> --
> cheers,
> -roger



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 04/14] mtd: rawnand: omap_gpmc: Optimize NAND reads

[Roger Quadros]

Hi Michael,

On 17/10/2022 09:39, Michael Nazzareno Trimarchi wrote:
> Hi Roger
> 
> On Sat, Oct 15, 2022 at 3:29 PM Roger Quadros <rogerq@kernel.org> wrote:
>>
>> Hi Michael,
>>
>> On 15/10/2022 10:24, Michael Nazzareno Trimarchi wrote:
>>> Hi
>>>
>>> On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>
>>>> Rename omap_nand_read() to omap_nand_read_buf() to reflect
>>>> actual behaviour.
>>>>
>>>> Use FIFO read address instead of raw read address for reads.
>>>>
>>>> The GPMC automatically converts 32-bit/16-bit reads to NAND
>>>> device specific reads (8/16 bit). Use the largest possible
>>>> read granularity size for more efficient reads.
>>>>
>>>> Signed-off-by: Roger Quadros <rogerq@kernel.org>
>>>> ---
>>>>  drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++--------------
>>>>  1 file changed, 28 insertions(+), 21 deletions(-)
>>>>
>>>> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
>>>> index d62c3e6fce..b36fe762b3 100644
>>>> --- a/drivers/mtd/nand/raw/omap_gpmc.c
>>>> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
>>>> @@ -55,6 +55,7 @@ struct omap_nand_info {
>>>>         enum omap_ecc ecc_scheme;
>>>>         uint8_t cs;
>>>>         uint8_t ws;             /* wait status pin (0,1) */
>>>> +       void __iomem *fifo;
>>>>  };
>>>>
>>>>  /* We are wasting a bit of memory but al least we are safe */
>>>> @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>>>>         return 0;
>>>>  }
>>>>
>>>> +static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>>>> +{
>>>> +       struct nand_chip *chip = mtd_to_nand(mtd);
>>>> +       struct omap_nand_info *info = nand_get_controller_data(chip);
>>>> +       u32 alignment = ((uintptr_t)buf | len) & 3;
>>>> +
>>>> +       if (alignment & 1)
>>>> +               readsb(info->fifo, buf, len);
>>>> +       else if (alignment & 3)
>>>> +               readsw(info->fifo, buf, len >> 1);
>>>> +       else
>>>> +               readsl(info->fifo, buf, len >> 2);
>>>> +}
>>>> +
> 
> Can you optimize more I think here.You can consider the disaligment
> portion and then read at max len. You read more
> than the actual lens but I think it should not be a big problem. In

This will overrun the passed buffer and we don't want to take that risk?

> case of SPL you can use byte read and then can reduce
> the code size here

Apart from some legacy chips SPL size is not a huge problem. So
unless we are sure that we can actually run this driver in SPL
there is no point in doing any SPL optimizations now.

> 
> Michael

cheers,
-roger

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Roger Quadros]

Hi,

On 11/10/2022 14:49, Roger Quadros wrote:
> Hi,
> 
> This series adds driver model support for rawnand: omap_gpmc
> and omap_elm drivers.
> 
> This will enable the driver to be used on K2/K3 platforms as well.

Any comments on patches 5 and later? Thanks


cheers,
-roger

> 
> cheers,
> -roger
> 
> Roger Quadros (14):
>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>   mtd: rawnand: omap_gpmc: Optimize NAND reads
>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
>     nand_bbt
>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>   mtd: rawnand: omap_gpmc: Reduce .bss usage
>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
>   mtd: rawnand: omap_gpmc: support u-boot driver model
>   mtd: rawnand: omap_gpmc: Add SPL NAND support
>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
>   dt-bindings: mtd: Add ti,elm DT binding documentation
>   mtd: rawnand: omap_elm: u-boot driver model support
> 
>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
>  drivers/mtd/nand/raw/Makefile                 |   2 +-
>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
>  9 files changed, 637 insertions(+), 136 deletions(-)
>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> 

Re: [u-boot][PATCH 07/14] mtd: rawnand: nand_spl_loaders: Fix cast type build warning

[Michael Nazzareno Trimarchi]

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Fixes the below build warning on 64-bit platforms.
>
> drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
>       dst = (void *)((int)dst - page_offset);
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c
> index 4befc75c04..156b44d835 100644
> --- a/drivers/mtd/nand/raw/nand_spl_loaders.c
> +++ b/drivers/mtd/nand/raw/nand_spl_loaders.c
> @@ -23,7 +23,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
>                                 if (unlikely(page_offset)) {
>                                         memmove(dst, dst + page_offset,
>                                                 CONFIG_SYS_NAND_PAGE_SIZE);
> -                                       dst = (void *)((int)dst - page_offset);
> +                                       dst = (void *)(dst - page_offset);
>                                         page_offset = 0;
>                                 }
>                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;

Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>

> --
> 2.17.1
>


-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Michael Nazzareno Trimarchi]

Hi Roger

On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Hi,
>
> On 11/10/2022 14:49, Roger Quadros wrote:
> > Hi,
> >
> > This series adds driver model support for rawnand: omap_gpmc
> > and omap_elm drivers.
> >
> > This will enable the driver to be used on K2/K3 platforms as well.
>
> Any comments on patches 5 and later? Thanks
>

We will try to close this week.

Michael

>
> cheers,
> -roger
>
> >
> > cheers,
> > -roger
> >
> > Roger Quadros (14):
> >   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >   mtd: rawnand: omap_gpmc: Optimize NAND reads
> >   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> >   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> >     nand_bbt
> >   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >   mtd: rawnand: omap_gpmc: Reduce .bss usage
> >   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> >   mtd: rawnand: omap_gpmc: support u-boot driver model
> >   mtd: rawnand: omap_gpmc: Add SPL NAND support
> >   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> >   dt-bindings: mtd: Add ti,elm DT binding documentation
> >   mtd: rawnand: omap_elm: u-boot driver model support
> >
> >  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> >  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> >  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> >  drivers/mtd/nand/raw/Makefile                 |   2 +-
> >  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> >  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> >  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> >  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> >  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> >  9 files changed, 637 insertions(+), 136 deletions(-)
> >  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> >  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> >  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> >



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Roger Quadros]

Hi Michael,

On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> Hi Roger
> 
> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
>>
>> Hi,
>>
>> On 11/10/2022 14:49, Roger Quadros wrote:
>>> Hi,
>>>
>>> This series adds driver model support for rawnand: omap_gpmc
>>> and omap_elm drivers.
>>>
>>> This will enable the driver to be used on K2/K3 platforms as well.
>>
>> Any comments on patches 5 and later? Thanks
>>
> 
> We will try to close this week.

Could you please give your comments on the last few patches. Thanks!

cheers,
-roger

> 
> Michael
> 
>>
>> cheers,
>> -roger
>>
>>>
>>> cheers,
>>> -roger
>>>
>>> Roger Quadros (14):
>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
>>>     nand_bbt
>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
>>>   mtd: rawnand: omap_elm: u-boot driver model support
>>>
>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
>>>  9 files changed, 637 insertions(+), 136 deletions(-)
>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
>>>
> 
> 
> 

Re: [u-boot][PATCH 05/14] mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction

[Michael Nazzareno Trimarchi]

Hi Roger

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> The BCH detection hardware can generate ECC bytes for multiple
> sectors in one go. Use that feature.
>
> correct() only corrects one sector at a time so we need to call it
> repeatedly for each sector.
>

Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>


> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/omap_gpmc.c | 325 +++++++++++++++++++++----------
>  1 file changed, 223 insertions(+), 102 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> index b36fe762b3..b5ad66ad49 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -27,6 +27,9 @@
>
>  #define BADBLOCK_MARKER_LENGTH 2
>  #define SECTOR_BYTES           512
> +#define ECCSIZE0_SHIFT         12
> +#define ECCSIZE1_SHIFT         22
> +#define ECC1RESULTSIZE         0x1
>  #define ECCCLEAR               (0x1 << 8)
>  #define ECCRESULTREG1          (0x1 << 0)
>  /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
> @@ -187,72 +190,35 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
>  __maybe_unused
>  static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
>  {
> -       struct nand_chip        *nand   = mtd_to_nand(mtd);
> -       struct omap_nand_info   *info   = nand_get_controller_data(nand);
> +       struct nand_chip *nand = mtd_to_nand(mtd);
> +       struct omap_nand_info *info = nand_get_controller_data(nand);
>         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
> -       unsigned int ecc_algo = 0;
> -       unsigned int bch_type = 0;
> -       unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
> -       u32 ecc_size_config_val = 0;
> -       u32 ecc_config_val = 0;
> -       int cs = info->cs;
> +       u32 val;
>
> -       /* configure GPMC for specific ecc-scheme */
> -       switch (info->ecc_scheme) {
> -       case OMAP_ECC_HAM1_CODE_SW:
> -               return;
> -       case OMAP_ECC_HAM1_CODE_HW:
> -               ecc_algo = 0x0;
> -               bch_type = 0x0;
> -               bch_wrapmode = 0x00;
> -               eccsize0 = 0xFF;
> -               eccsize1 = 0xFF;
> +       /* Clear ecc and enable bits */
> +       writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
> +
> +       /* program ecc and result sizes */
> +       val = ((((nand->ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
> +                       ECC1RESULTSIZE);
> +       writel(val, &gpmc_cfg->ecc_size_config);
> +
> +       switch (mode) {
> +       case NAND_ECC_READ:
> +       case NAND_ECC_WRITE:
> +               writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
>                 break;
> -       case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> -       case OMAP_ECC_BCH8_CODE_HW:
> -               ecc_algo = 0x1;
> -               bch_type = 0x1;
> -               if (mode == NAND_ECC_WRITE) {
> -                       bch_wrapmode = 0x01;
> -                       eccsize0 = 0;  /* extra bits in nibbles per sector */
> -                       eccsize1 = 28; /* OOB bits in nibbles per sector */
> -               } else {
> -                       bch_wrapmode = 0x01;
> -                       eccsize0 = 26; /* ECC bits in nibbles per sector */
> -                       eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
> -               }
> -               break;
> -       case OMAP_ECC_BCH16_CODE_HW:
> -               ecc_algo = 0x1;
> -               bch_type = 0x2;
> -               if (mode == NAND_ECC_WRITE) {
> -                       bch_wrapmode = 0x01;
> -                       eccsize0 = 0;  /* extra bits in nibbles per sector */
> -                       eccsize1 = 52; /* OOB bits in nibbles per sector */
> -               } else {
> -                       bch_wrapmode = 0x01;
> -                       eccsize0 = 52; /* ECC bits in nibbles per sector */
> -                       eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
> -               }
> +       case NAND_ECC_READSYN:
> +               writel(ECCCLEAR, &gpmc_cfg->ecc_control);
>                 break;
>         default:
> -               return;
> +               printf("%s: error: unrecognized Mode[%d]!\n", __func__, mode);
> +               break;
>         }
> -       /* Clear ecc and enable bits */
> -       writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
> -       /* Configure ecc size for BCH */
> -       ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
> -       writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
> -
> -       /* Configure device details for BCH engine */
> -       ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
> -                       (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
> -                       (bch_wrapmode << 8)     | /* wrap mode */
> -                       (dev_width << 7)        | /* bus width */
> -                       (0x0 << 4)              | /* number of sectors */
> -                       (cs <<  1)              | /* ECC CS */
> -                       (0x1));                   /* enable ECC */
> -       writel(ecc_config_val, &gpmc_cfg->ecc_config);
> +
> +       /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
> +       val = (dev_width << 7) | (info->cs << 1) | (0x1);
> +       writel(val, &gpmc_cfg->ecc_config);
>  }
>
>  /*
> @@ -271,6 +237,124 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
>   */
>  static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>                                 uint8_t *ecc_code)
> +{
> +       u32 val;
> +
> +       val = readl(&gpmc_cfg->ecc1_result);
> +       ecc_code[0] = val & 0xFF;
> +       ecc_code[1] = (val >> 16) & 0xFF;
> +       ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
> +
> +       return 0;
> +}
> +
> +/* GPMC ecc engine settings for read */
> +#define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
> +#define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
> +#define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
> +#define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
> +#define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
> +
> +/* GPMC ecc engine settings for write */
> +#define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
> +#define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
> +#define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
> +
> +/**
> + * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
> + * @mtd: MTD device structure
> + * @mode: Read/Write mode
> + *
> + * When using BCH with SW correction (i.e. no ELM), sector size is set
> + * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
> + * for both reading and writing with:
> + * eccsize0 = 0  (no additional protected byte in spare area)
> + * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
> + */
> +static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd,
> +                                                int mode)
> +{
> +       unsigned int bch_type;
> +       unsigned int dev_width, nsectors;
> +       struct nand_chip *chip = mtd_to_nand(mtd);
> +       struct omap_nand_info *info = nand_get_controller_data(chip);
> +       u32 val, wr_mode;
> +       unsigned int ecc_size1, ecc_size0;
> +
> +       /* GPMC configurations for calculating ECC */
> +       switch (info->ecc_scheme) {
> +       case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> +               bch_type = 1;
> +               nsectors = 1;
> +               wr_mode   = BCH_WRAPMODE_6;
> +               ecc_size0 = BCH_ECC_SIZE0;
> +               ecc_size1 = BCH_ECC_SIZE1;
> +               break;
> +       case OMAP_ECC_BCH8_CODE_HW:
> +               bch_type = 1;
> +               nsectors = chip->ecc.steps;
> +               if (mode == NAND_ECC_READ) {
> +                       wr_mode   = BCH_WRAPMODE_1;
> +                       ecc_size0 = BCH8R_ECC_SIZE0;
> +                       ecc_size1 = BCH8R_ECC_SIZE1;
> +               } else {
> +                       wr_mode   = BCH_WRAPMODE_6;
> +                       ecc_size0 = BCH_ECC_SIZE0;
> +                       ecc_size1 = BCH_ECC_SIZE1;
> +               }
> +               break;
> +       case OMAP_ECC_BCH16_CODE_HW:
> +               bch_type = 0x2;
> +               nsectors = chip->ecc.steps;
> +               if (mode == NAND_ECC_READ) {
> +                       wr_mode   = 0x01;
> +                       ecc_size0 = 52; /* ECC bits in nibbles per sector */
> +                       ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
> +               } else {
> +                       wr_mode   = 0x01;
> +                       ecc_size0 = 0;  /* extra bits in nibbles per sector */
> +                       ecc_size1 = 52; /* OOB bits in nibbles per sector */
> +               }
> +               break;
> +       default:
> +               return;
> +       }
> +
> +       writel(ECCRESULTREG1, &gpmc_cfg->ecc_control);
> +
> +       /* Configure ecc size for BCH */
> +       val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
> +       writel(val, &gpmc_cfg->ecc_size_config);
> +
> +       dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
> +
> +       /* BCH configuration */
> +       val = ((1                       << 16) | /* enable BCH */
> +              (bch_type                << 12) | /* BCH4/BCH8/BCH16 */
> +              (wr_mode                 <<  8) | /* wrap mode */
> +              (dev_width               <<  7) | /* bus width */
> +              (((nsectors - 1) & 0x7)  <<  4) | /* number of sectors */
> +              (info->cs                <<  1) | /* ECC CS */
> +              (0x1));                           /* enable ECC */
> +
> +       writel(val, &gpmc_cfg->ecc_config);
> +
> +       /* Clear ecc and enable bits */
> +       writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
> +}
> +
> +/**
> + * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> + * @mtd:        MTD device structure
> + * @dat:        The pointer to data on which ecc is computed
> + * @ecc_code:   The ecc_code buffer
> + * @sector:     The sector number (for a multi sector page)
> + *
> + * Support calculating of BCH4/8/16 ECC vectors for one sector
> + * within a page. Sector number is in @sector.
> + */
> +static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> +                                  u8 *ecc_code, int sector)
>  {
>         struct nand_chip *chip = mtd_to_nand(mtd);
>         struct omap_nand_info *info = nand_get_controller_data(chip);
> @@ -279,17 +363,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>         int8_t i = 0, j;
>
>         switch (info->ecc_scheme) {
> -       case OMAP_ECC_HAM1_CODE_HW:
> -               val = readl(&gpmc_cfg->ecc1_result);
> -               ecc_code[0] = val & 0xFF;
> -               ecc_code[1] = (val >> 16) & 0xFF;
> -               ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
> -               break;
>  #ifdef CONFIG_BCH
>         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
>  #endif
>         case OMAP_ECC_BCH8_CODE_HW:
> -               ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
> +               ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3];
>                 val = readl(ptr);
>                 ecc_code[i++] = (val >>  0) & 0xFF;
>                 ptr--;
> @@ -301,23 +379,24 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>                         ecc_code[i++] = (val >>  0) & 0xFF;
>                         ptr--;
>                 }
> +
>                 break;
>         case OMAP_ECC_BCH16_CODE_HW:
> -               val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
> +               val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]);
>                 ecc_code[i++] = (val >>  8) & 0xFF;
>                 ecc_code[i++] = (val >>  0) & 0xFF;
> -               val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
> +               val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]);
>                 ecc_code[i++] = (val >> 24) & 0xFF;
>                 ecc_code[i++] = (val >> 16) & 0xFF;
>                 ecc_code[i++] = (val >>  8) & 0xFF;
>                 ecc_code[i++] = (val >>  0) & 0xFF;
> -               val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
> +               val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]);
>                 ecc_code[i++] = (val >> 24) & 0xFF;
>                 ecc_code[i++] = (val >> 16) & 0xFF;
>                 ecc_code[i++] = (val >>  8) & 0xFF;
>                 ecc_code[i++] = (val >>  0) & 0xFF;
>                 for (j = 3; j >= 0; j--) {
> -                       val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
> +                       val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j]
>                                                                         );
>                         ecc_code[i++] = (val >> 24) & 0xFF;
>                         ecc_code[i++] = (val >> 16) & 0xFF;
> @@ -330,18 +409,18 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>         }
>         /* ECC scheme specific syndrome customizations */
>         switch (info->ecc_scheme) {
> -       case OMAP_ECC_HAM1_CODE_HW:
> -               break;
>  #ifdef CONFIG_BCH
>         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> -
> +               /* Add constant polynomial to remainder, so that
> +                * ECC of blank pages results in 0x0 on reading back
> +                */
>                 for (i = 0; i < chip->ecc.bytes; i++)
> -                       *(ecc_code + i) = *(ecc_code + i) ^
> -                                               bch8_polynomial[i];
> +                       ecc_code[i] ^= bch8_polynomial[i];
>                 break;
>  #endif
>         case OMAP_ECC_BCH8_CODE_HW:
> -               ecc_code[chip->ecc.bytes - 1] = 0x00;
> +               /* Set 14th ECC byte as 0x0 for ROM compatibility */
> +               ecc_code[chip->ecc.bytes - 1] = 0x0;
>                 break;
>         case OMAP_ECC_BCH16_CODE_HW:
>                 break;
> @@ -351,6 +430,22 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>         return 0;
>  }
>
> +/**
> + * omap_calculate_ecc_bch - ECC generator for 1 sector
> + * @mtd:        MTD device structure
> + * @dat:       The pointer to data on which ecc is computed
> + * @ecc_code:  The ecc_code buffer
> + *
> + * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
> + * when SW based correction is required as ECC is required for one sector
> + * at a time.
> + */
> +static int omap_calculate_ecc_bch(struct mtd_info *mtd,
> +                                 const u_char *dat, u_char *ecc_calc)
> +{
> +       return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0);
> +}
> +
>  static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>  {
>         struct nand_chip *chip = mtd_to_nand(mtd);
> @@ -475,6 +570,35 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>  #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
>
>  #ifdef CONFIG_NAND_OMAP_ELM
> +
> +/**
> + * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
> + * @mtd:       MTD device structure
> + * @dat:       The pointer to data on which ecc is computed
> + * @ecc_code:  The ecc_code buffer
> + *
> + * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
> + */
> +static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
> +                                       const u_char *dat, u_char *ecc_calc)
> +{
> +       struct nand_chip *chip = mtd_to_nand(mtd);
> +       int eccbytes = chip->ecc.bytes;
> +       unsigned long nsectors;
> +       int i, ret;
> +
> +       nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
> +       for (i = 0; i < nsectors; i++) {
> +               ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);
> +               if (ret)
> +                       return ret;
> +
> +               ecc_calc += eccbytes;
> +       }
> +
> +       return 0;
> +}
> +
>  /*
>   * omap_reverse_list - re-orders list elements in reverse order [internal]
>   * @list:      pointer to start of list
> @@ -627,52 +751,49 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
>  {
>         int i, eccsize = chip->ecc.size;
>         int eccbytes = chip->ecc.bytes;
> +       int ecctotal = chip->ecc.total;
>         int eccsteps = chip->ecc.steps;
>         uint8_t *p = buf;
>         uint8_t *ecc_calc = chip->buffers->ecccalc;
>         uint8_t *ecc_code = chip->buffers->ecccode;
>         uint32_t *eccpos = chip->ecc.layout->eccpos;
>         uint8_t *oob = chip->oob_poi;
> -       uint32_t data_pos;
>         uint32_t oob_pos;
>
> -       data_pos = 0;
>         /* oob area start */
>         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
>         oob += chip->ecc.layout->eccpos[0];
>
> -       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
> -                               oob += eccbytes) {
> -               chip->ecc.hwctl(mtd, NAND_ECC_READ);
> -               /* read data */
> -               chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
> -               chip->read_buf(mtd, p, eccsize);
> -
> -               /* read respective ecc from oob area */
> -               chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
> -               chip->read_buf(mtd, oob, eccbytes);
> -               /* read syndrome */
> -               chip->ecc.calculate(mtd, p, &ecc_calc[i]);
> -
> -               data_pos += eccsize;
> -               oob_pos += eccbytes;
> -       }
> +       /* Enable ECC engine */
> +       chip->ecc.hwctl(mtd, NAND_ECC_READ);
> +
> +       /* read entire page */
> +       chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);
> +       chip->read_buf(mtd, buf, mtd->writesize);
> +
> +       /* read all ecc bytes from oob area */
> +       chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
> +       chip->read_buf(mtd, oob, ecctotal);
> +
> +       /* Calculate ecc bytes */
> +       omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc);
>
>         for (i = 0; i < chip->ecc.total; i++)
>                 ecc_code[i] = chip->oob_poi[eccpos[i]];
>
> +       /* error detect & correct */
>         eccsteps = chip->ecc.steps;
>         p = buf;
>
>         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
>                 int stat;
> -
>                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
>                 if (stat < 0)
>                         mtd->ecc_stats.failed++;
>                 else
>                         mtd->ecc_stats.corrected += stat;
>         }
> +
>         return 0;
>  }
>  #endif /* CONFIG_NAND_OMAP_ELM */
> @@ -820,9 +941,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
>                 nand->ecc.strength      = 8;
>                 nand->ecc.size          = SECTOR_BYTES;
>                 nand->ecc.bytes         = 13;
> -               nand->ecc.hwctl         = omap_enable_hwecc;
> +               nand->ecc.hwctl         = omap_enable_hwecc_bch;
>                 nand->ecc.correct       = omap_correct_data_bch_sw;
> -               nand->ecc.calculate     = omap_calculate_ecc;
> +               nand->ecc.calculate     = omap_calculate_ecc_bch;
>                 /* define ecc-layout */
>                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
>                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
> @@ -861,9 +982,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
>                 nand->ecc.strength      = 8;
>                 nand->ecc.size          = SECTOR_BYTES;
>                 nand->ecc.bytes         = 14;
> -               nand->ecc.hwctl         = omap_enable_hwecc;
> +               nand->ecc.hwctl         = omap_enable_hwecc_bch;
>                 nand->ecc.correct       = omap_correct_data_bch;
> -               nand->ecc.calculate     = omap_calculate_ecc;
> +               nand->ecc.calculate     = omap_calculate_ecc_bch;
>                 nand->ecc.read_page     = omap_read_page_bch;
>                 /* define ecc-layout */
>                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
> @@ -894,9 +1015,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
>                 nand->ecc.size          = SECTOR_BYTES;
>                 nand->ecc.bytes         = 26;
>                 nand->ecc.strength      = 16;
> -               nand->ecc.hwctl         = omap_enable_hwecc;
> +               nand->ecc.hwctl         = omap_enable_hwecc_bch;
>                 nand->ecc.correct       = omap_correct_data_bch;
> -               nand->ecc.calculate     = omap_calculate_ecc;
> +               nand->ecc.calculate     = omap_calculate_ecc_bch;
>                 nand->ecc.read_page     = omap_read_page_bch;
>                 /* define ecc-layout */
>                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
> --
> 2.17.1
>


--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 08/14] mtd: rawnand: omap_gpmc: Reduce .bss usage

[Michael Nazzareno Trimarchi]

Hi

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Allocate omap_ecclayout on the heap as we have
> limited .bss space on AM64 R5 SPL configuration.
>
> Reduces .bss usage by 2984 bytes.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/omap_gpmc.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> index b5ad66ad49..e772a914c8 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -40,7 +40,6 @@ static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
>                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
>  #endif
>  static uint8_t cs_next;
> -static __maybe_unused struct nand_ecclayout omap_ecclayout;
>
>  #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
>  static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
> @@ -874,7 +873,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
>  static int omap_select_ecc_scheme(struct nand_chip *nand,
>         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
>         struct omap_nand_info   *info           = nand_get_controller_data(nand);
> -       struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
> +       struct nand_ecclayout   *ecclayout      = nand->ecc.layout;
>         int eccsteps = pagesize / SECTOR_BYTES;
>         int i;
>
> @@ -1167,7 +1166,9 @@ int board_nand_init(struct nand_chip *nand)
>         nand->cmd_ctrl  = omap_nand_hwcontrol;
>         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
>         nand->chip_delay = 100;
> -       nand->ecc.layout = &omap_ecclayout;
> +       nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL);
> +       if (!nand->ecc.layout)
> +               return -ENOMEM;
>
>         /* configure driver and controller based on NAND device bus-width */
>         gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
> --
> 2.17.1
>

Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>


-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 06/14] mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt

[Michael Nazzareno Trimarchi]

Hi

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> nand_bbt.c is not being built with the nand_base driver during SPL
> build. This results in build failures if we try to access any nand_bbt
> related functions.
>
> Don't use any nand_bbt functions for SPL build.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/nand_base.c | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
> index 4b09a11288..826ae633ce 100644
> --- a/drivers/mtd/nand/raw/nand_base.c
> +++ b/drivers/mtd/nand/raw/nand_base.c
> @@ -447,7 +447,10 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
>  static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
>  {
>         struct nand_chip *chip = mtd_to_nand(mtd);
> -       int res, ret = 0;
> +       int ret = 0;
> +#ifndef CONFIG_SPL_BUILD
> +       int res;
> +#endif
>
>         if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
>                 struct erase_info einfo;
> @@ -465,12 +468,14 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
>                 nand_release_device(mtd);
>         }
>
> +#ifndef CONFIG_SPL_BUILD
>         /* Mark block bad in BBT */
>         if (chip->bbt) {
>                 res = nand_markbad_bbt(mtd, ofs);
>                 if (!ret)
>                         ret = res;
>         }
> +#endif
>
>         if (!ret)
>                 mtd->ecc_stats.badblocks++;
> @@ -517,7 +522,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
>         if (!chip->bbt)
>                 return 0;
>         /* Return info from the table */
> +#ifndef CONFIG_SPL_BUILD
>         return nand_isreserved_bbt(mtd, ofs);
> +#else
> +       return 0;
> +#endif
>  }
>
>  /**
> @@ -543,7 +552,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
>                 return chip->block_bad(mtd, ofs);
>
>         /* Return info from the table */
> +#ifndef CONFIG_SPL_BUILD
>         return nand_isbad_bbt(mtd, ofs, allowbbt);
> +#else
> +       return 0;
> +#endif
>  }

Can you please send me the config that let this fail?

Michael
>
>  /**
> @@ -3752,8 +3765,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
>                 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
>         if (!chip->read_buf || chip->read_buf == nand_read_buf)
>                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
> +
> +#ifndef CONFIG_SPL_BUILD
>         if (!chip->scan_bbt)
>                 chip->scan_bbt = nand_default_bbt;
> +#endif
>
>         if (!chip->controller) {
>                 chip->controller = &chip->hwcontrol;
> --
> 2.17.1
>


-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 06/14] mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt

[Roger Quadros]

[-- Attachment #1: Type: text/plain, Size: 3247 bytes --]

Hi Michael,

On 28/11/2022 16:27, Michael Nazzareno Trimarchi wrote:
> Hi
> 
> On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>>
>> nand_bbt.c is not being built with the nand_base driver during SPL
>> build. This results in build failures if we try to access any nand_bbt
>> related functions.
>>
>> Don't use any nand_bbt functions for SPL build.
>>
>> Signed-off-by: Roger Quadros <rogerq@kernel.org>
>> ---
>>  drivers/mtd/nand/raw/nand_base.c | 18 +++++++++++++++++-
>>  1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
>> index 4b09a11288..826ae633ce 100644
>> --- a/drivers/mtd/nand/raw/nand_base.c
>> +++ b/drivers/mtd/nand/raw/nand_base.c
>> @@ -447,7 +447,10 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
>>  static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
>>  {
>>         struct nand_chip *chip = mtd_to_nand(mtd);
>> -       int res, ret = 0;
>> +       int ret = 0;
>> +#ifndef CONFIG_SPL_BUILD
>> +       int res;
>> +#endif
>>
>>         if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
>>                 struct erase_info einfo;
>> @@ -465,12 +468,14 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
>>                 nand_release_device(mtd);
>>         }
>>
>> +#ifndef CONFIG_SPL_BUILD
>>         /* Mark block bad in BBT */
>>         if (chip->bbt) {
>>                 res = nand_markbad_bbt(mtd, ofs);
>>                 if (!ret)
>>                         ret = res;
>>         }
>> +#endif
>>
>>         if (!ret)
>>                 mtd->ecc_stats.badblocks++;
>> @@ -517,7 +522,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
>>         if (!chip->bbt)
>>                 return 0;
>>         /* Return info from the table */
>> +#ifndef CONFIG_SPL_BUILD
>>         return nand_isreserved_bbt(mtd, ofs);
>> +#else
>> +       return 0;
>> +#endif
>>  }
>>
>>  /**
>> @@ -543,7 +552,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
>>                 return chip->block_bad(mtd, ofs);
>>
>>         /* Return info from the table */
>> +#ifndef CONFIG_SPL_BUILD
>>         return nand_isbad_bbt(mtd, ofs, allowbbt);
>> +#else
>> +       return 0;
>> +#endif
>>  }
> 
> Can you please send me the config that let this fail?

I've pushed a test branch here where relevant changes are done to am64x_evm_a53_defconfig
https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-test

Attaching the resulting spl/u-boot.cfg that causes the failure

> 
> Michael
>>
>>  /**
>> @@ -3752,8 +3765,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
>>                 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
>>         if (!chip->read_buf || chip->read_buf == nand_read_buf)
>>                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
>> +
>> +#ifndef CONFIG_SPL_BUILD
>>         if (!chip->scan_bbt)
>>                 chip->scan_bbt = nand_default_bbt;
>> +#endif
>>
>>         if (!chip->controller) {
>>                 chip->controller = &chip->hwcontrol;
>> --
>> 2.17.1
>>
> 
> 

--
cheers,
-roger

[-- Attachment #2: u-boot.cfg --]
[-- Type: text/plain, Size: 20775 bytes --]

#define CONFIG_CMD_MTD 1
#define CONFIG_ETH 1
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FIT_SOURCE ""
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x280000
#define CONFIG_CMD_FAT 1
#define CONFIG_TI_K3_PSIL 1
#define CONFIG_SPL_DM_SERIAL 1
#define CONFIG_TOOLS_SHA1 1
#define CONFIG_EFI_DEVICE_PATH_UTIL 1
#define CONFIG_BOOTM_NETBSD 1
#define CONFIG_OF_SPL_REMOVE_PROPS "interrupt-parent interrupts"
#define CONFIG_CMD_FDT 1
#define CONFIG_SPL_DFU 1
#define CONFIG_OMAP_SERIAL 1
#define CONFIG_NAND_OMAP_GPMC 1
#define CONFIG_USB_GADGET_DOWNLOAD 1
#define CONFIG_SYS_CLK_FREQ 0
#define CONFIG_BOOTMETH_VBE_SIMPLE 1
#define CONFIG_CMD_ITEST 1
#define CONFIG_SPL_POWER_DOMAIN 1
#define CONFIG_REMOTEPROC_TI_K3_ARM64 1
#define CONFIG_BOOTM_VXWORKS 1
#define CONFIG_ERR_PTR_OFFSET 0x0
#define CONFIG_CMD_EDITENV 1
#define CONFIG_OF_OVERLAY_LIST ""
#define CONFIG_SPL_SPRINTF 1
#define CONFIG_SPL_DMA 1
#define CONFIG_CMD_MTDPARTS 1
#define CONFIG_EFI_PLATFORM_LANG_CODES "en-US"
#define CONFIG_SPL_NAND_SUPPORT 1
#define CONFIG_ARM_PSCI_FW 1
#define CONFIG_CMD_SETEXPR 1
#define CONFIG_TOOLS_SHA384 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_TOOLS_OF_LIBFDT 1
#define CONFIG_CMD_BOOTP 1
#define CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION 1
#define CONFIG_SYS_MEM_TOP_HIDE 0x0
#define CONFIG_CMD_PART 1
#define CONFIG_MISC 1
#define CONFIG_DFU_OVER_USB 1
#define CONFIG_ENV_SUPPORT 1
#define CONFIG_SPL_LOGLEVEL 4
#define CONFIG_CMD_ENV_EXISTS 1
#define CONFIG_SF_DEFAULT_MODE 0x0
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_SYS_NAND_5_ADDR_CYCLE 
#define CONFIG_GCC_VERSION 90201
#define CONFIG_DM_MAILBOX 1
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_HASH 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_CMD_XIMG 1
#define CONFIG_EXPERT 1
#define CONFIG_PXE_UTILS 1
#define CONFIG_CMDLINE 1
#define CONFIG_SYS_SPL_MALLOC 1
#define CONFIG_BOOTDELAY 2
#define CONFIG_SYS_NAND_BASE 0x51000000
#define CONFIG_SPL_SYS_NAND_SELF_INIT 1
#define CONFIG_CMD_BOOTEFI 1
#define CONFIG_SPI_FLASH 1
#define CONFIG_BOOTP_BOOTPATH 1
#define CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY 1
#define CONFIG_SPL_CLK_CCF 1
#define CONFIG_SPL_FS_FAT 1
#define CONFIG_SPL_SPI 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_EFI_PARTITION 1
#define CONFIG_DM_PMIC 1
#define CONFIG_SPL_BSS_LIMIT 1
#define CONFIG_SPL_DM_I2C 1
#define CONFIG_SPL_SEPARATE_BSS 1
#define CONFIG_FS_FAT 1
#define CONFIG_BOOTM_RTEMS 1
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT 1
#define CONFIG_CMD_UBI 1
#define CONFIG_DM_I2C 1
#define CONFIG_SYS_NAND_ONFI_DETECTION 1
#define CONFIG_MD5 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1400
#define CONFIG_BOOTM_LINUX 1
#define CONFIG_SPL_NAND_BASE 1
#define CONFIG_BOARD_LATE_INIT 1
#define CONFIG_MULTI_DTB_FIT_NO_COMPRESSION 1
#define CONFIG_CREATE_ARCH_SYMLINK 1
#define CONFIG_CMD_CONSOLE 1
#define CONFIG_SUPPORT_OF_CONTROL 1
#define CONFIG_SPL_STRTO 1
#define CONFIG_PINCTRL_FULL 1
#define CONFIG_BLK 1
#define CONFIG_SYS_CPU "armv8"
#define CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR 1
#define CONFIG_SPL_BOARD_INIT 1
#define CONFIG_SPL_STACK_R_ADDR 0x82000000
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x16
#define CONFIG_SPL_YMODEM_SUPPORT 1
#define CONFIG_BOOTP_GATEWAY 1
#define CONFIG_SPL_NAND_INIT 1
#define CONFIG_SUPPORT_ACPI 1
#define CONFIG_SYS_K3_BOOT_CORE_ID 16
#define CONFIG_PINCTRL 1
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MMC 1
#define CONFIG_DM_ETH 1
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x800000
#define CONFIG_SPL_OF_CONTROL 1
#define CONFIG_MTD_PARTITIONS 1
#define CONFIG_BOOTMETH_GLOBAL 1
#define CONFIG_NFS_TIMEOUT 2000
#define CONFIG_CMD_PINMUX 1
#define CONFIG_SYS_ARM_CACHE_WRITEBACK 1
#define CONFIG_CLK_TI_SCI 1
#define CONFIG_TOOLS_MD5 1
#define CONFIG_ARM_SMCCC 1
#define CONFIG_SYS_XTRACE 1
#define CONFIG_FIT 1
#define CONFIG_MTD 1
#define CONFIG_TI_I2C_BOARD_DETECT 1
#define CONFIG_SPL_LIBCOMMON_SUPPORT 1
#define CONFIG_TOOLS_FIT_SIGNATURE 1
#define CONFIG_SYS_DFU_MAX_FILE_SIZE 0x800000
#define CONFIG_MISC_INIT_R 1
#define CONFIG_ENV_OFFSET 0x680000
#define CONFIG_DISTRO_DEFAULTS 1
#define CONFIG_DM_DEVICE_REMOVE 1
#define CONFIG_SOC_K3_AM642 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_USB_CDNS3_HOST 1
#define CONFIG_MMC_WRITE 1
#define CONFIG_SYS_SRAM_BASE 0x0
#define CONFIG_CMD_NET 1
#define CONFIG_SPL_SIZE_LIMIT 0x0
#define CONFIG_CMD_LZMADEC 1
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_NFS 1
#define CONFIG_DFU_SF 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_TOOLS_CRC32 1
#define CONFIG_VPL_LZMA 1
#define CONFIG_SUPPORT_RAW_INITRD 1
#define CONFIG_NAND_OMAP_GPMC_PREFETCH 1
#define CONFIG_K3_SEC_PROXY 1
#define CONFIG_CMD_FS_GENERIC 1
#define CONFIG_CMD_PING 1
#define CONFIG_SPL_GPIO 1
#define CONFIG_SPL_BUILD 1
#define CONFIG_SPL_PARTITIONS 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET 0x0
#define CONFIG_SPL_MMC_SDHCI_ADMA 1
#define CONFIG_SPL_DM_GPIO 1
#define CONFIG_SYS_MALLOC_LEN 0x2000000
#define CONFIG_EFI_VARIABLE_FILE_STORE 1
#define CONFIG_ARCH_K3 1
#define CONFIG_EFI_VAR_BUF_SIZE 16384
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS 100
#define CONFIG_MUX_MMIO 1
#define CONFIG_SPL_LIBDISK_SUPPORT 1
#define CONFIG_SPI_FLASH_SPANSION 1
#define CONFIG_SPL_PINCONF_RECURSIVE 1
#define CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX 0x701bebfc
#define CONFIG_LOCALVERSION ""
#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
#define CONFIG_CUSTOM_SYS_INIT_SP_ADDR 0x80480000
#define CONFIG_SYS_BOOTM_LEN 0x800000
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_ARCH_SUPPORTS_LTO 1
#define CONFIG_CC_OPTIMIZE_FOR_SIZE 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 1
#define CONFIG_SPL_MMC_HS400_SUPPORT 1
#define CONFIG_TFTP_WINDOWSIZE 1
#define CONFIG_REGEX 1
#define CONFIG_EFI_PARTITION_ENTRIES_NUMBERS 128
#define CONFIG_SYS_CONFIG_NAME "am64x_evm"
#define CONFIG_MMC_SDHCI 1
#define CONFIG_TOOLS_FIT 1
#define CONFIG_SPL_SYS_MALLOC_SIMPLE 1
#define CONFIG_SYS_NAND_OOBSIZE 0x100
#define CONFIG_CMD_FLASH 1
#define CONFIG_USB_FUNCTION_MASS_STORAGE 1
#define CONFIG_SPL_SHA1 1
#define CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE 0x10000000
#define CONFIG_CMD_SAVEENV 1
#define CONFIG_PMIC_CHILDREN 1
#define CONFIG_MKIMAGE_DTC_PATH "dtc"
#define CONFIG_SPL_I2C 1
#define CONFIG_SPL_RAM_SUPPORT 1
#define CONFIG_OF_REAL 1
#define CONFIG_BOOTM_PLAN9 1
#define CONFIG_MULTI_DTB_FIT 1
#define CONFIG_SPL_TEXT_BASE 0x80080000
#define CONFIG_SPL_PHY 1
#define CONFIG_SYSRESET_TI_SCI 1
#define CONFIG_SPL_DM_MMC 1
#define CONFIG_DFU_SF_PART 1
#define CONFIG_K3_X509_SWRV 1
#define CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2 1
#define CONFIG_SERIAL_PRESENT 1
#define CONFIG_TOOLS_FIT_PRINT 1
#define CONFIG_SYS_NAND_PAGE_COUNT 0x40
#define CONFIG_SPL_PINCTRL_FULL 1
#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x2000000
#define CONFIG_DM_MMC 1
#define CONFIG_SPL_NAND_DRIVERS 1
#define CONFIG_CMD_NAND 1
#define CONFIG_SPL_EFI_PARTITION 1
#define CONFIG_TARGET_AM642_A53_EVM 1
#define CONFIG_LZMA 1
#define CONFIG_BUILD_TARGET ""
#define CONFIG_OF_LIST "k3-am642-evm k3-am642-sk"
#define CONFIG_CMD_GPT 1
#define CONFIG_SPL_SHARES_INIT_SP_ADDR 1
#define CONFIG_PHY_FIXED 1
#define CONFIG_PHY_TI_DP83867 1
#define CONFIG_SPL_ETH 1
#define CONFIG_SPL_CRC32 1
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_DM_DEV_READ_INLINE 1
#define CONFIG_DM_MTD 1
#define CONFIG_PHY_J721E_WIZ 1
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_DM_WARN 1
#define CONFIG_EFI_ECPT 1
#define CONFIG_BOOTP_DNS 1
#define CONFIG_TOOLS_FIT_FULL_CHECK 1
#define CONFIG_CMD_MEMORY 1
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_MMC_SDHCI_AM654 1
#define CONFIG_SYSRESET 1
#define CONFIG_DM_USB_GADGET 1
#define CONFIG_MMC_HW_PARTITIONING 1
#define CONFIG_SPL_MTD_SUPPORT 1
#define CONFIG_SUPPORT_SPL 1
#define CONFIG_CMD_RUN 1
#define CONFIG_LMB_USE_MAX_REGIONS 1
#define CONFIG_SYS_PBSIZE 1044
#define CONFIG_ENV_VARS_UBOOT_CONFIG 1
#define CONFIG_SPL_SYS_STACK_F_CHECK_BYTE 0xaa
#define CONFIG_CMD_CRC32 1
#define CONFIG_DM_SPI_FLASH 1
#define CONFIG_USB 1
#define CONFIG_USB_CDNS3_GADGET 1
#define CONFIG_BOOTP_HOSTNAME 1
#define CONFIG_CMD_SLEEP 1
#define CONFIG_LMB_MAX_REGIONS 8
#define CONFIG_BOARDDIR board/ti/am64x
#define CONFIG_SPL_DFU_RAM 1
#define CONFIG_POWER 1
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x81000000
#define CONFIG_DM_RESET 1
#define CONFIG_TI_GPMC 1
#define CONFIG_ENV_MIN_ENTRIES 64
#define CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ 0x10000
#define CONFIG_NET 1
#define CONFIG_BLOCK_CACHE 1
#define CONFIG_REMOTEPROC 1
#define CONFIG_SPI_FLASH_STMICRO 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_TFTP_BLOCKSIZE 1468
#define CONFIG_PSCI_RESET 1
#define CONFIG_MMC_HS200_SUPPORT 1
#define CONFIG_CLK 1
#define CONFIG_TI_SCI_POWER_DOMAIN 1
#define CONFIG_PHYLIB 1
#define CONFIG_GENERATE_SMBIOS_TABLE 1
#define CONFIG_SPL_DRIVERS_MISC 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_CMD_USB 1
#define CONFIG_SPL_TARGET ""
#define CONFIG_DM_SERIAL 1
#define CONFIG_PHYS_64BIT 1
#define CONFIG_PHY_CADENCE_TORRENT 1
#define CONFIG_PHY 1
#define CONFIG_CMD_EXT2 1
#define CONFIG_CMD_EXT4 1
#define CONFIG_BOOTCOMMAND "run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
#define CONFIG_ARCH_FIXUP_FDT_MEMORY 1
#define CONFIG_USB_GADGET_VENDOR_NUM 0x0451
#define CONFIG_SPL_USB_GADGET 1
#define CONFIG_SPL_SIMPLE_BUS 1
#define CONFIG_EFI_DT_FIXUP 1
#define CONFIG_SOC_DEVICE_TI_K3 1
#define CONFIG_SOC_DEVICE 1
#define CONFIG_ISO_PARTITION 1
#define CONFIG_ARM64_CRC32 1
#define CONFIG_NET_RETRY_COUNT 5
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x600000
#define CONFIG_CMD_RANDOM 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_BOOT_RAMDISK_HIGH 1
#define CONFIG_CMD_DFU 1
#define CONFIG_EEPROM_BUS_ADDRESS 0
#define CONFIG_CMD_BOOTEFI_HELLO_COMPILE 1
#define CONFIG_CAAM_64BIT 1
#define CONFIG_HUSH_PARSER 1
#define CONFIG_DEFAULT_FDT_FILE ""
#define CONFIG_CMD_DM 1
#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8"
#define CONFIG_DM 1
#define CONFIG_PMIC_TPS65219 1
#define CONFIG_EFI_EBBR_2_0_CONFORMANCE 1
#define CONFIG_ZLIB 1
#define CONFIG_OF_LIBFDT_ASSUME_MASK 0x0
#define CONFIG_USB_GADGET_DUALSPEED 1
#define CONFIG_LIB_UUID 1
#define CONFIG_SYS_I2C_OMAP24XX 1
#define CONFIG_CMD_GO 1
#define CONFIG_SPL_BLK 1
#define CONFIG_SDP_LOADADDR 0x0
#define CONFIG_USB_HOST 1
#define CONFIG_CMD_BOOTD 1
#define CONFIG_CMD_BOOTI 1
#define CONFIG_CMD_BOOTM 1
#define CONFIG_EFI_LOADER_HII 1
#define CONFIG_SPL_SPI_FLASH_SUPPORT 1
#define CONFIG_SYS_NS16550 1
#define CONFIG_SPL_MISC 1
#define CONFIG_SYS_MALLOC_F 1
#define CONFIG_CADENCE_QSPI 1
#define CONFIG_SYS_SRAM_SIZE 0x0
#define CONFIG_CMD_BOOTFLOW 1
#define CONFIG_SPL_MMC 1
#define CONFIG_SYS_RX_ETH_BUFFER 4
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_EFI_LOAD_FILE2_INITRD 1
#define CONFIG_SPI_FLASH_USE_4K_SECTORS 1
#define CONFIG_SPL_SPI_FLASH_TINY 1
#define CONFIG_SPRINTF 1
#define CONFIG_DM_REGULATOR 1
#define CONFIG_CMD_SYSBOOT 1
#define CONFIG_SYS_SOC "k3"
#define CONFIG_SPL_PMIC_CHILDREN 1
#define CONFIG_SPL_HASH 1
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MALLOC_F_LEN 0x8000
#define CONFIG_BOOTMETH_DISTRO 1
#define CONFIG_SPL_MULTI_DTB_FIT 1
#define CONFIG_SPL_DM_USB 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_USB_CDNS3 1
#define CONFIG_GZIP 1
#define CONFIG_SYS_VENDOR "ti"
#define CONFIG_DFU_MMC 1
#define CONFIG_CLANG_VERSION 0
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x40000
#define CONFIG_IMX_DCD_ADDR 0x00910000
#define CONFIG_DM_USB 1
#define CONFIG_CMD_SF 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 0
#define CONFIG_REQUIRE_SERIAL_CONSOLE 1
#define CONFIG_TOOLS_LIBCRYPTO 1
#define CONFIG_SYS_NAND_SELF_INIT 1
#define CONFIG_IDENT_STRING ""
#define CONFIG_SYSRESET_CMD_RESET 1
#define CONFIG_SPL_DM_SPI_FLASH 1
#define CONFIG_SPL_PRINTF 1
#define CONFIG_MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define CONFIG_ENV_SOURCE_FILE ""
#define CONFIG_PRINTF 1
#define CONFIG_PINCTRL_GENERIC 1
#define CONFIG_SPL_SERIAL 1
#define CONFIG_TOOLS_SHA512 1
#define CONFIG_MMC_SDHCI_ADMA 1
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPL_DM_MAILBOX 1
#define CONFIG_SERIAL 1
#define CONFIG_PINCTRL_SINGLE 1
#define CONFIG_SPL_FIT 1
#define CONFIG_CLK_CCF 1
#define CONFIG_PHY_RESET_DELAY 0
#define CONFIG_SPL_LIBGENERIC_SUPPORT 1
#define CONFIG_SPL_SYSRESET 1
#define CONFIG_LOCALVERSION_AUTO 1
#define CONFIG_SPL_DM_USB_GADGET 1
#define CONFIG_CMD_TFTPBOOT 1
#define CONFIG_SUPPORT_EMMC_BOOT 1
#define CONFIG_SOC_TI 1
#define CONFIG_SPL_USB_STORAGE 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_MMC_VERBOSE 1
#define CONFIG_BOOTSTD 1
#define CONFIG_COUNTER_FREQUENCY 0
#define CONFIG_EFI_SETUP_EARLY 1
#define CONFIG_TI_AM65_CPSW_NUSS 1
#define CONFIG_DM_EVENT 1
#define CONFIG_NET_TFTP_VARS 1
#define CONFIG_K3_SYSTEM_CONTROLLER 1
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_STACK_SIZE 0x1000000
#define CONFIG_SPL_DFU_NO_RESET 1
#define CONFIG_CC_IS_GCC 1
#define CONFIG_K3_ATF_LOAD_ADDR 0x701c0000
#define CONFIG_CMD_DHCP 1
#define CONFIG_SPL_PINCTRL_GENERIC 1
#define CONFIG_LEGACY_IMAGE_FORMAT 1
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SPL_DM_PMIC 1
#define CONFIG_CMD_ECHO 1
#define CONFIG_TOOLS_FIT_RSASSA_PSS 1
#define CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE 0x1c0000
#define CONFIG_SPL_REGMAP 1
#define CONFIG_DMA_CHANNELS 1
#define CONFIG_SPL_SPI_LOAD 1
#define CONFIG_STRTO 1
#define CONFIG_REGMAP 1
#define CONFIG_PLATFORM_ELFENTRY "_start"
#define CONFIG_FAT_WRITE 1
#define CONFIG_SYS_CACHE_SHIFT_6 1
#define CONFIG_SYS_FDT_PAD 0x3000
#define CONFIG_SPL_IMAGE "spl/u-boot-spl.bin"
#define CONFIG_CMD_TIME 1
#define CONFIG_SPL_FIT_GENERATOR ""
#define CONFIG_CMD_PMIC 1
#define CONFIG_DFU 1
#define CONFIG_SPL_DM 1
#define CONFIG_PHY_TI 1
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_CHARSET 1
#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
#define CONFIG_SPL_PAD_TO 0x180000
#define CONFIG_FIT_PRINT 1
#define CONFIG_LINKER_LIST_ALIGN 8
#define CONFIG_OF_CONTROL 1
#define CONFIG_EXTRA_ENV_SETTINGS DEFAULT_LINUX_BOOT_ENV DEFAULT_MMC_TI_ARGS EXTRA_ENV_AM642_BOARD_SETTINGS EXTRA_ENV_AM642_BOARD_SETTINGS_MMC EXTRA_ENV_DFUARGS EXTRA_ENV_AM642_BOARD_SETTING_USBMSC EXTRA_ENV_AM642_BOARD_SETTINGS_NAND
#define CONFIG_EFI_PARTITION_ENTRIES_OFF 0
#define CONFIG_SPL_OF_LIBFDT_ASSUME_MASK 0xff
#define CONFIG_SPL_PINCTRL 1
#define CONFIG_BOOTP_PXE 1
#define CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE 0x180000
#define CONFIG_INPUT 1
#define CONFIG_MTD_UBI 1
#define CONFIG_SPL_USE_TINY_PRINTF 1
#define CONFIG_DMA 1
#define CONFIG_FIT_EXTERNAL_OFFSET 0x0
#define CONFIG_SPI_MEM 1
#define CONFIG_TFTP_TSIZE 1
#define CONFIG_BOOTSTAGE_STASH_SIZE 0x1000
#define CONFIG_SYS_ARCH "arm"
#define CONFIG_NAND_OMAP_ECCSCHEME 6
#define CONFIG_CMD_ASKENV 1
#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
#define CONFIG_SPL_PARTITION_UUIDS 1
#define CONFIG_SYS_BOARD "am64x"
#define CONFIG_SPL_USB_HOST 1
#define CONFIG_SPL_USB_CDNS3_GADGET 1
#define CONFIG_PARTITION_UUIDS 1
#define CONFIG_DM_GPIO 1
#define CONFIG_MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:2m(NAND.tiboot3),2m(NAND.tispl),2m(NAND.tiboot3.backup),4m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup),-(NAND.file-system)"
#define CONFIG_CMD_UNZIP 1
#define CONFIG_BOOTMETH_DISTRO_PXE 1
#define CONFIG_SPL_NAND_ECC 1
#define CONFIG_DEVICE_TREE_INCLUDES ""
#define CONFIG_FIRMWARE 1
#define CONFIG_SYS_ARM_ARCH 8
#define CONFIG_NET_RANDOM_ETHADDR 1
#define CONFIG_MTD_UBI_BEB_LIMIT 20
#define CONFIG_OF_LIBFDT_OVERLAY 1
#define CONFIG_SPL_PINMUX 1
#define CONFIG_SYS_K3_KEY ""
#define CONFIG_ARM64_SUPPORT_AARCH32 1
#define CONFIG_CMD_IMPORTENV 1
#define CONFIG_MMC_QUIRKS 1
#define CONFIG_PINMUX 1
#define CONFIG_SPL_ENV_IS_IN_MMC 1
#define CONFIG_IMX_CONTAINER_CFG ""
#define CONFIG_CMD_EXPORTENV 1
#define CONFIG_PARTITIONS 1
#define CONFIG_SPL_NET 1
#define CONFIG_SPL_DOS_PARTITION 1
#define CONFIG_ARM64 1
#define CONFIG_OF_TRANSLATE 1
#define CONFIG_SPL_STACK_R 1
#define CONFIG_CMD_I2C 1
#define CONFIG_TOOLS_SHA256 1
#define CONFIG_CMD_UBIFS 1
#define CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ 0x8000
#define CONFIG_SPI_FLASH_SMART_HWCAPS 1
#define CONFIG_SPL_CLK 1
#define CONFIG_SYS_MMC_ENV_PART 1
#define CONFIG_SPL_NET_VCI_STRING "AM64X U-Boot A53 SPL"
#define CONFIG_CMD_ELF 1
#define CONFIG_CMD_MDIO 1
#define CONFIG_NAND_OMAP_ELM 1
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
#define CONFIG_BOOTP_MAX_ROOT_PATH_LEN 64
#define CONFIG_EFI_LOADER 1
#define CONFIG_TI_K3_NAVSS_UDMA 1
#define CONFIG_DM_MEMORY 1
#define CONFIG_USB_CDNS3_TI 1
#define CONFIG_RANDOM_UUID 1
#define CONFIG_CMD_BOOTEFI_BOOTMGR 1
#define CONFIG_ARP_TIMEOUT 5000
#define CONFIG_DM_SEQ_ALIAS 1
#define CONFIG_RESET_TI_SCI 1
#define CONFIG_GPIO 1
#define CONFIG_EVENT_DYNAMIC 1
#define CONFIG_EVENT 1
#define CONFIG_FS_EXT4 1
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_MAX_SIZE 0x180000
#define CONFIG_SPL_FRAMEWORK 1
#define CONFIG_SPL_HAS_BSS_LINKER_SECTION 1
#define CONFIG_MTD_RAW_NAND 1
#define CONFIG_BOOTSTAGE_STASH_ADDR 0x0
#define CONFIG_SPI 1
#define CONFIG_EFI_DEVICE_PATH_TO_TEXT 1
#define CONFIG_SPL 1
#define CONFIG_BOOTM_EFI 1
#define CONFIG_SPL_NAND_IDENT 1
#define CONFIG_SPL_ENV_SUPPORT 1
#define CONFIG_MULTIPLEXER 1
#define CONFIG_CMD_SOURCE 1
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_TI_K3_NAVSS_RINGACC 1
#define CONFIG_MMC_SDHCI_ADMA_HELPERS 1
#define CONFIG_SPL_RAM_DEVICE 1
#define CONFIG_TI_SCI_PROTOCOL 1
#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1
#define CONFIG_USB_STORAGE 1
#define CONFIG_SPL_OF_REAL 1
#define CONFIG_CMD_PXE 1
#define CONFIG_SPL_MMC_HS200_SUPPORT 1
#define CONFIG_CMD_REGULATOR 1
#define CONFIG_PINCONF_RECURSIVE 1
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_LOGLEVEL 4
#define CONFIG_POWER_DOMAIN 1
#define CONFIG_BOOTDEV_ETH 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SHA1 1
#define CONFIG_SAVEENV 1
#define CONFIG_CRC32 1
#define CONFIG_MMC_HS400_SUPPORT 1
#define CONFIG_DFU_RAM 1
#define CONFIG_SPL_DM_INLINE_OFNODE 1
#define CONFIG_SPL_SYS_MALLOC_F_LEN 0x8000
#define CONFIG_SPL_OF_LIST "k3-am642-evm k3-am642-sk"
#define CONFIG_CMD_LOADB 1
#define CONFIG_HAVE_SYS_TEXT_BASE 1
#define CONFIG_CMD_LOADS 1
#define CONFIG_FS_FAT_MAX_CLUSTSIZE 16384
#define CONFIG_USE_BOOTCOMMAND 1
#define CONFIG_CMD_IMI 1
#define CONFIG_TOOLS_FIT_VERBOSE 1
#define CONFIG_DM_REGULATOR_TPS65219 1
#define CONFIG_SPL_SYSCON 1
#define CONFIG_SPL_PAYLOAD "u-boot.bin"
#define CONFIG_SPL_USB_CDNS3_HOST 1
#define CONFIG_SPL_POWER 1
#define CONFIG_BOOTMETH_EFILOADER 1
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SYSCON 1
#define CONFIG_EFI_HAVE_RUNTIME_RESET 1
#define CONFIG_LMB 1
#define CONFIG_AUTOBOOT 1
#define CONFIG_SPL_BANNER_PRINT 1
#define CONFIG_ARM 1
#define CONFIG_RBTREE 1
#define CONFIG_HAVE_BLOCK_DEVICE 1
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
#define CONFIG_EFI_UNICODE_CAPITALIZATION 1
#define CONFIG_USB_XHCI_HCD 1
#define CONFIG_CMD_BLOCK_CACHE 1
#define CONFIG_OF_SEPARATE 1
#define CONFIG_CMD_BDI 1
#define CONFIG_STATIC_RELA 1
#define CONFIG_SPL_SHA256 1
#define CONFIG_SHA256 1
#define CONFIG_BOOTP_SUBNETMASK 1
#define CONFIG_CC_HAS_ASM_INLINE 1
#define CONFIG_SPL_OF_TRANSLATE 1
#define CONFIG_LZ4 1
#define CONFIG_LIB_ELF 1
#define CONFIG_LZO 1
#define CONFIG_SPL_FIRMWARE 1
#define CONFIG_ENV_MAX_ENTRIES 512
#define CONFIG_MENU 1
#define CONFIG_NETDEVICES 1
#define CONFIG_DEFAULT_DEVICE_TREE "k3-am642-evm"
#define CONFIG_SPL_RAW_IMAGE_SUPPORT 1
#define CONFIG_CMD_UNLZ4 1
#define CONFIG_USB_GADGET_MANUFACTURER "Texas Instruments"
#define CONFIG_CMD_MII 1
#define CONFIG_USB_GADGET 1
#define CONFIG_I2C 1
#define CONFIG_LIB_RAND 1
#define CONFIG_SIMPLE_BUS 1
#define CONFIG_USB_GADGET_PRODUCT_NUM 0x6165
#define CONFIG_ARM_ASM_UNIFIED 1
#define CONFIG_CMD_MMC 1
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_ARCH_TIMER 1
#define CONFIG_DMA_ADDR_T_64BIT 1
#define CONFIG_SPL_DM_SPI 1
#define CONFIG_SPL_DM_SEQ_ALIAS 1
#define CONFIG_FIT_FULL_CHECK 1
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_BOOTMETH_VBE 1
#define CONFIG_SPI_FLASH_UNLOCK_ALL 1
#define CONFIG_DM_SPI 1
#define CONFIG_SPL_OF_LIBFDT 1
#define CONFIG_SPL_LOAD_FIT 1
#define CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW 1
#define CONFIG_USE_SPL_FIT_GENERATOR 1
#define CONFIG_SPL_SERIAL_PRESENT 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"

Re: [u-boot][PATCH 05/14] mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction

[Dario Binacchi]

Hi Roger,

On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> The BCH detection hardware can generate ECC bytes for multiple
> sectors in one go. Use that feature.
>
> correct() only corrects one sector at a time so we need to call it
> repeatedly for each sector.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/mtd/nand/raw/omap_gpmc.c | 325 +++++++++++++++++++++----------
>  1 file changed, 223 insertions(+), 102 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> index b36fe762b3..b5ad66ad49 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -27,6 +27,9 @@
>
>  #define BADBLOCK_MARKER_LENGTH 2
>  #define SECTOR_BYTES           512
> +#define ECCSIZE0_SHIFT         12
> +#define ECCSIZE1_SHIFT         22
> +#define ECC1RESULTSIZE         0x1
>  #define ECCCLEAR               (0x1 << 8)
>  #define ECCRESULTREG1          (0x1 << 0)
>  /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
> @@ -187,72 +190,35 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
>  __maybe_unused
>  static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
>  {
> -       struct nand_chip        *nand   = mtd_to_nand(mtd);
> -       struct omap_nand_info   *info   = nand_get_controller_data(nand);
> +       struct nand_chip *nand = mtd_to_nand(mtd);
> +       struct omap_nand_info *info = nand_get_controller_data(nand);
>         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
> -       unsigned int ecc_algo = 0;
> -       unsigned int bch_type = 0;
> -       unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
> -       u32 ecc_size_config_val = 0;
> -       u32 ecc_config_val = 0;
> -       int cs = info->cs;
> +       u32 val;
>
> -       /* configure GPMC for specific ecc-scheme */
> -       switch (info->ecc_scheme) {
> -       case OMAP_ECC_HAM1_CODE_SW:
> -               return;
> -       case OMAP_ECC_HAM1_CODE_HW:
> -               ecc_algo = 0x0;
> -               bch_type = 0x0;
> -               bch_wrapmode = 0x00;
> -               eccsize0 = 0xFF;
> -               eccsize1 = 0xFF;
> +       /* Clear ecc and enable bits */
> +       writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
> +
> +       /* program ecc and result sizes */
> +       val = ((((nand->ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
> +                       ECC1RESULTSIZE);
> +       writel(val, &gpmc_cfg->ecc_size_config);
> +
> +       switch (mode) {
> +       case NAND_ECC_READ:
> +       case NAND_ECC_WRITE:
> +               writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
>                 break;
> -       case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> -       case OMAP_ECC_BCH8_CODE_HW:
> -               ecc_algo = 0x1;
> -               bch_type = 0x1;
> -               if (mode == NAND_ECC_WRITE) {
> -                       bch_wrapmode = 0x01;
> -                       eccsize0 = 0;  /* extra bits in nibbles per sector */
> -                       eccsize1 = 28; /* OOB bits in nibbles per sector */
> -               } else {
> -                       bch_wrapmode = 0x01;
> -                       eccsize0 = 26; /* ECC bits in nibbles per sector */
> -                       eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
> -               }
> -               break;
> -       case OMAP_ECC_BCH16_CODE_HW:
> -               ecc_algo = 0x1;
> -               bch_type = 0x2;
> -               if (mode == NAND_ECC_WRITE) {
> -                       bch_wrapmode = 0x01;
> -                       eccsize0 = 0;  /* extra bits in nibbles per sector */
> -                       eccsize1 = 52; /* OOB bits in nibbles per sector */
> -               } else {
> -                       bch_wrapmode = 0x01;
> -                       eccsize0 = 52; /* ECC bits in nibbles per sector */
> -                       eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
> -               }
> +       case NAND_ECC_READSYN:
> +               writel(ECCCLEAR, &gpmc_cfg->ecc_control);
>                 break;
>         default:
> -               return;
> +               printf("%s: error: unrecognized Mode[%d]!\n", __func__, mode);
> +               break;
>         }
> -       /* Clear ecc and enable bits */
> -       writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
> -       /* Configure ecc size for BCH */
> -       ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
> -       writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
> -
> -       /* Configure device details for BCH engine */
> -       ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
> -                       (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
> -                       (bch_wrapmode << 8)     | /* wrap mode */
> -                       (dev_width << 7)        | /* bus width */
> -                       (0x0 << 4)              | /* number of sectors */
> -                       (cs <<  1)              | /* ECC CS */
> -                       (0x1));                   /* enable ECC */
> -       writel(ecc_config_val, &gpmc_cfg->ecc_config);
> +
> +       /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
> +       val = (dev_width << 7) | (info->cs << 1) | (0x1);
> +       writel(val, &gpmc_cfg->ecc_config);
>  }
>
>  /*
> @@ -271,6 +237,124 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
>   */
>  static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>                                 uint8_t *ecc_code)
> +{
> +       u32 val;
> +
> +       val = readl(&gpmc_cfg->ecc1_result);
> +       ecc_code[0] = val & 0xFF;
> +       ecc_code[1] = (val >> 16) & 0xFF;
> +       ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
> +
> +       return 0;
> +}
> +
> +/* GPMC ecc engine settings for read */
> +#define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
> +#define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
> +#define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
> +#define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
> +#define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
> +
> +/* GPMC ecc engine settings for write */
> +#define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
> +#define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
> +#define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
> +
> +/**
> + * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
> + * @mtd: MTD device structure
> + * @mode: Read/Write mode
> + *
> + * When using BCH with SW correction (i.e. no ELM), sector size is set
> + * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
> + * for both reading and writing with:
> + * eccsize0 = 0  (no additional protected byte in spare area)
> + * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
> + */
> +static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd,
> +                                                int mode)
> +{
> +       unsigned int bch_type;
> +       unsigned int dev_width, nsectors;
> +       struct nand_chip *chip = mtd_to_nand(mtd);
> +       struct omap_nand_info *info = nand_get_controller_data(chip);
> +       u32 val, wr_mode;
> +       unsigned int ecc_size1, ecc_size0;
> +
> +       /* GPMC configurations for calculating ECC */
> +       switch (info->ecc_scheme) {
> +       case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> +               bch_type = 1;
> +               nsectors = 1;
> +               wr_mode   = BCH_WRAPMODE_6;
> +               ecc_size0 = BCH_ECC_SIZE0;
> +               ecc_size1 = BCH_ECC_SIZE1;
> +               break;
> +       case OMAP_ECC_BCH8_CODE_HW:
> +               bch_type = 1;
> +               nsectors = chip->ecc.steps;
> +               if (mode == NAND_ECC_READ) {
> +                       wr_mode   = BCH_WRAPMODE_1;
> +                       ecc_size0 = BCH8R_ECC_SIZE0;
> +                       ecc_size1 = BCH8R_ECC_SIZE1;
> +               } else {
> +                       wr_mode   = BCH_WRAPMODE_6;
> +                       ecc_size0 = BCH_ECC_SIZE0;
> +                       ecc_size1 = BCH_ECC_SIZE1;
> +               }
> +               break;
> +       case OMAP_ECC_BCH16_CODE_HW:
> +               bch_type = 0x2;
> +               nsectors = chip->ecc.steps;
> +               if (mode == NAND_ECC_READ) {
> +                       wr_mode   = 0x01;
> +                       ecc_size0 = 52; /* ECC bits in nibbles per sector */
> +                       ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
> +               } else {
> +                       wr_mode   = 0x01;
> +                       ecc_size0 = 0;  /* extra bits in nibbles per sector */
> +                       ecc_size1 = 52; /* OOB bits in nibbles per sector */
> +               }
> +               break;
> +       default:
> +               return;
> +       }
> +
> +       writel(ECCRESULTREG1, &gpmc_cfg->ecc_control);
> +
> +       /* Configure ecc size for BCH */
> +       val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
> +       writel(val, &gpmc_cfg->ecc_size_config);
> +
> +       dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
> +
> +       /* BCH configuration */
> +       val = ((1                       << 16) | /* enable BCH */
> +              (bch_type                << 12) | /* BCH4/BCH8/BCH16 */
> +              (wr_mode                 <<  8) | /* wrap mode */
> +              (dev_width               <<  7) | /* bus width */
> +              (((nsectors - 1) & 0x7)  <<  4) | /* number of sectors */
> +              (info->cs                <<  1) | /* ECC CS */
> +              (0x1));                           /* enable ECC */
> +
> +       writel(val, &gpmc_cfg->ecc_config);
> +
> +       /* Clear ecc and enable bits */
> +       writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
> +}
> +
> +/**
> + * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
> + * @mtd:        MTD device structure
> + * @dat:        The pointer to data on which ecc is computed
> + * @ecc_code:   The ecc_code buffer
> + * @sector:     The sector number (for a multi sector page)
> + *
> + * Support calculating of BCH4/8/16 ECC vectors for one sector
> + * within a page. Sector number is in @sector.
> + */
> +static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
> +                                  u8 *ecc_code, int sector)
>  {
>         struct nand_chip *chip = mtd_to_nand(mtd);
>         struct omap_nand_info *info = nand_get_controller_data(chip);
> @@ -279,17 +363,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>         int8_t i = 0, j;
>
>         switch (info->ecc_scheme) {
> -       case OMAP_ECC_HAM1_CODE_HW:
> -               val = readl(&gpmc_cfg->ecc1_result);
> -               ecc_code[0] = val & 0xFF;
> -               ecc_code[1] = (val >> 16) & 0xFF;
> -               ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
> -               break;
>  #ifdef CONFIG_BCH
>         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
>  #endif
>         case OMAP_ECC_BCH8_CODE_HW:
> -               ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
> +               ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3];
>                 val = readl(ptr);
>                 ecc_code[i++] = (val >>  0) & 0xFF;
>                 ptr--;
> @@ -301,23 +379,24 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>                         ecc_code[i++] = (val >>  0) & 0xFF;
>                         ptr--;
>                 }
> +
>                 break;
>         case OMAP_ECC_BCH16_CODE_HW:
> -               val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
> +               val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]);
>                 ecc_code[i++] = (val >>  8) & 0xFF;
>                 ecc_code[i++] = (val >>  0) & 0xFF;
> -               val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
> +               val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]);
>                 ecc_code[i++] = (val >> 24) & 0xFF;
>                 ecc_code[i++] = (val >> 16) & 0xFF;
>                 ecc_code[i++] = (val >>  8) & 0xFF;
>                 ecc_code[i++] = (val >>  0) & 0xFF;
> -               val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
> +               val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]);
>                 ecc_code[i++] = (val >> 24) & 0xFF;
>                 ecc_code[i++] = (val >> 16) & 0xFF;
>                 ecc_code[i++] = (val >>  8) & 0xFF;
>                 ecc_code[i++] = (val >>  0) & 0xFF;
>                 for (j = 3; j >= 0; j--) {
> -                       val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
> +                       val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j]
>                                                                         );
>                         ecc_code[i++] = (val >> 24) & 0xFF;
>                         ecc_code[i++] = (val >> 16) & 0xFF;
> @@ -330,18 +409,18 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>         }
>         /* ECC scheme specific syndrome customizations */
>         switch (info->ecc_scheme) {
> -       case OMAP_ECC_HAM1_CODE_HW:
> -               break;
>  #ifdef CONFIG_BCH
>         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
> -
> +               /* Add constant polynomial to remainder, so that
> +                * ECC of blank pages results in 0x0 on reading back
> +                */
>                 for (i = 0; i < chip->ecc.bytes; i++)
> -                       *(ecc_code + i) = *(ecc_code + i) ^
> -                                               bch8_polynomial[i];
> +                       ecc_code[i] ^= bch8_polynomial[i];
>                 break;
>  #endif
>         case OMAP_ECC_BCH8_CODE_HW:
> -               ecc_code[chip->ecc.bytes - 1] = 0x00;
> +               /* Set 14th ECC byte as 0x0 for ROM compatibility */
> +               ecc_code[chip->ecc.bytes - 1] = 0x0;
>                 break;
>         case OMAP_ECC_BCH16_CODE_HW:
>                 break;
> @@ -351,6 +430,22 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
>         return 0;
>  }
>
> +/**
> + * omap_calculate_ecc_bch - ECC generator for 1 sector
> + * @mtd:        MTD device structure
> + * @dat:       The pointer to data on which ecc is computed
> + * @ecc_code:  The ecc_code buffer
> + *
> + * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
> + * when SW based correction is required as ECC is required for one sector
> + * at a time.
> + */
> +static int omap_calculate_ecc_bch(struct mtd_info *mtd,
> +                                 const u_char *dat, u_char *ecc_calc)

Please add __maybe_unused. Without it the CI/CD pipeline fails:

       arm:  +   devkit8000
+drivers/mtd/nand/raw/omap_gpmc.c:442:12: error:
'omap_calculate_ecc_bch' defined but not used
[-Werror=unused-function]
+  442 | static int omap_calculate_ecc_bch(struct mtd_info *mtd,
+      |            ^~~~~~~~~~~~~~~~~~~~~~
+cc1: all warnings being treated as errors
+make[5]: *** [scripts/Makefile.build:258:
drivers/mtd/nand/raw/omap_gpmc.o] Error 1
+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
+make[1]: *** [Makefile:1874: drivers] Error 2
+make: *** [Makefile:177: sub-make] Error 2

Thanks and regards,
Dario

> +{
> +       return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0);
> +}
> +
>  static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>  {
>         struct nand_chip *chip = mtd_to_nand(mtd);
> @@ -475,6 +570,35 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
>  #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
>
>  #ifdef CONFIG_NAND_OMAP_ELM
> +
> +/**
> + * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
> + * @mtd:       MTD device structure
> + * @dat:       The pointer to data on which ecc is computed
> + * @ecc_code:  The ecc_code buffer
> + *
> + * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
> + */
> +static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
> +                                       const u_char *dat, u_char *ecc_calc)
> +{
> +       struct nand_chip *chip = mtd_to_nand(mtd);
> +       int eccbytes = chip->ecc.bytes;
> +       unsigned long nsectors;
> +       int i, ret;
> +
> +       nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
> +       for (i = 0; i < nsectors; i++) {
> +               ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);
> +               if (ret)
> +                       return ret;
> +
> +               ecc_calc += eccbytes;
> +       }
> +
> +       return 0;
> +}
> +
>  /*
>   * omap_reverse_list - re-orders list elements in reverse order [internal]
>   * @list:      pointer to start of list
> @@ -627,52 +751,49 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
>  {
>         int i, eccsize = chip->ecc.size;
>         int eccbytes = chip->ecc.bytes;
> +       int ecctotal = chip->ecc.total;
>         int eccsteps = chip->ecc.steps;
>         uint8_t *p = buf;
>         uint8_t *ecc_calc = chip->buffers->ecccalc;
>         uint8_t *ecc_code = chip->buffers->ecccode;
>         uint32_t *eccpos = chip->ecc.layout->eccpos;
>         uint8_t *oob = chip->oob_poi;
> -       uint32_t data_pos;
>         uint32_t oob_pos;
>
> -       data_pos = 0;
>         /* oob area start */
>         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
>         oob += chip->ecc.layout->eccpos[0];
>
> -       for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
> -                               oob += eccbytes) {
> -               chip->ecc.hwctl(mtd, NAND_ECC_READ);
> -               /* read data */
> -               chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
> -               chip->read_buf(mtd, p, eccsize);
> -
> -               /* read respective ecc from oob area */
> -               chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
> -               chip->read_buf(mtd, oob, eccbytes);
> -               /* read syndrome */
> -               chip->ecc.calculate(mtd, p, &ecc_calc[i]);
> -
> -               data_pos += eccsize;
> -               oob_pos += eccbytes;
> -       }
> +       /* Enable ECC engine */
> +       chip->ecc.hwctl(mtd, NAND_ECC_READ);
> +
> +       /* read entire page */
> +       chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);
> +       chip->read_buf(mtd, buf, mtd->writesize);
> +
> +       /* read all ecc bytes from oob area */
> +       chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
> +       chip->read_buf(mtd, oob, ecctotal);
> +
> +       /* Calculate ecc bytes */
> +       omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc);
>
>         for (i = 0; i < chip->ecc.total; i++)
>                 ecc_code[i] = chip->oob_poi[eccpos[i]];
>
> +       /* error detect & correct */
>         eccsteps = chip->ecc.steps;
>         p = buf;
>
>         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
>                 int stat;
> -
>                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
>                 if (stat < 0)
>                         mtd->ecc_stats.failed++;
>                 else
>                         mtd->ecc_stats.corrected += stat;
>         }
> +
>         return 0;
>  }
>  #endif /* CONFIG_NAND_OMAP_ELM */
> @@ -820,9 +941,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
>                 nand->ecc.strength      = 8;
>                 nand->ecc.size          = SECTOR_BYTES;
>                 nand->ecc.bytes         = 13;
> -               nand->ecc.hwctl         = omap_enable_hwecc;
> +               nand->ecc.hwctl         = omap_enable_hwecc_bch;
>                 nand->ecc.correct       = omap_correct_data_bch_sw;
> -               nand->ecc.calculate     = omap_calculate_ecc;
> +               nand->ecc.calculate     = omap_calculate_ecc_bch;
>                 /* define ecc-layout */
>                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
>                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
> @@ -861,9 +982,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
>                 nand->ecc.strength      = 8;
>                 nand->ecc.size          = SECTOR_BYTES;
>                 nand->ecc.bytes         = 14;
> -               nand->ecc.hwctl         = omap_enable_hwecc;
> +               nand->ecc.hwctl         = omap_enable_hwecc_bch;
>                 nand->ecc.correct       = omap_correct_data_bch;
> -               nand->ecc.calculate     = omap_calculate_ecc;
> +               nand->ecc.calculate     = omap_calculate_ecc_bch;
>                 nand->ecc.read_page     = omap_read_page_bch;
>                 /* define ecc-layout */
>                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
> @@ -894,9 +1015,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
>                 nand->ecc.size          = SECTOR_BYTES;
>                 nand->ecc.bytes         = 26;
>                 nand->ecc.strength      = 16;
> -               nand->ecc.hwctl         = omap_enable_hwecc;
> +               nand->ecc.hwctl         = omap_enable_hwecc_bch;
>                 nand->ecc.correct       = omap_correct_data_bch;
> -               nand->ecc.calculate     = omap_calculate_ecc;
> +               nand->ecc.calculate     = omap_calculate_ecc_bch;
>                 nand->ecc.read_page     = omap_read_page_bch;
>                 /* define ecc-layout */
>                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
> --
> 2.17.1
>


-- 

Dario Binacchi

Embedded Linux Developer

dario.binacchi@amarulasolutions.com

__________________________________


Amarula Solutions SRL

Via Le Canevare 30, 31100 Treviso, Veneto, IT

T. +39 042 243 5310
info@amarulasolutions.com

www.amarulasolutions.com

Re: [u-boot][PATCH 05/14] mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction

[Tom Rini]

[-- Attachment #1: Type: text/plain, Size: 1659 bytes --]

On Tue, Nov 29, 2022 at 04:25:13PM +0100, Dario Binacchi wrote:
> Hi Roger,
> 
> On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
> >
> > The BCH detection hardware can generate ECC bytes for multiple
> > sectors in one go. Use that feature.
> >
> > correct() only corrects one sector at a time so we need to call it
> > repeatedly for each sector.
> >
> > Signed-off-by: Roger Quadros <rogerq@kernel.org>
[snip]
> > +/**
> > + * omap_calculate_ecc_bch - ECC generator for 1 sector
> > + * @mtd:        MTD device structure
> > + * @dat:       The pointer to data on which ecc is computed
> > + * @ecc_code:  The ecc_code buffer
> > + *
> > + * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
> > + * when SW based correction is required as ECC is required for one sector
> > + * at a time.
> > + */
> > +static int omap_calculate_ecc_bch(struct mtd_info *mtd,
> > +                                 const u_char *dat, u_char *ecc_calc)
> 
> Please add __maybe_unused. Without it the CI/CD pipeline fails:
> 
>        arm:  +   devkit8000
> +drivers/mtd/nand/raw/omap_gpmc.c:442:12: error:
> 'omap_calculate_ecc_bch' defined but not used
> [-Werror=unused-function]
> +  442 | static int omap_calculate_ecc_bch(struct mtd_info *mtd,
> +      |            ^~~~~~~~~~~~~~~~~~~~~~
> +cc1: all warnings being treated as errors

While not a firm rule, a general suggestion is if it's easy to fix a CI
error like this, do so (and add Signed-off-by tag) during testing a PR
rather than ask for a resubmit.  Unless there's other more complex
changes needed as well.

-- 
Tom

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]

Re: [u-boot][PATCH 05/14] mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction

[Dario Binacchi]

Hi Tom,

On Tue, Nov 29, 2022 at 5:18 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Tue, Nov 29, 2022 at 04:25:13PM +0100, Dario Binacchi wrote:
> > Hi Roger,
> >
> > On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >
> > > The BCH detection hardware can generate ECC bytes for multiple
> > > sectors in one go. Use that feature.
> > >
> > > correct() only corrects one sector at a time so we need to call it
> > > repeatedly for each sector.
> > >
> > > Signed-off-by: Roger Quadros <rogerq@kernel.org>
> [snip]
> > > +/**
> > > + * omap_calculate_ecc_bch - ECC generator for 1 sector
> > > + * @mtd:        MTD device structure
> > > + * @dat:       The pointer to data on which ecc is computed
> > > + * @ecc_code:  The ecc_code buffer
> > > + *
> > > + * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
> > > + * when SW based correction is required as ECC is required for one sector
> > > + * at a time.
> > > + */
> > > +static int omap_calculate_ecc_bch(struct mtd_info *mtd,
> > > +                                 const u_char *dat, u_char *ecc_calc)
> >
> > Please add __maybe_unused. Without it the CI/CD pipeline fails:
> >
> >        arm:  +   devkit8000
> > +drivers/mtd/nand/raw/omap_gpmc.c:442:12: error:
> > 'omap_calculate_ecc_bch' defined but not used
> > [-Werror=unused-function]
> > +  442 | static int omap_calculate_ecc_bch(struct mtd_info *mtd,
> > +      |            ^~~~~~~~~~~~~~~~~~~~~~
> > +cc1: all warnings being treated as errors
>
> While not a firm rule, a general suggestion is if it's easy to fix a CI
> error like this, do so (and add Signed-off-by tag) during testing a PR
> rather than ask for a resubmit.  Unless there's other more complex
> changes needed as well.

I'll do it. Thanks for the suggestion and the explanation.
Best regards,
Dario
>
> --
> Tom



-- 

Dario Binacchi

Embedded Linux Developer

dario.binacchi@amarulasolutions.com

__________________________________


Amarula Solutions SRL

Via Le Canevare 30, 31100 Treviso, Veneto, IT

T. +39 042 243 5310
info@amarulasolutions.com

www.amarulasolutions.com

Re: [u-boot][PATCH 05/14] mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction

[Roger Quadros]

On 30/11/2022 10:11, Dario Binacchi wrote:
> Hi Tom,
> 
> On Tue, Nov 29, 2022 at 5:18 PM Tom Rini <trini@konsulko.com> wrote:
>>
>> On Tue, Nov 29, 2022 at 04:25:13PM +0100, Dario Binacchi wrote:
>>> Hi Roger,
>>>
>>> On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>
>>>> The BCH detection hardware can generate ECC bytes for multiple
>>>> sectors in one go. Use that feature.
>>>>
>>>> correct() only corrects one sector at a time so we need to call it
>>>> repeatedly for each sector.
>>>>
>>>> Signed-off-by: Roger Quadros <rogerq@kernel.org>
>> [snip]
>>>> +/**
>>>> + * omap_calculate_ecc_bch - ECC generator for 1 sector
>>>> + * @mtd:        MTD device structure
>>>> + * @dat:       The pointer to data on which ecc is computed
>>>> + * @ecc_code:  The ecc_code buffer
>>>> + *
>>>> + * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
>>>> + * when SW based correction is required as ECC is required for one sector
>>>> + * at a time.
>>>> + */
>>>> +static int omap_calculate_ecc_bch(struct mtd_info *mtd,
>>>> +                                 const u_char *dat, u_char *ecc_calc)
>>>
>>> Please add __maybe_unused. Without it the CI/CD pipeline fails:
>>>
>>>        arm:  +   devkit8000
>>> +drivers/mtd/nand/raw/omap_gpmc.c:442:12: error:
>>> 'omap_calculate_ecc_bch' defined but not used
>>> [-Werror=unused-function]
>>> +  442 | static int omap_calculate_ecc_bch(struct mtd_info *mtd,
>>> +      |            ^~~~~~~~~~~~~~~~~~~~~~
>>> +cc1: all warnings being treated as errors
>>
>> While not a firm rule, a general suggestion is if it's easy to fix a CI
>> error like this, do so (and add Signed-off-by tag) during testing a PR
>> rather than ask for a resubmit.  Unless there's other more complex
>> changes needed as well.
> 
> I'll do it. Thanks for the suggestion and the explanation.

Thanks for saving me from a re-spin. :)

--
cheers,
-roger

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Dario Binacchi]

Hi Roger,

On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Hi Michael,
>
> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> > Hi Roger
> >
> > On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>
> >> Hi,
> >>
> >> On 11/10/2022 14:49, Roger Quadros wrote:
> >>> Hi,
> >>>
> >>> This series adds driver model support for rawnand: omap_gpmc
> >>> and omap_elm drivers.
> >>>
> >>> This will enable the driver to be used on K2/K3 platforms as well.
> >>
> >> Any comments on patches 5 and later? Thanks
> >>
> >
> > We will try to close this week.
>
> Could you please give your comments on the last few patches. Thanks!
>
> cheers,
> -roger
>
> >
> > Michael
> >
> >>
> >> cheers,
> >> -roger
> >>
> >>>
> >>> cheers,
> >>> -roger
> >>>
> >>> Roger Quadros (14):
> >>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> >>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> >>>     nand_bbt
> >>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> >>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> >>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> >>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> >>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> >>>   mtd: rawnand: omap_elm: u-boot driver model support
> >>>
> >>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> >>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> >>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> >>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> >>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> >>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> >>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> >>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> >>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> >>>  9 files changed, 637 insertions(+), 136 deletions(-)
> >>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> >>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> >>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> >>>
> >
> >
> >

I tried to merge your whole series but after the second fix and the
third time the CI/CD pipeline failed
I thought it's better you fix the problems. So, I only accepted some
of the first few patches in the series:
01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage

For the others, please fix them to run the tests successfully.

Thanks and regards,
Dario

-- 

Dario Binacchi

Embedded Linux Developer

dario.binacchi@amarulasolutions.com

__________________________________


Amarula Solutions SRL

Via Le Canevare 30, 31100 Treviso, Veneto, IT

T. +39 042 243 5310
info@amarulasolutions.com

www.amarulasolutions.com

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Roger Quadros]

Hi Dario,

On 11/12/2022 15:56, Dario Binacchi wrote:
> Hi Roger,
> 
> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
>>
>> Hi Michael,
>>
>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
>>> Hi Roger
>>>
>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>
>>>> Hi,
>>>>
>>>> On 11/10/2022 14:49, Roger Quadros wrote:
>>>>> Hi,
>>>>>
>>>>> This series adds driver model support for rawnand: omap_gpmc
>>>>> and omap_elm drivers.
>>>>>
>>>>> This will enable the driver to be used on K2/K3 platforms as well.
>>>>
>>>> Any comments on patches 5 and later? Thanks
>>>>
>>>
>>> We will try to close this week.
>>
>> Could you please give your comments on the last few patches. Thanks!
>>
>> cheers,
>> -roger
>>
>>>
>>> Michael
>>>
>>>>
>>>> cheers,
>>>> -roger
>>>>
>>>>>
>>>>> cheers,
>>>>> -roger
>>>>>
>>>>> Roger Quadros (14):
>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
>>>>>     nand_bbt
>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
>>>>>
>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
>>>>>
>>>
>>>
>>>
> 
> I tried to merge your whole series but after the second fix and the
> third time the CI/CD pipeline failed

Do you have the link to the failure?

> I thought it's better you fix the problems. So, I only accepted some
> of the first few patches in the series:
> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
> 
> For the others, please fix them to run the tests successfully.

No problem. I will try to fix and run them through the CI testing myself
before re-posting.

cheers,
-roger

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Dario Binacchi]

Hi Roger,

On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
>
> Hi Dario,
>
> On 11/12/2022 15:56, Dario Binacchi wrote:
> > Hi Roger,
> >
> > On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>
> >> Hi Michael,
> >>
> >> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> >>> Hi Roger
> >>>
> >>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>
> >>>> Hi,
> >>>>
> >>>> On 11/10/2022 14:49, Roger Quadros wrote:
> >>>>> Hi,
> >>>>>
> >>>>> This series adds driver model support for rawnand: omap_gpmc
> >>>>> and omap_elm drivers.
> >>>>>
> >>>>> This will enable the driver to be used on K2/K3 platforms as well.
> >>>>
> >>>> Any comments on patches 5 and later? Thanks
> >>>>
> >>>
> >>> We will try to close this week.
> >>
> >> Could you please give your comments on the last few patches. Thanks!
> >>
> >> cheers,
> >> -roger
> >>
> >>>
> >>> Michael
> >>>
> >>>>
> >>>> cheers,
> >>>> -roger
> >>>>
> >>>>>
> >>>>> cheers,
> >>>>> -roger
> >>>>>
> >>>>> Roger Quadros (14):
> >>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> >>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> >>>>>     nand_bbt
> >>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> >>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> >>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> >>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> >>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> >>>>>   mtd: rawnand: omap_elm: u-boot driver model support
> >>>>>
> >>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> >>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> >>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> >>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> >>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> >>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> >>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> >>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> >>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> >>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
> >>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> >>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> >>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> >>>>>
> >>>
> >>>
> >>>
> >
> > I tried to merge your whole series but after the second fix and the
> > third time the CI/CD pipeline failed
>
> Do you have the link to the failure?

These are the CI/CD pipelines links:
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
but I think you don't have permission to access them.

Anyway:

for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
+====================================================
345 arm: + am335x_guardian
346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
defined but not used [-Werror=unused-variable]
347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
SPL use only */
348+ | ^~~~~~~~~
349+cc1: all warnings being treated as errors
350+make[5]: *** [scripts/Makefile.build:258:
drivers/mtd/nand/raw/omap_gpmc.o] Error 1
351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
354+make[1]: *** [Makefile:1871: drivers] Error 2
355+make: *** [Makefile:177: sub-make] Error 2

for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
+====================================================
498 arm: + chiliboard
499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
`nand_init_chip':
500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
501+make[1]: *** [Makefile:1778: u-boot] Error 1
502+make: *** [Makefile:177: sub-make] Error 2
503 arm: w+ am335x_shc_netboot
504+===================== WARNING ======================
505+This board does not use CONFIG_DM_I2C (Driver Model
506+for I2C drivers). Please update the board to use
507+CONFIG_DM_I2C before the v2022.04 release. Failure to
508+update by the deadline may result in board removal.
509+See doc/develop/driver-model/migration.rst for more info.
510+====================================================
511 arm: + cm_t43
512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
`nand_init_chip':
513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
514+make[1]: *** [Makefile:1778: u-boot] Error 1
515+make: *** [Makefile:177: sub-make] Error 2
516 arm: w+ am335x_shc_sdboot

In both cases failed the "build all 32bit ARM platforms" test.

I think you have to run the command:
./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
if you have to run the tests locally.

Thanks and regards,
Dario

>
> > I thought it's better you fix the problems. So, I only accepted some
> > of the first few patches in the series:
> > 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> > 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> > 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> > 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
> > 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> > 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
> >
> > For the others, please fix them to run the tests successfully.
>
> No problem. I will try to fix and run them through the CI testing myself
> before re-posting.
>
> cheers,
> -roger



-- 

Dario Binacchi

Embedded Linux Developer

dario.binacchi@amarulasolutions.com

__________________________________


Amarula Solutions SRL

Via Le Canevare 30, 31100 Treviso, Veneto, IT

T. +39 042 243 5310
info@amarulasolutions.com

www.amarulasolutions.com

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Michael Nazzareno Trimarchi]

Hi Roger

Most of the building problem can be tested with this configuration

make ARCH=arm chiliboard_defconfig

Michael

On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
<dario.binacchi@amarulasolutions.com> wrote:
>
> Hi Roger,
>
> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
> >
> > Hi Dario,
> >
> > On 11/12/2022 15:56, Dario Binacchi wrote:
> > > Hi Roger,
> > >
> > > On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>
> > >> Hi Michael,
> > >>
> > >> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> > >>> Hi Roger
> > >>>
> > >>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>
> > >>>> Hi,
> > >>>>
> > >>>> On 11/10/2022 14:49, Roger Quadros wrote:
> > >>>>> Hi,
> > >>>>>
> > >>>>> This series adds driver model support for rawnand: omap_gpmc
> > >>>>> and omap_elm drivers.
> > >>>>>
> > >>>>> This will enable the driver to be used on K2/K3 platforms as well.
> > >>>>
> > >>>> Any comments on patches 5 and later? Thanks
> > >>>>
> > >>>
> > >>> We will try to close this week.
> > >>
> > >> Could you please give your comments on the last few patches. Thanks!
> > >>
> > >> cheers,
> > >> -roger
> > >>
> > >>>
> > >>> Michael
> > >>>
> > >>>>
> > >>>> cheers,
> > >>>> -roger
> > >>>>
> > >>>>>
> > >>>>> cheers,
> > >>>>> -roger
> > >>>>>
> > >>>>> Roger Quadros (14):
> > >>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> > >>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> > >>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> > >>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> > >>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> > >>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> > >>>>>     nand_bbt
> > >>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> > >>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> > >>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> > >>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> > >>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> > >>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> > >>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> > >>>>>   mtd: rawnand: omap_elm: u-boot driver model support
> > >>>>>
> > >>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> > >>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> > >>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> > >>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> > >>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> > >>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> > >>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> > >>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> > >>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> > >>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
> > >>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> > >>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> > >>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> > >>>>>
> > >>>
> > >>>
> > >>>
> > >
> > > I tried to merge your whole series but after the second fix and the
> > > third time the CI/CD pipeline failed
> >
> > Do you have the link to the failure?
>
> These are the CI/CD pipelines links:
> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
> but I think you don't have permission to access them.
>
> Anyway:
>
> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
> +====================================================
> 345 arm: + am335x_guardian
> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
> defined but not used [-Werror=unused-variable]
> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
> SPL use only */
> 348+ | ^~~~~~~~~
> 349+cc1: all warnings being treated as errors
> 350+make[5]: *** [scripts/Makefile.build:258:
> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
> 354+make[1]: *** [Makefile:1871: drivers] Error 2
> 355+make: *** [Makefile:177: sub-make] Error 2
>
> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
> +====================================================
> 498 arm: + chiliboard
> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> `nand_init_chip':
> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
> 502+make: *** [Makefile:177: sub-make] Error 2
> 503 arm: w+ am335x_shc_netboot
> 504+===================== WARNING ======================
> 505+This board does not use CONFIG_DM_I2C (Driver Model
> 506+for I2C drivers). Please update the board to use
> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
> 508+update by the deadline may result in board removal.
> 509+See doc/develop/driver-model/migration.rst for more info.
> 510+====================================================
> 511 arm: + cm_t43
> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> `nand_init_chip':
> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
> 515+make: *** [Makefile:177: sub-make] Error 2
> 516 arm: w+ am335x_shc_sdboot
>
> In both cases failed the "build all 32bit ARM platforms" test.
>
> I think you have to run the command:
> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
> if you have to run the tests locally.
>
> Thanks and regards,
> Dario
>
> >
> > > I thought it's better you fix the problems. So, I only accepted some
> > > of the first few patches in the series:
> > > 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> > > 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> > > 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> > > 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
> > > 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> > > 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
> > >
> > > For the others, please fix them to run the tests successfully.
> >
> > No problem. I will try to fix and run them through the CI testing myself
> > before re-posting.
> >
> > cheers,
> > -roger
>
>
>
> --
>
> Dario Binacchi
>
> Embedded Linux Developer
>
> dario.binacchi@amarulasolutions.com
>
> __________________________________
>
>
> Amarula Solutions SRL
>
> Via Le Canevare 30, 31100 Treviso, Veneto, IT
>
> T. +39 042 243 5310
> info@amarulasolutions.com
>
> www.amarulasolutions.com



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Tom Rini]

[-- Attachment #1: Type: text/plain, Size: 3834 bytes --]

On Mon, Dec 12, 2022 at 10:27:41AM +0100, Dario Binacchi wrote:
> Hi Roger,
> 
> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
> >
> > Hi Dario,
> >
> > On 11/12/2022 15:56, Dario Binacchi wrote:
> > > Hi Roger,
> > >
> > > On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>
> > >> Hi Michael,
> > >>
> > >> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> > >>> Hi Roger
> > >>>
> > >>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>
> > >>>> Hi,
> > >>>>
> > >>>> On 11/10/2022 14:49, Roger Quadros wrote:
> > >>>>> Hi,
> > >>>>>
> > >>>>> This series adds driver model support for rawnand: omap_gpmc
> > >>>>> and omap_elm drivers.
> > >>>>>
> > >>>>> This will enable the driver to be used on K2/K3 platforms as well.
> > >>>>
> > >>>> Any comments on patches 5 and later? Thanks
> > >>>>
> > >>>
> > >>> We will try to close this week.
> > >>
> > >> Could you please give your comments on the last few patches. Thanks!
> > >>
> > >> cheers,
> > >> -roger
> > >>
> > >>>
> > >>> Michael
> > >>>
> > >>>>
> > >>>> cheers,
> > >>>> -roger
> > >>>>
> > >>>>>
> > >>>>> cheers,
> > >>>>> -roger
> > >>>>>
> > >>>>> Roger Quadros (14):
> > >>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> > >>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> > >>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> > >>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> > >>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> > >>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> > >>>>>     nand_bbt
> > >>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> > >>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> > >>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> > >>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> > >>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> > >>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> > >>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> > >>>>>   mtd: rawnand: omap_elm: u-boot driver model support
> > >>>>>
> > >>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> > >>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> > >>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> > >>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> > >>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> > >>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> > >>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> > >>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> > >>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> > >>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
> > >>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> > >>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> > >>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> > >>>>>
> > >>>
> > >>>
> > >>>
> > >
> > > I tried to merge your whole series but after the second fix and the
> > > third time the CI/CD pipeline failed
> >
> > Do you have the link to the failure?
> 
> These are the CI/CD pipelines links:
> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
> but I think you don't have permission to access them.

Note that under CI settings you can make your pipeline visible to all.
It's just not the default for some reason and I'm not sure we can change
it globally.

-- 
Tom

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Roger Quadros]

Hi Michael & Dario,

On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
> Hi Roger
> 
> Most of the building problem can be tested with this configuration
> 
> make ARCH=arm chiliboard_defconfig

I resolved the original issue for all boards but now face a new issue
only with the chiliboard.

arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource':
/work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource'
  AR      common/built-in.o
make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
make[1]: *** Waiting for unfinished jobs....
make[1]: Leaving directory '/tmp'
make: *** [Makefile:177: sub-make] Error 2

The following config options are set
CONFIG_DM_DEV_READ_INLINE=y
CONFIG_SUPPORT_OF_CONTROL=y

My understanding is that in case of spl build (Makefile.spl), the
drivers/core/ofnode.o does not seem to be included
thus causing the linking error.

Any suggestions how to fix this?

I've pushed the patches here
https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4

cheers,
-roger

> 
> Michael
> 
> On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
> <dario.binacchi@amarulasolutions.com> wrote:
>>
>> Hi Roger,
>>
>> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
>>>
>>> Hi Dario,
>>>
>>> On 11/12/2022 15:56, Dario Binacchi wrote:
>>>> Hi Roger,
>>>>
>>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>
>>>>> Hi Michael,
>>>>>
>>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
>>>>>> Hi Roger
>>>>>>
>>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> On 11/10/2022 14:49, Roger Quadros wrote:
>>>>>>>> Hi,
>>>>>>>>
>>>>>>>> This series adds driver model support for rawnand: omap_gpmc
>>>>>>>> and omap_elm drivers.
>>>>>>>>
>>>>>>>> This will enable the driver to be used on K2/K3 platforms as well.
>>>>>>>
>>>>>>> Any comments on patches 5 and later? Thanks
>>>>>>>
>>>>>>
>>>>>> We will try to close this week.
>>>>>
>>>>> Could you please give your comments on the last few patches. Thanks!
>>>>>
>>>>> cheers,
>>>>> -roger
>>>>>
>>>>>>
>>>>>> Michael
>>>>>>
>>>>>>>
>>>>>>> cheers,
>>>>>>> -roger
>>>>>>>
>>>>>>>>
>>>>>>>> cheers,
>>>>>>>> -roger
>>>>>>>>
>>>>>>>> Roger Quadros (14):
>>>>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>>>>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>>>>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>>>>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
>>>>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
>>>>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
>>>>>>>>     nand_bbt
>>>>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>>>>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
>>>>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
>>>>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
>>>>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
>>>>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
>>>>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
>>>>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
>>>>>>>>
>>>>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
>>>>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
>>>>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
>>>>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
>>>>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
>>>>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
>>>>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
>>>>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
>>>>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
>>>>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
>>>>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
>>>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>
>>>> I tried to merge your whole series but after the second fix and the
>>>> third time the CI/CD pipeline failed
>>>
>>> Do you have the link to the failure?
>>
>> These are the CI/CD pipelines links:
>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
>> but I think you don't have permission to access them.
>>
>> Anyway:
>>
>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
>> +====================================================
>> 345 arm: + am335x_guardian
>> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
>> defined but not used [-Werror=unused-variable]
>> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
>> SPL use only */
>> 348+ | ^~~~~~~~~
>> 349+cc1: all warnings being treated as errors
>> 350+make[5]: *** [scripts/Makefile.build:258:
>> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
>> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
>> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
>> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
>> 354+make[1]: *** [Makefile:1871: drivers] Error 2
>> 355+make: *** [Makefile:177: sub-make] Error 2
>>
>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
>> +====================================================
>> 498 arm: + chiliboard
>> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
>> `nand_init_chip':
>> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
>> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
>> 502+make: *** [Makefile:177: sub-make] Error 2
>> 503 arm: w+ am335x_shc_netboot
>> 504+===================== WARNING ======================
>> 505+This board does not use CONFIG_DM_I2C (Driver Model
>> 506+for I2C drivers). Please update the board to use
>> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
>> 508+update by the deadline may result in board removal.
>> 509+See doc/develop/driver-model/migration.rst for more info.
>> 510+====================================================
>> 511 arm: + cm_t43
>> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
>> `nand_init_chip':
>> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
>> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
>> 515+make: *** [Makefile:177: sub-make] Error 2
>> 516 arm: w+ am335x_shc_sdboot
>>
>> In both cases failed the "build all 32bit ARM platforms" test.
>>
>> I think you have to run the command:
>> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
>> if you have to run the tests locally.
>>
>> Thanks and regards,
>> Dario
>>
>>>
>>>> I thought it's better you fix the problems. So, I only accepted some
>>>> of the first few patches in the series:
>>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
>>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
>>>>
>>>> For the others, please fix them to run the tests successfully.
>>>
>>> No problem. I will try to fix and run them through the CI testing myself
>>> before re-posting.
>>>
>>> cheers,
>>> -roger
>>
>>
>>
>> --
>>
>> Dario Binacchi
>>
>> Embedded Linux Developer
>>
>> dario.binacchi@amarulasolutions.com
>>
>> __________________________________
>>
>>
>> Amarula Solutions SRL
>>
>> Via Le Canevare 30, 31100 Treviso, Veneto, IT
>>
>> T. +39 042 243 5310
>> info@amarulasolutions.com
>>
>> www.amarulasolutions.com
> 
> 
> 

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Michael Nazzareno Trimarchi]

Hi

On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Hi Michael & Dario,
>
> On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
> > Hi Roger
> >
> > Most of the building problem can be tested with this configuration
> >
> > make ARCH=arm chiliboard_defconfig
>
> I resolved the original issue for all boards but now face a new issue
> only with the chiliboard.
>
> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource':
> /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource'
>   AR      common/built-in.o
> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> make[1]: *** Waiting for unfinished jobs....
> make[1]: Leaving directory '/tmp'
> make: *** [Makefile:177: sub-make] Error 2
>
> The following config options are set
> CONFIG_DM_DEV_READ_INLINE=y

What happen is that is not set?

Michael

> CONFIG_SUPPORT_OF_CONTROL=y
>
> My understanding is that in case of spl build (Makefile.spl), the
> drivers/core/ofnode.o does not seem to be included
> thus causing the linking error.
>
> Any suggestions how to fix this?
>
> I've pushed the patches here
> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
>
> cheers,
> -roger
>
> >
> > Michael
> >
> > On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
> > <dario.binacchi@amarulasolutions.com> wrote:
> >>
> >> Hi Roger,
> >>
> >> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
> >>>
> >>> Hi Dario,
> >>>
> >>> On 11/12/2022 15:56, Dario Binacchi wrote:
> >>>> Hi Roger,
> >>>>
> >>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>
> >>>>> Hi Michael,
> >>>>>
> >>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> >>>>>> Hi Roger
> >>>>>>
> >>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>>>
> >>>>>>> Hi,
> >>>>>>>
> >>>>>>> On 11/10/2022 14:49, Roger Quadros wrote:
> >>>>>>>> Hi,
> >>>>>>>>
> >>>>>>>> This series adds driver model support for rawnand: omap_gpmc
> >>>>>>>> and omap_elm drivers.
> >>>>>>>>
> >>>>>>>> This will enable the driver to be used on K2/K3 platforms as well.
> >>>>>>>
> >>>>>>> Any comments on patches 5 and later? Thanks
> >>>>>>>
> >>>>>>
> >>>>>> We will try to close this week.
> >>>>>
> >>>>> Could you please give your comments on the last few patches. Thanks!
> >>>>>
> >>>>> cheers,
> >>>>> -roger
> >>>>>
> >>>>>>
> >>>>>> Michael
> >>>>>>
> >>>>>>>
> >>>>>>> cheers,
> >>>>>>> -roger
> >>>>>>>
> >>>>>>>>
> >>>>>>>> cheers,
> >>>>>>>> -roger
> >>>>>>>>
> >>>>>>>> Roger Quadros (14):
> >>>>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>>>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>>>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>>>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>>>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> >>>>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> >>>>>>>>     nand_bbt
> >>>>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>>>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>>>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> >>>>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> >>>>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> >>>>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> >>>>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> >>>>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
> >>>>>>>>
> >>>>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> >>>>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> >>>>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> >>>>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> >>>>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> >>>>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> >>>>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> >>>>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> >>>>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> >>>>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
> >>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> >>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> >>>>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> >>>>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>
> >>>> I tried to merge your whole series but after the second fix and the
> >>>> third time the CI/CD pipeline failed
> >>>
> >>> Do you have the link to the failure?
> >>
> >> These are the CI/CD pipelines links:
> >> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
> >> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
> >> but I think you don't have permission to access them.
> >>
> >> Anyway:
> >>
> >> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
> >> +====================================================
> >> 345 arm: + am335x_guardian
> >> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
> >> defined but not used [-Werror=unused-variable]
> >> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
> >> SPL use only */
> >> 348+ | ^~~~~~~~~
> >> 349+cc1: all warnings being treated as errors
> >> 350+make[5]: *** [scripts/Makefile.build:258:
> >> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
> >> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
> >> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
> >> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
> >> 354+make[1]: *** [Makefile:1871: drivers] Error 2
> >> 355+make: *** [Makefile:177: sub-make] Error 2
> >>
> >> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
> >> +====================================================
> >> 498 arm: + chiliboard
> >> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> >> `nand_init_chip':
> >> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> >> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
> >> 502+make: *** [Makefile:177: sub-make] Error 2
> >> 503 arm: w+ am335x_shc_netboot
> >> 504+===================== WARNING ======================
> >> 505+This board does not use CONFIG_DM_I2C (Driver Model
> >> 506+for I2C drivers). Please update the board to use
> >> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
> >> 508+update by the deadline may result in board removal.
> >> 509+See doc/develop/driver-model/migration.rst for more info.
> >> 510+====================================================
> >> 511 arm: + cm_t43
> >> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> >> `nand_init_chip':
> >> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> >> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
> >> 515+make: *** [Makefile:177: sub-make] Error 2
> >> 516 arm: w+ am335x_shc_sdboot
> >>
> >> In both cases failed the "build all 32bit ARM platforms" test.
> >>
> >> I think you have to run the command:
> >> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
> >> if you have to run the tests locally.
> >>
> >> Thanks and regards,
> >> Dario
> >>
> >>>
> >>>> I thought it's better you fix the problems. So, I only accepted some
> >>>> of the first few patches in the series:
> >>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>>>
> >>>> For the others, please fix them to run the tests successfully.
> >>>
> >>> No problem. I will try to fix and run them through the CI testing myself
> >>> before re-posting.
> >>>
> >>> cheers,
> >>> -roger
> >>
> >>
> >>
> >> --
> >>
> >> Dario Binacchi
> >>
> >> Embedded Linux Developer
> >>
> >> dario.binacchi@amarulasolutions.com
> >>
> >> __________________________________
> >>
> >>
> >> Amarula Solutions SRL
> >>
> >> Via Le Canevare 30, 31100 Treviso, Veneto, IT
> >>
> >> T. +39 042 243 5310
> >> info@amarulasolutions.com
> >>
> >> www.amarulasolutions.com
> >
> >
> >



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Roger Quadros]

On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
> Hi
> 
> On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros <rogerq@kernel.org> wrote:
>>
>> Hi Michael & Dario,
>>
>> On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
>>> Hi Roger
>>>
>>> Most of the building problem can be tested with this configuration
>>>
>>> make ARCH=arm chiliboard_defconfig
>>
>> I resolved the original issue for all boards but now face a new issue
>> only with the chiliboard.
>>
>> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource':
>> /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource'
>>   AR      common/built-in.o
>> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
>> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
>> make[1]: *** Waiting for unfinished jobs....
>> make[1]: Leaving directory '/tmp'
>> make: *** [Makefile:177: sub-make] Error 2
>>
>> The following config options are set
>> CONFIG_DM_DEV_READ_INLINE=y
> 
> What happen is that is not set?

I removed "default y" for it in drivers/core/Kconfig

Now I get

arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe':
/work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource'
make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
make[1]: *** Waiting for unfinished jobs....

cheers,
-roger

> 
> Michael
> 
>> CONFIG_SUPPORT_OF_CONTROL=y
>>
>> My understanding is that in case of spl build (Makefile.spl), the
>> drivers/core/ofnode.o does not seem to be included
>> thus causing the linking error.
>>
>> Any suggestions how to fix this?
>>
>> I've pushed the patches here
>> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
>>
>> cheers,
>> -roger
>>
>>>
>>> Michael
>>>
>>> On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
>>> <dario.binacchi@amarulasolutions.com> wrote:
>>>>
>>>> Hi Roger,
>>>>
>>>> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>
>>>>> Hi Dario,
>>>>>
>>>>> On 11/12/2022 15:56, Dario Binacchi wrote:
>>>>>> Hi Roger,
>>>>>>
>>>>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>>>
>>>>>>> Hi Michael,
>>>>>>>
>>>>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
>>>>>>>> Hi Roger
>>>>>>>>
>>>>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>>>>>
>>>>>>>>> Hi,
>>>>>>>>>
>>>>>>>>> On 11/10/2022 14:49, Roger Quadros wrote:
>>>>>>>>>> Hi,
>>>>>>>>>>
>>>>>>>>>> This series adds driver model support for rawnand: omap_gpmc
>>>>>>>>>> and omap_elm drivers.
>>>>>>>>>>
>>>>>>>>>> This will enable the driver to be used on K2/K3 platforms as well.
>>>>>>>>>
>>>>>>>>> Any comments on patches 5 and later? Thanks
>>>>>>>>>
>>>>>>>>
>>>>>>>> We will try to close this week.
>>>>>>>
>>>>>>> Could you please give your comments on the last few patches. Thanks!
>>>>>>>
>>>>>>> cheers,
>>>>>>> -roger
>>>>>>>
>>>>>>>>
>>>>>>>> Michael
>>>>>>>>
>>>>>>>>>
>>>>>>>>> cheers,
>>>>>>>>> -roger
>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> cheers,
>>>>>>>>>> -roger
>>>>>>>>>>
>>>>>>>>>> Roger Quadros (14):
>>>>>>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>>>>>>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
>>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
>>>>>>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
>>>>>>>>>>     nand_bbt
>>>>>>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>>>>>>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
>>>>>>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
>>>>>>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
>>>>>>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
>>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
>>>>>>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
>>>>>>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
>>>>>>>>>>
>>>>>>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
>>>>>>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
>>>>>>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
>>>>>>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
>>>>>>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
>>>>>>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
>>>>>>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
>>>>>>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
>>>>>>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
>>>>>>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
>>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
>>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
>>>>>>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
>>>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>
>>>>>> I tried to merge your whole series but after the second fix and the
>>>>>> third time the CI/CD pipeline failed
>>>>>
>>>>> Do you have the link to the failure?
>>>>
>>>> These are the CI/CD pipelines links:
>>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
>>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
>>>> but I think you don't have permission to access them.
>>>>
>>>> Anyway:
>>>>
>>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
>>>> +====================================================
>>>> 345 arm: + am335x_guardian
>>>> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
>>>> defined but not used [-Werror=unused-variable]
>>>> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
>>>> SPL use only */
>>>> 348+ | ^~~~~~~~~
>>>> 349+cc1: all warnings being treated as errors
>>>> 350+make[5]: *** [scripts/Makefile.build:258:
>>>> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
>>>> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
>>>> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
>>>> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
>>>> 354+make[1]: *** [Makefile:1871: drivers] Error 2
>>>> 355+make: *** [Makefile:177: sub-make] Error 2
>>>>
>>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
>>>> +====================================================
>>>> 498 arm: + chiliboard
>>>> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
>>>> `nand_init_chip':
>>>> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
>>>> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
>>>> 502+make: *** [Makefile:177: sub-make] Error 2
>>>> 503 arm: w+ am335x_shc_netboot
>>>> 504+===================== WARNING ======================
>>>> 505+This board does not use CONFIG_DM_I2C (Driver Model
>>>> 506+for I2C drivers). Please update the board to use
>>>> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
>>>> 508+update by the deadline may result in board removal.
>>>> 509+See doc/develop/driver-model/migration.rst for more info.
>>>> 510+====================================================
>>>> 511 arm: + cm_t43
>>>> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
>>>> `nand_init_chip':
>>>> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
>>>> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
>>>> 515+make: *** [Makefile:177: sub-make] Error 2
>>>> 516 arm: w+ am335x_shc_sdboot
>>>>
>>>> In both cases failed the "build all 32bit ARM platforms" test.
>>>>
>>>> I think you have to run the command:
>>>> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
>>>> if you have to run the tests locally.
>>>>
>>>> Thanks and regards,
>>>> Dario
>>>>
>>>>>
>>>>>> I thought it's better you fix the problems. So, I only accepted some
>>>>>> of the first few patches in the series:
>>>>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>>>>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>>>>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>>>>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
>>>>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>>>>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
>>>>>>
>>>>>> For the others, please fix them to run the tests successfully.
>>>>>
>>>>> No problem. I will try to fix and run them through the CI testing myself
>>>>> before re-posting.
>>>>>
>>>>> cheers,
>>>>> -roger
>>>>
>>>>
>>>>
>>>> --
>>>>
>>>> Dario Binacchi
>>>>
>>>> Embedded Linux Developer
>>>>
>>>> dario.binacchi@amarulasolutions.com
>>>>
>>>> __________________________________
>>>>
>>>>
>>>> Amarula Solutions SRL
>>>>
>>>> Via Le Canevare 30, 31100 Treviso, Veneto, IT
>>>>
>>>> T. +39 042 243 5310
>>>> info@amarulasolutions.com
>>>>
>>>> www.amarulasolutions.com
>>>
>>>
>>>
> 
> 
> 

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Michael Nazzareno Trimarchi]

[-- Attachment #1: Type: text/plain, Size: 10159 bytes --]

Hi

take my config

Michael

On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>
> >> Hi Michael & Dario,
> >>
> >> On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
> >>> Hi Roger
> >>>
> >>> Most of the building problem can be tested with this configuration
> >>>
> >>> make ARCH=arm chiliboard_defconfig
> >>
> >> I resolved the original issue for all boards but now face a new issue
> >> only with the chiliboard.
> >>
> >> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource':
> >> /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource'
> >>   AR      common/built-in.o
> >> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> >> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> >> make[1]: *** Waiting for unfinished jobs....
> >> make[1]: Leaving directory '/tmp'
> >> make: *** [Makefile:177: sub-make] Error 2
> >>
> >> The following config options are set
> >> CONFIG_DM_DEV_READ_INLINE=y
> >
> > What happen is that is not set?
>
> I removed "default y" for it in drivers/core/Kconfig
>
> Now I get
>
> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe':
> /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource'
> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> make[1]: *** Waiting for unfinished jobs....
>
> cheers,
> -roger
>
> >
> > Michael
> >
> >> CONFIG_SUPPORT_OF_CONTROL=y
> >>
> >> My understanding is that in case of spl build (Makefile.spl), the
> >> drivers/core/ofnode.o does not seem to be included
> >> thus causing the linking error.
> >>
> >> Any suggestions how to fix this?
> >>
> >> I've pushed the patches here
> >> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
> >>
> >> cheers,
> >> -roger
> >>
> >>>
> >>> Michael
> >>>
> >>> On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
> >>> <dario.binacchi@amarulasolutions.com> wrote:
> >>>>
> >>>> Hi Roger,
> >>>>
> >>>> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>
> >>>>> Hi Dario,
> >>>>>
> >>>>> On 11/12/2022 15:56, Dario Binacchi wrote:
> >>>>>> Hi Roger,
> >>>>>>
> >>>>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>>>
> >>>>>>> Hi Michael,
> >>>>>>>
> >>>>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> >>>>>>>> Hi Roger
> >>>>>>>>
> >>>>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>>>>>
> >>>>>>>>> Hi,
> >>>>>>>>>
> >>>>>>>>> On 11/10/2022 14:49, Roger Quadros wrote:
> >>>>>>>>>> Hi,
> >>>>>>>>>>
> >>>>>>>>>> This series adds driver model support for rawnand: omap_gpmc
> >>>>>>>>>> and omap_elm drivers.
> >>>>>>>>>>
> >>>>>>>>>> This will enable the driver to be used on K2/K3 platforms as well.
> >>>>>>>>>
> >>>>>>>>> Any comments on patches 5 and later? Thanks
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> We will try to close this week.
> >>>>>>>
> >>>>>>> Could you please give your comments on the last few patches. Thanks!
> >>>>>>>
> >>>>>>> cheers,
> >>>>>>> -roger
> >>>>>>>
> >>>>>>>>
> >>>>>>>> Michael
> >>>>>>>>
> >>>>>>>>>
> >>>>>>>>> cheers,
> >>>>>>>>> -roger
> >>>>>>>>>
> >>>>>>>>>>
> >>>>>>>>>> cheers,
> >>>>>>>>>> -roger
> >>>>>>>>>>
> >>>>>>>>>> Roger Quadros (14):
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> >>>>>>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> >>>>>>>>>>     nand_bbt
> >>>>>>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>>>>>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> >>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> >>>>>>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> >>>>>>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
> >>>>>>>>>>
> >>>>>>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> >>>>>>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> >>>>>>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> >>>>>>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> >>>>>>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> >>>>>>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> >>>>>>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> >>>>>>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> >>>>>>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> >>>>>>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
> >>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> >>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> >>>>>>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> >>>>>>>>>>
> >>>>>>>>
> >>>>>>>>
> >>>>>>>>
> >>>>>>
> >>>>>> I tried to merge your whole series but after the second fix and the
> >>>>>> third time the CI/CD pipeline failed
> >>>>>
> >>>>> Do you have the link to the failure?
> >>>>
> >>>> These are the CI/CD pipelines links:
> >>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
> >>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
> >>>> but I think you don't have permission to access them.
> >>>>
> >>>> Anyway:
> >>>>
> >>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
> >>>> +====================================================
> >>>> 345 arm: + am335x_guardian
> >>>> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
> >>>> defined but not used [-Werror=unused-variable]
> >>>> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
> >>>> SPL use only */
> >>>> 348+ | ^~~~~~~~~
> >>>> 349+cc1: all warnings being treated as errors
> >>>> 350+make[5]: *** [scripts/Makefile.build:258:
> >>>> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
> >>>> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
> >>>> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
> >>>> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
> >>>> 354+make[1]: *** [Makefile:1871: drivers] Error 2
> >>>> 355+make: *** [Makefile:177: sub-make] Error 2
> >>>>
> >>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
> >>>> +====================================================
> >>>> 498 arm: + chiliboard
> >>>> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> >>>> `nand_init_chip':
> >>>> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> >>>> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
> >>>> 502+make: *** [Makefile:177: sub-make] Error 2
> >>>> 503 arm: w+ am335x_shc_netboot
> >>>> 504+===================== WARNING ======================
> >>>> 505+This board does not use CONFIG_DM_I2C (Driver Model
> >>>> 506+for I2C drivers). Please update the board to use
> >>>> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
> >>>> 508+update by the deadline may result in board removal.
> >>>> 509+See doc/develop/driver-model/migration.rst for more info.
> >>>> 510+====================================================
> >>>> 511 arm: + cm_t43
> >>>> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> >>>> `nand_init_chip':
> >>>> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> >>>> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
> >>>> 515+make: *** [Makefile:177: sub-make] Error 2
> >>>> 516 arm: w+ am335x_shc_sdboot
> >>>>
> >>>> In both cases failed the "build all 32bit ARM platforms" test.
> >>>>
> >>>> I think you have to run the command:
> >>>> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
> >>>> if you have to run the tests locally.
> >>>>
> >>>> Thanks and regards,
> >>>> Dario
> >>>>
> >>>>>
> >>>>>> I thought it's better you fix the problems. So, I only accepted some
> >>>>>> of the first few patches in the series:
> >>>>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>>>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>>>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>>>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>>>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>>>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>>>>>
> >>>>>> For the others, please fix them to run the tests successfully.
> >>>>>
> >>>>> No problem. I will try to fix and run them through the CI testing myself
> >>>>> before re-posting.
> >>>>>
> >>>>> cheers,
> >>>>> -roger
> >>>>
> >>>>
> >>>>
> >>>> --
> >>>>
> >>>> Dario Binacchi
> >>>>
> >>>> Embedded Linux Developer
> >>>>
> >>>> dario.binacchi@amarulasolutions.com
> >>>>
> >>>> __________________________________
> >>>>
> >>>>
> >>>> Amarula Solutions SRL
> >>>>
> >>>> Via Le Canevare 30, 31100 Treviso, Veneto, IT
> >>>>
> >>>> T. +39 042 243 5310
> >>>> info@amarulasolutions.com
> >>>>
> >>>> www.amarulasolutions.com
> >>>
> >>>
> >>>
> >
> >
> >



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

[-- Attachment #2: chiliboard_defconfig --]
[-- Type: application/octet-stream, Size: 2357 bytes --]

CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-chiliboard"
CONFIG_AM33XX=y
CONFIG_TARGET_CHILIBOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x22000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0
CONFIG_TIMESTAMP=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run mmcboot; run nandboot; run netboot"
CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
CONFIG_OFNODE_MULTI_TREE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MISC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PMIC_TPS65217=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_TI=y
CONFIG_LZO=y

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Michael Nazzareno Trimarchi]

Hi

Minimal diff

diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index 458c4558fd..c7f8fd2e25 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -47,12 +47,14 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RETRY_COUNT=10
 CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SPL_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_SYS_I2C_LEGACY=y

On Sat, Dec 17, 2022 at 2:46 PM Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:
>
> Hi
>
> take my config
>
> Michael
>
> On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros <rogerq@kernel.org> wrote:
> >
> > On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
> > > Hi
> > >
> > > On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>
> > >> Hi Michael & Dario,
> > >>
> > >> On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
> > >>> Hi Roger
> > >>>
> > >>> Most of the building problem can be tested with this configuration
> > >>>
> > >>> make ARCH=arm chiliboard_defconfig
> > >>
> > >> I resolved the original issue for all boards but now face a new issue
> > >> only with the chiliboard.
> > >>
> > >> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource':
> > >> /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource'
> > >>   AR      common/built-in.o
> > >> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> > >> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> > >> make[1]: *** Waiting for unfinished jobs....
> > >> make[1]: Leaving directory '/tmp'
> > >> make: *** [Makefile:177: sub-make] Error 2
> > >>
> > >> The following config options are set
> > >> CONFIG_DM_DEV_READ_INLINE=y
> > >
> > > What happen is that is not set?
> >
> > I removed "default y" for it in drivers/core/Kconfig
> >
> > Now I get
> >
> > arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe':
> > /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource'
> > make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> > make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> > make[1]: *** Waiting for unfinished jobs....
> >
> > cheers,
> > -roger
> >
> > >
> > > Michael
> > >
> > >> CONFIG_SUPPORT_OF_CONTROL=y
> > >>
> > >> My understanding is that in case of spl build (Makefile.spl), the
> > >> drivers/core/ofnode.o does not seem to be included
> > >> thus causing the linking error.
> > >>
> > >> Any suggestions how to fix this?
> > >>
> > >> I've pushed the patches here
> > >> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
> > >>
> > >> cheers,
> > >> -roger
> > >>
> > >>>
> > >>> Michael
> > >>>
> > >>> On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
> > >>> <dario.binacchi@amarulasolutions.com> wrote:
> > >>>>
> > >>>> Hi Roger,
> > >>>>
> > >>>> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>>
> > >>>>> Hi Dario,
> > >>>>>
> > >>>>> On 11/12/2022 15:56, Dario Binacchi wrote:
> > >>>>>> Hi Roger,
> > >>>>>>
> > >>>>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>>>>
> > >>>>>>> Hi Michael,
> > >>>>>>>
> > >>>>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> > >>>>>>>> Hi Roger
> > >>>>>>>>
> > >>>>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>>>>>>
> > >>>>>>>>> Hi,
> > >>>>>>>>>
> > >>>>>>>>> On 11/10/2022 14:49, Roger Quadros wrote:
> > >>>>>>>>>> Hi,
> > >>>>>>>>>>
> > >>>>>>>>>> This series adds driver model support for rawnand: omap_gpmc
> > >>>>>>>>>> and omap_elm drivers.
> > >>>>>>>>>>
> > >>>>>>>>>> This will enable the driver to be used on K2/K3 platforms as well.
> > >>>>>>>>>
> > >>>>>>>>> Any comments on patches 5 and later? Thanks
> > >>>>>>>>>
> > >>>>>>>>
> > >>>>>>>> We will try to close this week.
> > >>>>>>>
> > >>>>>>> Could you please give your comments on the last few patches. Thanks!
> > >>>>>>>
> > >>>>>>> cheers,
> > >>>>>>> -roger
> > >>>>>>>
> > >>>>>>>>
> > >>>>>>>> Michael
> > >>>>>>>>
> > >>>>>>>>>
> > >>>>>>>>> cheers,
> > >>>>>>>>> -roger
> > >>>>>>>>>
> > >>>>>>>>>>
> > >>>>>>>>>> cheers,
> > >>>>>>>>>> -roger
> > >>>>>>>>>>
> > >>>>>>>>>> Roger Quadros (14):
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> > >>>>>>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> > >>>>>>>>>>     nand_bbt
> > >>>>>>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> > >>>>>>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> > >>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> > >>>>>>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> > >>>>>>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
> > >>>>>>>>>>
> > >>>>>>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> > >>>>>>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> > >>>>>>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> > >>>>>>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> > >>>>>>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> > >>>>>>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> > >>>>>>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> > >>>>>>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> > >>>>>>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> > >>>>>>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
> > >>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> > >>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> > >>>>>>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> > >>>>>>>>>>
> > >>>>>>>>
> > >>>>>>>>
> > >>>>>>>>
> > >>>>>>
> > >>>>>> I tried to merge your whole series but after the second fix and the
> > >>>>>> third time the CI/CD pipeline failed
> > >>>>>
> > >>>>> Do you have the link to the failure?
> > >>>>
> > >>>> These are the CI/CD pipelines links:
> > >>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
> > >>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
> > >>>> but I think you don't have permission to access them.
> > >>>>
> > >>>> Anyway:
> > >>>>
> > >>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
> > >>>> +====================================================
> > >>>> 345 arm: + am335x_guardian
> > >>>> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
> > >>>> defined but not used [-Werror=unused-variable]
> > >>>> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
> > >>>> SPL use only */
> > >>>> 348+ | ^~~~~~~~~
> > >>>> 349+cc1: all warnings being treated as errors
> > >>>> 350+make[5]: *** [scripts/Makefile.build:258:
> > >>>> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
> > >>>> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
> > >>>> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
> > >>>> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
> > >>>> 354+make[1]: *** [Makefile:1871: drivers] Error 2
> > >>>> 355+make: *** [Makefile:177: sub-make] Error 2
> > >>>>
> > >>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
> > >>>> +====================================================
> > >>>> 498 arm: + chiliboard
> > >>>> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> > >>>> `nand_init_chip':
> > >>>> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> > >>>> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
> > >>>> 502+make: *** [Makefile:177: sub-make] Error 2
> > >>>> 503 arm: w+ am335x_shc_netboot
> > >>>> 504+===================== WARNING ======================
> > >>>> 505+This board does not use CONFIG_DM_I2C (Driver Model
> > >>>> 506+for I2C drivers). Please update the board to use
> > >>>> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
> > >>>> 508+update by the deadline may result in board removal.
> > >>>> 509+See doc/develop/driver-model/migration.rst for more info.
> > >>>> 510+====================================================
> > >>>> 511 arm: + cm_t43
> > >>>> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> > >>>> `nand_init_chip':
> > >>>> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> > >>>> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
> > >>>> 515+make: *** [Makefile:177: sub-make] Error 2
> > >>>> 516 arm: w+ am335x_shc_sdboot
> > >>>>
> > >>>> In both cases failed the "build all 32bit ARM platforms" test.
> > >>>>
> > >>>> I think you have to run the command:
> > >>>> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
> > >>>> if you have to run the tests locally.
> > >>>>
> > >>>> Thanks and regards,
> > >>>> Dario
> > >>>>
> > >>>>>
> > >>>>>> I thought it's better you fix the problems. So, I only accepted some
> > >>>>>> of the first few patches in the series:
> > >>>>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> > >>>>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> > >>>>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> > >>>>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
> > >>>>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> > >>>>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
> > >>>>>>
> > >>>>>> For the others, please fix them to run the tests successfully.
> > >>>>>
> > >>>>> No problem. I will try to fix and run them through the CI testing myself
> > >>>>> before re-posting.
> > >>>>>
> > >>>>> cheers,
> > >>>>> -roger
> > >>>>
> > >>>>
> > >>>>
> > >>>> --
> > >>>>
> > >>>> Dario Binacchi
> > >>>>
> > >>>> Embedded Linux Developer
> > >>>>
> > >>>> dario.binacchi@amarulasolutions.com
> > >>>>
> > >>>> __________________________________
> > >>>>
> > >>>>
> > >>>> Amarula Solutions SRL
> > >>>>
> > >>>> Via Le Canevare 30, 31100 Treviso, Veneto, IT
> > >>>>
> > >>>> T. +39 042 243 5310
> > >>>> info@amarulasolutions.com
> > >>>>
> > >>>> www.amarulasolutions.com
> > >>>
> > >>>
> > >>>
> > >
> > >
> > >
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> info@amarulasolutions.com
> www.amarulasolutions.com



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Roger Quadros]

On 17/12/2022 15:51, Michael Nazzareno Trimarchi wrote:
> Hi
> 
> Minimal diff
> 
> diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
> index 458c4558fd..c7f8fd2e25 100644
> --- a/configs/chiliboard_defconfig
> +++ b/configs/chiliboard_defconfig
> @@ -47,12 +47,14 @@ CONFIG_CMD_MTDPARTS=y
>  CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand"
>  CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
>  CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
>  CONFIG_ENV_OVERWRITE=y
>  CONFIG_ENV_IS_IN_MMC=y
>  CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>  CONFIG_NET_RETRY_COUNT=10
>  CONFIG_BOOTP_SEND_HOSTNAME=y
> +CONFIG_SPL_DM=y
>  CONFIG_BOOTCOUNT_LIMIT=y
>  CONFIG_SYS_BOOTCOUNT_BE=y
>  CONFIG_SYS_I2C_LEGACY=y

This worked perfectly.
But this platform my not yet be utilizing DM for NAND/ELM driver yet
so is this change acceptable?

cheers,
-roger

> 
> On Sat, Dec 17, 2022 at 2:46 PM Michael Nazzareno Trimarchi
> <michael@amarulasolutions.com> wrote:
>>
>> Hi
>>
>> take my config
>>
>> Michael
>>
>> On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>
>>> On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
>>>> Hi
>>>>
>>>> On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>
>>>>> Hi Michael & Dario,
>>>>>
>>>>> On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
>>>>>> Hi Roger
>>>>>>
>>>>>> Most of the building problem can be tested with this configuration
>>>>>>
>>>>>> make ARCH=arm chiliboard_defconfig
>>>>>
>>>>> I resolved the original issue for all boards but now face a new issue
>>>>> only with the chiliboard.
>>>>>
>>>>> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource':
>>>>> /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource'
>>>>>   AR      common/built-in.o
>>>>> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
>>>>> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
>>>>> make[1]: *** Waiting for unfinished jobs....
>>>>> make[1]: Leaving directory '/tmp'
>>>>> make: *** [Makefile:177: sub-make] Error 2
>>>>>
>>>>> The following config options are set
>>>>> CONFIG_DM_DEV_READ_INLINE=y
>>>>
>>>> What happen is that is not set?
>>>
>>> I removed "default y" for it in drivers/core/Kconfig
>>>
>>> Now I get
>>>
>>> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe':
>>> /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource'
>>> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
>>> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
>>> make[1]: *** Waiting for unfinished jobs....
>>>
>>> cheers,
>>> -roger
>>>
>>>>
>>>> Michael
>>>>
>>>>> CONFIG_SUPPORT_OF_CONTROL=y
>>>>>
>>>>> My understanding is that in case of spl build (Makefile.spl), the
>>>>> drivers/core/ofnode.o does not seem to be included
>>>>> thus causing the linking error.
>>>>>
>>>>> Any suggestions how to fix this?
>>>>>
>>>>> I've pushed the patches here
>>>>> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
>>>>>
>>>>> cheers,
>>>>> -roger
>>>>>
>>>>>>
>>>>>> Michael
>>>>>>
>>>>>> On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
>>>>>> <dario.binacchi@amarulasolutions.com> wrote:
>>>>>>>
>>>>>>> Hi Roger,
>>>>>>>
>>>>>>> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>>>>
>>>>>>>> Hi Dario,
>>>>>>>>
>>>>>>>> On 11/12/2022 15:56, Dario Binacchi wrote:
>>>>>>>>> Hi Roger,
>>>>>>>>>
>>>>>>>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>>>>>>
>>>>>>>>>> Hi Michael,
>>>>>>>>>>
>>>>>>>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
>>>>>>>>>>> Hi Roger
>>>>>>>>>>>
>>>>>>>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>> Hi,
>>>>>>>>>>>>
>>>>>>>>>>>> On 11/10/2022 14:49, Roger Quadros wrote:
>>>>>>>>>>>>> Hi,
>>>>>>>>>>>>>
>>>>>>>>>>>>> This series adds driver model support for rawnand: omap_gpmc
>>>>>>>>>>>>> and omap_elm drivers.
>>>>>>>>>>>>>
>>>>>>>>>>>>> This will enable the driver to be used on K2/K3 platforms as well.
>>>>>>>>>>>>
>>>>>>>>>>>> Any comments on patches 5 and later? Thanks
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> We will try to close this week.
>>>>>>>>>>
>>>>>>>>>> Could you please give your comments on the last few patches. Thanks!
>>>>>>>>>>
>>>>>>>>>> cheers,
>>>>>>>>>> -roger
>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Michael
>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> cheers,
>>>>>>>>>>>> -roger
>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> cheers,
>>>>>>>>>>>>> -roger
>>>>>>>>>>>>>
>>>>>>>>>>>>> Roger Quadros (14):
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
>>>>>>>>>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
>>>>>>>>>>>>>     nand_bbt
>>>>>>>>>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
>>>>>>>>>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
>>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
>>>>>>>>>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
>>>>>>>>>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
>>>>>>>>>>>>>
>>>>>>>>>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
>>>>>>>>>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
>>>>>>>>>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
>>>>>>>>>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
>>>>>>>>>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
>>>>>>>>>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
>>>>>>>>>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
>>>>>>>>>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
>>>>>>>>>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
>>>>>>>>>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
>>>>>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
>>>>>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
>>>>>>>>>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
>>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> I tried to merge your whole series but after the second fix and the
>>>>>>>>> third time the CI/CD pipeline failed
>>>>>>>>
>>>>>>>> Do you have the link to the failure?
>>>>>>>
>>>>>>> These are the CI/CD pipelines links:
>>>>>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
>>>>>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
>>>>>>> but I think you don't have permission to access them.
>>>>>>>
>>>>>>> Anyway:
>>>>>>>
>>>>>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
>>>>>>> +====================================================
>>>>>>> 345 arm: + am335x_guardian
>>>>>>> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
>>>>>>> defined but not used [-Werror=unused-variable]
>>>>>>> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
>>>>>>> SPL use only */
>>>>>>> 348+ | ^~~~~~~~~
>>>>>>> 349+cc1: all warnings being treated as errors
>>>>>>> 350+make[5]: *** [scripts/Makefile.build:258:
>>>>>>> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
>>>>>>> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
>>>>>>> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
>>>>>>> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
>>>>>>> 354+make[1]: *** [Makefile:1871: drivers] Error 2
>>>>>>> 355+make: *** [Makefile:177: sub-make] Error 2
>>>>>>>
>>>>>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
>>>>>>> +====================================================
>>>>>>> 498 arm: + chiliboard
>>>>>>> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
>>>>>>> `nand_init_chip':
>>>>>>> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
>>>>>>> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
>>>>>>> 502+make: *** [Makefile:177: sub-make] Error 2
>>>>>>> 503 arm: w+ am335x_shc_netboot
>>>>>>> 504+===================== WARNING ======================
>>>>>>> 505+This board does not use CONFIG_DM_I2C (Driver Model
>>>>>>> 506+for I2C drivers). Please update the board to use
>>>>>>> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
>>>>>>> 508+update by the deadline may result in board removal.
>>>>>>> 509+See doc/develop/driver-model/migration.rst for more info.
>>>>>>> 510+====================================================
>>>>>>> 511 arm: + cm_t43
>>>>>>> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
>>>>>>> `nand_init_chip':
>>>>>>> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
>>>>>>> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
>>>>>>> 515+make: *** [Makefile:177: sub-make] Error 2
>>>>>>> 516 arm: w+ am335x_shc_sdboot
>>>>>>>
>>>>>>> In both cases failed the "build all 32bit ARM platforms" test.
>>>>>>>
>>>>>>> I think you have to run the command:
>>>>>>> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
>>>>>>> if you have to run the tests locally.
>>>>>>>
>>>>>>> Thanks and regards,
>>>>>>> Dario
>>>>>>>
>>>>>>>>
>>>>>>>>> I thought it's better you fix the problems. So, I only accepted some
>>>>>>>>> of the first few patches in the series:
>>>>>>>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
>>>>>>>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
>>>>>>>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
>>>>>>>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
>>>>>>>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
>>>>>>>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
>>>>>>>>>
>>>>>>>>> For the others, please fix them to run the tests successfully.
>>>>>>>>
>>>>>>>> No problem. I will try to fix and run them through the CI testing myself
>>>>>>>> before re-posting.
>>>>>>>>
>>>>>>>> cheers,
>>>>>>>> -roger
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>>
>>>>>>> Dario Binacchi
>>>>>>>
>>>>>>> Embedded Linux Developer
>>>>>>>
>>>>>>> dario.binacchi@amarulasolutions.com
>>>>>>>
>>>>>>> __________________________________
>>>>>>>
>>>>>>>
>>>>>>> Amarula Solutions SRL
>>>>>>>
>>>>>>> Via Le Canevare 30, 31100 Treviso, Veneto, IT
>>>>>>>
>>>>>>> T. +39 042 243 5310
>>>>>>> info@amarulasolutions.com
>>>>>>>
>>>>>>> www.amarulasolutions.com
>>>>>>
>>>>>>
>>>>>>
>>>>
>>>>
>>>>
>>
>>
>>
>> --
>> Michael Nazzareno Trimarchi
>> Co-Founder & Chief Executive Officer
>> M. +39 347 913 2170
>> michael@amarulasolutions.com
>> __________________________________
>>
>> Amarula Solutions BV
>> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
>> T. +31 (0)85 111 9172
>> info@amarulasolutions.com
>> www.amarulasolutions.com
> 
> 
> 

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Michael Nazzareno Trimarchi]

Hi Roger

On Sat, Dec 17, 2022 at 2:59 PM Roger Quadros <rogerq@kernel.org> wrote:
>
>
>
> On 17/12/2022 15:51, Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > Minimal diff
> >
> > diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
> > index 458c4558fd..c7f8fd2e25 100644
> > --- a/configs/chiliboard_defconfig
> > +++ b/configs/chiliboard_defconfig
> > @@ -47,12 +47,14 @@ CONFIG_CMD_MTDPARTS=y
> >  CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand"
> >  CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
> >  CONFIG_OF_CONTROL=y
> > +CONFIG_SPL_OF_CONTROL=y
> >  CONFIG_ENV_OVERWRITE=y
> >  CONFIG_ENV_IS_IN_MMC=y
> >  CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> >  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> >  CONFIG_NET_RETRY_COUNT=10
> >  CONFIG_BOOTP_SEND_HOSTNAME=y
> > +CONFIG_SPL_DM=y
> >  CONFIG_BOOTCOUNT_LIMIT=y
> >  CONFIG_SYS_BOOTCOUNT_BE=y
> >  CONFIG_SYS_I2C_LEGACY=y
>
> This worked perfectly.
> But this platform my not yet be utilizing DM for NAND/ELM driver yet
> so is this change acceptable?
>

Can you restrict to platforms that support it?

I have added the author of this upstream

Michael

> cheers,
> -roger
>
> >
> > On Sat, Dec 17, 2022 at 2:46 PM Michael Nazzareno Trimarchi
> > <michael@amarulasolutions.com> wrote:
> >>
> >> Hi
> >>
> >> take my config
> >>
> >> Michael
> >>
> >> On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>
> >>> On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
> >>>> Hi
> >>>>
> >>>> On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>
> >>>>> Hi Michael & Dario,
> >>>>>
> >>>>> On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
> >>>>>> Hi Roger
> >>>>>>
> >>>>>> Most of the building problem can be tested with this configuration
> >>>>>>
> >>>>>> make ARCH=arm chiliboard_defconfig
> >>>>>
> >>>>> I resolved the original issue for all boards but now face a new issue
> >>>>> only with the chiliboard.
> >>>>>
> >>>>> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource':
> >>>>> /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource'
> >>>>>   AR      common/built-in.o
> >>>>> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> >>>>> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> >>>>> make[1]: *** Waiting for unfinished jobs....
> >>>>> make[1]: Leaving directory '/tmp'
> >>>>> make: *** [Makefile:177: sub-make] Error 2
> >>>>>
> >>>>> The following config options are set
> >>>>> CONFIG_DM_DEV_READ_INLINE=y
> >>>>
> >>>> What happen is that is not set?
> >>>
> >>> I removed "default y" for it in drivers/core/Kconfig
> >>>
> >>> Now I get
> >>>
> >>> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe':
> >>> /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource'
> >>> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> >>> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> >>> make[1]: *** Waiting for unfinished jobs....
> >>>
> >>> cheers,
> >>> -roger
> >>>
> >>>>
> >>>> Michael
> >>>>
> >>>>> CONFIG_SUPPORT_OF_CONTROL=y
> >>>>>
> >>>>> My understanding is that in case of spl build (Makefile.spl), the
> >>>>> drivers/core/ofnode.o does not seem to be included
> >>>>> thus causing the linking error.
> >>>>>
> >>>>> Any suggestions how to fix this?
> >>>>>
> >>>>> I've pushed the patches here
> >>>>> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
> >>>>>
> >>>>> cheers,
> >>>>> -roger
> >>>>>
> >>>>>>
> >>>>>> Michael
> >>>>>>
> >>>>>> On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
> >>>>>> <dario.binacchi@amarulasolutions.com> wrote:
> >>>>>>>
> >>>>>>> Hi Roger,
> >>>>>>>
> >>>>>>> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>>>>
> >>>>>>>> Hi Dario,
> >>>>>>>>
> >>>>>>>> On 11/12/2022 15:56, Dario Binacchi wrote:
> >>>>>>>>> Hi Roger,
> >>>>>>>>>
> >>>>>>>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>>>>>>
> >>>>>>>>>> Hi Michael,
> >>>>>>>>>>
> >>>>>>>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> >>>>>>>>>>> Hi Roger
> >>>>>>>>>>>
> >>>>>>>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> >>>>>>>>>>>>
> >>>>>>>>>>>> Hi,
> >>>>>>>>>>>>
> >>>>>>>>>>>> On 11/10/2022 14:49, Roger Quadros wrote:
> >>>>>>>>>>>>> Hi,
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> This series adds driver model support for rawnand: omap_gpmc
> >>>>>>>>>>>>> and omap_elm drivers.
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> This will enable the driver to be used on K2/K3 platforms as well.
> >>>>>>>>>>>>
> >>>>>>>>>>>> Any comments on patches 5 and later? Thanks
> >>>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>>> We will try to close this week.
> >>>>>>>>>>
> >>>>>>>>>> Could you please give your comments on the last few patches. Thanks!
> >>>>>>>>>>
> >>>>>>>>>> cheers,
> >>>>>>>>>> -roger
> >>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>>> Michael
> >>>>>>>>>>>
> >>>>>>>>>>>>
> >>>>>>>>>>>> cheers,
> >>>>>>>>>>>> -roger
> >>>>>>>>>>>>
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> cheers,
> >>>>>>>>>>>>> -roger
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> Roger Quadros (14):
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> >>>>>>>>>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> >>>>>>>>>>>>>     nand_bbt
> >>>>>>>>>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>>>>>>>>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> >>>>>>>>>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> >>>>>>>>>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
> >>>>>>>>>>>>>
> >>>>>>>>>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> >>>>>>>>>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> >>>>>>>>>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> >>>>>>>>>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> >>>>>>>>>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> >>>>>>>>>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> >>>>>>>>>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> >>>>>>>>>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> >>>>>>>>>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> >>>>>>>>>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
> >>>>>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> >>>>>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> >>>>>>>>>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> >>>>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>
> >>>>>>>>> I tried to merge your whole series but after the second fix and the
> >>>>>>>>> third time the CI/CD pipeline failed
> >>>>>>>>
> >>>>>>>> Do you have the link to the failure?
> >>>>>>>
> >>>>>>> These are the CI/CD pipelines links:
> >>>>>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
> >>>>>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
> >>>>>>> but I think you don't have permission to access them.
> >>>>>>>
> >>>>>>> Anyway:
> >>>>>>>
> >>>>>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
> >>>>>>> +====================================================
> >>>>>>> 345 arm: + am335x_guardian
> >>>>>>> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
> >>>>>>> defined but not used [-Werror=unused-variable]
> >>>>>>> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
> >>>>>>> SPL use only */
> >>>>>>> 348+ | ^~~~~~~~~
> >>>>>>> 349+cc1: all warnings being treated as errors
> >>>>>>> 350+make[5]: *** [scripts/Makefile.build:258:
> >>>>>>> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
> >>>>>>> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
> >>>>>>> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
> >>>>>>> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
> >>>>>>> 354+make[1]: *** [Makefile:1871: drivers] Error 2
> >>>>>>> 355+make: *** [Makefile:177: sub-make] Error 2
> >>>>>>>
> >>>>>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
> >>>>>>> +====================================================
> >>>>>>> 498 arm: + chiliboard
> >>>>>>> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> >>>>>>> `nand_init_chip':
> >>>>>>> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> >>>>>>> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
> >>>>>>> 502+make: *** [Makefile:177: sub-make] Error 2
> >>>>>>> 503 arm: w+ am335x_shc_netboot
> >>>>>>> 504+===================== WARNING ======================
> >>>>>>> 505+This board does not use CONFIG_DM_I2C (Driver Model
> >>>>>>> 506+for I2C drivers). Please update the board to use
> >>>>>>> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
> >>>>>>> 508+update by the deadline may result in board removal.
> >>>>>>> 509+See doc/develop/driver-model/migration.rst for more info.
> >>>>>>> 510+====================================================
> >>>>>>> 511 arm: + cm_t43
> >>>>>>> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> >>>>>>> `nand_init_chip':
> >>>>>>> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> >>>>>>> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
> >>>>>>> 515+make: *** [Makefile:177: sub-make] Error 2
> >>>>>>> 516 arm: w+ am335x_shc_sdboot
> >>>>>>>
> >>>>>>> In both cases failed the "build all 32bit ARM platforms" test.
> >>>>>>>
> >>>>>>> I think you have to run the command:
> >>>>>>> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
> >>>>>>> if you have to run the tests locally.
> >>>>>>>
> >>>>>>> Thanks and regards,
> >>>>>>> Dario
> >>>>>>>
> >>>>>>>>
> >>>>>>>>> I thought it's better you fix the problems. So, I only accepted some
> >>>>>>>>> of the first few patches in the series:
> >>>>>>>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>>>>>>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>>>>>>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>>>>>>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>>>>>>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>>>>>>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>>>>>>>>
> >>>>>>>>> For the others, please fix them to run the tests successfully.
> >>>>>>>>
> >>>>>>>> No problem. I will try to fix and run them through the CI testing myself
> >>>>>>>> before re-posting.
> >>>>>>>>
> >>>>>>>> cheers,
> >>>>>>>> -roger
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>> --
> >>>>>>>
> >>>>>>> Dario Binacchi
> >>>>>>>
> >>>>>>> Embedded Linux Developer
> >>>>>>>
> >>>>>>> dario.binacchi@amarulasolutions.com
> >>>>>>>
> >>>>>>> __________________________________
> >>>>>>>
> >>>>>>>
> >>>>>>> Amarula Solutions SRL
> >>>>>>>
> >>>>>>> Via Le Canevare 30, 31100 Treviso, Veneto, IT
> >>>>>>>
> >>>>>>> T. +39 042 243 5310
> >>>>>>> info@amarulasolutions.com
> >>>>>>>
> >>>>>>> www.amarulasolutions.com
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>
> >>>>
> >>>>
> >>
> >>
> >>
> >> --
> >> Michael Nazzareno Trimarchi
> >> Co-Founder & Chief Executive Officer
> >> M. +39 347 913 2170
> >> michael@amarulasolutions.com
> >> __________________________________
> >>
> >> Amarula Solutions BV
> >> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> >> T. +31 (0)85 111 9172
> >> info@amarulasolutions.com
> >> www.amarulasolutions.com
> >
> >
> >



-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support

[Michael Nazzareno Trimarchi]

Hi

On Sat, Dec 17, 2022 at 3:09 PM Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:
>
> Hi Roger
>
> On Sat, Dec 17, 2022 at 2:59 PM Roger Quadros <rogerq@kernel.org> wrote:
> >
> >
> >
> > On 17/12/2022 15:51, Michael Nazzareno Trimarchi wrote:
> > > Hi
> > >
> > > Minimal diff
> > >
> > > diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
> > > index 458c4558fd..c7f8fd2e25 100644
> > > --- a/configs/chiliboard_defconfig
> > > +++ b/configs/chiliboard_defconfig
> > > @@ -47,12 +47,14 @@ CONFIG_CMD_MTDPARTS=y
> > >  CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand"
> > >  CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
> > >  CONFIG_OF_CONTROL=y
> > > +CONFIG_SPL_OF_CONTROL=y
> > >  CONFIG_ENV_OVERWRITE=y
> > >  CONFIG_ENV_IS_IN_MMC=y
> > >  CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> > >  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> > >  CONFIG_NET_RETRY_COUNT=10
> > >  CONFIG_BOOTP_SEND_HOSTNAME=y
> > > +CONFIG_SPL_DM=y
> > >  CONFIG_BOOTCOUNT_LIMIT=y
> > >  CONFIG_SYS_BOOTCOUNT_BE=y
> > >  CONFIG_SYS_I2C_LEGACY=y
> >
> > This worked perfectly.
> > But this platform my not yet be utilizing DM for NAND/ELM driver yet
> > so is this change acceptable?
> >
>
> Can you restrict to platforms that support it?
>
> I have added the author of this upstream

I will explain it better. I can not test the TI platform for now with
nand, waiting to get one of them. This board was upstream by marcin
and maybe he can test it


Michael

>
> Michael
>
> > cheers,
> > -roger
> >
> > >
> > > On Sat, Dec 17, 2022 at 2:46 PM Michael Nazzareno Trimarchi
> > > <michael@amarulasolutions.com> wrote:
> > >>
> > >> Hi
> > >>
> > >> take my config
> > >>
> > >> Michael
> > >>
> > >> On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>
> > >>> On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
> > >>>> Hi
> > >>>>
> > >>>> On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>>
> > >>>>> Hi Michael & Dario,
> > >>>>>
> > >>>>> On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
> > >>>>>> Hi Roger
> > >>>>>>
> > >>>>>> Most of the building problem can be tested with this configuration
> > >>>>>>
> > >>>>>> make ARCH=arm chiliboard_defconfig
> > >>>>>
> > >>>>> I resolved the original issue for all boards but now face a new issue
> > >>>>> only with the chiliboard.
> > >>>>>
> > >>>>> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource':
> > >>>>> /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource'
> > >>>>>   AR      common/built-in.o
> > >>>>> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> > >>>>> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> > >>>>> make[1]: *** Waiting for unfinished jobs....
> > >>>>> make[1]: Leaving directory '/tmp'
> > >>>>> make: *** [Makefile:177: sub-make] Error 2
> > >>>>>
> > >>>>> The following config options are set
> > >>>>> CONFIG_DM_DEV_READ_INLINE=y
> > >>>>
> > >>>> What happen is that is not set?
> > >>>
> > >>> I removed "default y" for it in drivers/core/Kconfig
> > >>>
> > >>> Now I get
> > >>>
> > >>> arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe':
> > >>> /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource'
> > >>> make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
> > >>> make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2
> > >>> make[1]: *** Waiting for unfinished jobs....
> > >>>
> > >>> cheers,
> > >>> -roger
> > >>>
> > >>>>
> > >>>> Michael
> > >>>>
> > >>>>> CONFIG_SUPPORT_OF_CONTROL=y
> > >>>>>
> > >>>>> My understanding is that in case of spl build (Makefile.spl), the
> > >>>>> drivers/core/ofnode.o does not seem to be included
> > >>>>> thus causing the linking error.
> > >>>>>
> > >>>>> Any suggestions how to fix this?
> > >>>>>
> > >>>>> I've pushed the patches here
> > >>>>> https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
> > >>>>>
> > >>>>> cheers,
> > >>>>> -roger
> > >>>>>
> > >>>>>>
> > >>>>>> Michael
> > >>>>>>
> > >>>>>> On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi
> > >>>>>> <dario.binacchi@amarulasolutions.com> wrote:
> > >>>>>>>
> > >>>>>>> Hi Roger,
> > >>>>>>>
> > >>>>>>> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>>>>>
> > >>>>>>>> Hi Dario,
> > >>>>>>>>
> > >>>>>>>> On 11/12/2022 15:56, Dario Binacchi wrote:
> > >>>>>>>>> Hi Roger,
> > >>>>>>>>>
> > >>>>>>>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>>>>>>>
> > >>>>>>>>>> Hi Michael,
> > >>>>>>>>>>
> > >>>>>>>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> > >>>>>>>>>>> Hi Roger
> > >>>>>>>>>>>
> > >>>>>>>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros <rogerq@kernel.org> wrote:
> > >>>>>>>>>>>>
> > >>>>>>>>>>>> Hi,
> > >>>>>>>>>>>>
> > >>>>>>>>>>>> On 11/10/2022 14:49, Roger Quadros wrote:
> > >>>>>>>>>>>>> Hi,
> > >>>>>>>>>>>>>
> > >>>>>>>>>>>>> This series adds driver model support for rawnand: omap_gpmc
> > >>>>>>>>>>>>> and omap_elm drivers.
> > >>>>>>>>>>>>>
> > >>>>>>>>>>>>> This will enable the driver to be used on K2/K3 platforms as well.
> > >>>>>>>>>>>>
> > >>>>>>>>>>>> Any comments on patches 5 and later? Thanks
> > >>>>>>>>>>>>
> > >>>>>>>>>>>
> > >>>>>>>>>>> We will try to close this week.
> > >>>>>>>>>>
> > >>>>>>>>>> Could you please give your comments on the last few patches. Thanks!
> > >>>>>>>>>>
> > >>>>>>>>>> cheers,
> > >>>>>>>>>> -roger
> > >>>>>>>>>>
> > >>>>>>>>>>>
> > >>>>>>>>>>> Michael
> > >>>>>>>>>>>
> > >>>>>>>>>>>>
> > >>>>>>>>>>>> cheers,
> > >>>>>>>>>>>> -roger
> > >>>>>>>>>>>>
> > >>>>>>>>>>>>>
> > >>>>>>>>>>>>> cheers,
> > >>>>>>>>>>>>> -roger
> > >>>>>>>>>>>>>
> > >>>>>>>>>>>>> Roger Quadros (14):
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Optimize NAND reads
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> > >>>>>>>>>>>>>   mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> > >>>>>>>>>>>>>     nand_bbt
> > >>>>>>>>>>>>>   mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Reduce .bss usage
> > >>>>>>>>>>>>>   dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: support u-boot driver model
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Add SPL NAND support
> > >>>>>>>>>>>>>   mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> > >>>>>>>>>>>>>   dt-bindings: mtd: Add ti,elm DT binding documentation
> > >>>>>>>>>>>>>   mtd: rawnand: omap_elm: u-boot driver model support
> > >>>>>>>>>>>>>
> > >>>>>>>>>>>>>  doc/device-tree-bindings/mtd/ti,elm.yaml      |  72 +++
> > >>>>>>>>>>>>>  .../mtd/ti,gpmc-nand.yaml                     | 129 +++++
> > >>>>>>>>>>>>>  drivers/mtd/nand/raw/Kconfig                  |  11 +-
> > >>>>>>>>>>>>>  drivers/mtd/nand/raw/Makefile                 |   2 +-
> > >>>>>>>>>>>>>  drivers/mtd/nand/raw/nand_base.c              |  18 +-
> > >>>>>>>>>>>>>  drivers/mtd/nand/raw/nand_spl_loaders.c       |   2 +-
> > >>>>>>>>>>>>>  drivers/mtd/nand/raw/omap_elm.c               |  33 +-
> > >>>>>>>>>>>>>  .../mtd => drivers/mtd/nand/raw}/omap_elm.h   |   6 +
> > >>>>>>>>>>>>>  drivers/mtd/nand/raw/omap_gpmc.c              | 500 +++++++++++++-----
> > >>>>>>>>>>>>>  9 files changed, 637 insertions(+), 136 deletions(-)
> > >>>>>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> > >>>>>>>>>>>>>  create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> > >>>>>>>>>>>>>  rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> > >>>>>>>>>>>>>
> > >>>>>>>>>>>
> > >>>>>>>>>>>
> > >>>>>>>>>>>
> > >>>>>>>>>
> > >>>>>>>>> I tried to merge your whole series but after the second fix and the
> > >>>>>>>>> third time the CI/CD pipeline failed
> > >>>>>>>>
> > >>>>>>>> Do you have the link to the failure?
> > >>>>>>>
> > >>>>>>> These are the CI/CD pipelines links:
> > >>>>>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827
> > >>>>>>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876
> > >>>>>>> but I think you don't have permission to access them.
> > >>>>>>>
> > >>>>>>> Anyway:
> > >>>>>>>
> > >>>>>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827:
> > >>>>>>> +====================================================
> > >>>>>>> 345 arm: + am335x_guardian
> > >>>>>>> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip'
> > >>>>>>> defined but not used [-Werror=unused-variable]
> > >>>>>>> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for
> > >>>>>>> SPL use only */
> > >>>>>>> 348+ | ^~~~~~~~~
> > >>>>>>> 349+cc1: all warnings being treated as errors
> > >>>>>>> 350+make[5]: *** [scripts/Makefile.build:258:
> > >>>>>>> drivers/mtd/nand/raw/omap_gpmc.o] Error 1
> > >>>>>>> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2
> > >>>>>>> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2
> > >>>>>>> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2
> > >>>>>>> 354+make[1]: *** [Makefile:1871: drivers] Error 2
> > >>>>>>> 355+make: *** [Makefile:177: sub-make] Error 2
> > >>>>>>>
> > >>>>>>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876:
> > >>>>>>> +====================================================
> > >>>>>>> 498 arm: + chiliboard
> > >>>>>>> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> > >>>>>>> `nand_init_chip':
> > >>>>>>> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> > >>>>>>> 501+make[1]: *** [Makefile:1778: u-boot] Error 1
> > >>>>>>> 502+make: *** [Makefile:177: sub-make] Error 2
> > >>>>>>> 503 arm: w+ am335x_shc_netboot
> > >>>>>>> 504+===================== WARNING ======================
> > >>>>>>> 505+This board does not use CONFIG_DM_I2C (Driver Model
> > >>>>>>> 506+for I2C drivers). Please update the board to use
> > >>>>>>> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to
> > >>>>>>> 508+update by the deadline may result in board removal.
> > >>>>>>> 509+See doc/develop/driver-model/migration.rst for more info.
> > >>>>>>> 510+====================================================
> > >>>>>>> 511 arm: + cm_t43
> > >>>>>>> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function
> > >>>>>>> `nand_init_chip':
> > >>>>>>> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init'
> > >>>>>>> 514+make[1]: *** [Makefile:1778: u-boot] Error 1
> > >>>>>>> 515+make: *** [Makefile:177: sub-make] Error 2
> > >>>>>>> 516 arm: w+ am335x_shc_sdboot
> > >>>>>>>
> > >>>>>>> In both cases failed the "build all 32bit ARM platforms" test.
> > >>>>>>>
> > >>>>>>> I think you have to run the command:
> > >>>>>>> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64
> > >>>>>>> if you have to run the tests locally.
> > >>>>>>>
> > >>>>>>> Thanks and regards,
> > >>>>>>> Dario
> > >>>>>>>
> > >>>>>>>>
> > >>>>>>>>> I thought it's better you fix the problems. So, I only accepted some
> > >>>>>>>>> of the first few patches in the series:
> > >>>>>>>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> > >>>>>>>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> > >>>>>>>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> > >>>>>>>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
> > >>>>>>>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> > >>>>>>>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
> > >>>>>>>>>
> > >>>>>>>>> For the others, please fix them to run the tests successfully.
> > >>>>>>>>
> > >>>>>>>> No problem. I will try to fix and run them through the CI testing myself
> > >>>>>>>> before re-posting.
> > >>>>>>>>
> > >>>>>>>> cheers,
> > >>>>>>>> -roger
> > >>>>>>>
> > >>>>>>>
> > >>>>>>>
> > >>>>>>> --
> > >>>>>>>
> > >>>>>>> Dario Binacchi
> > >>>>>>>
> > >>>>>>> Embedded Linux Developer
> > >>>>>>>
> > >>>>>>> dario.binacchi@amarulasolutions.com
> > >>>>>>>
> > >>>>>>> __________________________________
> > >>>>>>>
> > >>>>>>>
> > >>>>>>> Amarula Solutions SRL
> > >>>>>>>
> > >>>>>>> Via Le Canevare 30, 31100 Treviso, Veneto, IT
> > >>>>>>>
> > >>>>>>> T. +39 042 243 5310
> > >>>>>>> info@amarulasolutions.com
> > >>>>>>>
> > >>>>>>> www.amarulasolutions.com
> > >>>>>>
> > >>>>>>
> > >>>>>>
> > >>>>
> > >>>>
> > >>>>
> > >>
> > >>
> > >>
> > >> --
> > >> Michael Nazzareno Trimarchi
> > >> Co-Founder & Chief Executive Officer
> > >> M. +39 347 913 2170
> > >> michael@amarulasolutions.com
> > >> __________________________________
> > >>
> > >> Amarula Solutions BV
> > >> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> > >> T. +31 (0)85 111 9172
> > >> info@amarulasolutions.com
> > >> www.amarulasolutions.com
> > >
> > >
> > >
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> info@amarulasolutions.com
> www.amarulasolutions.com



--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com