* [PATCH] arm: dts: imx8mq-evk: add phy-reset-gpios for fec1
@ 2020-02-14 17:18 Alifer Moraes
2020-02-14 17:21 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 3+ messages in thread
From: Alifer Moraes @ 2020-02-14 17:18 UTC (permalink / raw)
To: u-boot
Let the driver reset the phy via dts description instead of doing it
through functions in imx8mq_evk.c
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
---
arch/arm/dts/imx8mq-evk.dts | 2 ++
board/freescale/imx8mq_evk/imx8mq_evk.c | 18 ------------------
2 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 3693933451..55294ba9c8 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -104,6 +104,8 @@
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
fsl,magic-packet;
status = "okay";
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
index cb39d0f2d6..b2f464abb1 100644
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -64,29 +64,11 @@ int dram_init(void)
}
#ifdef CONFIG_FEC_MXC
-#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
-static iomux_v3_cfg_t const fec1_rst_pads[] = {
- IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
- ARRAY_SIZE(fec1_rst_pads));
-
- gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
- gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
- udelay(500);
- gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
-}
-
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
- setup_iomux_fec();
-
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
return set_clk_enet(ENET_125MHZ);
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] arm: dts: imx8mq-evk: add phy-reset-gpios for fec1
2020-02-14 17:18 [PATCH] arm: dts: imx8mq-evk: add phy-reset-gpios for fec1 Alifer Moraes
@ 2020-02-14 17:21 ` Michael Nazzareno Trimarchi
[not found] ` <CA+W=15b025G3HQFMZH-N+yvgr4aYUUFH0zTw2Aq7T8+ETx3nGw@mail.gmail.com>
0 siblings, 1 reply; 3+ messages in thread
From: Michael Nazzareno Trimarchi @ 2020-02-14 17:21 UTC (permalink / raw)
To: u-boot
Hi
On Fri, Feb 14, 2020 at 6:18 PM Alifer Moraes <alifer.wsdm@gmail.com> wrote:
>
> Let the driver reset the phy via dts description instead of doing it
> through functions in imx8mq_evk.c
>
> Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
> ---
> arch/arm/dts/imx8mq-evk.dts | 2 ++
> board/freescale/imx8mq_evk/imx8mq_evk.c | 18 ------------------
> 2 files changed, 2 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
> index 3693933451..55294ba9c8 100644
> --- a/arch/arm/dts/imx8mq-evk.dts
> +++ b/arch/arm/dts/imx8mq-evk.dts
> @@ -104,6 +104,8 @@
> pinctrl-0 = <&pinctrl_fec1>;
> phy-mode = "rgmii-id";
> phy-handle = <ðphy0>;
> + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <10>;
Where is the relative pinctrl change to mux the pin? why now is 10 the
reset duration
Michael
> fsl,magic-packet;
> status = "okay";
>
> diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
> index cb39d0f2d6..b2f464abb1 100644
> --- a/board/freescale/imx8mq_evk/imx8mq_evk.c
> +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
> @@ -64,29 +64,11 @@ int dram_init(void)
> }
>
> #ifdef CONFIG_FEC_MXC
> -#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
> -static iomux_v3_cfg_t const fec1_rst_pads[] = {
> - IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
> -};
> -
> -static void setup_iomux_fec(void)
> -{
> - imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> - ARRAY_SIZE(fec1_rst_pads));
> -
> - gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
> - gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
> - udelay(500);
> - gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
> -}
> -
> static int setup_fec(void)
> {
> struct iomuxc_gpr_base_regs *gpr =
> (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
>
> - setup_iomux_fec();
> -
> /* Use 125M anatop REF_CLK1 for ENET1, not from external */
> clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
> return set_clk_enet(ENET_125MHZ);
> --
> 2.17.1
>
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] arm: dts: imx8mq-evk: add phy-reset-gpios for fec1
[not found] ` <CA+W=15b025G3HQFMZH-N+yvgr4aYUUFH0zTw2Aq7T8+ETx3nGw@mail.gmail.com>
@ 2020-02-14 17:36 ` Michael Nazzareno Trimarchi
0 siblings, 0 replies; 3+ messages in thread
From: Michael Nazzareno Trimarchi @ 2020-02-14 17:36 UTC (permalink / raw)
To: u-boot
Hi
On Fri, Feb 14, 2020 at 6:33 PM Alifer Moraes <alifer.wsdm@gmail.com> wrote:
>
> Hello, Michael,
>
> > Where is the relative pinctrl change to mux the pin? why now is 10 the
> > reset duration
>
> The pinctrl change is described in arch/arm/dts/imx8mq-evk.dts in the
> subnode pinctrl_fec1.
Ok, so was already defined the pinmux there.
> The ethernet phy used by this board is an atheros 8031, its datasheet
> says that the reset duration should be 10ms.
Please upload the commit message with this information
Michael
PS: this way to reset is deprecated but uboot I think does not have
the reset at mdio bus level
>
> Regards,
>
> Alifer
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-02-14 17:18 [PATCH] arm: dts: imx8mq-evk: add phy-reset-gpios for fec1 Alifer Moraes
2020-02-14 17:21 ` Michael Nazzareno Trimarchi
[not found] ` <CA+W=15b025G3HQFMZH-N+yvgr4aYUUFH0zTw2Aq7T8+ETx3nGw@mail.gmail.com>
2020-02-14 17:36 ` Michael Nazzareno Trimarchi
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