* [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
This series does first does few cleanups/fixes (PATCH1 to PATCH5) and
adds ONE-REG interface for customizing the SBI interface visible to the
Guest/VM.
The testing of this series has been done with KVMTOOL changes in
riscv_sbi_imp_v1 branch at:
https://github.com/avpatel/kvmtool.git
These patches can also be found in the riscv_kvm_sbi_imp_v1 branch at:
https://github.com/avpatel/linux.git
Anup Patel (9):
RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
RISC-V: KVM: Remove redundant includes of asm/csr.h
RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
RISC-V: Export sbi_get_mvendorid() and friends
RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions
arch/riscv/include/asm/kvm_host.h | 16 ++-
arch/riscv/include/asm/kvm_vcpu_sbi.h | 14 ++-
arch/riscv/include/uapi/asm/kvm.h | 22 ++++
arch/riscv/kernel/sbi.c | 3 +
arch/riscv/kvm/vcpu.c | 82 +++++++++++----
arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++---
arch/riscv/kvm/vcpu_sbi_base.c | 15 ++-
arch/riscv/kvm/vcpu_sbi_hsm.c | 1 -
arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
arch/riscv/kvm/vcpu_sbi_v01.c | 1 -
10 files changed, 244 insertions(+), 56 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
This series does first does few cleanups/fixes (PATCH1 to PATCH5) and
adds ONE-REG interface for customizing the SBI interface visible to the
Guest/VM.
The testing of this series has been done with KVMTOOL changes in
riscv_sbi_imp_v1 branch at:
https://github.com/avpatel/kvmtool.git
These patches can also be found in the riscv_kvm_sbi_imp_v1 branch at:
https://github.com/avpatel/linux.git
Anup Patel (9):
RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
RISC-V: KVM: Remove redundant includes of asm/csr.h
RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
RISC-V: Export sbi_get_mvendorid() and friends
RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions
arch/riscv/include/asm/kvm_host.h | 16 ++-
arch/riscv/include/asm/kvm_vcpu_sbi.h | 14 ++-
arch/riscv/include/uapi/asm/kvm.h | 22 ++++
arch/riscv/kernel/sbi.c | 3 +
arch/riscv/kvm/vcpu.c | 82 +++++++++++----
arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++---
arch/riscv/kvm/vcpu_sbi_base.c | 15 ++-
arch/riscv/kvm/vcpu_sbi_hsm.c | 1 -
arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
arch/riscv/kvm/vcpu_sbi_v01.c | 1 -
10 files changed, 244 insertions(+), 56 deletions(-)
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
The reg_val check in kvm_riscv_vcpu_set_reg_config() should only
be done for isa config register.
Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/kvm/vcpu.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 17d5b3f8c2ee..982a3f5e7130 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -296,12 +296,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
return -EFAULT;
- /* This ONE REG interface is only defined for single letter extensions */
- if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
- return -EINVAL;
-
switch (reg_num) {
case KVM_REG_RISCV_CONFIG_REG(isa):
+ /*
+ * This ONE REG interface is only defined for
+ * single letter extensions.
+ */
+ if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
+ return -EINVAL;
+
if (!vcpu->arch.ran_atleast_once) {
/* Ignore the enable/disable request for certain extensions */
for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
The reg_val check in kvm_riscv_vcpu_set_reg_config() should only
be done for isa config register.
Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/kvm/vcpu.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 17d5b3f8c2ee..982a3f5e7130 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -296,12 +296,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
return -EFAULT;
- /* This ONE REG interface is only defined for single letter extensions */
- if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
- return -EINVAL;
-
switch (reg_num) {
case KVM_REG_RISCV_CONFIG_REG(isa):
+ /*
+ * This ONE REG interface is only defined for
+ * single letter extensions.
+ */
+ if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
+ return -EINVAL;
+
if (!vcpu->arch.ran_atleast_once) {
/* Ignore the enable/disable request for certain extensions */
for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c
so let us remove it.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/kvm/vcpu_sbi_base.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 48f431091cdb..22b9126e2872 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -12,7 +12,6 @@
#include <linux/version.h>
#include <asm/csr.h>
#include <asm/sbi.h>
-#include <asm/kvm_vcpu_timer.h>
#include <asm/kvm_vcpu_sbi.h>
static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c
so let us remove it.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/kvm/vcpu_sbi_base.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 48f431091cdb..22b9126e2872 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -12,7 +12,6 @@
#include <linux/version.h>
#include <asm/csr.h>
#include <asm/sbi.h>
-#include <asm/kvm_vcpu_timer.h>
#include <asm/kvm_vcpu_sbi.h>
static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We should include asm/csr.h only where required so let us remove
redundant includes of this header.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/kvm_host.h | 1 -
arch/riscv/kvm/vcpu_sbi_base.c | 1 -
arch/riscv/kvm/vcpu_sbi_hsm.c | 1 -
arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
arch/riscv/kvm/vcpu_sbi_v01.c | 1 -
5 files changed, 5 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index dbbf43d52623..6502f9099965 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -13,7 +13,6 @@
#include <linux/kvm.h>
#include <linux/kvm_types.h>
#include <linux/spinlock.h>
-#include <asm/csr.h>
#include <asm/hwcap.h>
#include <asm/kvm_vcpu_fp.h>
#include <asm/kvm_vcpu_insn.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 22b9126e2872..0c806f61c629 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -10,7 +10,6 @@
#include <linux/err.h>
#include <linux/kvm_host.h>
#include <linux/version.h>
-#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_sbi.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c
index 239dec0a628a..2e915cafd551 100644
--- a/arch/riscv/kvm/vcpu_sbi_hsm.c
+++ b/arch/riscv/kvm/vcpu_sbi_hsm.c
@@ -9,7 +9,6 @@
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/kvm_host.h>
-#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_sbi.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c
index 4c034d8a606a..03a0198389f0 100644
--- a/arch/riscv/kvm/vcpu_sbi_replace.c
+++ b/arch/riscv/kvm/vcpu_sbi_replace.c
@@ -9,7 +9,6 @@
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/kvm_host.h>
-#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_timer.h>
#include <asm/kvm_vcpu_sbi.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c
index 8a91a14e7139..489f225ee66d 100644
--- a/arch/riscv/kvm/vcpu_sbi_v01.c
+++ b/arch/riscv/kvm/vcpu_sbi_v01.c
@@ -9,7 +9,6 @@
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/kvm_host.h>
-#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_timer.h>
#include <asm/kvm_vcpu_sbi.h>
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We should include asm/csr.h only where required so let us remove
redundant includes of this header.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/kvm_host.h | 1 -
arch/riscv/kvm/vcpu_sbi_base.c | 1 -
arch/riscv/kvm/vcpu_sbi_hsm.c | 1 -
arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
arch/riscv/kvm/vcpu_sbi_v01.c | 1 -
5 files changed, 5 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index dbbf43d52623..6502f9099965 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -13,7 +13,6 @@
#include <linux/kvm.h>
#include <linux/kvm_types.h>
#include <linux/spinlock.h>
-#include <asm/csr.h>
#include <asm/hwcap.h>
#include <asm/kvm_vcpu_fp.h>
#include <asm/kvm_vcpu_insn.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 22b9126e2872..0c806f61c629 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -10,7 +10,6 @@
#include <linux/err.h>
#include <linux/kvm_host.h>
#include <linux/version.h>
-#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_sbi.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c
index 239dec0a628a..2e915cafd551 100644
--- a/arch/riscv/kvm/vcpu_sbi_hsm.c
+++ b/arch/riscv/kvm/vcpu_sbi_hsm.c
@@ -9,7 +9,6 @@
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/kvm_host.h>
-#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_sbi.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c
index 4c034d8a606a..03a0198389f0 100644
--- a/arch/riscv/kvm/vcpu_sbi_replace.c
+++ b/arch/riscv/kvm/vcpu_sbi_replace.c
@@ -9,7 +9,6 @@
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/kvm_host.h>
-#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_timer.h>
#include <asm/kvm_vcpu_sbi.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c
index 8a91a14e7139..489f225ee66d 100644
--- a/arch/riscv/kvm/vcpu_sbi_v01.c
+++ b/arch/riscv/kvm/vcpu_sbi_v01.c
@@ -9,7 +9,6 @@
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/kvm_host.h>
-#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_timer.h>
#include <asm/kvm_vcpu_sbi.h>
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions
because the else-if ladder is quite big now.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/kvm/vcpu.c | 36 ++++++++++++++++++++++--------------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 982a3f5e7130..68c86f632d37 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -544,22 +544,26 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
- if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
+ switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
+ case KVM_REG_RISCV_CONFIG:
return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
+ case KVM_REG_RISCV_CORE:
return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
+ case KVM_REG_RISCV_CSR:
return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
+ case KVM_REG_RISCV_TIMER:
return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
+ case KVM_REG_RISCV_FP_F:
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_F);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
+ case KVM_REG_RISCV_FP_D:
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_D);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
+ case KVM_REG_RISCV_ISA_EXT:
return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
+ default:
+ break;
+ }
return -EINVAL;
}
@@ -567,22 +571,26 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
- if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
+ switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
+ case KVM_REG_RISCV_CONFIG:
return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
+ case KVM_REG_RISCV_CORE:
return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
+ case KVM_REG_RISCV_CSR:
return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
+ case KVM_REG_RISCV_TIMER:
return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
+ case KVM_REG_RISCV_FP_F:
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_F);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
+ case KVM_REG_RISCV_FP_D:
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_D);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
+ case KVM_REG_RISCV_ISA_EXT:
return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
+ default:
+ break;
+ }
return -EINVAL;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions
because the else-if ladder is quite big now.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/kvm/vcpu.c | 36 ++++++++++++++++++++++--------------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 982a3f5e7130..68c86f632d37 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -544,22 +544,26 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
- if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
+ switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
+ case KVM_REG_RISCV_CONFIG:
return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
+ case KVM_REG_RISCV_CORE:
return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
+ case KVM_REG_RISCV_CSR:
return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
+ case KVM_REG_RISCV_TIMER:
return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
+ case KVM_REG_RISCV_FP_F:
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_F);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
+ case KVM_REG_RISCV_FP_D:
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_D);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
+ case KVM_REG_RISCV_ISA_EXT:
return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
+ default:
+ break;
+ }
return -EINVAL;
}
@@ -567,22 +571,26 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
- if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
+ switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
+ case KVM_REG_RISCV_CONFIG:
return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
+ case KVM_REG_RISCV_CORE:
return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
+ case KVM_REG_RISCV_CSR:
return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
+ case KVM_REG_RISCV_TIMER:
return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
+ case KVM_REG_RISCV_FP_F:
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_F);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
+ case KVM_REG_RISCV_FP_D:
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_D);
- else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
+ case KVM_REG_RISCV_ISA_EXT:
return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
+ default:
+ break;
+ }
return -EINVAL;
}
--
2.34.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct
and functions in asm/kvm_vcpu_sbi.h.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/kvm_host.h | 10 ++--------
arch/riscv/include/asm/kvm_vcpu_sbi.h | 6 ++++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 6502f9099965..91c74b09a970 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -16,6 +16,7 @@
#include <asm/hwcap.h>
#include <asm/kvm_vcpu_fp.h>
#include <asm/kvm_vcpu_insn.h>
+#include <asm/kvm_vcpu_sbi.h>
#include <asm/kvm_vcpu_timer.h>
#define KVM_MAX_VCPUS 1024
@@ -94,10 +95,6 @@ struct kvm_arch {
struct kvm_guest_timer timer;
};
-struct kvm_sbi_context {
- int return_handled;
-};
-
struct kvm_cpu_trap {
unsigned long sepc;
unsigned long scause;
@@ -216,7 +213,7 @@ struct kvm_vcpu_arch {
struct kvm_csr_decode csr_decode;
/* SBI context */
- struct kvm_sbi_context sbi_context;
+ struct kvm_vcpu_sbi_context sbi_context;
/* Cache pages needed to program page tables with spinlock held */
struct kvm_mmu_memory_cache mmu_page_cache;
@@ -326,7 +323,4 @@ bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask);
void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu);
void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu);
-int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
-
#endif /* __RISCV_KVM_HOST_H__ */
diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
index d4e3e600beef..f79478a85d2d 100644
--- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
+++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
@@ -14,6 +14,10 @@
#define KVM_SBI_VERSION_MAJOR 1
#define KVM_SBI_VERSION_MINOR 0
+struct kvm_vcpu_sbi_context {
+ int return_handled;
+};
+
struct kvm_vcpu_sbi_extension {
unsigned long extid_start;
unsigned long extid_end;
@@ -31,7 +35,9 @@ void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run);
void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
struct kvm_run *run,
u32 type, u64 flags);
+int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
+int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
#ifdef CONFIG_RISCV_SBI_V01
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01;
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct
and functions in asm/kvm_vcpu_sbi.h.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/kvm_host.h | 10 ++--------
arch/riscv/include/asm/kvm_vcpu_sbi.h | 6 ++++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 6502f9099965..91c74b09a970 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -16,6 +16,7 @@
#include <asm/hwcap.h>
#include <asm/kvm_vcpu_fp.h>
#include <asm/kvm_vcpu_insn.h>
+#include <asm/kvm_vcpu_sbi.h>
#include <asm/kvm_vcpu_timer.h>
#define KVM_MAX_VCPUS 1024
@@ -94,10 +95,6 @@ struct kvm_arch {
struct kvm_guest_timer timer;
};
-struct kvm_sbi_context {
- int return_handled;
-};
-
struct kvm_cpu_trap {
unsigned long sepc;
unsigned long scause;
@@ -216,7 +213,7 @@ struct kvm_vcpu_arch {
struct kvm_csr_decode csr_decode;
/* SBI context */
- struct kvm_sbi_context sbi_context;
+ struct kvm_vcpu_sbi_context sbi_context;
/* Cache pages needed to program page tables with spinlock held */
struct kvm_mmu_memory_cache mmu_page_cache;
@@ -326,7 +323,4 @@ bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask);
void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu);
void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu);
-int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
-
#endif /* __RISCV_KVM_HOST_H__ */
diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
index d4e3e600beef..f79478a85d2d 100644
--- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
+++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
@@ -14,6 +14,10 @@
#define KVM_SBI_VERSION_MAJOR 1
#define KVM_SBI_VERSION_MINOR 0
+struct kvm_vcpu_sbi_context {
+ int return_handled;
+};
+
struct kvm_vcpu_sbi_extension {
unsigned long extid_start;
unsigned long extid_end;
@@ -31,7 +35,9 @@ void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run);
void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
struct kvm_run *run,
u32 type, u64 flags);
+int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
+int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
#ifdef CONFIG_RISCV_SBI_V01
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01;
--
2.34.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
can be used by KVM module so let us export these functions.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/kernel/sbi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422..5c87db8fdff2 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
}
+EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
long sbi_get_marchid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
}
+EXPORT_SYMBOL_GPL(sbi_get_marchid);
long sbi_get_mimpid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
}
+EXPORT_SYMBOL_GPL(sbi_get_mimpid);
static void sbi_send_cpumask_ipi(const struct cpumask *target)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
can be used by KVM module so let us export these functions.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/kernel/sbi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422..5c87db8fdff2 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
}
+EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
long sbi_get_marchid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
}
+EXPORT_SYMBOL_GPL(sbi_get_marchid);
long sbi_get_mimpid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
}
+EXPORT_SYMBOL_GPL(sbi_get_mimpid);
static void sbi_send_cpumask_ipi(const struct cpumask *target)
{
--
2.34.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We should save VCPU mvendorid, marchid, and mimpid at the time
of creating VCPU so that we don't have to do host SBI call every
time Guest/VM ask for these details.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/kvm_host.h | 5 +++++
arch/riscv/kvm/vcpu.c | 6 ++++++
arch/riscv/kvm/vcpu_sbi_base.c | 11 +++++------
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 91c74b09a970..93f43a3e7886 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -165,6 +165,11 @@ struct kvm_vcpu_arch {
/* ISA feature bits (similar to MISA) */
DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
+ /* Vendor, Arch, and Implementation details */
+ unsigned long mvendorid;
+ unsigned long marchid;
+ unsigned long mimpid;
+
/* SSCRATCH, STVEC, and SCOUNTEREN of Host */
unsigned long host_sscratch;
unsigned long host_stvec;
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 68c86f632d37..312a8a926867 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -21,6 +21,7 @@
#include <asm/csr.h>
#include <asm/cacheflush.h>
#include <asm/hwcap.h>
+#include <asm/sbi.h>
const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
KVM_GENERIC_VCPU_STATS(),
@@ -171,6 +172,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
set_bit(host_isa, vcpu->arch.isa);
}
+ /* Setup vendor, arch, and implementation details */
+ vcpu->arch.mvendorid = sbi_get_mvendorid();
+ vcpu->arch.marchid = sbi_get_marchid();
+ vcpu->arch.mimpid = sbi_get_mimpid();
+
/* Setup VCPU hfence queue */
spin_lock_init(&vcpu->arch.hfence_lock);
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 0c806f61c629..5d65c634d301 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -19,7 +19,6 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
{
int ret = 0;
struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
- struct sbiret ecall_ret;
switch (cp->a6) {
case SBI_EXT_BASE_GET_SPEC_VERSION:
@@ -48,13 +47,13 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
*out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
break;
case SBI_EXT_BASE_GET_MVENDORID:
+ *out_val = vcpu->arch.mvendorid;
+ break;
case SBI_EXT_BASE_GET_MARCHID:
+ *out_val = vcpu->arch.marchid;
+ break;
case SBI_EXT_BASE_GET_MIMPID:
- ecall_ret = sbi_ecall(SBI_EXT_BASE, cp->a6, 0, 0, 0, 0, 0, 0);
- if (!ecall_ret.error)
- *out_val = ecall_ret.value;
- /*TODO: We are unnecessarily converting the error twice */
- ret = sbi_err_map_linux_errno(ecall_ret.error);
+ *out_val = vcpu->arch.mimpid;
break;
default:
ret = -EOPNOTSUPP;
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We should save VCPU mvendorid, marchid, and mimpid at the time
of creating VCPU so that we don't have to do host SBI call every
time Guest/VM ask for these details.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/kvm_host.h | 5 +++++
arch/riscv/kvm/vcpu.c | 6 ++++++
arch/riscv/kvm/vcpu_sbi_base.c | 11 +++++------
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 91c74b09a970..93f43a3e7886 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -165,6 +165,11 @@ struct kvm_vcpu_arch {
/* ISA feature bits (similar to MISA) */
DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
+ /* Vendor, Arch, and Implementation details */
+ unsigned long mvendorid;
+ unsigned long marchid;
+ unsigned long mimpid;
+
/* SSCRATCH, STVEC, and SCOUNTEREN of Host */
unsigned long host_sscratch;
unsigned long host_stvec;
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 68c86f632d37..312a8a926867 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -21,6 +21,7 @@
#include <asm/csr.h>
#include <asm/cacheflush.h>
#include <asm/hwcap.h>
+#include <asm/sbi.h>
const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
KVM_GENERIC_VCPU_STATS(),
@@ -171,6 +172,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
set_bit(host_isa, vcpu->arch.isa);
}
+ /* Setup vendor, arch, and implementation details */
+ vcpu->arch.mvendorid = sbi_get_mvendorid();
+ vcpu->arch.marchid = sbi_get_marchid();
+ vcpu->arch.mimpid = sbi_get_mimpid();
+
/* Setup VCPU hfence queue */
spin_lock_init(&vcpu->arch.hfence_lock);
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 0c806f61c629..5d65c634d301 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -19,7 +19,6 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
{
int ret = 0;
struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
- struct sbiret ecall_ret;
switch (cp->a6) {
case SBI_EXT_BASE_GET_SPEC_VERSION:
@@ -48,13 +47,13 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
*out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
break;
case SBI_EXT_BASE_GET_MVENDORID:
+ *out_val = vcpu->arch.mvendorid;
+ break;
case SBI_EXT_BASE_GET_MARCHID:
+ *out_val = vcpu->arch.marchid;
+ break;
case SBI_EXT_BASE_GET_MIMPID:
- ecall_ret = sbi_ecall(SBI_EXT_BASE, cp->a6, 0, 0, 0, 0, 0, 0);
- if (!ecall_ret.error)
- *out_val = ecall_ret.value;
- /*TODO: We are unnecessarily converting the error twice */
- ret = sbi_err_map_linux_errno(ecall_ret.error);
+ *out_val = vcpu->arch.mimpid;
break;
default:
ret = -EOPNOTSUPP;
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
so that KVM user-space can change this details to support migration
across heterogeneous hosts.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/uapi/asm/kvm.h | 3 +++
arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 8985ff234c01..92af6f3f057c 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -49,6 +49,9 @@ struct kvm_sregs {
struct kvm_riscv_config {
unsigned long isa;
unsigned long zicbom_block_size;
+ unsigned long mvendorid;
+ unsigned long marchid;
+ unsigned long mimpid;
};
/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 312a8a926867..7c08567097f0 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
return -EINVAL;
reg_val = riscv_cbom_block_size;
break;
+ case KVM_REG_RISCV_CONFIG_REG(mvendorid):
+ reg_val = vcpu->arch.mvendorid;
+ break;
+ case KVM_REG_RISCV_CONFIG_REG(marchid):
+ reg_val = vcpu->arch.marchid;
+ break;
+ case KVM_REG_RISCV_CONFIG_REG(mimpid):
+ reg_val = vcpu->arch.mimpid;
+ break;
default:
return -EINVAL;
}
@@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
break;
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
return -EOPNOTSUPP;
+ case KVM_REG_RISCV_CONFIG_REG(mvendorid):
+ if (!vcpu->arch.ran_atleast_once)
+ vcpu->arch.mvendorid = reg_val;
+ else
+ return -EBUSY;
+ break;
+ case KVM_REG_RISCV_CONFIG_REG(marchid):
+ if (!vcpu->arch.ran_atleast_once)
+ vcpu->arch.marchid = reg_val;
+ else
+ return -EBUSY;
+ break;
+ case KVM_REG_RISCV_CONFIG_REG(mimpid):
+ if (!vcpu->arch.ran_atleast_once)
+ vcpu->arch.mimpid = reg_val;
+ else
+ return -EBUSY;
+ break;
default:
return -EINVAL;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
so that KVM user-space can change this details to support migration
across heterogeneous hosts.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/uapi/asm/kvm.h | 3 +++
arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 8985ff234c01..92af6f3f057c 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -49,6 +49,9 @@ struct kvm_sregs {
struct kvm_riscv_config {
unsigned long isa;
unsigned long zicbom_block_size;
+ unsigned long mvendorid;
+ unsigned long marchid;
+ unsigned long mimpid;
};
/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 312a8a926867..7c08567097f0 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
return -EINVAL;
reg_val = riscv_cbom_block_size;
break;
+ case KVM_REG_RISCV_CONFIG_REG(mvendorid):
+ reg_val = vcpu->arch.mvendorid;
+ break;
+ case KVM_REG_RISCV_CONFIG_REG(marchid):
+ reg_val = vcpu->arch.marchid;
+ break;
+ case KVM_REG_RISCV_CONFIG_REG(mimpid):
+ reg_val = vcpu->arch.mimpid;
+ break;
default:
return -EINVAL;
}
@@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
break;
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
return -EOPNOTSUPP;
+ case KVM_REG_RISCV_CONFIG_REG(mvendorid):
+ if (!vcpu->arch.ran_atleast_once)
+ vcpu->arch.mvendorid = reg_val;
+ else
+ return -EBUSY;
+ break;
+ case KVM_REG_RISCV_CONFIG_REG(marchid):
+ if (!vcpu->arch.ran_atleast_once)
+ vcpu->arch.marchid = reg_val;
+ else
+ return -EBUSY;
+ break;
+ case KVM_REG_RISCV_CONFIG_REG(mimpid):
+ if (!vcpu->arch.ran_atleast_once)
+ vcpu->arch.mimpid = reg_val;
+ else
+ return -EBUSY;
+ break;
default:
return -EINVAL;
}
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 16:14 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We add ONE_REG interface to enable/disable SBI extensions (just
like the ONE_REG interface for ISA extensions). This allows KVM
user-space to decide the set of SBI extension enabled for a Guest
and by default all SBI extensions are enabled.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/kvm_vcpu_sbi.h | 8 +-
arch/riscv/include/uapi/asm/kvm.h | 19 ++++
arch/riscv/kvm/vcpu.c | 2 +
arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++---
arch/riscv/kvm/vcpu_sbi_base.c | 2 +-
5 files changed, 158 insertions(+), 18 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
index f79478a85d2d..baa342dadf95 100644
--- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
+++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
@@ -16,6 +16,7 @@
struct kvm_vcpu_sbi_context {
int return_handled;
+ bool extension_disabled[KVM_RISCV_SBI_EXT_MAX];
};
struct kvm_vcpu_sbi_extension {
@@ -36,7 +37,12 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
struct kvm_run *run,
u32 type, u64 flags);
int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
-const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
+int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg);
+int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg);
+const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
+ struct kvm_vcpu *vcpu, unsigned long extid);
int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
#ifdef CONFIG_RISCV_SBI_V01
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 92af6f3f057c..71992ff1f9dd 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -108,6 +108,22 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_MAX,
};
+/*
+ * SBI extension IDs specific to KVM. This is not the same as the SBI
+ * extension IDs defined by the RISC-V SBI specification.
+ */
+enum KVM_RISCV_SBI_EXT_ID {
+ KVM_RISCV_SBI_EXT_V01 = 0,
+ KVM_RISCV_SBI_EXT_TIME,
+ KVM_RISCV_SBI_EXT_IPI,
+ KVM_RISCV_SBI_EXT_RFENCE,
+ KVM_RISCV_SBI_EXT_SRST,
+ KVM_RISCV_SBI_EXT_HSM,
+ KVM_RISCV_SBI_EXT_EXPERIMENTAL,
+ KVM_RISCV_SBI_EXT_VENDOR,
+ KVM_RISCV_SBI_EXT_MAX,
+};
+
/* Possible states for kvm_riscv_timer */
#define KVM_RISCV_TIMER_STATE_OFF 0
#define KVM_RISCV_TIMER_STATE_ON 1
@@ -152,6 +168,9 @@ enum KVM_RISCV_ISA_EXT_ID {
/* ISA Extension registers are mapped as type 7 */
#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
+/* SBI extension registers are mapped as type 8 */
+#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
+
#endif
#endif /* __LINUX_KVM_RISCV_H */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 7c08567097f0..2260adaf2de8 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -594,6 +594,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
KVM_REG_RISCV_FP_D);
case KVM_REG_RISCV_ISA_EXT:
return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
+ case KVM_REG_RISCV_SBI_EXT:
+ return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg);
default:
break;
}
diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
index f96991d230bf..0abb44f8f4d1 100644
--- a/arch/riscv/kvm/vcpu_sbi.c
+++ b/arch/riscv/kvm/vcpu_sbi.c
@@ -40,16 +40,48 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = {
};
#endif
-static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
- &vcpu_sbi_ext_v01,
- &vcpu_sbi_ext_base,
- &vcpu_sbi_ext_time,
- &vcpu_sbi_ext_ipi,
- &vcpu_sbi_ext_rfence,
- &vcpu_sbi_ext_srst,
- &vcpu_sbi_ext_hsm,
- &vcpu_sbi_ext_experimental,
- &vcpu_sbi_ext_vendor,
+struct kvm_riscv_sbi_extension_entry {
+ enum KVM_RISCV_SBI_EXT_ID dis_idx;
+ const struct kvm_vcpu_sbi_extension *ext_ptr;
+};
+
+static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = {
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_V01,
+ .ext_ptr = &vcpu_sbi_ext_v01,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_MAX, /* Can't be disabled */
+ .ext_ptr = &vcpu_sbi_ext_base,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_TIME,
+ .ext_ptr = &vcpu_sbi_ext_time,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_IPI,
+ .ext_ptr = &vcpu_sbi_ext_ipi,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_RFENCE,
+ .ext_ptr = &vcpu_sbi_ext_rfence,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_SRST,
+ .ext_ptr = &vcpu_sbi_ext_srst,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_HSM,
+ .ext_ptr = &vcpu_sbi_ext_hsm,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_EXPERIMENTAL,
+ .ext_ptr = &vcpu_sbi_ext_experimental,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_VENDOR,
+ .ext_ptr = &vcpu_sbi_ext_vendor,
+ },
};
void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
@@ -108,14 +140,95 @@ int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
return 0;
}
-const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid)
+int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg)
+{
+ unsigned long __user *uaddr =
+ (unsigned long __user *)(unsigned long)reg->addr;
+ unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
+ KVM_REG_SIZE_MASK |
+ KVM_REG_RISCV_SBI_EXT);
+ unsigned long i, reg_val;
+ const struct kvm_riscv_sbi_extension_entry *sext = NULL;
+ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
+
+ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
+ return -EINVAL;
+
+ if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
+ return -EFAULT;
+
+ if (reg_num >= KVM_RISCV_SBI_EXT_MAX ||
+ (reg_val != 1 && reg_val != 0))
+ return -EINVAL;
+
+ if (vcpu->arch.ran_atleast_once)
+ return -EBUSY;
+
+ for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
+ if (sbi_ext[i].dis_idx == reg_num) {
+ sext = &sbi_ext[i];
+ break;
+ }
+ }
+ if (!sext)
+ return -ENOENT;
+
+ scontext->extension_disabled[sext->dis_idx] = !reg_val;
+
+ return 0;
+}
+
+int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg)
+{
+ unsigned long __user *uaddr =
+ (unsigned long __user *)(unsigned long)reg->addr;
+ unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
+ KVM_REG_SIZE_MASK |
+ KVM_REG_RISCV_SBI_EXT);
+ unsigned long i, reg_val;
+ const struct kvm_riscv_sbi_extension_entry *sext = NULL;
+ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
+
+ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
+ return -EINVAL;
+
+ if (reg_num >= KVM_RISCV_SBI_EXT_MAX)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
+ if (sbi_ext[i].dis_idx == reg_num) {
+ sext = &sbi_ext[i];
+ break;
+ }
+ }
+ if (!sext)
+ return -ENOENT;
+
+ reg_val = !scontext->extension_disabled[sext->dis_idx];
+ if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
+ return -EFAULT;
+
+ return 0;
+}
+
+const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
+ struct kvm_vcpu *vcpu, unsigned long extid)
{
- int i = 0;
+ int i;
+ const struct kvm_riscv_sbi_extension_entry *sext;
+ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
- if (sbi_ext[i]->extid_start <= extid &&
- sbi_ext[i]->extid_end >= extid)
- return sbi_ext[i];
+ sext = &sbi_ext[i];
+ if (sext->ext_ptr->extid_start <= extid &&
+ sext->ext_ptr->extid_end >= extid) {
+ if (sext->dis_idx < KVM_RISCV_SBI_EXT_MAX &&
+ scontext->extension_disabled[sext->dis_idx])
+ return NULL;
+ return sbi_ext[i].ext_ptr;
+ }
}
return NULL;
@@ -132,7 +245,7 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run)
unsigned long out_val = 0;
bool ext_is_v01 = false;
- sbi_ext = kvm_vcpu_sbi_find_ext(cp->a7);
+ sbi_ext = kvm_vcpu_sbi_find_ext(vcpu, cp->a7);
if (sbi_ext && sbi_ext->handler) {
#ifdef CONFIG_RISCV_SBI_V01
if (cp->a7 >= SBI_EXT_0_1_SET_TIMER &&
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 5d65c634d301..a51ed0c615bf 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -44,7 +44,7 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
kvm_riscv_vcpu_sbi_forward(vcpu, run);
*exit = true;
} else
- *out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
+ *out_val = kvm_vcpu_sbi_find_ext(vcpu, cp->a0) ? 1 : 0;
break;
case SBI_EXT_BASE_GET_MVENDORID:
*out_val = vcpu->arch.mvendorid;
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions
@ 2022-11-28 16:14 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-11-28 16:14 UTC (permalink / raw)
To: Paolo Bonzini, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Andrew Jones, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, Anup Patel
We add ONE_REG interface to enable/disable SBI extensions (just
like the ONE_REG interface for ISA extensions). This allows KVM
user-space to decide the set of SBI extension enabled for a Guest
and by default all SBI extensions are enabled.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/kvm_vcpu_sbi.h | 8 +-
arch/riscv/include/uapi/asm/kvm.h | 19 ++++
arch/riscv/kvm/vcpu.c | 2 +
arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++---
arch/riscv/kvm/vcpu_sbi_base.c | 2 +-
5 files changed, 158 insertions(+), 18 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
index f79478a85d2d..baa342dadf95 100644
--- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
+++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
@@ -16,6 +16,7 @@
struct kvm_vcpu_sbi_context {
int return_handled;
+ bool extension_disabled[KVM_RISCV_SBI_EXT_MAX];
};
struct kvm_vcpu_sbi_extension {
@@ -36,7 +37,12 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
struct kvm_run *run,
u32 type, u64 flags);
int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
-const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
+int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg);
+int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg);
+const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
+ struct kvm_vcpu *vcpu, unsigned long extid);
int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
#ifdef CONFIG_RISCV_SBI_V01
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 92af6f3f057c..71992ff1f9dd 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -108,6 +108,22 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_MAX,
};
+/*
+ * SBI extension IDs specific to KVM. This is not the same as the SBI
+ * extension IDs defined by the RISC-V SBI specification.
+ */
+enum KVM_RISCV_SBI_EXT_ID {
+ KVM_RISCV_SBI_EXT_V01 = 0,
+ KVM_RISCV_SBI_EXT_TIME,
+ KVM_RISCV_SBI_EXT_IPI,
+ KVM_RISCV_SBI_EXT_RFENCE,
+ KVM_RISCV_SBI_EXT_SRST,
+ KVM_RISCV_SBI_EXT_HSM,
+ KVM_RISCV_SBI_EXT_EXPERIMENTAL,
+ KVM_RISCV_SBI_EXT_VENDOR,
+ KVM_RISCV_SBI_EXT_MAX,
+};
+
/* Possible states for kvm_riscv_timer */
#define KVM_RISCV_TIMER_STATE_OFF 0
#define KVM_RISCV_TIMER_STATE_ON 1
@@ -152,6 +168,9 @@ enum KVM_RISCV_ISA_EXT_ID {
/* ISA Extension registers are mapped as type 7 */
#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
+/* SBI extension registers are mapped as type 8 */
+#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
+
#endif
#endif /* __LINUX_KVM_RISCV_H */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 7c08567097f0..2260adaf2de8 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -594,6 +594,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
KVM_REG_RISCV_FP_D);
case KVM_REG_RISCV_ISA_EXT:
return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
+ case KVM_REG_RISCV_SBI_EXT:
+ return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg);
default:
break;
}
diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
index f96991d230bf..0abb44f8f4d1 100644
--- a/arch/riscv/kvm/vcpu_sbi.c
+++ b/arch/riscv/kvm/vcpu_sbi.c
@@ -40,16 +40,48 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = {
};
#endif
-static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
- &vcpu_sbi_ext_v01,
- &vcpu_sbi_ext_base,
- &vcpu_sbi_ext_time,
- &vcpu_sbi_ext_ipi,
- &vcpu_sbi_ext_rfence,
- &vcpu_sbi_ext_srst,
- &vcpu_sbi_ext_hsm,
- &vcpu_sbi_ext_experimental,
- &vcpu_sbi_ext_vendor,
+struct kvm_riscv_sbi_extension_entry {
+ enum KVM_RISCV_SBI_EXT_ID dis_idx;
+ const struct kvm_vcpu_sbi_extension *ext_ptr;
+};
+
+static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = {
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_V01,
+ .ext_ptr = &vcpu_sbi_ext_v01,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_MAX, /* Can't be disabled */
+ .ext_ptr = &vcpu_sbi_ext_base,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_TIME,
+ .ext_ptr = &vcpu_sbi_ext_time,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_IPI,
+ .ext_ptr = &vcpu_sbi_ext_ipi,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_RFENCE,
+ .ext_ptr = &vcpu_sbi_ext_rfence,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_SRST,
+ .ext_ptr = &vcpu_sbi_ext_srst,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_HSM,
+ .ext_ptr = &vcpu_sbi_ext_hsm,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_EXPERIMENTAL,
+ .ext_ptr = &vcpu_sbi_ext_experimental,
+ },
+ {
+ .dis_idx = KVM_RISCV_SBI_EXT_VENDOR,
+ .ext_ptr = &vcpu_sbi_ext_vendor,
+ },
};
void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
@@ -108,14 +140,95 @@ int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
return 0;
}
-const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid)
+int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg)
+{
+ unsigned long __user *uaddr =
+ (unsigned long __user *)(unsigned long)reg->addr;
+ unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
+ KVM_REG_SIZE_MASK |
+ KVM_REG_RISCV_SBI_EXT);
+ unsigned long i, reg_val;
+ const struct kvm_riscv_sbi_extension_entry *sext = NULL;
+ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
+
+ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
+ return -EINVAL;
+
+ if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
+ return -EFAULT;
+
+ if (reg_num >= KVM_RISCV_SBI_EXT_MAX ||
+ (reg_val != 1 && reg_val != 0))
+ return -EINVAL;
+
+ if (vcpu->arch.ran_atleast_once)
+ return -EBUSY;
+
+ for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
+ if (sbi_ext[i].dis_idx == reg_num) {
+ sext = &sbi_ext[i];
+ break;
+ }
+ }
+ if (!sext)
+ return -ENOENT;
+
+ scontext->extension_disabled[sext->dis_idx] = !reg_val;
+
+ return 0;
+}
+
+int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg)
+{
+ unsigned long __user *uaddr =
+ (unsigned long __user *)(unsigned long)reg->addr;
+ unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
+ KVM_REG_SIZE_MASK |
+ KVM_REG_RISCV_SBI_EXT);
+ unsigned long i, reg_val;
+ const struct kvm_riscv_sbi_extension_entry *sext = NULL;
+ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
+
+ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
+ return -EINVAL;
+
+ if (reg_num >= KVM_RISCV_SBI_EXT_MAX)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
+ if (sbi_ext[i].dis_idx == reg_num) {
+ sext = &sbi_ext[i];
+ break;
+ }
+ }
+ if (!sext)
+ return -ENOENT;
+
+ reg_val = !scontext->extension_disabled[sext->dis_idx];
+ if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
+ return -EFAULT;
+
+ return 0;
+}
+
+const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
+ struct kvm_vcpu *vcpu, unsigned long extid)
{
- int i = 0;
+ int i;
+ const struct kvm_riscv_sbi_extension_entry *sext;
+ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
- if (sbi_ext[i]->extid_start <= extid &&
- sbi_ext[i]->extid_end >= extid)
- return sbi_ext[i];
+ sext = &sbi_ext[i];
+ if (sext->ext_ptr->extid_start <= extid &&
+ sext->ext_ptr->extid_end >= extid) {
+ if (sext->dis_idx < KVM_RISCV_SBI_EXT_MAX &&
+ scontext->extension_disabled[sext->dis_idx])
+ return NULL;
+ return sbi_ext[i].ext_ptr;
+ }
}
return NULL;
@@ -132,7 +245,7 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run)
unsigned long out_val = 0;
bool ext_is_v01 = false;
- sbi_ext = kvm_vcpu_sbi_find_ext(cp->a7);
+ sbi_ext = kvm_vcpu_sbi_find_ext(vcpu, cp->a7);
if (sbi_ext && sbi_ext->handler) {
#ifdef CONFIG_RISCV_SBI_V01
if (cp->a7 >= SBI_EXT_0_1_SET_TIMER &&
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 5d65c634d301..a51ed0c615bf 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -44,7 +44,7 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
kvm_riscv_vcpu_sbi_forward(vcpu, run);
*exit = true;
} else
- *out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
+ *out_val = kvm_vcpu_sbi_find_ext(vcpu, cp->a0) ? 1 : 0;
break;
case SBI_EXT_BASE_GET_MVENDORID:
*out_val = vcpu->arch.mvendorid;
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 21:03 ` Atish Patra
-1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:03 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The reg_val check in kvm_riscv_vcpu_set_reg_config() should only
> be done for isa config register.
>
> Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 17d5b3f8c2ee..982a3f5e7130 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -296,12 +296,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
> return -EFAULT;
>
> - /* This ONE REG interface is only defined for single letter extensions */
> - if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
> - return -EINVAL;
> -
> switch (reg_num) {
> case KVM_REG_RISCV_CONFIG_REG(isa):
> + /*
> + * This ONE REG interface is only defined for
> + * single letter extensions.
> + */
> + if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
> + return -EINVAL;
> +
> if (!vcpu->arch.ran_atleast_once) {
> /* Ignore the enable/disable request for certain extensions */
> for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
@ 2022-11-28 21:03 ` Atish Patra
0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:03 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The reg_val check in kvm_riscv_vcpu_set_reg_config() should only
> be done for isa config register.
>
> Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 17d5b3f8c2ee..982a3f5e7130 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -296,12 +296,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
> return -EFAULT;
>
> - /* This ONE REG interface is only defined for single letter extensions */
> - if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
> - return -EINVAL;
> -
> switch (reg_num) {
> case KVM_REG_RISCV_CONFIG_REG(isa):
> + /*
> + * This ONE REG interface is only defined for
> + * single letter extensions.
> + */
> + if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
> + return -EINVAL;
> +
> if (!vcpu->arch.ran_atleast_once) {
> /* Ignore the enable/disable request for certain extensions */
> for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 21:04 ` Atish Patra
-1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:04 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c
> so let us remove it.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu_sbi_base.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 48f431091cdb..22b9126e2872 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -12,7 +12,6 @@
> #include <linux/version.h>
> #include <asm/csr.h>
> #include <asm/sbi.h>
> -#include <asm/kvm_vcpu_timer.h>
> #include <asm/kvm_vcpu_sbi.h>
>
> static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
@ 2022-11-28 21:04 ` Atish Patra
0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:04 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c
> so let us remove it.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu_sbi_base.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 48f431091cdb..22b9126e2872 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -12,7 +12,6 @@
> #include <linux/version.h>
> #include <asm/csr.h>
> #include <asm/sbi.h>
> -#include <asm/kvm_vcpu_timer.h>
> #include <asm/kvm_vcpu_sbi.h>
>
> static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 21:04 ` Atish Patra
-1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:04 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should include asm/csr.h only where required so let us remove
> redundant includes of this header.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 -
> arch/riscv/kvm/vcpu_sbi_base.c | 1 -
> arch/riscv/kvm/vcpu_sbi_hsm.c | 1 -
> arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
> arch/riscv/kvm/vcpu_sbi_v01.c | 1 -
> 5 files changed, 5 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index dbbf43d52623..6502f9099965 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -13,7 +13,6 @@
> #include <linux/kvm.h>
> #include <linux/kvm_types.h>
> #include <linux/spinlock.h>
> -#include <asm/csr.h>
> #include <asm/hwcap.h>
> #include <asm/kvm_vcpu_fp.h>
> #include <asm/kvm_vcpu_insn.h>
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 22b9126e2872..0c806f61c629 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -10,7 +10,6 @@
> #include <linux/err.h>
> #include <linux/kvm_host.h>
> #include <linux/version.h>
> -#include <asm/csr.h>
> #include <asm/sbi.h>
> #include <asm/kvm_vcpu_sbi.h>
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c
> index 239dec0a628a..2e915cafd551 100644
> --- a/arch/riscv/kvm/vcpu_sbi_hsm.c
> +++ b/arch/riscv/kvm/vcpu_sbi_hsm.c
> @@ -9,7 +9,6 @@
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/kvm_host.h>
> -#include <asm/csr.h>
> #include <asm/sbi.h>
> #include <asm/kvm_vcpu_sbi.h>
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c
> index 4c034d8a606a..03a0198389f0 100644
> --- a/arch/riscv/kvm/vcpu_sbi_replace.c
> +++ b/arch/riscv/kvm/vcpu_sbi_replace.c
> @@ -9,7 +9,6 @@
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/kvm_host.h>
> -#include <asm/csr.h>
> #include <asm/sbi.h>
> #include <asm/kvm_vcpu_timer.h>
> #include <asm/kvm_vcpu_sbi.h>
> diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c
> index 8a91a14e7139..489f225ee66d 100644
> --- a/arch/riscv/kvm/vcpu_sbi_v01.c
> +++ b/arch/riscv/kvm/vcpu_sbi_v01.c
> @@ -9,7 +9,6 @@
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/kvm_host.h>
> -#include <asm/csr.h>
> #include <asm/sbi.h>
> #include <asm/kvm_vcpu_timer.h>
> #include <asm/kvm_vcpu_sbi.h>
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h
@ 2022-11-28 21:04 ` Atish Patra
0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:04 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should include asm/csr.h only where required so let us remove
> redundant includes of this header.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 -
> arch/riscv/kvm/vcpu_sbi_base.c | 1 -
> arch/riscv/kvm/vcpu_sbi_hsm.c | 1 -
> arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
> arch/riscv/kvm/vcpu_sbi_v01.c | 1 -
> 5 files changed, 5 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index dbbf43d52623..6502f9099965 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -13,7 +13,6 @@
> #include <linux/kvm.h>
> #include <linux/kvm_types.h>
> #include <linux/spinlock.h>
> -#include <asm/csr.h>
> #include <asm/hwcap.h>
> #include <asm/kvm_vcpu_fp.h>
> #include <asm/kvm_vcpu_insn.h>
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 22b9126e2872..0c806f61c629 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -10,7 +10,6 @@
> #include <linux/err.h>
> #include <linux/kvm_host.h>
> #include <linux/version.h>
> -#include <asm/csr.h>
> #include <asm/sbi.h>
> #include <asm/kvm_vcpu_sbi.h>
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c
> index 239dec0a628a..2e915cafd551 100644
> --- a/arch/riscv/kvm/vcpu_sbi_hsm.c
> +++ b/arch/riscv/kvm/vcpu_sbi_hsm.c
> @@ -9,7 +9,6 @@
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/kvm_host.h>
> -#include <asm/csr.h>
> #include <asm/sbi.h>
> #include <asm/kvm_vcpu_sbi.h>
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c
> index 4c034d8a606a..03a0198389f0 100644
> --- a/arch/riscv/kvm/vcpu_sbi_replace.c
> +++ b/arch/riscv/kvm/vcpu_sbi_replace.c
> @@ -9,7 +9,6 @@
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/kvm_host.h>
> -#include <asm/csr.h>
> #include <asm/sbi.h>
> #include <asm/kvm_vcpu_timer.h>
> #include <asm/kvm_vcpu_sbi.h>
> diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c
> index 8a91a14e7139..489f225ee66d 100644
> --- a/arch/riscv/kvm/vcpu_sbi_v01.c
> +++ b/arch/riscv/kvm/vcpu_sbi_v01.c
> @@ -9,7 +9,6 @@
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/kvm_host.h>
> -#include <asm/csr.h>
> #include <asm/sbi.h>
> #include <asm/kvm_vcpu_timer.h>
> #include <asm/kvm_vcpu_sbi.h>
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 21:04 ` Atish Patra
-1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:04 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions
> because the else-if ladder is quite big now.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu.c | 36 ++++++++++++++++++++++--------------
> 1 file changed, 22 insertions(+), 14 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 982a3f5e7130..68c86f632d37 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -544,22 +544,26 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
> static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
> + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
> + case KVM_REG_RISCV_CONFIG:
> return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
> + case KVM_REG_RISCV_CORE:
> return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
> + case KVM_REG_RISCV_CSR:
> return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> + case KVM_REG_RISCV_TIMER:
> return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + case KVM_REG_RISCV_FP_F:
> return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_F);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + case KVM_REG_RISCV_FP_D:
> return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_D);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
> + case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
> + default:
> + break;
> + }
>
> return -EINVAL;
> }
> @@ -567,22 +571,26 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
> + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
> + case KVM_REG_RISCV_CONFIG:
> return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
> + case KVM_REG_RISCV_CORE:
> return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
> + case KVM_REG_RISCV_CSR:
> return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> + case KVM_REG_RISCV_TIMER:
> return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + case KVM_REG_RISCV_FP_F:
> return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_F);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + case KVM_REG_RISCV_FP_D:
> return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_D);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
> + case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
> + default:
> + break;
> + }
>
> return -EINVAL;
> }
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
@ 2022-11-28 21:04 ` Atish Patra
0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:04 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions
> because the else-if ladder is quite big now.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu.c | 36 ++++++++++++++++++++++--------------
> 1 file changed, 22 insertions(+), 14 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 982a3f5e7130..68c86f632d37 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -544,22 +544,26 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
> static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
> + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
> + case KVM_REG_RISCV_CONFIG:
> return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
> + case KVM_REG_RISCV_CORE:
> return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
> + case KVM_REG_RISCV_CSR:
> return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> + case KVM_REG_RISCV_TIMER:
> return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + case KVM_REG_RISCV_FP_F:
> return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_F);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + case KVM_REG_RISCV_FP_D:
> return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_D);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
> + case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
> + default:
> + break;
> + }
>
> return -EINVAL;
> }
> @@ -567,22 +571,26 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
> + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
> + case KVM_REG_RISCV_CONFIG:
> return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
> + case KVM_REG_RISCV_CORE:
> return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
> + case KVM_REG_RISCV_CSR:
> return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> + case KVM_REG_RISCV_TIMER:
> return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + case KVM_REG_RISCV_FP_F:
> return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_F);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + case KVM_REG_RISCV_FP_D:
> return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_D);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
> + case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
> + default:
> + break;
> + }
>
> return -EINVAL;
> }
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 21:06 ` Atish Patra
-1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:06 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct
> and functions in asm/kvm_vcpu_sbi.h.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 10 ++--------
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 6 ++++++
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 6502f9099965..91c74b09a970 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -16,6 +16,7 @@
> #include <asm/hwcap.h>
> #include <asm/kvm_vcpu_fp.h>
> #include <asm/kvm_vcpu_insn.h>
> +#include <asm/kvm_vcpu_sbi.h>
> #include <asm/kvm_vcpu_timer.h>
>
> #define KVM_MAX_VCPUS 1024
> @@ -94,10 +95,6 @@ struct kvm_arch {
> struct kvm_guest_timer timer;
> };
>
> -struct kvm_sbi_context {
> - int return_handled;
> -};
> -
> struct kvm_cpu_trap {
> unsigned long sepc;
> unsigned long scause;
> @@ -216,7 +213,7 @@ struct kvm_vcpu_arch {
> struct kvm_csr_decode csr_decode;
>
> /* SBI context */
> - struct kvm_sbi_context sbi_context;
> + struct kvm_vcpu_sbi_context sbi_context;
>
> /* Cache pages needed to program page tables with spinlock held */
> struct kvm_mmu_memory_cache mmu_page_cache;
> @@ -326,7 +323,4 @@ bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask);
> void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu);
> void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu);
>
> -int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
> -int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
> -
> #endif /* __RISCV_KVM_HOST_H__ */
> diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> index d4e3e600beef..f79478a85d2d 100644
> --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
> +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> @@ -14,6 +14,10 @@
> #define KVM_SBI_VERSION_MAJOR 1
> #define KVM_SBI_VERSION_MINOR 0
>
> +struct kvm_vcpu_sbi_context {
> + int return_handled;
> +};
> +
> struct kvm_vcpu_sbi_extension {
> unsigned long extid_start;
> unsigned long extid_end;
> @@ -31,7 +35,9 @@ void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run);
> void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
> struct kvm_run *run,
> u32 type, u64 flags);
> +int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
> const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
> +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
>
> #ifdef CONFIG_RISCV_SBI_V01
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01;
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
@ 2022-11-28 21:06 ` Atish Patra
0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:06 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct
> and functions in asm/kvm_vcpu_sbi.h.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 10 ++--------
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 6 ++++++
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 6502f9099965..91c74b09a970 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -16,6 +16,7 @@
> #include <asm/hwcap.h>
> #include <asm/kvm_vcpu_fp.h>
> #include <asm/kvm_vcpu_insn.h>
> +#include <asm/kvm_vcpu_sbi.h>
> #include <asm/kvm_vcpu_timer.h>
>
> #define KVM_MAX_VCPUS 1024
> @@ -94,10 +95,6 @@ struct kvm_arch {
> struct kvm_guest_timer timer;
> };
>
> -struct kvm_sbi_context {
> - int return_handled;
> -};
> -
> struct kvm_cpu_trap {
> unsigned long sepc;
> unsigned long scause;
> @@ -216,7 +213,7 @@ struct kvm_vcpu_arch {
> struct kvm_csr_decode csr_decode;
>
> /* SBI context */
> - struct kvm_sbi_context sbi_context;
> + struct kvm_vcpu_sbi_context sbi_context;
>
> /* Cache pages needed to program page tables with spinlock held */
> struct kvm_mmu_memory_cache mmu_page_cache;
> @@ -326,7 +323,4 @@ bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask);
> void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu);
> void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu);
>
> -int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
> -int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
> -
> #endif /* __RISCV_KVM_HOST_H__ */
> diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> index d4e3e600beef..f79478a85d2d 100644
> --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
> +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> @@ -14,6 +14,10 @@
> #define KVM_SBI_VERSION_MAJOR 1
> #define KVM_SBI_VERSION_MINOR 0
>
> +struct kvm_vcpu_sbi_context {
> + int return_handled;
> +};
> +
> struct kvm_vcpu_sbi_extension {
> unsigned long extid_start;
> unsigned long extid_end;
> @@ -31,7 +35,9 @@ void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run);
> void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
> struct kvm_run *run,
> u32 type, u64 flags);
> +int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
> const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
> +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
>
> #ifdef CONFIG_RISCV_SBI_V01
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01;
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 21:07 ` Atish Patra
-1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:07 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
> can be used by KVM module so let us export these functions.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kernel/sbi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 775d3322b422..5c87db8fdff2 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
>
> long sbi_get_marchid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_marchid);
>
> long sbi_get_mimpid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_mimpid);
>
> static void sbi_send_cpumask_ipi(const struct cpumask *target)
> {
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
@ 2022-11-28 21:07 ` Atish Patra
0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:07 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
> can be used by KVM module so let us export these functions.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kernel/sbi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 775d3322b422..5c87db8fdff2 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
>
> long sbi_get_marchid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_marchid);
>
> long sbi_get_mimpid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_mimpid);
>
> static void sbi_send_cpumask_ipi(const struct cpumask *target)
> {
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 21:08 ` Atish Patra
-1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:08 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:15 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should save VCPU mvendorid, marchid, and mimpid at the time
> of creating VCPU so that we don't have to do host SBI call every
> time Guest/VM ask for these details.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 5 +++++
> arch/riscv/kvm/vcpu.c | 6 ++++++
> arch/riscv/kvm/vcpu_sbi_base.c | 11 +++++------
> 3 files changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 91c74b09a970..93f43a3e7886 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -165,6 +165,11 @@ struct kvm_vcpu_arch {
> /* ISA feature bits (similar to MISA) */
> DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
>
> + /* Vendor, Arch, and Implementation details */
> + unsigned long mvendorid;
> + unsigned long marchid;
> + unsigned long mimpid;
> +
> /* SSCRATCH, STVEC, and SCOUNTEREN of Host */
> unsigned long host_sscratch;
> unsigned long host_stvec;
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 68c86f632d37..312a8a926867 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -21,6 +21,7 @@
> #include <asm/csr.h>
> #include <asm/cacheflush.h>
> #include <asm/hwcap.h>
> +#include <asm/sbi.h>
>
> const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
> KVM_GENERIC_VCPU_STATS(),
> @@ -171,6 +172,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
> set_bit(host_isa, vcpu->arch.isa);
> }
>
> + /* Setup vendor, arch, and implementation details */
> + vcpu->arch.mvendorid = sbi_get_mvendorid();
> + vcpu->arch.marchid = sbi_get_marchid();
> + vcpu->arch.mimpid = sbi_get_mimpid();
> +
> /* Setup VCPU hfence queue */
> spin_lock_init(&vcpu->arch.hfence_lock);
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 0c806f61c629..5d65c634d301 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -19,7 +19,6 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> {
> int ret = 0;
> struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
> - struct sbiret ecall_ret;
>
> switch (cp->a6) {
> case SBI_EXT_BASE_GET_SPEC_VERSION:
> @@ -48,13 +47,13 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> *out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
> break;
> case SBI_EXT_BASE_GET_MVENDORID:
> + *out_val = vcpu->arch.mvendorid;
> + break;
> case SBI_EXT_BASE_GET_MARCHID:
> + *out_val = vcpu->arch.marchid;
> + break;
> case SBI_EXT_BASE_GET_MIMPID:
> - ecall_ret = sbi_ecall(SBI_EXT_BASE, cp->a6, 0, 0, 0, 0, 0, 0);
> - if (!ecall_ret.error)
> - *out_val = ecall_ret.value;
> - /*TODO: We are unnecessarily converting the error twice */
> - ret = sbi_err_map_linux_errno(ecall_ret.error);
> + *out_val = vcpu->arch.mimpid;
> break;
> default:
> ret = -EOPNOTSUPP;
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
@ 2022-11-28 21:08 ` Atish Patra
0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:08 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:15 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should save VCPU mvendorid, marchid, and mimpid at the time
> of creating VCPU so that we don't have to do host SBI call every
> time Guest/VM ask for these details.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 5 +++++
> arch/riscv/kvm/vcpu.c | 6 ++++++
> arch/riscv/kvm/vcpu_sbi_base.c | 11 +++++------
> 3 files changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 91c74b09a970..93f43a3e7886 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -165,6 +165,11 @@ struct kvm_vcpu_arch {
> /* ISA feature bits (similar to MISA) */
> DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
>
> + /* Vendor, Arch, and Implementation details */
> + unsigned long mvendorid;
> + unsigned long marchid;
> + unsigned long mimpid;
> +
> /* SSCRATCH, STVEC, and SCOUNTEREN of Host */
> unsigned long host_sscratch;
> unsigned long host_stvec;
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 68c86f632d37..312a8a926867 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -21,6 +21,7 @@
> #include <asm/csr.h>
> #include <asm/cacheflush.h>
> #include <asm/hwcap.h>
> +#include <asm/sbi.h>
>
> const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
> KVM_GENERIC_VCPU_STATS(),
> @@ -171,6 +172,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
> set_bit(host_isa, vcpu->arch.isa);
> }
>
> + /* Setup vendor, arch, and implementation details */
> + vcpu->arch.mvendorid = sbi_get_mvendorid();
> + vcpu->arch.marchid = sbi_get_marchid();
> + vcpu->arch.mimpid = sbi_get_mimpid();
> +
> /* Setup VCPU hfence queue */
> spin_lock_init(&vcpu->arch.hfence_lock);
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 0c806f61c629..5d65c634d301 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -19,7 +19,6 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> {
> int ret = 0;
> struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
> - struct sbiret ecall_ret;
>
> switch (cp->a6) {
> case SBI_EXT_BASE_GET_SPEC_VERSION:
> @@ -48,13 +47,13 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> *out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
> break;
> case SBI_EXT_BASE_GET_MVENDORID:
> + *out_val = vcpu->arch.mvendorid;
> + break;
> case SBI_EXT_BASE_GET_MARCHID:
> + *out_val = vcpu->arch.marchid;
> + break;
> case SBI_EXT_BASE_GET_MIMPID:
> - ecall_ret = sbi_ecall(SBI_EXT_BASE, cp->a6, 0, 0, 0, 0, 0, 0);
> - if (!ecall_ret.error)
> - *out_val = ecall_ret.value;
> - /*TODO: We are unnecessarily converting the error twice */
> - ret = sbi_err_map_linux_errno(ecall_ret.error);
> + *out_val = vcpu->arch.mimpid;
> break;
> default:
> ret = -EOPNOTSUPP;
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
2022-11-28 16:14 ` Anup Patel
@ 2022-11-28 21:09 ` Atish Patra
-1 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:09 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:15 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
> so that KVM user-space can change this details to support migration
> across heterogeneous hosts.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 3 +++
> arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 8985ff234c01..92af6f3f057c 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -49,6 +49,9 @@ struct kvm_sregs {
> struct kvm_riscv_config {
> unsigned long isa;
> unsigned long zicbom_block_size;
> + unsigned long mvendorid;
> + unsigned long marchid;
> + unsigned long mimpid;
> };
>
> /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 312a8a926867..7c08567097f0 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> return -EINVAL;
> reg_val = riscv_cbom_block_size;
> break;
> + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> + reg_val = vcpu->arch.mvendorid;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(marchid):
> + reg_val = vcpu->arch.marchid;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> + reg_val = vcpu->arch.mimpid;
> + break;
> default:
> return -EINVAL;
> }
> @@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> break;
> case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> return -EOPNOTSUPP;
> + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.mvendorid = reg_val;
> + else
> + return -EBUSY;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(marchid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.marchid = reg_val;
> + else
> + return -EBUSY;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.mimpid = reg_val;
> + else
> + return -EBUSY;
> + break;
> default:
> return -EINVAL;
> }
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
@ 2022-11-28 21:09 ` Atish Patra
0 siblings, 0 replies; 56+ messages in thread
From: Atish Patra @ 2022-11-28 21:09 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Palmer Dabbelt, Paul Walmsley, Andrew Jones,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 8:15 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
> so that KVM user-space can change this details to support migration
> across heterogeneous hosts.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 3 +++
> arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 8985ff234c01..92af6f3f057c 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -49,6 +49,9 @@ struct kvm_sregs {
> struct kvm_riscv_config {
> unsigned long isa;
> unsigned long zicbom_block_size;
> + unsigned long mvendorid;
> + unsigned long marchid;
> + unsigned long mimpid;
> };
>
> /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 312a8a926867..7c08567097f0 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> return -EINVAL;
> reg_val = riscv_cbom_block_size;
> break;
> + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> + reg_val = vcpu->arch.mvendorid;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(marchid):
> + reg_val = vcpu->arch.marchid;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> + reg_val = vcpu->arch.mimpid;
> + break;
> default:
> return -EINVAL;
> }
> @@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> break;
> case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> return -EOPNOTSUPP;
> + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.mvendorid = reg_val;
> + else
> + return -EBUSY;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(marchid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.marchid = reg_val;
> + else
> + return -EBUSY;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.mimpid = reg_val;
> + else
> + return -EBUSY;
> + break;
> default:
> return -EINVAL;
> }
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
2022-11-28 16:14 ` Anup Patel
@ 2022-11-29 5:20 ` Andrew Jones
-1 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:20 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:17PM +0530, Anup Patel wrote:
> The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c
> so let us remove it.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu_sbi_base.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 48f431091cdb..22b9126e2872 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -12,7 +12,6 @@
> #include <linux/version.h>
> #include <asm/csr.h>
> #include <asm/sbi.h>
> -#include <asm/kvm_vcpu_timer.h>
> #include <asm/kvm_vcpu_sbi.h>
>
> static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
@ 2022-11-29 5:20 ` Andrew Jones
0 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:20 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:17PM +0530, Anup Patel wrote:
> The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c
> so let us remove it.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu_sbi_base.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 48f431091cdb..22b9126e2872 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -12,7 +12,6 @@
> #include <linux/version.h>
> #include <asm/csr.h>
> #include <asm/sbi.h>
> -#include <asm/kvm_vcpu_timer.h>
> #include <asm/kvm_vcpu_sbi.h>
>
> static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
2022-11-28 16:14 ` Anup Patel
@ 2022-11-29 5:21 ` Andrew Jones
-1 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:21 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:20PM +0530, Anup Patel wrote:
> Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct
> and functions in asm/kvm_vcpu_sbi.h.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 10 ++--------
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 6 ++++++
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
@ 2022-11-29 5:21 ` Andrew Jones
0 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:21 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:20PM +0530, Anup Patel wrote:
> Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct
> and functions in asm/kvm_vcpu_sbi.h.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 10 ++--------
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 6 ++++++
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
2022-11-28 16:14 ` Anup Patel
@ 2022-11-29 5:21 ` Andrew Jones
-1 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:21 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:21PM +0530, Anup Patel wrote:
> The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
> can be used by KVM module so let us export these functions.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kernel/sbi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
@ 2022-11-29 5:21 ` Andrew Jones
0 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:21 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:21PM +0530, Anup Patel wrote:
> The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
> can be used by KVM module so let us export these functions.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kernel/sbi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
2022-11-28 16:14 ` Anup Patel
@ 2022-11-29 5:22 ` Andrew Jones
-1 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:22 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:22PM +0530, Anup Patel wrote:
> We should save VCPU mvendorid, marchid, and mimpid at the time
> of creating VCPU so that we don't have to do host SBI call every
> time Guest/VM ask for these details.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 5 +++++
> arch/riscv/kvm/vcpu.c | 6 ++++++
> arch/riscv/kvm/vcpu_sbi_base.c | 11 +++++------
> 3 files changed, 16 insertions(+), 6 deletions(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
@ 2022-11-29 5:22 ` Andrew Jones
0 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:22 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:22PM +0530, Anup Patel wrote:
> We should save VCPU mvendorid, marchid, and mimpid at the time
> of creating VCPU so that we don't have to do host SBI call every
> time Guest/VM ask for these details.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 5 +++++
> arch/riscv/kvm/vcpu.c | 6 ++++++
> arch/riscv/kvm/vcpu_sbi_base.c | 11 +++++------
> 3 files changed, 16 insertions(+), 6 deletions(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
2022-11-28 16:14 ` Anup Patel
@ 2022-11-29 5:46 ` Andrew Jones
-1 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:46 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:23PM +0530, Anup Patel wrote:
> We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
> so that KVM user-space can change this details to support migration
> across heterogeneous hosts.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 3 +++
> arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 8985ff234c01..92af6f3f057c 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -49,6 +49,9 @@ struct kvm_sregs {
> struct kvm_riscv_config {
> unsigned long isa;
> unsigned long zicbom_block_size;
> + unsigned long mvendorid;
> + unsigned long marchid;
> + unsigned long mimpid;
> };
>
> /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 312a8a926867..7c08567097f0 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> return -EINVAL;
> reg_val = riscv_cbom_block_size;
> break;
> + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> + reg_val = vcpu->arch.mvendorid;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(marchid):
> + reg_val = vcpu->arch.marchid;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> + reg_val = vcpu->arch.mimpid;
> + break;
> default:
> return -EINVAL;
> }
> @@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> break;
> case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> return -EOPNOTSUPP;
> + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.mvendorid = reg_val;
> + else
> + return -EBUSY;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(marchid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.marchid = reg_val;
> + else
> + return -EBUSY;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.mimpid = reg_val;
> + else
> + return -EBUSY;
> + break;
> default:
> return -EINVAL;
> }
> --
> 2.34.1
>
At some point we should patch Documentation/virt/kvm/api.rst to describe
the possible errors we have. It's missing EOPNOTSUPP and EBUSY.
Also, I see a couple places were we use EOPNOTSUPP that would be better
as EBUSY. And finally I wonder if we shouldn't use ENOENT when the reg_num
is wrong/unknown, which would allow us to differentiate between bad
reg_num and bad reg_val in set-one ioctls.
I can send an RFC series to better describe these thoughts.
And for this patch,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
@ 2022-11-29 5:46 ` Andrew Jones
0 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 5:46 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:23PM +0530, Anup Patel wrote:
> We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
> so that KVM user-space can change this details to support migration
> across heterogeneous hosts.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 3 +++
> arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 8985ff234c01..92af6f3f057c 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -49,6 +49,9 @@ struct kvm_sregs {
> struct kvm_riscv_config {
> unsigned long isa;
> unsigned long zicbom_block_size;
> + unsigned long mvendorid;
> + unsigned long marchid;
> + unsigned long mimpid;
> };
>
> /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 312a8a926867..7c08567097f0 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> return -EINVAL;
> reg_val = riscv_cbom_block_size;
> break;
> + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> + reg_val = vcpu->arch.mvendorid;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(marchid):
> + reg_val = vcpu->arch.marchid;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> + reg_val = vcpu->arch.mimpid;
> + break;
> default:
> return -EINVAL;
> }
> @@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> break;
> case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> return -EOPNOTSUPP;
> + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.mvendorid = reg_val;
> + else
> + return -EBUSY;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(marchid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.marchid = reg_val;
> + else
> + return -EBUSY;
> + break;
> + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> + if (!vcpu->arch.ran_atleast_once)
> + vcpu->arch.mimpid = reg_val;
> + else
> + return -EBUSY;
> + break;
> default:
> return -EINVAL;
> }
> --
> 2.34.1
>
At some point we should patch Documentation/virt/kvm/api.rst to describe
the possible errors we have. It's missing EOPNOTSUPP and EBUSY.
Also, I see a couple places were we use EOPNOTSUPP that would be better
as EBUSY. And finally I wonder if we shouldn't use ENOENT when the reg_num
is wrong/unknown, which would allow us to differentiate between bad
reg_num and bad reg_val in set-one ioctls.
I can send an RFC series to better describe these thoughts.
And for this patch,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions
2022-11-28 16:14 ` Anup Patel
@ 2022-11-29 6:09 ` Andrew Jones
-1 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 6:09 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:24PM +0530, Anup Patel wrote:
> We add ONE_REG interface to enable/disable SBI extensions (just
> like the ONE_REG interface for ISA extensions). This allows KVM
> user-space to decide the set of SBI extension enabled for a Guest
> and by default all SBI extensions are enabled.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 8 +-
> arch/riscv/include/uapi/asm/kvm.h | 19 ++++
> arch/riscv/kvm/vcpu.c | 2 +
> arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++---
> arch/riscv/kvm/vcpu_sbi_base.c | 2 +-
> 5 files changed, 158 insertions(+), 18 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> index f79478a85d2d..baa342dadf95 100644
> --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
> +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> @@ -16,6 +16,7 @@
>
> struct kvm_vcpu_sbi_context {
> int return_handled;
> + bool extension_disabled[KVM_RISCV_SBI_EXT_MAX];
> };
>
> struct kvm_vcpu_sbi_extension {
> @@ -36,7 +37,12 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
> struct kvm_run *run,
> u32 type, u64 flags);
> int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
> -const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
> +int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg);
> +int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg);
> +const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
> + struct kvm_vcpu *vcpu, unsigned long extid);
> int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
>
> #ifdef CONFIG_RISCV_SBI_V01
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 92af6f3f057c..71992ff1f9dd 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -108,6 +108,22 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> +/*
> + * SBI extension IDs specific to KVM. This is not the same as the SBI
> + * extension IDs defined by the RISC-V SBI specification.
> + */
> +enum KVM_RISCV_SBI_EXT_ID {
> + KVM_RISCV_SBI_EXT_V01 = 0,
> + KVM_RISCV_SBI_EXT_TIME,
> + KVM_RISCV_SBI_EXT_IPI,
> + KVM_RISCV_SBI_EXT_RFENCE,
> + KVM_RISCV_SBI_EXT_SRST,
> + KVM_RISCV_SBI_EXT_HSM,
> + KVM_RISCV_SBI_EXT_EXPERIMENTAL,
> + KVM_RISCV_SBI_EXT_VENDOR,
> + KVM_RISCV_SBI_EXT_MAX,
> +};
> +
> /* Possible states for kvm_riscv_timer */
> #define KVM_RISCV_TIMER_STATE_OFF 0
> #define KVM_RISCV_TIMER_STATE_ON 1
> @@ -152,6 +168,9 @@ enum KVM_RISCV_ISA_EXT_ID {
> /* ISA Extension registers are mapped as type 7 */
> #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
>
> +/* SBI extension registers are mapped as type 8 */
> +#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
> +
> #endif
>
> #endif /* __LINUX_KVM_RISCV_H */
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 7c08567097f0..2260adaf2de8 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -594,6 +594,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> KVM_REG_RISCV_FP_D);
> case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
> + case KVM_REG_RISCV_SBI_EXT:
> + return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg);
> default:
> break;
> }
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index f96991d230bf..0abb44f8f4d1 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -40,16 +40,48 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = {
> };
> #endif
>
> -static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> - &vcpu_sbi_ext_v01,
> - &vcpu_sbi_ext_base,
> - &vcpu_sbi_ext_time,
> - &vcpu_sbi_ext_ipi,
> - &vcpu_sbi_ext_rfence,
> - &vcpu_sbi_ext_srst,
> - &vcpu_sbi_ext_hsm,
> - &vcpu_sbi_ext_experimental,
> - &vcpu_sbi_ext_vendor,
> +struct kvm_riscv_sbi_extension_entry {
> + enum KVM_RISCV_SBI_EXT_ID dis_idx;
nit: I think I'd prefer this to be spelled out (disable_idx)
(although keeping it 7 chars does make the table below line up nicely :-)
> + const struct kvm_vcpu_sbi_extension *ext_ptr;
> +};
> +
> +static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = {
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_V01,
> + .ext_ptr = &vcpu_sbi_ext_v01,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_MAX, /* Can't be disabled */
> + .ext_ptr = &vcpu_sbi_ext_base,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_TIME,
> + .ext_ptr = &vcpu_sbi_ext_time,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_IPI,
> + .ext_ptr = &vcpu_sbi_ext_ipi,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_RFENCE,
> + .ext_ptr = &vcpu_sbi_ext_rfence,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_SRST,
> + .ext_ptr = &vcpu_sbi_ext_srst,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_HSM,
> + .ext_ptr = &vcpu_sbi_ext_hsm,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_EXPERIMENTAL,
> + .ext_ptr = &vcpu_sbi_ext_experimental,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_VENDOR,
> + .ext_ptr = &vcpu_sbi_ext_vendor,
> + },
> };
>
> void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
> @@ -108,14 +140,95 @@ int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
> return 0;
> }
>
> -const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid)
> +int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg)
> +{
> + unsigned long __user *uaddr =
> + (unsigned long __user *)(unsigned long)reg->addr;
> + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
> + KVM_REG_SIZE_MASK |
> + KVM_REG_RISCV_SBI_EXT);
I think we should create a macro that extracts reg_num from reg->id for
all types, i.e.
#define KVM_REG_NUM(id) ((id) & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_TYPE_MASK))
and then we can use it throughout this file.
> + unsigned long i, reg_val;
> + const struct kvm_riscv_sbi_extension_entry *sext = NULL;
> + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
> +
> + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
> + return -EINVAL;
> +
> + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
> + return -EFAULT;
> +
> + if (reg_num >= KVM_RISCV_SBI_EXT_MAX ||
> + (reg_val != 1 && reg_val != 0))
> + return -EINVAL;
Maybe
if (reg_num >= KVM_RISCV_SBI_EXT_MAX)
return -ENOENT;
if (reg_val != 1 && reg_val != 0)
return -EINVAL;
> +
> + if (vcpu->arch.ran_atleast_once)
> + return -EBUSY;
> +
> + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
> + if (sbi_ext[i].dis_idx == reg_num) {
> + sext = &sbi_ext[i];
> + break;
> + }
> + }
> + if (!sext)
> + return -ENOENT;
> +
> + scontext->extension_disabled[sext->dis_idx] = !reg_val;
> +
> + return 0;
> +}
> +
> +int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg)
> +{
> + unsigned long __user *uaddr =
> + (unsigned long __user *)(unsigned long)reg->addr;
> + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
> + KVM_REG_SIZE_MASK |
> + KVM_REG_RISCV_SBI_EXT);
> + unsigned long i, reg_val;
> + const struct kvm_riscv_sbi_extension_entry *sext = NULL;
> + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
> +
> + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
> + return -EINVAL;
> +
> + if (reg_num >= KVM_RISCV_SBI_EXT_MAX)
> + return -EINVAL;
ENOENT?
> +
> + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
> + if (sbi_ext[i].dis_idx == reg_num) {
> + sext = &sbi_ext[i];
> + break;
> + }
> + }
> + if (!sext)
> + return -ENOENT;
> +
> + reg_val = !scontext->extension_disabled[sext->dis_idx];
> + if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> +const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
> + struct kvm_vcpu *vcpu, unsigned long extid)
> {
> - int i = 0;
> + int i;
> + const struct kvm_riscv_sbi_extension_entry *sext;
> + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
>
> for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
> - if (sbi_ext[i]->extid_start <= extid &&
> - sbi_ext[i]->extid_end >= extid)
> - return sbi_ext[i];
> + sext = &sbi_ext[i];
> + if (sext->ext_ptr->extid_start <= extid &&
> + sext->ext_ptr->extid_end >= extid) {
> + if (sext->dis_idx < KVM_RISCV_SBI_EXT_MAX &&
> + scontext->extension_disabled[sext->dis_idx])
> + return NULL;
> + return sbi_ext[i].ext_ptr;
> + }
> }
>
> return NULL;
> @@ -132,7 +245,7 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run)
> unsigned long out_val = 0;
> bool ext_is_v01 = false;
>
> - sbi_ext = kvm_vcpu_sbi_find_ext(cp->a7);
> + sbi_ext = kvm_vcpu_sbi_find_ext(vcpu, cp->a7);
> if (sbi_ext && sbi_ext->handler) {
> #ifdef CONFIG_RISCV_SBI_V01
> if (cp->a7 >= SBI_EXT_0_1_SET_TIMER &&
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 5d65c634d301..a51ed0c615bf 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -44,7 +44,7 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> kvm_riscv_vcpu_sbi_forward(vcpu, run);
> *exit = true;
> } else
> - *out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
> + *out_val = kvm_vcpu_sbi_find_ext(vcpu, cp->a0) ? 1 : 0;
> break;
> case SBI_EXT_BASE_GET_MVENDORID:
> *out_val = vcpu->arch.mvendorid;
> --
> 2.34.1
>
Other than the EINVAL / ENOENT comment and the nits and stuff that can be
done later, this looks good to me, so
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions
@ 2022-11-29 6:09 ` Andrew Jones
0 siblings, 0 replies; 56+ messages in thread
From: Andrew Jones @ 2022-11-29 6:09 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 09:44:24PM +0530, Anup Patel wrote:
> We add ONE_REG interface to enable/disable SBI extensions (just
> like the ONE_REG interface for ISA extensions). This allows KVM
> user-space to decide the set of SBI extension enabled for a Guest
> and by default all SBI extensions are enabled.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 8 +-
> arch/riscv/include/uapi/asm/kvm.h | 19 ++++
> arch/riscv/kvm/vcpu.c | 2 +
> arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++---
> arch/riscv/kvm/vcpu_sbi_base.c | 2 +-
> 5 files changed, 158 insertions(+), 18 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> index f79478a85d2d..baa342dadf95 100644
> --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
> +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> @@ -16,6 +16,7 @@
>
> struct kvm_vcpu_sbi_context {
> int return_handled;
> + bool extension_disabled[KVM_RISCV_SBI_EXT_MAX];
> };
>
> struct kvm_vcpu_sbi_extension {
> @@ -36,7 +37,12 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
> struct kvm_run *run,
> u32 type, u64 flags);
> int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
> -const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
> +int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg);
> +int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg);
> +const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
> + struct kvm_vcpu *vcpu, unsigned long extid);
> int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
>
> #ifdef CONFIG_RISCV_SBI_V01
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 92af6f3f057c..71992ff1f9dd 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -108,6 +108,22 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> +/*
> + * SBI extension IDs specific to KVM. This is not the same as the SBI
> + * extension IDs defined by the RISC-V SBI specification.
> + */
> +enum KVM_RISCV_SBI_EXT_ID {
> + KVM_RISCV_SBI_EXT_V01 = 0,
> + KVM_RISCV_SBI_EXT_TIME,
> + KVM_RISCV_SBI_EXT_IPI,
> + KVM_RISCV_SBI_EXT_RFENCE,
> + KVM_RISCV_SBI_EXT_SRST,
> + KVM_RISCV_SBI_EXT_HSM,
> + KVM_RISCV_SBI_EXT_EXPERIMENTAL,
> + KVM_RISCV_SBI_EXT_VENDOR,
> + KVM_RISCV_SBI_EXT_MAX,
> +};
> +
> /* Possible states for kvm_riscv_timer */
> #define KVM_RISCV_TIMER_STATE_OFF 0
> #define KVM_RISCV_TIMER_STATE_ON 1
> @@ -152,6 +168,9 @@ enum KVM_RISCV_ISA_EXT_ID {
> /* ISA Extension registers are mapped as type 7 */
> #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
>
> +/* SBI extension registers are mapped as type 8 */
> +#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
> +
> #endif
>
> #endif /* __LINUX_KVM_RISCV_H */
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 7c08567097f0..2260adaf2de8 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -594,6 +594,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> KVM_REG_RISCV_FP_D);
> case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
> + case KVM_REG_RISCV_SBI_EXT:
> + return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg);
> default:
> break;
> }
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index f96991d230bf..0abb44f8f4d1 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -40,16 +40,48 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = {
> };
> #endif
>
> -static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> - &vcpu_sbi_ext_v01,
> - &vcpu_sbi_ext_base,
> - &vcpu_sbi_ext_time,
> - &vcpu_sbi_ext_ipi,
> - &vcpu_sbi_ext_rfence,
> - &vcpu_sbi_ext_srst,
> - &vcpu_sbi_ext_hsm,
> - &vcpu_sbi_ext_experimental,
> - &vcpu_sbi_ext_vendor,
> +struct kvm_riscv_sbi_extension_entry {
> + enum KVM_RISCV_SBI_EXT_ID dis_idx;
nit: I think I'd prefer this to be spelled out (disable_idx)
(although keeping it 7 chars does make the table below line up nicely :-)
> + const struct kvm_vcpu_sbi_extension *ext_ptr;
> +};
> +
> +static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = {
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_V01,
> + .ext_ptr = &vcpu_sbi_ext_v01,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_MAX, /* Can't be disabled */
> + .ext_ptr = &vcpu_sbi_ext_base,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_TIME,
> + .ext_ptr = &vcpu_sbi_ext_time,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_IPI,
> + .ext_ptr = &vcpu_sbi_ext_ipi,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_RFENCE,
> + .ext_ptr = &vcpu_sbi_ext_rfence,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_SRST,
> + .ext_ptr = &vcpu_sbi_ext_srst,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_HSM,
> + .ext_ptr = &vcpu_sbi_ext_hsm,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_EXPERIMENTAL,
> + .ext_ptr = &vcpu_sbi_ext_experimental,
> + },
> + {
> + .dis_idx = KVM_RISCV_SBI_EXT_VENDOR,
> + .ext_ptr = &vcpu_sbi_ext_vendor,
> + },
> };
>
> void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
> @@ -108,14 +140,95 @@ int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
> return 0;
> }
>
> -const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid)
> +int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg)
> +{
> + unsigned long __user *uaddr =
> + (unsigned long __user *)(unsigned long)reg->addr;
> + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
> + KVM_REG_SIZE_MASK |
> + KVM_REG_RISCV_SBI_EXT);
I think we should create a macro that extracts reg_num from reg->id for
all types, i.e.
#define KVM_REG_NUM(id) ((id) & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_TYPE_MASK))
and then we can use it throughout this file.
> + unsigned long i, reg_val;
> + const struct kvm_riscv_sbi_extension_entry *sext = NULL;
> + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
> +
> + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
> + return -EINVAL;
> +
> + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
> + return -EFAULT;
> +
> + if (reg_num >= KVM_RISCV_SBI_EXT_MAX ||
> + (reg_val != 1 && reg_val != 0))
> + return -EINVAL;
Maybe
if (reg_num >= KVM_RISCV_SBI_EXT_MAX)
return -ENOENT;
if (reg_val != 1 && reg_val != 0)
return -EINVAL;
> +
> + if (vcpu->arch.ran_atleast_once)
> + return -EBUSY;
> +
> + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
> + if (sbi_ext[i].dis_idx == reg_num) {
> + sext = &sbi_ext[i];
> + break;
> + }
> + }
> + if (!sext)
> + return -ENOENT;
> +
> + scontext->extension_disabled[sext->dis_idx] = !reg_val;
> +
> + return 0;
> +}
> +
> +int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg)
> +{
> + unsigned long __user *uaddr =
> + (unsigned long __user *)(unsigned long)reg->addr;
> + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
> + KVM_REG_SIZE_MASK |
> + KVM_REG_RISCV_SBI_EXT);
> + unsigned long i, reg_val;
> + const struct kvm_riscv_sbi_extension_entry *sext = NULL;
> + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
> +
> + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
> + return -EINVAL;
> +
> + if (reg_num >= KVM_RISCV_SBI_EXT_MAX)
> + return -EINVAL;
ENOENT?
> +
> + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
> + if (sbi_ext[i].dis_idx == reg_num) {
> + sext = &sbi_ext[i];
> + break;
> + }
> + }
> + if (!sext)
> + return -ENOENT;
> +
> + reg_val = !scontext->extension_disabled[sext->dis_idx];
> + if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> +const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
> + struct kvm_vcpu *vcpu, unsigned long extid)
> {
> - int i = 0;
> + int i;
> + const struct kvm_riscv_sbi_extension_entry *sext;
> + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
>
> for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
> - if (sbi_ext[i]->extid_start <= extid &&
> - sbi_ext[i]->extid_end >= extid)
> - return sbi_ext[i];
> + sext = &sbi_ext[i];
> + if (sext->ext_ptr->extid_start <= extid &&
> + sext->ext_ptr->extid_end >= extid) {
> + if (sext->dis_idx < KVM_RISCV_SBI_EXT_MAX &&
> + scontext->extension_disabled[sext->dis_idx])
> + return NULL;
> + return sbi_ext[i].ext_ptr;
> + }
> }
>
> return NULL;
> @@ -132,7 +245,7 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run)
> unsigned long out_val = 0;
> bool ext_is_v01 = false;
>
> - sbi_ext = kvm_vcpu_sbi_find_ext(cp->a7);
> + sbi_ext = kvm_vcpu_sbi_find_ext(vcpu, cp->a7);
> if (sbi_ext && sbi_ext->handler) {
> #ifdef CONFIG_RISCV_SBI_V01
> if (cp->a7 >= SBI_EXT_0_1_SET_TIMER &&
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 5d65c634d301..a51ed0c615bf 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -44,7 +44,7 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> kvm_riscv_vcpu_sbi_forward(vcpu, run);
> *exit = true;
> } else
> - *out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
> + *out_val = kvm_vcpu_sbi_find_ext(vcpu, cp->a0) ? 1 : 0;
> break;
> case SBI_EXT_BASE_GET_MVENDORID:
> *out_val = vcpu->arch.mvendorid;
> --
> 2.34.1
>
Other than the EINVAL / ENOENT comment and the nits and stuff that can be
done later, this looks good to me, so
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
2022-11-28 16:14 ` Anup Patel
@ 2022-12-02 17:53 ` Palmer Dabbelt
-1 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2022-12-02 17:53 UTC (permalink / raw)
To: apatel
Cc: pbonzini, atishp, Paul Walmsley, ajones, anup, kvm, kvm-riscv,
linux-riscv, linux-kernel, apatel
On Mon, 28 Nov 2022 08:14:21 PST (-0800), apatel@ventanamicro.com wrote:
> The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
> can be used by KVM module so let us export these functions.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kernel/sbi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 775d3322b422..5c87db8fdff2 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
>
> long sbi_get_marchid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_marchid);
>
> long sbi_get_mimpid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_mimpid);
>
> static void sbi_send_cpumask_ipi(const struct cpumask *target)
> {
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
@ 2022-12-02 17:53 ` Palmer Dabbelt
0 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2022-12-02 17:53 UTC (permalink / raw)
To: apatel
Cc: pbonzini, atishp, Paul Walmsley, ajones, anup, kvm, kvm-riscv,
linux-riscv, linux-kernel, apatel
On Mon, 28 Nov 2022 08:14:21 PST (-0800), apatel@ventanamicro.com wrote:
> The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
> can be used by KVM module so let us export these functions.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kernel/sbi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 775d3322b422..5c87db8fdff2 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
>
> long sbi_get_marchid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_marchid);
>
> long sbi_get_mimpid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
> }
> +EXPORT_SYMBOL_GPL(sbi_get_mimpid);
>
> static void sbi_send_cpumask_ipi(const struct cpumask *target)
> {
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
2022-11-29 5:46 ` Andrew Jones
@ 2022-12-03 12:18 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-12-03 12:18 UTC (permalink / raw)
To: Andrew Jones
Cc: Anup Patel, Paolo Bonzini, Atish Patra, Palmer Dabbelt,
Paul Walmsley, kvm, kvm-riscv, linux-riscv, linux-kernel
On Tue, Nov 29, 2022 at 11:16 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Mon, Nov 28, 2022 at 09:44:23PM +0530, Anup Patel wrote:
> > We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
> > so that KVM user-space can change this details to support migration
> > across heterogeneous hosts.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > arch/riscv/include/uapi/asm/kvm.h | 3 +++
> > arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
> > 2 files changed, 30 insertions(+)
> >
> > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> > index 8985ff234c01..92af6f3f057c 100644
> > --- a/arch/riscv/include/uapi/asm/kvm.h
> > +++ b/arch/riscv/include/uapi/asm/kvm.h
> > @@ -49,6 +49,9 @@ struct kvm_sregs {
> > struct kvm_riscv_config {
> > unsigned long isa;
> > unsigned long zicbom_block_size;
> > + unsigned long mvendorid;
> > + unsigned long marchid;
> > + unsigned long mimpid;
> > };
> >
> > /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> > index 312a8a926867..7c08567097f0 100644
> > --- a/arch/riscv/kvm/vcpu.c
> > +++ b/arch/riscv/kvm/vcpu.c
> > @@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> > return -EINVAL;
> > reg_val = riscv_cbom_block_size;
> > break;
> > + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> > + reg_val = vcpu->arch.mvendorid;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(marchid):
> > + reg_val = vcpu->arch.marchid;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> > + reg_val = vcpu->arch.mimpid;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > @@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> > break;
> > case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> > return -EOPNOTSUPP;
> > + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.mvendorid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(marchid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.marchid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.mimpid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > --
> > 2.34.1
> >
>
> At some point we should patch Documentation/virt/kvm/api.rst to describe
> the possible errors we have. It's missing EOPNOTSUPP and EBUSY.
>
> Also, I see a couple places were we use EOPNOTSUPP that would be better
> as EBUSY. And finally I wonder if we shouldn't use ENOENT when the reg_num
> is wrong/unknown, which would allow us to differentiate between bad
> reg_num and bad reg_val in set-one ioctls.
>
> I can send an RFC series to better describe these thoughts.
Sure, go ahead.
>
> And for this patch,
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> Thanks,
> drew
Regards,
Anup
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
@ 2022-12-03 12:18 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-12-03 12:18 UTC (permalink / raw)
To: Andrew Jones
Cc: Anup Patel, Paolo Bonzini, Atish Patra, Palmer Dabbelt,
Paul Walmsley, kvm, kvm-riscv, linux-riscv, linux-kernel
On Tue, Nov 29, 2022 at 11:16 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Mon, Nov 28, 2022 at 09:44:23PM +0530, Anup Patel wrote:
> > We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
> > so that KVM user-space can change this details to support migration
> > across heterogeneous hosts.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > arch/riscv/include/uapi/asm/kvm.h | 3 +++
> > arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
> > 2 files changed, 30 insertions(+)
> >
> > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> > index 8985ff234c01..92af6f3f057c 100644
> > --- a/arch/riscv/include/uapi/asm/kvm.h
> > +++ b/arch/riscv/include/uapi/asm/kvm.h
> > @@ -49,6 +49,9 @@ struct kvm_sregs {
> > struct kvm_riscv_config {
> > unsigned long isa;
> > unsigned long zicbom_block_size;
> > + unsigned long mvendorid;
> > + unsigned long marchid;
> > + unsigned long mimpid;
> > };
> >
> > /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> > index 312a8a926867..7c08567097f0 100644
> > --- a/arch/riscv/kvm/vcpu.c
> > +++ b/arch/riscv/kvm/vcpu.c
> > @@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> > return -EINVAL;
> > reg_val = riscv_cbom_block_size;
> > break;
> > + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> > + reg_val = vcpu->arch.mvendorid;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(marchid):
> > + reg_val = vcpu->arch.marchid;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> > + reg_val = vcpu->arch.mimpid;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > @@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> > break;
> > case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> > return -EOPNOTSUPP;
> > + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.mvendorid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(marchid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.marchid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.mimpid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > --
> > 2.34.1
> >
>
> At some point we should patch Documentation/virt/kvm/api.rst to describe
> the possible errors we have. It's missing EOPNOTSUPP and EBUSY.
>
> Also, I see a couple places were we use EOPNOTSUPP that would be better
> as EBUSY. And finally I wonder if we shouldn't use ENOENT when the reg_num
> is wrong/unknown, which would allow us to differentiate between bad
> reg_num and bad reg_val in set-one ioctls.
>
> I can send an RFC series to better describe these thoughts.
Sure, go ahead.
>
> And for this patch,
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> Thanks,
> drew
Regards,
Anup
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI
2022-11-28 16:14 ` Anup Patel
@ 2022-12-03 12:39 ` Anup Patel
-1 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-12-03 12:39 UTC (permalink / raw)
To: Andrew Jones, Atish Patra
Cc: Paolo Bonzini, Anup Patel, Palmer Dabbelt, Paul Walmsley, kvm,
kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 9:44 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> This series does first does few cleanups/fixes (PATCH1 to PATCH5) and
> adds ONE-REG interface for customizing the SBI interface visible to the
> Guest/VM.
>
> The testing of this series has been done with KVMTOOL changes in
> riscv_sbi_imp_v1 branch at:
> https://github.com/avpatel/kvmtool.git
>
> These patches can also be found in the riscv_kvm_sbi_imp_v1 branch at:
> https://github.com/avpatel/linux.git
>
> Anup Patel (9):
> RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
> RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
> RISC-V: KVM: Remove redundant includes of asm/csr.h
> RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
> RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
> RISC-V: Export sbi_get_mvendorid() and friends
> RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
> RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
> RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions
I have queued PATCH1 to PATCH8 for Linux-6.2.
I have deferred PATCH9 until we have an agreement about how to deal
with VM-level attributes. This is also required for the KVM SBI PMU series.
>
> arch/riscv/include/asm/kvm_host.h | 16 ++-
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 14 ++-
> arch/riscv/include/uapi/asm/kvm.h | 22 ++++
> arch/riscv/kernel/sbi.c | 3 +
> arch/riscv/kvm/vcpu.c | 82 +++++++++++----
> arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++---
> arch/riscv/kvm/vcpu_sbi_base.c | 15 ++-
> arch/riscv/kvm/vcpu_sbi_hsm.c | 1 -
> arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
> arch/riscv/kvm/vcpu_sbi_v01.c | 1 -
> 10 files changed, 244 insertions(+), 56 deletions(-)
>
> --
> 2.34.1
>
Thanks,
Anup
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI
@ 2022-12-03 12:39 ` Anup Patel
0 siblings, 0 replies; 56+ messages in thread
From: Anup Patel @ 2022-12-03 12:39 UTC (permalink / raw)
To: Andrew Jones, Atish Patra
Cc: Paolo Bonzini, Anup Patel, Palmer Dabbelt, Paul Walmsley, kvm,
kvm-riscv, linux-riscv, linux-kernel
On Mon, Nov 28, 2022 at 9:44 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> This series does first does few cleanups/fixes (PATCH1 to PATCH5) and
> adds ONE-REG interface for customizing the SBI interface visible to the
> Guest/VM.
>
> The testing of this series has been done with KVMTOOL changes in
> riscv_sbi_imp_v1 branch at:
> https://github.com/avpatel/kvmtool.git
>
> These patches can also be found in the riscv_kvm_sbi_imp_v1 branch at:
> https://github.com/avpatel/linux.git
>
> Anup Patel (9):
> RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()
> RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
> RISC-V: KVM: Remove redundant includes of asm/csr.h
> RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
> RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h
> RISC-V: Export sbi_get_mvendorid() and friends
> RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU
> RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
> RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions
I have queued PATCH1 to PATCH8 for Linux-6.2.
I have deferred PATCH9 until we have an agreement about how to deal
with VM-level attributes. This is also required for the KVM SBI PMU series.
>
> arch/riscv/include/asm/kvm_host.h | 16 ++-
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 14 ++-
> arch/riscv/include/uapi/asm/kvm.h | 22 ++++
> arch/riscv/kernel/sbi.c | 3 +
> arch/riscv/kvm/vcpu.c | 82 +++++++++++----
> arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++---
> arch/riscv/kvm/vcpu_sbi_base.c | 15 ++-
> arch/riscv/kvm/vcpu_sbi_hsm.c | 1 -
> arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
> arch/riscv/kvm/vcpu_sbi_v01.c | 1 -
> 10 files changed, 244 insertions(+), 56 deletions(-)
>
> --
> 2.34.1
>
Thanks,
Anup
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
2022-11-28 21:07 ` Atish Patra
@ 2022-12-09 4:33 ` Palmer Dabbelt
-1 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2022-12-09 4:33 UTC (permalink / raw)
To: atishp
Cc: apatel, pbonzini, Paul Walmsley, ajones, anup, kvm, kvm-riscv,
linux-riscv, linux-kernel
On Mon, 28 Nov 2022 13:07:27 PST (-0800), atishp@atishpatra.org wrote:
> On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>>
>> The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
>> can be used by KVM module so let us export these functions.
>>
>> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
>> ---
>> arch/riscv/kernel/sbi.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
>> index 775d3322b422..5c87db8fdff2 100644
>> --- a/arch/riscv/kernel/sbi.c
>> +++ b/arch/riscv/kernel/sbi.c
>> @@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
>> {
>> return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
>> }
>> +EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
>>
>> long sbi_get_marchid(void)
>> {
>> return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
>> }
>> +EXPORT_SYMBOL_GPL(sbi_get_marchid);
>>
>> long sbi_get_mimpid(void)
>> {
>> return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
>> }
>> +EXPORT_SYMBOL_GPL(sbi_get_mimpid);
>>
>> static void sbi_send_cpumask_ipi(const struct cpumask *target)
>> {
>> --
>> 2.34.1
>>
>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends
@ 2022-12-09 4:33 ` Palmer Dabbelt
0 siblings, 0 replies; 56+ messages in thread
From: Palmer Dabbelt @ 2022-12-09 4:33 UTC (permalink / raw)
To: atishp
Cc: apatel, pbonzini, Paul Walmsley, ajones, anup, kvm, kvm-riscv,
linux-riscv, linux-kernel
On Mon, 28 Nov 2022 13:07:27 PST (-0800), atishp@atishpatra.org wrote:
> On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>>
>> The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
>> can be used by KVM module so let us export these functions.
>>
>> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
>> ---
>> arch/riscv/kernel/sbi.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
>> index 775d3322b422..5c87db8fdff2 100644
>> --- a/arch/riscv/kernel/sbi.c
>> +++ b/arch/riscv/kernel/sbi.c
>> @@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
>> {
>> return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
>> }
>> +EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
>>
>> long sbi_get_marchid(void)
>> {
>> return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
>> }
>> +EXPORT_SYMBOL_GPL(sbi_get_marchid);
>>
>> long sbi_get_mimpid(void)
>> {
>> return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
>> }
>> +EXPORT_SYMBOL_GPL(sbi_get_mimpid);
>>
>> static void sbi_send_cpumask_ipi(const struct cpumask *target)
>> {
>> --
>> 2.34.1
>>
>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2022-12-09 4:33 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-28 16:14 [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 16:14 ` [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config() Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:03 ` Atish Patra
2022-11-28 21:03 ` Atish Patra
2022-11-28 16:14 ` [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:04 ` Atish Patra
2022-11-28 21:04 ` Atish Patra
2022-11-29 5:20 ` Andrew Jones
2022-11-29 5:20 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:04 ` Atish Patra
2022-11-28 21:04 ` Atish Patra
2022-11-28 16:14 ` [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg() Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:04 ` Atish Patra
2022-11-28 21:04 ` Atish Patra
2022-11-28 16:14 ` [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:06 ` Atish Patra
2022-11-28 21:06 ` Atish Patra
2022-11-29 5:21 ` Andrew Jones
2022-11-29 5:21 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:07 ` Atish Patra
2022-11-28 21:07 ` Atish Patra
2022-12-09 4:33 ` Palmer Dabbelt
2022-12-09 4:33 ` Palmer Dabbelt
2022-11-29 5:21 ` Andrew Jones
2022-11-29 5:21 ` Andrew Jones
2022-12-02 17:53 ` Palmer Dabbelt
2022-12-02 17:53 ` Palmer Dabbelt
2022-11-28 16:14 ` [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:08 ` Atish Patra
2022-11-28 21:08 ` Atish Patra
2022-11-29 5:22 ` Andrew Jones
2022-11-29 5:22 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:09 ` Atish Patra
2022-11-28 21:09 ` Atish Patra
2022-11-29 5:46 ` Andrew Jones
2022-11-29 5:46 ` Andrew Jones
2022-12-03 12:18 ` Anup Patel
2022-12-03 12:18 ` Anup Patel
2022-11-28 16:14 ` [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-29 6:09 ` Andrew Jones
2022-11-29 6:09 ` Andrew Jones
2022-12-03 12:39 ` [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI Anup Patel
2022-12-03 12:39 ` Anup Patel
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