* [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
@ 2020-12-01 11:03 ` conor.dooley
0 siblings, 0 replies; 8+ messages in thread
From: conor.dooley @ 2020-12-01 11:03 UTC (permalink / raw)
To: robh+dt, damien.lemoal, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv
Cc: lewis.hanly, cyril.jean, daire.mcnamara, atish.patra, anup.patel,
david.abdurachmanov, Conor Dooley
From: Conor Dooley <conor.dooley@microchip.com>
Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
directory
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2daa6ee673f7..2241bdac4816 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14989,6 +14989,15 @@ F: arch/riscv/
N: riscv
K: riscv
+RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
+M: Lewis Hanly <lewis.hanly@microchip.com>
+M: Cyril Jean <cyril.jean@microchip.com>
+L: linux-riscv@lists.infradead.org
+S: Supported
+F: drivers/mailbox/mailbox-mpfs.c
+F: drivers/soc/microchip/
+F: include/soc/microchip/mpfs.h
+
RNBD BLOCK DRIVERS
M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
M: Jack Wang <jinpu.wang@cloud.ionos.com>
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
@ 2020-12-01 11:03 ` conor.dooley
0 siblings, 0 replies; 8+ messages in thread
From: conor.dooley @ 2020-12-01 11:03 UTC (permalink / raw)
To: robh+dt, damien.lemoal, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv
Cc: cyril.jean, david.abdurachmanov, daire.mcnamara, anup.patel,
atish.patra, Conor Dooley, lewis.hanly
From: Conor Dooley <conor.dooley@microchip.com>
Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
directory
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2daa6ee673f7..2241bdac4816 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14989,6 +14989,15 @@ F: arch/riscv/
N: riscv
K: riscv
+RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
+M: Lewis Hanly <lewis.hanly@microchip.com>
+M: Cyril Jean <cyril.jean@microchip.com>
+L: linux-riscv@lists.infradead.org
+S: Supported
+F: drivers/mailbox/mailbox-mpfs.c
+F: drivers/soc/microchip/
+F: include/soc/microchip/mpfs.h
+
RNBD BLOCK DRIVERS
M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
M: Jack Wang <jinpu.wang@cloud.ionos.com>
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
2020-12-01 11:03 ` conor.dooley
@ 2020-12-01 18:06 ` Atish Patra
-1 siblings, 0 replies; 8+ messages in thread
From: Atish Patra @ 2020-12-01 18:06 UTC (permalink / raw)
To: conor.dooley
Cc: Rob Herring, Damien Le Moal, jassisinghbrar, Albert Ou,
Paul Walmsley, Palmer Dabbelt, devicetree, linux-riscv,
cyril.jean, David Abdurachmanov, Daire McNamara, Anup Patel,
Atish Patra, lewis.hanly
On Tue, Dec 1, 2020 at 3:03 AM <conor.dooley@microchip.com> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
> directory
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
I think this patch will make more sense in my basic SoC support patch.
Can I include this patch in my series as is?
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2daa6ee673f7..2241bdac4816 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14989,6 +14989,15 @@ F: arch/riscv/
> N: riscv
> K: riscv
>
> +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
> +M: Lewis Hanly <lewis.hanly@microchip.com>
> +M: Cyril Jean <cyril.jean@microchip.com>
> +L: linux-riscv@lists.infradead.org
> +S: Supported
> +F: drivers/mailbox/mailbox-mpfs.c
> +F: drivers/soc/microchip/
> +F: include/soc/microchip/mpfs.h
> +
> RNBD BLOCK DRIVERS
> M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
> M: Jack Wang <jinpu.wang@cloud.ionos.com>
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
@ 2020-12-01 18:06 ` Atish Patra
0 siblings, 0 replies; 8+ messages in thread
From: Atish Patra @ 2020-12-01 18:06 UTC (permalink / raw)
To: conor.dooley
Cc: devicetree, Damien Le Moal, Albert Ou, cyril.jean,
David Abdurachmanov, Daire McNamara, jassisinghbrar, Atish Patra,
Anup Patel, Rob Herring, Palmer Dabbelt, Paul Walmsley,
lewis.hanly, linux-riscv
On Tue, Dec 1, 2020 at 3:03 AM <conor.dooley@microchip.com> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
> directory
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
I think this patch will make more sense in my basic SoC support patch.
Can I include this patch in my series as is?
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2daa6ee673f7..2241bdac4816 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14989,6 +14989,15 @@ F: arch/riscv/
> N: riscv
> K: riscv
>
> +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
> +M: Lewis Hanly <lewis.hanly@microchip.com>
> +M: Cyril Jean <cyril.jean@microchip.com>
> +L: linux-riscv@lists.infradead.org
> +S: Supported
> +F: drivers/mailbox/mailbox-mpfs.c
> +F: drivers/soc/microchip/
> +F: include/soc/microchip/mpfs.h
> +
> RNBD BLOCK DRIVERS
> M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
> M: Jack Wang <jinpu.wang@cloud.ionos.com>
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
2020-12-01 18:06 ` Atish Patra
@ 2020-12-02 9:13 ` Conor.Dooley
-1 siblings, 0 replies; 8+ messages in thread
From: Conor.Dooley @ 2020-12-02 9:13 UTC (permalink / raw)
To: atishp
Cc: devicetree, damien.lemoal, aou, Cyril.Jean, david.abdurachmanov,
Daire.McNamara, jassisinghbrar, atish.patra, anup.patel, robh+dt,
palmer, paul.walmsley, Lewis.Hanly, linux-riscv
On 01/12/2020 18:06, Atish Patra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Tue, Dec 1, 2020 at 3:03 AM <conor.dooley@microchip.com> wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
>> directory
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> I think this patch will make more sense in my basic SoC support patch.
> Can I include this patch in my series as is?
Eh sure, I don't mind.
Should it be split and I add the mailbox entry in my series & you do the rest?
>
>> ---
>> MAINTAINERS | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 2daa6ee673f7..2241bdac4816 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -14989,6 +14989,15 @@ F: arch/riscv/
>> N: riscv
>> K: riscv
>>
>> +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>> +M: Lewis Hanly <lewis.hanly@microchip.com>
>> +M: Cyril Jean <cyril.jean@microchip.com>
>> +L: linux-riscv@lists.infradead.org
>> +S: Supported
>> +F: drivers/mailbox/mailbox-mpfs.c
>> +F: drivers/soc/microchip/
>> +F: include/soc/microchip/mpfs.h
>> +
>> RNBD BLOCK DRIVERS
>> M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
>> M: Jack Wang <jinpu.wang@cloud.ionos.com>
>> --
>> 2.17.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
> --
> Regards,
> Atish
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
@ 2020-12-02 9:13 ` Conor.Dooley
0 siblings, 0 replies; 8+ messages in thread
From: Conor.Dooley @ 2020-12-02 9:13 UTC (permalink / raw)
To: atishp
Cc: devicetree, damien.lemoal, aou, Cyril.Jean, david.abdurachmanov,
Daire.McNamara, jassisinghbrar, atish.patra, anup.patel, robh+dt,
palmer, paul.walmsley, Lewis.Hanly, linux-riscv
On 01/12/2020 18:06, Atish Patra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Tue, Dec 1, 2020 at 3:03 AM <conor.dooley@microchip.com> wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
>> directory
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> I think this patch will make more sense in my basic SoC support patch.
> Can I include this patch in my series as is?
Eh sure, I don't mind.
Should it be split and I add the mailbox entry in my series & you do the rest?
>
>> ---
>> MAINTAINERS | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 2daa6ee673f7..2241bdac4816 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -14989,6 +14989,15 @@ F: arch/riscv/
>> N: riscv
>> K: riscv
>>
>> +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>> +M: Lewis Hanly <lewis.hanly@microchip.com>
>> +M: Cyril Jean <cyril.jean@microchip.com>
>> +L: linux-riscv@lists.infradead.org
>> +S: Supported
>> +F: drivers/mailbox/mailbox-mpfs.c
>> +F: drivers/soc/microchip/
>> +F: include/soc/microchip/mpfs.h
>> +
>> RNBD BLOCK DRIVERS
>> M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
>> M: Jack Wang <jinpu.wang@cloud.ionos.com>
>> --
>> 2.17.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
> --
> Regards,
> Atish
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
2020-12-02 9:13 ` Conor.Dooley
@ 2020-12-02 18:44 ` Atish Patra
-1 siblings, 0 replies; 8+ messages in thread
From: Atish Patra @ 2020-12-02 18:44 UTC (permalink / raw)
To: Conor.Dooley
Cc: devicetree, Damien Le Moal, Albert Ou, Cyril.Jean,
David Abdurachmanov, Daire McNamara, jassisinghbrar, Atish Patra,
Anup Patel, Rob Herring, Palmer Dabbelt, Paul Walmsley,
Lewis.Hanly, linux-riscv
On Wed, Dec 2, 2020 at 1:13 AM <Conor.Dooley@microchip.com> wrote:
>
> On 01/12/2020 18:06, Atish Patra wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Tue, Dec 1, 2020 at 3:03 AM <conor.dooley@microchip.com> wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
> >> directory
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > I think this patch will make more sense in my basic SoC support patch.
> > Can I include this patch in my series as is?
>
> Eh sure, I don't mind.
>
> Should it be split and I add the mailbox entry in my series & you do the rest?
>
Yeah. That's even better.
> >
> >> ---
> >> MAINTAINERS | 9 +++++++++
> >> 1 file changed, 9 insertions(+)
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index 2daa6ee673f7..2241bdac4816 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -14989,6 +14989,15 @@ F: arch/riscv/
> >> N: riscv
> >> K: riscv
> >>
> >> +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
> >> +M: Lewis Hanly <lewis.hanly@microchip.com>
> >> +M: Cyril Jean <cyril.jean@microchip.com>
> >> +L: linux-riscv@lists.infradead.org
> >> +S: Supported
> >> +F: drivers/mailbox/mailbox-mpfs.c
> >> +F: drivers/soc/microchip/
> >> +F: include/soc/microchip/mpfs.h
> >> +
> >> RNBD BLOCK DRIVERS
> >> M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
> >> M: Jack Wang <jinpu.wang@cloud.ionos.com>
> >> --
> >> 2.17.1
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> >
> > --
> > Regards,
> > Atish
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
@ 2020-12-02 18:44 ` Atish Patra
0 siblings, 0 replies; 8+ messages in thread
From: Atish Patra @ 2020-12-02 18:44 UTC (permalink / raw)
To: Conor.Dooley
Cc: devicetree, Damien Le Moal, Albert Ou, Cyril.Jean,
David Abdurachmanov, Daire McNamara, jassisinghbrar, Atish Patra,
Anup Patel, Rob Herring, Palmer Dabbelt, Paul Walmsley,
Lewis.Hanly, linux-riscv
On Wed, Dec 2, 2020 at 1:13 AM <Conor.Dooley@microchip.com> wrote:
>
> On 01/12/2020 18:06, Atish Patra wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Tue, Dec 1, 2020 at 3:03 AM <conor.dooley@microchip.com> wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
> >> directory
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > I think this patch will make more sense in my basic SoC support patch.
> > Can I include this patch in my series as is?
>
> Eh sure, I don't mind.
>
> Should it be split and I add the mailbox entry in my series & you do the rest?
>
Yeah. That's even better.
> >
> >> ---
> >> MAINTAINERS | 9 +++++++++
> >> 1 file changed, 9 insertions(+)
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index 2daa6ee673f7..2241bdac4816 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -14989,6 +14989,15 @@ F: arch/riscv/
> >> N: riscv
> >> K: riscv
> >>
> >> +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
> >> +M: Lewis Hanly <lewis.hanly@microchip.com>
> >> +M: Cyril Jean <cyril.jean@microchip.com>
> >> +L: linux-riscv@lists.infradead.org
> >> +S: Supported
> >> +F: drivers/mailbox/mailbox-mpfs.c
> >> +F: drivers/soc/microchip/
> >> +F: include/soc/microchip/mpfs.h
> >> +
> >> RNBD BLOCK DRIVERS
> >> M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
> >> M: Jack Wang <jinpu.wang@cloud.ionos.com>
> >> --
> >> 2.17.1
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> >
> > --
> > Regards,
> > Atish
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-12-02 18:49 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-01 11:03 [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support conor.dooley
2020-12-01 11:03 ` conor.dooley
2020-12-01 18:06 ` Atish Patra
2020-12-01 18:06 ` Atish Patra
2020-12-02 9:13 ` Conor.Dooley
2020-12-02 9:13 ` Conor.Dooley
2020-12-02 18:44 ` Atish Patra
2020-12-02 18:44 ` Atish Patra
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