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* [OpenRISC] [PATCH] libgloss/or1k: Correct the IMMU SXE and UXE flags
@ 2021-07-01 23:17 Stafford Horne
  2021-07-05 20:59 ` Jeff Johnston
  0 siblings, 1 reply; 4+ messages in thread
From: Stafford Horne @ 2021-07-01 23:17 UTC (permalink / raw)
  To: openrisc

These have been defined incorrectly, as per specification and CPU
implementations SXE is bit 6 and UXE is bit 7.  This was noticed when
tracking down our test suite mmu test failures.

 Test Suite: https://github.com/openrisc/or1k-tests/blob/master/native/or1k/or1k-mmu.c#L68-L72
 Spec: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.3-rev1.pdf

See section 8.4.8 Instruction Translation Lookaside Buffer Way y Translate
Registers where these are defined.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 libgloss/or1k/include/or1k-sprs.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/libgloss/or1k/include/or1k-sprs.h b/libgloss/or1k/include/or1k-sprs.h
index 8d1fe5ed9..d545fb1d3 100644
--- a/libgloss/or1k/include/or1k-sprs.h
+++ b/libgloss/or1k/include/or1k-sprs.h
@@ -1797,17 +1797,17 @@
 #define OR1K_SPR_IMMU_ITLBW_TR_D_GET(X) (((X) >> 5) & 0x1)
 #define OR1K_SPR_IMMU_ITLBW_TR_D_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5))
 
-/* User Execute Enable */
-#define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 6
-#define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK   0x00000040
-#define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 6) & 0x1)
-#define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6))
-
 /* Supervisor Execute Enable */
-#define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 7
-#define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK   0x00000080
-#define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 7) & 0x1)
-#define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7))
+#define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 6
+#define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK   0x00000040
+#define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 6) & 0x1)
+#define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6))
+
+/* User Execute Enable */
+#define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 7
+#define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK   0x00000080
+#define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 7) & 0x1)
+#define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7))
 
 /* Physical Page Number */
 #define OR1K_SPR_IMMU_ITLBW_TR_PPN_LSB    13
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [OpenRISC] [PATCH] libgloss/or1k: Correct the IMMU SXE and UXE flags
  2021-07-01 23:17 [OpenRISC] [PATCH] libgloss/or1k: Correct the IMMU SXE and UXE flags Stafford Horne
@ 2021-07-05 20:59 ` Jeff Johnston
  2021-07-05 21:21   ` Stafford Horne
  0 siblings, 1 reply; 4+ messages in thread
From: Jeff Johnston @ 2021-07-05 20:59 UTC (permalink / raw)
  To: openrisc

Hi Stafford,

Please resend with the patch as an attachment.

Thanks,

-- Jeff J.

On Thu, Jul 1, 2021 at 7:18 PM Stafford Horne <shorne@gmail.com> wrote:

> These have been defined incorrectly, as per specification and CPU
> implementations SXE is bit 6 and UXE is bit 7.  This was noticed when
> tracking down our test suite mmu test failures.
>
>  Test Suite:
> https://github.com/openrisc/or1k-tests/blob/master/native/or1k/or1k-mmu.c#L68-L72
>  Spec:
> https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.3-rev1.pdf
>
> See section 8.4.8 Instruction Translation Lookaside Buffer Way y Translate
> Registers where these are defined.
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>  libgloss/or1k/include/or1k-sprs.h | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/libgloss/or1k/include/or1k-sprs.h
> b/libgloss/or1k/include/or1k-sprs.h
> index 8d1fe5ed9..d545fb1d3 100644
> --- a/libgloss/or1k/include/or1k-sprs.h
> +++ b/libgloss/or1k/include/or1k-sprs.h
> @@ -1797,17 +1797,17 @@
>  #define OR1K_SPR_IMMU_ITLBW_TR_D_GET(X) (((X) >> 5) & 0x1)
>  #define OR1K_SPR_IMMU_ITLBW_TR_D_SET(X, Y) (((X) &
> OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5))
>
> -/* User Execute Enable */
> -#define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 6
> -#define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK   0x00000040
> -#define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 6) & 0x1)
> -#define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) &
> OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6))
> -
>  /* Supervisor Execute Enable */
> -#define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 7
> -#define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK   0x00000080
> -#define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 7) & 0x1)
> -#define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) &
> OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7))
> +#define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 6
> +#define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK   0x00000040
> +#define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 6) & 0x1)
> +#define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) &
> OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6))
> +
> +/* User Execute Enable */
> +#define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 7
> +#define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK   0x00000080
> +#define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 7) & 0x1)
> +#define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) &
> OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7))
>
>  /* Physical Page Number */
>  #define OR1K_SPR_IMMU_ITLBW_TR_PPN_LSB    13
> --
> 2.31.1
>
>
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^ permalink raw reply	[flat|nested] 4+ messages in thread
* [OpenRISC] [PATCH] libgloss/or1k: Correct the IMMU SXE and UXE flags
  2021-07-05 20:59 ` Jeff Johnston
@ 2021-07-05 21:21   ` Stafford Horne
  2021-07-05 22:03     ` Jeff Johnston
  0 siblings, 1 reply; 4+ messages in thread
From: Stafford Horne @ 2021-07-05 21:21 UTC (permalink / raw)
  To: openrisc

On Mon, Jul 05, 2021 at 04:59:27PM -0400, Jeff Johnston wrote:
> Hi Stafford,
> 
> Please resend with the patch as an attachment.
> 
> Thanks,

Alright,

I hope it't OK in a reply here.  I usually send patches using git send-email, is
this something new for newlib?

Please find attached

-Stafford
-------------- next part --------------
From f25c7124bc88627baf532d79c08130f1d2b61efb Mon Sep 17 00:00:00 2001
From: Stafford Horne <shorne@gmail.com>
Date: Fri, 2 Jul 2021 06:24:57 +0900
Subject: [PATCH] libgloss/or1k: Correct the IMMU SXE and UXE flags

These have been defined incorrectly, as per specification and CPU
implementations SXE is bit 6 and UXE is bit 7.  This was noticed when
tracking down our test suite mmu test failures.

 Test Suite: https://github.com/openrisc/or1k-tests/blob/master/native/or1k/or1k-mmu.c#L68-L72
 Spec: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.3-rev1.pdf

See section 8.4.8 Instruction Translation Lookaside Buffer Way y Translate
Registers where these are defined.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 libgloss/or1k/include/or1k-sprs.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/libgloss/or1k/include/or1k-sprs.h b/libgloss/or1k/include/or1k-sprs.h
index 8d1fe5ed9..d545fb1d3 100644
--- a/libgloss/or1k/include/or1k-sprs.h
+++ b/libgloss/or1k/include/or1k-sprs.h
@@ -1797,17 +1797,17 @@
 #define OR1K_SPR_IMMU_ITLBW_TR_D_GET(X) (((X) >> 5) & 0x1)
 #define OR1K_SPR_IMMU_ITLBW_TR_D_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5))
 
-/* User Execute Enable */
-#define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 6
-#define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK   0x00000040
-#define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 6) & 0x1)
-#define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6))
-
 /* Supervisor Execute Enable */
-#define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 7
-#define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK   0x00000080
-#define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 7) & 0x1)
-#define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7))
+#define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 6
+#define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK   0x00000040
+#define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 6) & 0x1)
+#define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6))
+
+/* User Execute Enable */
+#define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 7
+#define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK   0x00000080
+#define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 7) & 0x1)
+#define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7))
 
 /* Physical Page Number */
 #define OR1K_SPR_IMMU_ITLBW_TR_PPN_LSB    13
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [OpenRISC] [PATCH] libgloss/or1k: Correct the IMMU SXE and UXE flags
  2021-07-05 21:21   ` Stafford Horne
@ 2021-07-05 22:03     ` Jeff Johnston
  0 siblings, 0 replies; 4+ messages in thread
From: Jeff Johnston @ 2021-07-05 22:03 UTC (permalink / raw)
  To: openrisc

Hi Stafford,

It's not you, it's on my side with gmail..  It often distorts git patches
unless they are attachments.

Anyway, patch applied and pushed to master.

Regards,

-- Jeff J.

On Mon, Jul 5, 2021 at 5:21 PM Stafford Horne <shorne@gmail.com> wrote:

> On Mon, Jul 05, 2021 at 04:59:27PM -0400, Jeff Johnston wrote:
> > Hi Stafford,
> >
> > Please resend with the patch as an attachment.
> >
> > Thanks,
>
> Alright,
>
> I hope it't OK in a reply here.  I usually send patches using git
> send-email, is
> this something new for newlib?
>
> Please find attached
>
> -Stafford
>
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-- links below jump to the message on this page --
2021-07-01 23:17 [OpenRISC] [PATCH] libgloss/or1k: Correct the IMMU SXE and UXE flags Stafford Horne
2021-07-05 20:59 ` Jeff Johnston
2021-07-05 21:21   ` Stafford Horne
2021-07-05 22:03     ` Jeff Johnston

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