* vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE)
@ 2013-06-28 21:02 Cyclonus J
2013-07-01 9:38 ` Jan Beulich
0 siblings, 1 reply; 6+ messages in thread
From: Cyclonus J @ 2013-06-28 21:02 UTC (permalink / raw)
To: Xen-devel; +Cc: keir.fraser
[-- Attachment #1.1: Type: text/plain, Size: 139 bytes --]
Hi,
I am wondering if we can disable the VMX interception for
MSR_SHADOW_GS_BASE as AMD is already doing that.
Any comments?
Thanks,
CJ
[-- Attachment #1.2: Type: text/html, Size: 207 bytes --]
[-- Attachment #2: Type: text/plain, Size: 126 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE)
2013-06-28 21:02 vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE) Cyclonus J
@ 2013-07-01 9:38 ` Jan Beulich
2013-07-01 9:44 ` Andrew Cooper
0 siblings, 1 reply; 6+ messages in thread
From: Jan Beulich @ 2013-07-01 9:38 UTC (permalink / raw)
To: Cyclonus J; +Cc: xen-devel
>>> On 28.06.13 at 23:02, Cyclonus J <cyclonusj@gmail.com> wrote:
> I am wondering if we can disable the VMX interception for
> MSR_SHADOW_GS_BASE as AMD is already doing that.
I can't immediately see any reason why we shouldn't be permitted
to do this, but I also don't think this should be performance critical.
If you feel this is important, why don't you contribute a patch,
with its description saying under what conditions this can yield
measurable benefit?
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE)
2013-07-01 9:38 ` Jan Beulich
@ 2013-07-01 9:44 ` Andrew Cooper
2013-07-01 9:48 ` Jan Beulich
2013-07-01 9:51 ` Keir Fraser
0 siblings, 2 replies; 6+ messages in thread
From: Andrew Cooper @ 2013-07-01 9:44 UTC (permalink / raw)
To: Jan Beulich; +Cc: Cyclonus J, xen-devel
On 01/07/13 10:38, Jan Beulich wrote:
>>>> On 28.06.13 at 23:02, Cyclonus J <cyclonusj@gmail.com> wrote:
>> I am wondering if we can disable the VMX interception for
>> MSR_SHADOW_GS_BASE as AMD is already doing that.
> I can't immediately see any reason why we shouldn't be permitted
> to do this, but I also don't think this should be performance critical.
>
> If you feel this is important, why don't you contribute a patch,
> with its description saying under what conditions this can yield
> measurable benefit?
>
> Jan
Will this not cause a VMexit on each swapgs instruction, as the
instruction itself does write to MSR 0xC0000102?
I have looked quite closely through the Intel manuals and cant find
confirmation one way or another.
~Andrew
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE)
2013-07-01 9:44 ` Andrew Cooper
@ 2013-07-01 9:48 ` Jan Beulich
2013-07-01 9:51 ` Keir Fraser
1 sibling, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2013-07-01 9:48 UTC (permalink / raw)
To: Andrew Cooper; +Cc: Cyclonus J, xen-devel
>>> On 01.07.13 at 11:44, Andrew Cooper <andrew.cooper3@citrix.com> wrote:
> On 01/07/13 10:38, Jan Beulich wrote:
>>>>> On 28.06.13 at 23:02, Cyclonus J <cyclonusj@gmail.com> wrote:
>>> I am wondering if we can disable the VMX interception for
>>> MSR_SHADOW_GS_BASE as AMD is already doing that.
>> I can't immediately see any reason why we shouldn't be permitted
>> to do this, but I also don't think this should be performance critical.
>>
>> If you feel this is important, why don't you contribute a patch,
>> with its description saying under what conditions this can yield
>> measurable benefit?
>
> Will this not cause a VMexit on each swapgs instruction, as the
> instruction itself does write to MSR 0xC0000102?
No - see the comments in vmx.c around the handling of that MSR.
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE)
2013-07-01 9:44 ` Andrew Cooper
2013-07-01 9:48 ` Jan Beulich
@ 2013-07-01 9:51 ` Keir Fraser
2013-07-01 10:00 ` Andrew Cooper
1 sibling, 1 reply; 6+ messages in thread
From: Keir Fraser @ 2013-07-01 9:51 UTC (permalink / raw)
To: Andrew Cooper, Jan Beulich; +Cc: Cyclonus J, xen-devel
On 01/07/2013 10:44, "Andrew Cooper" <andrew.cooper3@citrix.com> wrote:
> On 01/07/13 10:38, Jan Beulich wrote:
>>>>> On 28.06.13 at 23:02, Cyclonus J <cyclonusj@gmail.com> wrote:
>>> I am wondering if we can disable the VMX interception for
>>> MSR_SHADOW_GS_BASE as AMD is already doing that.
>> I can't immediately see any reason why we shouldn't be permitted
>> to do this, but I also don't think this should be performance critical.
>>
>> If you feel this is important, why don't you contribute a patch,
>> with its description saying under what conditions this can yield
>> measurable benefit?
>>
>> Jan
>
> Will this not cause a VMexit on each swapgs instruction, as the
> instruction itself does write to MSR 0xC0000102?
>
> I have looked quite closely through the Intel manuals and cant find
> confirmation one way or another.
Only RDMSR/WRMSR trap on the MSR bitmaps.
> ~Andrew
>
>>
>>
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xen.org
>> http://lists.xen.org/xen-devel
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE)
2013-07-01 9:51 ` Keir Fraser
@ 2013-07-01 10:00 ` Andrew Cooper
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Cooper @ 2013-07-01 10:00 UTC (permalink / raw)
To: Keir Fraser; +Cc: Cyclonus J, Jan Beulich, xen-devel
On 01/07/13 10:51, Keir Fraser wrote:
> On 01/07/2013 10:44, "Andrew Cooper" <andrew.cooper3@citrix.com> wrote:
>
>> On 01/07/13 10:38, Jan Beulich wrote:
>>>>>> On 28.06.13 at 23:02, Cyclonus J <cyclonusj@gmail.com> wrote:
>>>> I am wondering if we can disable the VMX interception for
>>>> MSR_SHADOW_GS_BASE as AMD is already doing that.
>>> I can't immediately see any reason why we shouldn't be permitted
>>> to do this, but I also don't think this should be performance critical.
>>>
>>> If you feel this is important, why don't you contribute a patch,
>>> with its description saying under what conditions this can yield
>>> measurable benefit?
>>>
>>> Jan
>> Will this not cause a VMexit on each swapgs instruction, as the
>> instruction itself does write to MSR 0xC0000102?
>>
>> I have looked quite closely through the Intel manuals and cant find
>> confirmation one way or another.
> Only RDMSR/WRMSR trap on the MSR bitmaps.
Ok - so the performance aspect depends on whether the guest is using
per-thread kernel areas or not, in combination with swapgs.
I would have thought that this would be a sensible change to make at the
start of 4.4
~Andrew
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-07-01 10:00 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-06-28 21:02 vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE) Cyclonus J
2013-07-01 9:38 ` Jan Beulich
2013-07-01 9:44 ` Andrew Cooper
2013-07-01 9:48 ` Jan Beulich
2013-07-01 9:51 ` Keir Fraser
2013-07-01 10:00 ` Andrew Cooper
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.