* [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some hybrid cache events
@ 2022-09-22 1:49 zhengjun.xing
2022-09-22 1:49 ` [PATCH 2/2] perf parse-events: Remove "not supported" " zhengjun.xing
2022-09-22 3:12 ` [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some " Ian Rogers
0 siblings, 2 replies; 6+ messages in thread
From: zhengjun.xing @ 2022-09-22 1:49 UTC (permalink / raw)
To: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung
Cc: linux-kernel, linux-perf-users, irogers, ak, kan.liang, zhengjun.xing
From: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Some hybrid hardware cache events are only available on one CPU PMU. For
example, 'L1-dcache-load-misses' is only available on cpu_core. We have
supported in the perf list clearly reporting this info, the function works
fine before but recently the argument "config" in API is_event_supported()
is changed from "u64" to "unsigned int" which caused a regression, the
"perf list" then can not display the PMU prefix for some hybrid cache
events. For the hybrid systems, the PMU type ID is stored at config[63:32],
define config to "unsigned int" will miss the PMU type ID information, then
the regression happened, the config should be defined as "u64".
Before:
# ./perf list |grep "Hardware cache event"
L1-dcache-load-misses [Hardware cache event]
L1-dcache-loads [Hardware cache event]
L1-dcache-stores [Hardware cache event]
L1-icache-load-misses [Hardware cache event]
L1-icache-loads [Hardware cache event]
LLC-load-misses [Hardware cache event]
LLC-loads [Hardware cache event]
LLC-store-misses [Hardware cache event]
LLC-stores [Hardware cache event]
branch-load-misses [Hardware cache event]
branch-loads [Hardware cache event]
dTLB-load-misses [Hardware cache event]
dTLB-loads [Hardware cache event]
dTLB-store-misses [Hardware cache event]
dTLB-stores [Hardware cache event]
iTLB-load-misses [Hardware cache event]
node-load-misses [Hardware cache event]
node-loads [Hardware cache event]
After:
# ./perf list |grep "Hardware cache event"
L1-dcache-loads [Hardware cache event]
L1-dcache-stores [Hardware cache event]
L1-icache-load-misses [Hardware cache event]
LLC-load-misses [Hardware cache event]
LLC-loads [Hardware cache event]
LLC-store-misses [Hardware cache event]
LLC-stores [Hardware cache event]
branch-load-misses [Hardware cache event]
branch-loads [Hardware cache event]
cpu_atom/L1-icache-loads/ [Hardware cache event]
cpu_core/L1-dcache-load-misses/ [Hardware cache event]
cpu_core/node-load-misses/ [Hardware cache event]
cpu_core/node-loads/ [Hardware cache event]
dTLB-load-misses [Hardware cache event]
dTLB-loads [Hardware cache event]
dTLB-store-misses [Hardware cache event]
dTLB-stores [Hardware cache event]
iTLB-load-misses [Hardware cache event]
Fixes: 9b7c7728f4e4 ("perf parse-events: Break out tracepoint and printing")
Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
---
tools/perf/util/print-events.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c
index ba1ab5134685..04050d4f6db8 100644
--- a/tools/perf/util/print-events.c
+++ b/tools/perf/util/print-events.c
@@ -239,7 +239,7 @@ void print_sdt_events(const char *subsys_glob, const char *event_glob,
strlist__delete(sdtlist);
}
-static bool is_event_supported(u8 type, unsigned int config)
+static bool is_event_supported(u8 type, u64 config)
{
bool ret = true;
int open_return;
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] perf parse-events: Remove "not supported" hybrid cache events 2022-09-22 1:49 [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some hybrid cache events zhengjun.xing @ 2022-09-22 1:49 ` zhengjun.xing 2022-09-22 3:16 ` Ian Rogers 2022-09-22 3:12 ` [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some " Ian Rogers 1 sibling, 1 reply; 6+ messages in thread From: zhengjun.xing @ 2022-09-22 1:49 UTC (permalink / raw) To: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung Cc: linux-kernel, linux-perf-users, irogers, ak, kan.liang, zhengjun.xing From: Zhengjun Xing <zhengjun.xing@linux.intel.com> By default, we create two hybrid cache events, one is for cpu_core, and another is for cpu_atom. But Some hybrid hardware cache events are only available on one CPU PMU. For example, the 'L1-dcache-load-misses' is only available on cpu_core, while the 'L1-icache-loads' is only available on cpu_atom. We need to remove "not supported" hybrid cache events. By extending is_event_supported() to global API and using it to check if the hybrid cache events are supported before being created, we can remove the "not supported" hybrid cache events. Before: # ./perf stat -e L1-dcache-load-misses,L1-icache-loads -a sleep 1 Performance counter stats for 'system wide': 52,570 cpu_core/L1-dcache-load-misses/ <not supported> cpu_atom/L1-dcache-load-misses/ <not supported> cpu_core/L1-icache-loads/ 1,471,817 cpu_atom/L1-icache-loads/ 1.004915229 seconds time elapsed After: # ./perf stat -e L1-dcache-load-misses,L1-icache-loads -a sleep 1 Performance counter stats for 'system wide': 54,510 cpu_core/L1-dcache-load-misses/ 1,441,286 cpu_atom/L1-icache-loads/ 1.005114281 seconds time elapsed Fixes: 30def61f64ba ("perf parse-events: Create two hybrid cache events") Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> --- tools/perf/util/parse-events-hybrid.c | 8 +++++++- tools/perf/util/print-events.c | 2 +- tools/perf/util/print-events.h | 3 ++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/parse-events-hybrid.c b/tools/perf/util/parse-events-hybrid.c index 284f8eabd3b9..cf2e1c2e968f 100644 --- a/tools/perf/util/parse-events-hybrid.c +++ b/tools/perf/util/parse-events-hybrid.c @@ -14,6 +14,7 @@ #include "pmu.h" #include "pmu-hybrid.h" #include "perf.h" +#include "print-events.h" static void config_hybrid_attr(struct perf_event_attr *attr, int type, int pmu_type) @@ -48,13 +49,18 @@ static int create_event_hybrid(__u32 config_type, int *idx, __u64 config = attr->config; config_hybrid_attr(attr, config_type, pmu->type); + + if (attr->type == PERF_TYPE_HW_CACHE + && !is_event_supported(attr->type, attr->config)) + goto out; + evsel = parse_events__add_event_hybrid(list, idx, attr, name, metric_id, pmu, config_terms); if (evsel) evsel->pmu_name = strdup(pmu->name); else return -ENOMEM; - +out: attr->type = type; attr->config = config; return 0; diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index 04050d4f6db8..fa5cc94cfcfe 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -239,7 +239,7 @@ void print_sdt_events(const char *subsys_glob, const char *event_glob, strlist__delete(sdtlist); } -static bool is_event_supported(u8 type, u64 config) +bool is_event_supported(u8 type, u64 config) { bool ret = true; int open_return; diff --git a/tools/perf/util/print-events.h b/tools/perf/util/print-events.h index 1da9910d83a6..ad2902fd0507 100644 --- a/tools/perf/util/print-events.h +++ b/tools/perf/util/print-events.h @@ -1,14 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __PERF_PRINT_EVENTS_H #define __PERF_PRINT_EVENTS_H - #include <stdbool.h> +#include <linux/types.h> struct event_symbol; void print_events(const char *event_glob, bool name_only, bool quiet_flag, bool long_desc, bool details_flag, bool deprecated, const char *pmu_name); +bool is_event_supported(u8 type, u64 config); int print_hwcache_events(const char *event_glob, bool name_only); void print_sdt_events(const char *subsys_glob, const char *event_glob, bool name_only); -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] perf parse-events: Remove "not supported" hybrid cache events 2022-09-22 1:49 ` [PATCH 2/2] perf parse-events: Remove "not supported" " zhengjun.xing @ 2022-09-22 3:16 ` Ian Rogers 2022-09-22 8:04 ` Xing Zhengjun 0 siblings, 1 reply; 6+ messages in thread From: Ian Rogers @ 2022-09-22 3:16 UTC (permalink / raw) To: zhengjun.xing Cc: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung, linux-kernel, linux-perf-users, ak, kan.liang On Wed, Sep 21, 2022 at 6:47 PM <zhengjun.xing@linux.intel.com> wrote: > > From: Zhengjun Xing <zhengjun.xing@linux.intel.com> > > By default, we create two hybrid cache events, one is for cpu_core, and > another is for cpu_atom. But Some hybrid hardware cache events are only > available on one CPU PMU. For example, the 'L1-dcache-load-misses' is only > available on cpu_core, while the 'L1-icache-loads' is only available on > cpu_atom. We need to remove "not supported" hybrid cache events. By > extending is_event_supported() to global API and using it to check if the > hybrid cache events are supported before being created, we can remove the > "not supported" hybrid cache events. > > Before: > > # ./perf stat -e L1-dcache-load-misses,L1-icache-loads -a sleep 1 > > Performance counter stats for 'system wide': > > 52,570 cpu_core/L1-dcache-load-misses/ > <not supported> cpu_atom/L1-dcache-load-misses/ > <not supported> cpu_core/L1-icache-loads/ > 1,471,817 cpu_atom/L1-icache-loads/ > > 1.004915229 seconds time elapsed > > After: > > # ./perf stat -e L1-dcache-load-misses,L1-icache-loads -a sleep 1 > > Performance counter stats for 'system wide': > > 54,510 cpu_core/L1-dcache-load-misses/ > 1,441,286 cpu_atom/L1-icache-loads/ > > 1.005114281 seconds time elapsed > > Fixes: 30def61f64ba ("perf parse-events: Create two hybrid cache events") > Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > Reviewed-by: Kan Liang <kan.liang@linux.intel.com> > --- > tools/perf/util/parse-events-hybrid.c | 8 +++++++- > tools/perf/util/print-events.c | 2 +- > tools/perf/util/print-events.h | 3 ++- > 3 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/tools/perf/util/parse-events-hybrid.c b/tools/perf/util/parse-events-hybrid.c > index 284f8eabd3b9..cf2e1c2e968f 100644 > --- a/tools/perf/util/parse-events-hybrid.c > +++ b/tools/perf/util/parse-events-hybrid.c > @@ -14,6 +14,7 @@ > #include "pmu.h" > #include "pmu-hybrid.h" > #include "perf.h" > +#include "print-events.h" > > static void config_hybrid_attr(struct perf_event_attr *attr, > int type, int pmu_type) > @@ -48,13 +49,18 @@ static int create_event_hybrid(__u32 config_type, int *idx, > __u64 config = attr->config; > > config_hybrid_attr(attr, config_type, pmu->type); > + > + if (attr->type == PERF_TYPE_HW_CACHE > + && !is_event_supported(attr->type, attr->config)) > + goto out; A comment to explain this would be useful. > + > evsel = parse_events__add_event_hybrid(list, idx, attr, name, metric_id, > pmu, config_terms); > if (evsel) > evsel->pmu_name = strdup(pmu->name); > else > return -ENOMEM; For consistency should this use the "goto" pattern now? You can also handle the ENOMEM case for strdup. > - > +out: > attr->type = type; > attr->config = config; > return 0; > diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c > index 04050d4f6db8..fa5cc94cfcfe 100644 > --- a/tools/perf/util/print-events.c > +++ b/tools/perf/util/print-events.c > @@ -239,7 +239,7 @@ void print_sdt_events(const char *subsys_glob, const char *event_glob, > strlist__delete(sdtlist); > } > > -static bool is_event_supported(u8 type, u64 config) > +bool is_event_supported(u8 type, u64 config) This makes me tempted to say this function should be in parse-events.c. Thanks, Ian > { > bool ret = true; > int open_return; > diff --git a/tools/perf/util/print-events.h b/tools/perf/util/print-events.h > index 1da9910d83a6..ad2902fd0507 100644 > --- a/tools/perf/util/print-events.h > +++ b/tools/perf/util/print-events.h > @@ -1,14 +1,15 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > #ifndef __PERF_PRINT_EVENTS_H > #define __PERF_PRINT_EVENTS_H > - > #include <stdbool.h> > +#include <linux/types.h> > > struct event_symbol; > > void print_events(const char *event_glob, bool name_only, bool quiet_flag, > bool long_desc, bool details_flag, bool deprecated, > const char *pmu_name); > +bool is_event_supported(u8 type, u64 config); > int print_hwcache_events(const char *event_glob, bool name_only); > void print_sdt_events(const char *subsys_glob, const char *event_glob, > bool name_only); > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] perf parse-events: Remove "not supported" hybrid cache events 2022-09-22 3:16 ` Ian Rogers @ 2022-09-22 8:04 ` Xing Zhengjun 0 siblings, 0 replies; 6+ messages in thread From: Xing Zhengjun @ 2022-09-22 8:04 UTC (permalink / raw) To: Ian Rogers Cc: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung, linux-kernel, linux-perf-users, ak, kan.liang On 9/22/2022 11:16 AM, Ian Rogers wrote: > On Wed, Sep 21, 2022 at 6:47 PM <zhengjun.xing@linux.intel.com> wrote: >> >> From: Zhengjun Xing <zhengjun.xing@linux.intel.com> >> >> By default, we create two hybrid cache events, one is for cpu_core, and >> another is for cpu_atom. But Some hybrid hardware cache events are only >> available on one CPU PMU. For example, the 'L1-dcache-load-misses' is only >> available on cpu_core, while the 'L1-icache-loads' is only available on >> cpu_atom. We need to remove "not supported" hybrid cache events. By >> extending is_event_supported() to global API and using it to check if the >> hybrid cache events are supported before being created, we can remove the >> "not supported" hybrid cache events. >> >> Before: >> >> # ./perf stat -e L1-dcache-load-misses,L1-icache-loads -a sleep 1 >> >> Performance counter stats for 'system wide': >> >> 52,570 cpu_core/L1-dcache-load-misses/ >> <not supported> cpu_atom/L1-dcache-load-misses/ >> <not supported> cpu_core/L1-icache-loads/ >> 1,471,817 cpu_atom/L1-icache-loads/ >> >> 1.004915229 seconds time elapsed >> >> After: >> >> # ./perf stat -e L1-dcache-load-misses,L1-icache-loads -a sleep 1 >> >> Performance counter stats for 'system wide': >> >> 54,510 cpu_core/L1-dcache-load-misses/ >> 1,441,286 cpu_atom/L1-icache-loads/ >> >> 1.005114281 seconds time elapsed >> >> Fixes: 30def61f64ba ("perf parse-events: Create two hybrid cache events") >> Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> >> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> >> --- >> tools/perf/util/parse-events-hybrid.c | 8 +++++++- >> tools/perf/util/print-events.c | 2 +- >> tools/perf/util/print-events.h | 3 ++- >> 3 files changed, 10 insertions(+), 3 deletions(-) >> >> diff --git a/tools/perf/util/parse-events-hybrid.c b/tools/perf/util/parse-events-hybrid.c >> index 284f8eabd3b9..cf2e1c2e968f 100644 >> --- a/tools/perf/util/parse-events-hybrid.c >> +++ b/tools/perf/util/parse-events-hybrid.c >> @@ -14,6 +14,7 @@ >> #include "pmu.h" >> #include "pmu-hybrid.h" >> #include "perf.h" >> +#include "print-events.h" >> >> static void config_hybrid_attr(struct perf_event_attr *attr, >> int type, int pmu_type) >> @@ -48,13 +49,18 @@ static int create_event_hybrid(__u32 config_type, int *idx, >> __u64 config = attr->config; >> >> config_hybrid_attr(attr, config_type, pmu->type); >> + >> + if (attr->type == PERF_TYPE_HW_CACHE >> + && !is_event_supported(attr->type, attr->config)) >> + goto out; > > A comment to explain this would be useful. Thanks, I will add a comment in the next version. > >> + >> evsel = parse_events__add_event_hybrid(list, idx, attr, name, metric_id, >> pmu, config_terms); >> if (evsel) >> evsel->pmu_name = strdup(pmu->name); >> else >> return -ENOMEM; > > For consistency should this use the "goto" pattern now? You can also > handle the ENOMEM case for strdup. > Yes, I will add a strdup check in the next version. >> - >> +out: >> attr->type = type; >> attr->config = config; >> return 0; >> diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c >> index 04050d4f6db8..fa5cc94cfcfe 100644 >> --- a/tools/perf/util/print-events.c >> +++ b/tools/perf/util/print-events.c >> @@ -239,7 +239,7 @@ void print_sdt_events(const char *subsys_glob, const char *event_glob, >> strlist__delete(sdtlist); >> } >> >> -static bool is_event_supported(u8 type, u64 config) >> +bool is_event_supported(u8 type, u64 config) > > This makes me tempted to say this function should be in parse-events.c. > "is_event_supported" move to parse-events.c should be better, I will do it in the next version. > Thanks, > Ian > >> { >> bool ret = true; >> int open_return; >> diff --git a/tools/perf/util/print-events.h b/tools/perf/util/print-events.h >> index 1da9910d83a6..ad2902fd0507 100644 >> --- a/tools/perf/util/print-events.h >> +++ b/tools/perf/util/print-events.h >> @@ -1,14 +1,15 @@ >> /* SPDX-License-Identifier: GPL-2.0 */ >> #ifndef __PERF_PRINT_EVENTS_H >> #define __PERF_PRINT_EVENTS_H >> - >> #include <stdbool.h> >> +#include <linux/types.h> >> >> struct event_symbol; >> >> void print_events(const char *event_glob, bool name_only, bool quiet_flag, >> bool long_desc, bool details_flag, bool deprecated, >> const char *pmu_name); >> +bool is_event_supported(u8 type, u64 config); >> int print_hwcache_events(const char *event_glob, bool name_only); >> void print_sdt_events(const char *subsys_glob, const char *event_glob, >> bool name_only); >> -- >> 2.25.1 >> -- Zhengjun Xing ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some hybrid cache events 2022-09-22 1:49 [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some hybrid cache events zhengjun.xing 2022-09-22 1:49 ` [PATCH 2/2] perf parse-events: Remove "not supported" " zhengjun.xing @ 2022-09-22 3:12 ` Ian Rogers 2022-09-22 6:44 ` Xing Zhengjun 1 sibling, 1 reply; 6+ messages in thread From: Ian Rogers @ 2022-09-22 3:12 UTC (permalink / raw) To: zhengjun.xing Cc: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung, linux-kernel, linux-perf-users, ak, kan.liang On Wed, Sep 21, 2022 at 6:47 PM <zhengjun.xing@linux.intel.com> wrote: > > From: Zhengjun Xing <zhengjun.xing@linux.intel.com> > > Some hybrid hardware cache events are only available on one CPU PMU. For > example, 'L1-dcache-load-misses' is only available on cpu_core. We have > supported in the perf list clearly reporting this info, the function works > fine before but recently the argument "config" in API is_event_supported() > is changed from "u64" to "unsigned int" which caused a regression, the > "perf list" then can not display the PMU prefix for some hybrid cache > events. For the hybrid systems, the PMU type ID is stored at config[63:32], > define config to "unsigned int" will miss the PMU type ID information, then > the regression happened, the config should be defined as "u64". > > Before: > # ./perf list |grep "Hardware cache event" > L1-dcache-load-misses [Hardware cache event] > L1-dcache-loads [Hardware cache event] > L1-dcache-stores [Hardware cache event] > L1-icache-load-misses [Hardware cache event] > L1-icache-loads [Hardware cache event] > LLC-load-misses [Hardware cache event] > LLC-loads [Hardware cache event] > LLC-store-misses [Hardware cache event] > LLC-stores [Hardware cache event] > branch-load-misses [Hardware cache event] > branch-loads [Hardware cache event] > dTLB-load-misses [Hardware cache event] > dTLB-loads [Hardware cache event] > dTLB-store-misses [Hardware cache event] > dTLB-stores [Hardware cache event] > iTLB-load-misses [Hardware cache event] > node-load-misses [Hardware cache event] > node-loads [Hardware cache event] > > After: > # ./perf list |grep "Hardware cache event" > L1-dcache-loads [Hardware cache event] > L1-dcache-stores [Hardware cache event] > L1-icache-load-misses [Hardware cache event] > LLC-load-misses [Hardware cache event] > LLC-loads [Hardware cache event] > LLC-store-misses [Hardware cache event] > LLC-stores [Hardware cache event] > branch-load-misses [Hardware cache event] > branch-loads [Hardware cache event] > cpu_atom/L1-icache-loads/ [Hardware cache event] > cpu_core/L1-dcache-load-misses/ [Hardware cache event] > cpu_core/node-load-misses/ [Hardware cache event] > cpu_core/node-loads/ [Hardware cache event] > dTLB-load-misses [Hardware cache event] > dTLB-loads [Hardware cache event] > dTLB-store-misses [Hardware cache event] > dTLB-stores [Hardware cache event] > iTLB-load-misses [Hardware cache event] > > Fixes: 9b7c7728f4e4 ("perf parse-events: Break out tracepoint and printing") > Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Acked-by: Ian Rogers <irogers@google.com> Sorry for this breakage, I suspect that a long review on the refactoring CL meant that I missed the intervening fix. Can we add a test on this? It would need to be hybrid specific and skip otherwise. Thanks, Ian > --- > tools/perf/util/print-events.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c > index ba1ab5134685..04050d4f6db8 100644 > --- a/tools/perf/util/print-events.c > +++ b/tools/perf/util/print-events.c > @@ -239,7 +239,7 @@ void print_sdt_events(const char *subsys_glob, const char *event_glob, > strlist__delete(sdtlist); > } > > -static bool is_event_supported(u8 type, unsigned int config) > +static bool is_event_supported(u8 type, u64 config) > { > bool ret = true; > int open_return; > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some hybrid cache events 2022-09-22 3:12 ` [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some " Ian Rogers @ 2022-09-22 6:44 ` Xing Zhengjun 0 siblings, 0 replies; 6+ messages in thread From: Xing Zhengjun @ 2022-09-22 6:44 UTC (permalink / raw) To: Ian Rogers Cc: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung, linux-kernel, linux-perf-users, ak, kan.liang On 9/22/2022 11:12 AM, Ian Rogers wrote: > On Wed, Sep 21, 2022 at 6:47 PM <zhengjun.xing@linux.intel.com> wrote: >> >> From: Zhengjun Xing <zhengjun.xing@linux.intel.com> >> >> Some hybrid hardware cache events are only available on one CPU PMU. For >> example, 'L1-dcache-load-misses' is only available on cpu_core. We have >> supported in the perf list clearly reporting this info, the function works >> fine before but recently the argument "config" in API is_event_supported() >> is changed from "u64" to "unsigned int" which caused a regression, the >> "perf list" then can not display the PMU prefix for some hybrid cache >> events. For the hybrid systems, the PMU type ID is stored at config[63:32], >> define config to "unsigned int" will miss the PMU type ID information, then >> the regression happened, the config should be defined as "u64". >> >> Before: >> # ./perf list |grep "Hardware cache event" >> L1-dcache-load-misses [Hardware cache event] >> L1-dcache-loads [Hardware cache event] >> L1-dcache-stores [Hardware cache event] >> L1-icache-load-misses [Hardware cache event] >> L1-icache-loads [Hardware cache event] >> LLC-load-misses [Hardware cache event] >> LLC-loads [Hardware cache event] >> LLC-store-misses [Hardware cache event] >> LLC-stores [Hardware cache event] >> branch-load-misses [Hardware cache event] >> branch-loads [Hardware cache event] >> dTLB-load-misses [Hardware cache event] >> dTLB-loads [Hardware cache event] >> dTLB-store-misses [Hardware cache event] >> dTLB-stores [Hardware cache event] >> iTLB-load-misses [Hardware cache event] >> node-load-misses [Hardware cache event] >> node-loads [Hardware cache event] >> >> After: >> # ./perf list |grep "Hardware cache event" >> L1-dcache-loads [Hardware cache event] >> L1-dcache-stores [Hardware cache event] >> L1-icache-load-misses [Hardware cache event] >> LLC-load-misses [Hardware cache event] >> LLC-loads [Hardware cache event] >> LLC-store-misses [Hardware cache event] >> LLC-stores [Hardware cache event] >> branch-load-misses [Hardware cache event] >> branch-loads [Hardware cache event] >> cpu_atom/L1-icache-loads/ [Hardware cache event] >> cpu_core/L1-dcache-load-misses/ [Hardware cache event] >> cpu_core/node-load-misses/ [Hardware cache event] >> cpu_core/node-loads/ [Hardware cache event] >> dTLB-load-misses [Hardware cache event] >> dTLB-loads [Hardware cache event] >> dTLB-store-misses [Hardware cache event] >> dTLB-stores [Hardware cache event] >> iTLB-load-misses [Hardware cache event] >> >> Fixes: 9b7c7728f4e4 ("perf parse-events: Break out tracepoint and printing") >> Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> >> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> > > Acked-by: Ian Rogers <irogers@google.com> > > Sorry for this breakage, I suspect that a long review on the > refactoring CL meant that I missed the intervening fix. Can we add a > test on this? It would need to be hybrid specific and skip otherwise. Thanks. I will add a test case for hybrid-specific later. > > Thanks, > Ian > >> --- >> tools/perf/util/print-events.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c >> index ba1ab5134685..04050d4f6db8 100644 >> --- a/tools/perf/util/print-events.c >> +++ b/tools/perf/util/print-events.c >> @@ -239,7 +239,7 @@ void print_sdt_events(const char *subsys_glob, const char *event_glob, >> strlist__delete(sdtlist); >> } >> >> -static bool is_event_supported(u8 type, unsigned int config) >> +static bool is_event_supported(u8 type, u64 config) >> { >> bool ret = true; >> int open_return; >> -- >> 2.25.1 >> -- Zhengjun Xing ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-09-22 8:04 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-09-22 1:49 [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some hybrid cache events zhengjun.xing 2022-09-22 1:49 ` [PATCH 2/2] perf parse-events: Remove "not supported" " zhengjun.xing 2022-09-22 3:16 ` Ian Rogers 2022-09-22 8:04 ` Xing Zhengjun 2022-09-22 3:12 ` [PATCH 1/2] perf print-events: Fix "perf list" can not display the PMU prefix for some " Ian Rogers 2022-09-22 6:44 ` Xing Zhengjun
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