* [meta-fsl-arm-extra][PATCH 1/3] Add kernel support for Wandboard Dual
@ 2013-02-23 20:29 John Weber
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 2/3] Add U-boot " John Weber
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: John Weber @ 2013-02-23 20:29 UTC (permalink / raw)
To: meta-freescale
This patch adds kernel support for Wandboard Dual. It is meant
to be over the 1.1.0 SDK kernel from Freescale.
Signed-off-by: John Weber <rjohnweber@gmail.com>
---
Upstream-Status: Pending
.../Initial-kernel-support-for-Wandboard.patch | 3195 ++++++++++++++++++++
.../linux-imx-3.0.35/wandboard-dual/defconfig | 2762 +++++++++++++++++
recipes-kernel/linux/linux-imx_3.0.35.bbappend | 8 +
3 files changed, 5965 insertions(+)
create mode 100644 recipes-kernel/linux/linux-imx-3.0.35/Initial-kernel-support-for-Wandboard.patch
create mode 100644 recipes-kernel/linux/linux-imx-3.0.35/wandboard-dual/defconfig
create mode 100644 recipes-kernel/linux/linux-imx_3.0.35.bbappend
diff --git a/recipes-kernel/linux/linux-imx-3.0.35/Initial-kernel-support-for-Wandboard.patch b/recipes-kernel/linux/linux-imx-3.0.35/Initial-kernel-support-for-Wandboard.patch
new file mode 100644
index 0000000..5dfbc96
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.0.35/Initial-kernel-support-for-Wandboard.patch
@@ -0,0 +1,3195 @@
+From f82dfc918b80905559bc1b97877a88bd85ede40f Mon Sep 17 00:00:00 2001
+From: John Weber <rjohnweber@gmail.com>
+Date: Fri, 22 Feb 2013 01:12:20 -0600
+Subject: [PATCH] Initial kernel support Wandboard
+
+ This patch adds support for Wandboard. It depends on
+ the FSL SDK 1.1.0 kernel (3.0.35). It has been minimally
+ tested on a Wandboard-Dual, rev A0. The serial port and
+ module SD card were found to work. Testers welcome!
+
+ Most of this was lifted and ported from the Wandboard SDK
+ released Feb 2, 2013. That original work was done by Tapani.
+
+
+diff --git a/arch/arm/configs/wandboard_defconfig b/arch/arm/configs/wandboard_defconfig
+new file mode 100644
+index 0000000..da75924
+--- /dev/null
++++ b/arch/arm/configs/wandboard_defconfig
+@@ -0,0 +1,1976 @@
++#
++# Automatically generated make config: don't edit
++# Linux/arm 3.0.35 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_SCHED_CLOCK=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++CONFIG_KTIME_SCALAR=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_LOCKBREAK=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_ARCH_HAS_CPUFREQ=y
++CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_FIQ=y
++CONFIG_VECTORS_BASE=0xffff0000
++# CONFIG_ARM_PATCH_PHYS_VIRT is not set
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_HAVE_IRQ_WORK=y
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_LZO=y
++# CONFIG_KERNEL_GZIP is not set
++CONFIG_KERNEL_LZMA=y
++# CONFIG_KERNEL_LZO is not set
++CONFIG_DEFAULT_HOSTNAME="wandboard"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_FHANDLE is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_GENERIC_HARDIRQS=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_HAVE_SPARSE_IRQ=y
++CONFIG_GENERIC_IRQ_SHOW=y
++# CONFIG_SPARSE_IRQ is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_PREEMPT_RCU=y
++CONFIG_PREEMPT_RCU=y
++# CONFIG_RCU_TRACE is not set
++CONFIG_RCU_FANOUT=32
++# CONFIG_RCU_FANOUT_EXACT is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_BOOST is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_CGROUPS is not set
++# CONFIG_NAMESPACES is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++# CONFIG_BUG is not set
++# CONFIG_ELF_CORE is not set
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++# CONFIG_SHMEM is not set
++# CONFIG_AIO is not set
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++# CONFIG_PERF_COUNTERS is not set
++# CONFIG_VM_EVENT_COUNTERS is not set
++# CONFIG_SLUB_DEBUG is not set
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_USE_GENERIC_SMP_HELPERS=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++
++#
++# GCOV-based kernel profiling
++#
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++CONFIG_MODVERSIONS=y
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_STOP_MACHINE=y
++CONFIG_BLOCK=y
++# CONFIG_LBDAF is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_DEADLINE is not set
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++# CONFIG_INLINE_SPIN_TRYLOCK is not set
++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
++# CONFIG_INLINE_SPIN_LOCK is not set
++# CONFIG_INLINE_SPIN_LOCK_BH is not set
++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
++# CONFIG_INLINE_SPIN_UNLOCK is not set
++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
++# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
++# CONFIG_INLINE_READ_TRYLOCK is not set
++# CONFIG_INLINE_READ_LOCK is not set
++# CONFIG_INLINE_READ_LOCK_BH is not set
++# CONFIG_INLINE_READ_LOCK_IRQ is not set
++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
++# CONFIG_INLINE_READ_UNLOCK is not set
++# CONFIG_INLINE_READ_UNLOCK_BH is not set
++# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
++# CONFIG_INLINE_WRITE_TRYLOCK is not set
++# CONFIG_INLINE_WRITE_LOCK is not set
++# CONFIG_INLINE_WRITE_LOCK_BH is not set
++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
++# CONFIG_INLINE_WRITE_UNLOCK is not set
++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
++# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCMRING is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CNS3XXX is not set
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++CONFIG_ARCH_MXC=y
++# CONFIG_ARCH_MXS is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_NUC93X is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_SHMOBILE is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_S5P64X0 is not set
++# CONFIG_ARCH_S5PC100 is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS4 is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_TCC_926 is not set
++# CONFIG_ARCH_U300 is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_NOMADIK is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_VT8500 is not set
++# CONFIG_GPIO_PCA953X is not set
++CONFIG_IMX_HAVE_PLATFORM_DMA=y
++CONFIG_IMX_HAVE_PLATFORM_FEC=y
++CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
++CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
++CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
++CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
++CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
++CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
++CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
++
++#
++# Freescale MXC Implementations
++#
++# CONFIG_ARCH_MX1 is not set
++# CONFIG_ARCH_MX2 is not set
++# CONFIG_ARCH_MX25 is not set
++# CONFIG_ARCH_MX3 is not set
++# CONFIG_ARCH_MX503 is not set
++# CONFIG_ARCH_MX51 is not set
++CONFIG_ARCH_MX6=y
++CONFIG_FORCE_MAX_ZONEORDER=14
++CONFIG_ARCH_MX6Q=y
++CONFIG_SOC_IMX6Q=y
++# CONFIG_MACH_MX6Q_ARM2 is not set
++# CONFIG_MACH_MX6SL_ARM2 is not set
++# CONFIG_MACH_MX6SL_EVK is not set
++# CONFIG_MACH_MX6Q_SABRELITE is not set
++# CONFIG_MACH_MX6Q_SABRESD is not set
++# CONFIG_MACH_MX6Q_SABREAUTO is not set
++CONFIG_MACH_WANDBOARD=y
++CONFIG_WANDBOARD_BASE=y
++
++#
++# MX6 Options:
++#
++# CONFIG_IMX_PCIE is not set
++CONFIG_USB_EHCI_ARC_H1=y
++CONFIG_USB_FSL_ARC_OTG=y
++# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS is not set
++# CONFIG_ISP1504_MXC is not set
++# CONFIG_MXC_IRQ_PRIOR is not set
++# CONFIG_MXC_PWM is not set
++# CONFIG_MXC_DEBUG_BOARD is not set
++# CONFIG_MXC_REBOOT_MFGMODE is not set
++# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
++CONFIG_ARCH_MXC_IOMUX_V3=y
++CONFIG_ARCH_MXC_AUDMUX_V2=y
++CONFIG_IRAM_ALLOC=y
++CONFIG_DMA_ZONE_SIZE=184
++
++#
++# System MMU
++#
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_SWP_EMULATE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_OUTER_CACHE=y
++CONFIG_OUTER_CACHE_SYNC=y
++CONFIG_CACHE_L2X0=y
++CONFIG_CACHE_PL310=y
++CONFIG_ARM_L1_CACHE_SHIFT=5
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_CPU_HAS_PMU=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_458693 is not set
++# CONFIG_ARM_ERRATA_460075 is not set
++# CONFIG_ARM_ERRATA_742230 is not set
++# CONFIG_ARM_ERRATA_742231 is not set
++# CONFIG_PL310_ERRATA_588369 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_PL310_ERRATA_727915 is not set
++CONFIG_ARM_ERRATA_743622=y
++# CONFIG_ARM_ERRATA_751472 is not set
++CONFIG_ARM_ERRATA_753970=y
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_754327 is not set
++CONFIG_ARM_GIC=y
++# CONFIG_FIQ_DEBUGGER is not set
++
++#
++# Bus support
++#
++CONFIG_ARM_AMBA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++# CONFIG_ARM_ERRATA_764369 is not set
++# CONFIG_PL310_ERRATA_769419 is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_HAVE_ARM_SCU=y
++CONFIG_HAVE_ARM_TWD=y
++# CONFIG_VMSPLIT_3G is not set
++CONFIG_VMSPLIT_2G=y
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0x80000000
++CONFIG_NR_CPUS=4
++CONFIG_HOTPLUG_CPU=y
++CONFIG_LOCAL_TIMERS=y
++# CONFIG_PREEMPT_NONE is not set
++# CONFIG_PREEMPT_VOLUNTARY is not set
++CONFIG_PREEMPT=y
++CONFIG_HZ=100
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++# CONFIG_HIGHPTE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_CLEANCACHE is not set
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++# CONFIG_CC_STACKPROTECTOR is not set
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set
++
++#
++# Boot options
++#
++# CONFIG_USE_OF is not set
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_CMDLINE_EXTEND is not set
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_TABLE=y
++CONFIG_CPU_FREQ_STAT=y
++# CONFIG_CPU_FREQ_STAT_DETAILS is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
++# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set
++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
++CONFIG_CPU_FREQ_IMX=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_CPU_IDLE_GOV_MENU=y
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++CONFIG_PM_RUNTIME=y
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_RUNTIME_CLK=y
++# CONFIG_SUSPEND_TIME is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_IP_MROUTE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++CONFIG_INET_LRO=y
++# CONFIG_INET_DIAG is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_ANDROID_PARANOID_NETWORK is not set
++# CONFIG_NET_ACTIVITY_STATS is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++CONFIG_BT=y
++CONFIG_BT_L2CAP=y
++CONFIG_BT_SCO=y
++CONFIG_BT_RFCOMM=y
++# CONFIG_BT_RFCOMM_TTY is not set
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++# CONFIG_BT_BNEP_PROTO_FILTER is not set
++
++#
++# Bluetooth device drivers
++#
++# CONFIG_BT_HCIBTUSB is not set
++# CONFIG_BT_HCIBTSDIO is not set
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_H4=y
++# CONFIG_BT_HCIUART_BCSP is not set
++# CONFIG_BT_HCIUART_ATH3K is not set
++# CONFIG_BT_HCIUART_LL is not set
++# CONFIG_BT_HCIBCM203X is not set
++# CONFIG_BT_HCIBPA10X is not set
++# CONFIG_BT_HCIBFUSB is not set
++# CONFIG_BT_HCIVHCI is not set
++# CONFIG_BT_MRVL is not set
++# CONFIG_AF_RXRPC is not set
++CONFIG_WIRELESS=y
++CONFIG_WEXT_CORE=y
++CONFIG_WEXT_PROC=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++# CONFIG_CFG80211_REG_DEBUG is not set
++# CONFIG_CFG80211_DEFAULT_PS is not set
++# CONFIG_CFG80211_INTERNAL_REGDB is not set
++CONFIG_CFG80211_WEXT=y
++# CONFIG_WIRELESS_EXT_SYSFS is not set
++# CONFIG_LIB80211 is not set
++# CONFIG_CFG80211_ALLOW_RECONNECT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++CONFIG_RFKILL_REGULATOR=y
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++# CONFIG_DEVTMPFS is not set
++# CONFIG_STANDALONE is not set
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_SYNC is not set
++# CONFIG_CONNECTOR is not set
++# CONFIG_MTD is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++
++#
++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
++#
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++# CONFIG_BLK_DEV_RAM is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_MISC_DEVICES is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_SCSI_PROC_FS is not set
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++# CONFIG_SCSI_WAIT_SCAN is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_MII is not set
++CONFIG_PHYLIB=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_FIXED_PHY is not set
++# CONFIG_MDIO_BITBANG is not set
++CONFIG_NET_ETHERNET=y
++# CONFIG_AX88796 is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++# CONFIG_ENC28J60 is not set
++# CONFIG_ETHOC is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SMSC911X is not set
++# CONFIG_DNET is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
++# CONFIG_B44 is not set
++# CONFIG_KS8842 is not set
++# CONFIG_KS8851 is not set
++# CONFIG_KS8851_MLL is not set
++CONFIG_FEC=y
++CONFIG_FEC_NAPI=y
++# CONFIG_FEC_1588 is not set
++# CONFIG_FTMAC100 is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++CONFIG_WLAN=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++# CONFIG_WIFI_CONTROL_FUNC is not set
++# CONFIG_ATH_COMMON is not set
++# CONFIG_BCM4329 is not set
++# CONFIG_BCMDHD is not set
++CONFIG_BRCMUTIL=m
++CONFIG_BRCMFMAC=m
++CONFIG_BRCMFMAC_SDIO=y
++# CONFIG_BRCMFMAC_SDIO_OOB is not set
++# CONFIG_BRCMFMAC_USB is not set
++# CONFIG_BRCMDBG is not set
++# CONFIG_HOSTAP is not set
++# CONFIG_IWM is not set
++# CONFIG_LIBERTAS is not set
++# CONFIG_MWIFIEX is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++# CONFIG_WAN is not set
++
++#
++# CAIF transport drivers
++#
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++# CONFIG_INPUT_KEYRESET is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++# CONFIG_SERIO_SERPORT is not set
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_LIBPS2 is not set
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++# CONFIG_CONSOLE_TRANSLATIONS is not set
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++# CONFIG_DEVMEM is not set
++# CONFIG_DEVKMEM is not set
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++# CONFIG_SERIAL_AMBA_PL011 is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX3107 is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_FSL_OTP is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_DCC_TTY is not set
++# CONFIG_RAMOOPS is not set
++# CONFIG_MXS_VIIM is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_MUX is not set
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_DESIGNWARE is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_IMX=y
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++CONFIG_SPI_BITBANG=y
++# CONFIG_SPI_GPIO is not set
++CONFIG_SPI_IMX_VER_2_3=y
++CONFIG_SPI_IMX=y
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_PL022 is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_DESIGNWARE is not set
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++
++#
++# Enable Device Drivers -> PPS to see the PTP clock options.
++#
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++CONFIG_GPIO_SYSFS=y
++
++#
++# Memory mapped GPIO drivers:
++#
++# CONFIG_GPIO_BASIC_MMIO is not set
++# CONFIG_GPIO_IT8761E is not set
++# CONFIG_GPIO_PL061 is not set
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_ADP5588 is not set
++
++#
++# PCI GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MCP23S08 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_74X164 is not set
++
++#
++# AC97 GPIO expanders:
++#
++
++#
++# MODULbus GPIO expanders:
++#
++# CONFIG_W1 is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_BQ20Z75 is not set
++# CONFIG_BATTERY_BQ27x00 is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_ISP1704 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_SABRESD_MAX8903 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++CONFIG_MFD_SUPPORT=y
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_UCB1400_CORE is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_MFD_STMPE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_PMIC_DIALOG is not set
++# CONFIG_MFD_MC_PMIC is not set
++# CONFIG_MFD_MC34708 is not set
++# CONFIG_MFD_PFUZE is not set
++# CONFIG_MFD_MC13XXX is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_MAX17135 is not set
++CONFIG_MFD_MXC_HDMI=y
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++CONFIG_REGULATOR_DUMMY=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_BQ24022 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_MC34708 is not set
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_AD5398 is not set
++CONFIG_REGULATOR_ANATOP=y
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2_COMMON=y
++# CONFIG_DVB_CORE is not set
++CONFIG_VIDEO_MEDIA=y
++
++#
++# Multimedia drivers
++#
++# CONFIG_RC_CORE is not set
++# CONFIG_MEDIA_ATTACH is not set
++CONFIG_MEDIA_TUNER=y
++# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
++CONFIG_MEDIA_TUNER_SIMPLE=y
++CONFIG_MEDIA_TUNER_TDA8290=y
++CONFIG_MEDIA_TUNER_TDA827X=y
++CONFIG_MEDIA_TUNER_TDA18271=y
++CONFIG_MEDIA_TUNER_TDA9887=y
++CONFIG_MEDIA_TUNER_TEA5761=y
++CONFIG_MEDIA_TUNER_TEA5767=y
++CONFIG_MEDIA_TUNER_MT20XX=y
++CONFIG_MEDIA_TUNER_XC2028=y
++CONFIG_MEDIA_TUNER_XC5000=y
++CONFIG_MEDIA_TUNER_MC44S803=y
++CONFIG_VIDEO_V4L2=y
++CONFIG_VIDEOBUF_GEN=y
++CONFIG_VIDEOBUF_DMA_CONTIG=y
++CONFIG_VIDEO_CAPTURE_DRIVERS=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
++
++#
++# Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7180 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_SAA7191 is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# MPEG video encoders
++#
++# CONFIG_VIDEO_CX2341X is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_AK881X is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_TCM825X is not set
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Miscelaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++# CONFIG_VIDEO_VIVI is not set
++# CONFIG_VIDEO_MXC_CAMERA is not set
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
++# CONFIG_VIDEO_MXC_OPL is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_VIDEO_TIMBERDALE is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++# CONFIG_VIDEO_NOON010PC30 is not set
++# CONFIG_SOC_CAMERA is not set
++# CONFIG_V4L_USB_DRIVERS is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_RADIO_ADAPTERS is not set
++
++#
++# Graphics support
++#
++# CONFIG_DRM is not set
++# CONFIG_ION is not set
++# CONFIG_VGASTATE is not set
++CONFIG_VIDEO_OUTPUT_CONTROL=y
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_WMT_GE_ROPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_ARMCLCD is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++CONFIG_DISPLAY_SUPPORT=y
++
++#
++# Display hardware drivers
++#
++CONFIG_FB_MXC=y
++CONFIG_FB_MXC_EDID=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
++CONFIG_FB_MXC_LDB=y
++# CONFIG_FB_MXC_MIPI_DSI is not set
++# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
++# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
++# CONFIG_FB_MXC_SII902X is not set
++# CONFIG_FB_MXC_CH7026 is not set
++# CONFIG_FB_MXC_TVOUT_CH7024 is not set
++# CONFIG_FB_MXC_ASYNC_PANEL is not set
++# CONFIG_FB_MXC_EINK_PANEL is not set
++# CONFIG_FB_MXC_SIPIX_PANEL is not set
++# CONFIG_FB_MXC_ELCDIF_FB is not set
++CONFIG_FB_MXC_HDMI=y
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_LOGO_LINUX_CLUT224=y
++CONFIG_SOUND=y
++# CONFIG_SOUND_OSS_CORE is not set
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_JACK=y
++# CONFIG_SND_SEQUENCER is not set
++# CONFIG_SND_MIXER_OSS is not set
++# CONFIG_SND_PCM_OSS is not set
++# CONFIG_SND_HRTIMER is not set
++# CONFIG_SND_DYNAMIC_MINORS is not set
++# CONFIG_SND_SUPPORT_OLD_API is not set
++# CONFIG_SND_VERBOSE_PROCFS is not set
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++# CONFIG_SND_RAWMIDI_SEQ is not set
++# CONFIG_SND_OPL3_LIB_SEQ is not set
++# CONFIG_SND_OPL4_LIB_SEQ is not set
++# CONFIG_SND_SBAWE_SEQ is not set
++# CONFIG_SND_EMU10K1_SEQ is not set
++# CONFIG_SND_DRIVERS is not set
++# CONFIG_SND_ARM is not set
++# CONFIG_SND_SPI is not set
++# CONFIG_SND_USB is not set
++CONFIG_SND_SOC=y
++# CONFIG_SND_SOC_CACHE_LZO is not set
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_MXC_SOC_MX2=y
++CONFIG_SND_MXC_SOC_SPDIF_DAI=y
++CONFIG_SND_SOC_IMX_SGTL5000=y
++# CONFIG_SND_SOC_IMX_WM8962 is not set
++# CONFIG_SND_SOC_IMX_SI4763 is not set
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_SND_SOC_I2C_AND_SPI=y
++# CONFIG_SND_SOC_ALL_CODECS is not set
++CONFIG_SND_SOC_MXC_HDMI=y
++CONFIG_SND_SOC_MXC_SPDIF=y
++CONFIG_SND_SOC_SGTL5000=y
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++# CONFIG_HID_SUPPORT is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++# CONFIG_USB_ARCH_HAS_OHCI is not set
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_DEVICE_CLASS is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_ARC=y
++CONFIG_USB_EHCI_ARC_OTG=y
++# CONFIG_USB_EHCI_ARC_HSIC is not set
++# CONFIG_USB_STATIC_IRAM is not set
++CONFIG_USB_EHCI_ROOT_HUB_TT=y
++CONFIG_USB_EHCI_TT_NEWSCHED=y
++# CONFIG_USB_EHCI_MXC is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1760_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HWA_HCD is not set
++# CONFIG_USB_MUSB_HDRC is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_SISUSBVGA is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++CONFIG_USB_GADGET_VBUS_DRAW=100
++CONFIG_USB_GADGET_SELECTED=y
++CONFIG_USB_GADGET_ARC=y
++# CONFIG_IMX_USB_CHARGER is not set
++CONFIG_USB_ARC=y
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_FUSB300 is not set
++# CONFIG_USB_GADGET_R8A66597 is not set
++# CONFIG_USB_GADGET_PXA_U2O is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_AUDIO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++CONFIG_USB_MASS_STORAGE=y
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_G_ANDROID is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++CONFIG_USB_GPIO_VBUS=y
++CONFIG_USB_ULPI=y
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_MXC_OTG is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_CLKGATE=y
++# CONFIG_MMC_EMBEDDED_SDIO is not set
++# CONFIG_MMC_PARANOID_SD_INIT is not set
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_ARMMMCI is not set
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_IO_ACCESSORS=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_NFC_DEVICES is not set
++CONFIG_SWITCH=y
++# CONFIG_SWITCH_GPIO is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_RTC_LIB=y
++# CONFIG_RTC_CLASS is not set
++CONFIG_DMADEVICES=y
++# CONFIG_DMADEVICES_DEBUG is not set
++
++#
++# DMA Devices
++#
++# CONFIG_AMBA_PL08X is not set
++# CONFIG_DW_DMAC is not set
++# CONFIG_MXC_PXP_V2 is not set
++# CONFIG_TIMB_DMA is not set
++CONFIG_IMX_SDMA=y
++# CONFIG_MXS_DMA is not set
++CONFIG_DMA_ENGINE=y
++
++#
++# DMA Clients
++#
++# CONFIG_NET_DMA is not set
++# CONFIG_ASYNC_TX_DMA is not set
++# CONFIG_DMATEST is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++CONFIG_STAGING=y
++# CONFIG_USBIP_CORE is not set
++# CONFIG_PRISM2_USB is not set
++# CONFIG_ECHO is not set
++# CONFIG_ASUS_OLED is not set
++# CONFIG_R8712U is not set
++# CONFIG_TRANZPORT is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# CONFIG_POHMELFS is not set
++# CONFIG_LINE6_USB is not set
++# CONFIG_VT6656 is not set
++# CONFIG_IIO is not set
++# CONFIG_XVMALLOC is not set
++# CONFIG_ZRAM is not set
++# CONFIG_FB_SM7XX is not set
++# CONFIG_EASYCAP is not set
++CONFIG_MACH_NO_WESTBRIDGE=y
++# CONFIG_ATH6K_LEGACY is not set
++# CONFIG_USB_ENESTORAGE is not set
++# CONFIG_BCM_WIMAX is not set
++# CONFIG_FT1000 is not set
++
++#
++# Speakup console speech
++#
++# CONFIG_SPEAKUP is not set
++# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_CLKSRC_MMIO=y
++
++#
++# MXC support drivers
++#
++CONFIG_MXC_IPU=y
++CONFIG_MXC_IPU_V3=y
++CONFIG_MXC_IPU_V3H=y
++
++#
++# MXC SSI support
++#
++CONFIG_MXC_SSI=y
++
++#
++# MXC Digital Audio Multiplexer support
++#
++# CONFIG_MXC_DAM is not set
++
++#
++# MXC PMIC support
++#
++# CONFIG_MXC_PMIC_MC13783 is not set
++# CONFIG_MXC_PMIC_MC13892 is not set
++# CONFIG_MXC_PMIC_MC34704 is not set
++# CONFIG_MXC_PMIC_MC9SDZ60 is not set
++# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
++
++#
++# MXC Security Drivers
++#
++# CONFIG_MXC_SECURITY_SCC is not set
++# CONFIG_MXC_SECURITY_RNG is not set
++
++#
++# MXC MPEG4 Encoder Kernel module support
++#
++# CONFIG_MXC_HMP4E is not set
++
++#
++# MXC HARDWARE EVENT
++#
++# CONFIG_MXC_HWEVENT is not set
++
++#
++# MXC VPU(Video Processing Unit) support
++#
++CONFIG_MXC_VPU=y
++# CONFIG_MXC_VPU_DEBUG is not set
++# CONFIG_MX6_VPU_352M is not set
++
++#
++# MXC Asynchronous Sample Rate Converter support
++#
++CONFIG_MXC_ASRC=y
++
++#
++# MXC Bluetooth support
++#
++
++#
++# Broadcom GPS ioctrl support
++#
++
++#
++# MXC Media Local Bus Driver
++#
++# CONFIG_MXC_MLB150 is not set
++
++#
++# i.MX ADC support
++#
++# CONFIG_IMX_ADC is not set
++
++#
++# MXC Vivante GPU support
++#
++CONFIG_MXC_GPU_VIV=y
++
++#
++# ANATOP_THERMAL
++#
++CONFIG_ANATOP_THERMAL=y
++
++#
++# MXC MIPI Support
++#
++# CONFIG_MXC_MIPI_CSI2 is not set
++
++#
++# MXC HDMI CEC (Consumer Electronics Control) support
++#
++# CONFIG_MXC_HDMI_CEC is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
++# CONFIG_EXT3_FS_XATTR is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_JBD=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_FSNOTIFY=y
++# CONFIG_DNOTIFY is not set
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++# CONFIG_MSDOS_FS is not set
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++# CONFIG_PROC_PAGE_MONITOR is not set
++CONFIG_SYSFS=y
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++# CONFIG_MISC_FILESYSTEMS is not set
++# CONFIG_NETWORK_FILESYSTEMS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++
++#
++# Kernel hacking
++#
++CONFIG_PRINTK_TIME=y
++CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=4096
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_STRIP_ASM_SYMS=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++# CONFIG_DEBUG_KERNEL is not set
++# CONFIG_HARDLOCKUP_DETECTOR is not set
++# CONFIG_SLUB_STATS is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_MEMORY_INIT is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++CONFIG_RCU_CPU_STALL_VERBOSE=y
++CONFIG_SYSCTL_SYSCALL_CHECK=y
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_ARM_UNWIND is not set
++# CONFIG_DEBUG_USER is not set
++CONFIG_OC_ETM=y
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_PCOMP2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++# CONFIG_CRYPTO_CRYPTODEV is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++# CONFIG_CRYPTO_CRC32C is not set
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_ZLIB is not set
++# CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_HW is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_RATIONAL=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_NLATTR=y
++# CONFIG_AVERAGE is not set
+diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
+index 2ffd90d..e49c56f 100644
+--- a/arch/arm/mach-mx6/Kconfig
++++ b/arch/arm/mach-mx6/Kconfig
+@@ -251,6 +251,47 @@ config MACH_MX6Q_SABREAUTO
+ Include support for i.MX 6Quad SABRE Auto platform. This includes specific
+ configurations for the board and its peripherals.
+
++config MACH_WANDBOARD
++ bool "Support for the WandBoard"
++ select ARCH_MX6Q
++ select SOC_IMX6Q
++ select IMX_HAVE_PLATFORM_DMA if IMX_SDMA
++ select IMX_HAVE_PLATFORM_IMX_UART if SERIAL_IMX
++ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX if MMC_SDHCI_ESDHC_IMX
++ select IMX_HAVE_PLATFORM_IMX_I2C if I2C_IMX
++ select IMX_HAVE_PLATFORM_IMX_ASRC if SND_IMX_SOC
++ select ARCH_MXC_AUDMUX_V2 if SND_IMX_SOC
++ select IMX_HAVE_PLATFORM_IMX_SSI if MXC_SSI
++ select IMX_HAVE_PLATFORM_IMX_ESAI if MXC_SSI
++ select IMX_HAVE_PLATFORM_IMX_SPDIF if SND_SOC_IMX_SPDIF
++ select IMX_HAVE_PLATFORM_FEC if NETDEVICES
++ select IMX_HAVE_PLATFORM_FSL_USB2_UDC if USB
++ select IMX_HAVE_PLATFORM_MXC_EHCI if USB
++ select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP if USB
++ select IMX_HAVE_PLATFORM_FSL_OTG if USB_OTG
++ select IMX_HAVE_PLATFORM_MXC_HDMI if FB_MXC_HDMI
++ select IMX_HAVE_PLATFORM_IMX_IPUV3 if MXC_IPU_V3
++ select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL if ANATOP_THERMAL
++ select IMX_HAVE_PLATFORM_IMX_PM if PM
++ select IMX_HAVE_PLATFORM_IMX_DVFS if CPU_FREQ_IMX
++ select IMX_HAVE_PLATFORM_SPI_IMX if SPI
++ select IMX_HAVE_PLATFORM_VIV_GPU if MXC_GPU_VIV
++ select IMX_HAVE_PLATFORM_IMX_VPU if MXC_VPU
++ select IMX_HAVE_PLATFORM_IMX_MIPI_DSI if VIDEO_MXC_IPU_OUTPUT
++ help
++ Include support for the WandBoard SoM.
++
++
++config WANDBOARD_BASE
++ tristate "Support for Wand baseboard"
++ depends on MACH_WANDBOARD
++ default y
++ help
++ Include support for the devices on the default wand baseboard.
++
++ If you have a standard Wandboard, say Y.
++
++
+ comment "MX6 Options:"
+
+ config IMX_PCIE
+diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile
+index 5cac9bc..3f43098 100644
+--- a/arch/arm/mach-mx6/Makefile
++++ b/arch/arm/mach-mx6/Makefile
+@@ -14,6 +14,8 @@ obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o
+ obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o
+ obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o
+ obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o
++obj-$(CONFIG_MACH_WANDBOARD) += board-wand.o
++obj-$(CONFIG_WANDBOARD_BASE) += baseboard-wand.o
+ obj-$(CONFIG_SMP) += plat_hotplug.o platsmp.o headsmp.o
+ obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+ obj-$(CONFIG_IMX_PCIE) += pcie.o
+diff --git a/arch/arm/mach-mx6/baseboard-wand.c b/arch/arm/mach-mx6/baseboard-wand.c
+new file mode 100644
+index 0000000..e9e9378
+--- /dev/null
++++ b/arch/arm/mach-mx6/baseboard-wand.c
+@@ -0,0 +1,137 @@
++
++#include <asm/mach/arch.h>
++
++#include <linux/clk.h>
++#include <linux/i2c.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/fixed.h>
++#include <linux/regulator/machine.h>
++
++#include <mach/common.h>
++#include <mach/devices-common.h>
++
++
++/****************************************************************************
++ *
++ * SGTL5000 Audio Codec
++ *
++ ****************************************************************************/
++
++static struct regulator_consumer_supply wandbase_sgtl5000_consumer_vdda = {
++ .supply = "VDDA",
++ .dev_name = "0-000a", /* Modified load time */
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct regulator_consumer_supply wandbase_sgtl5000_consumer_vddio = {
++ .supply = "VDDIO",
++ .dev_name = "0-000a", /* Modified load time */
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct regulator_init_data wandbase_sgtl5000_vdda_reg_initdata = {
++ .num_consumer_supplies = 1,
++ .consumer_supplies = &wandbase_sgtl5000_consumer_vdda,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct regulator_init_data wandbase_sgtl5000_vddio_reg_initdata = {
++ .num_consumer_supplies = 1,
++ .consumer_supplies = &wandbase_sgtl5000_consumer_vddio,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct fixed_voltage_config wandbase_sgtl5000_vdda_reg_config = {
++ .supply_name = "VDDA",
++ .microvolts = 2500000,
++ .gpio = -1,
++ .init_data = &wandbase_sgtl5000_vdda_reg_initdata,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct fixed_voltage_config wandbase_sgtl5000_vddio_reg_config = {
++ .supply_name = "VDDIO",
++ .microvolts = 3300000,
++ .gpio = -1,
++ .init_data = &wandbase_sgtl5000_vddio_reg_initdata,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct platform_device wandbase_sgtl5000_vdda_reg_devices = {
++ .name = "reg-fixed-voltage",
++ .id = 0,
++ .dev = {
++ .platform_data = &wandbase_sgtl5000_vdda_reg_config,
++ },
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct platform_device wandbase_sgtl5000_vddio_reg_devices = {
++ .name = "reg-fixed-voltage",
++ .id = 1,
++ .dev = {
++ .platform_data = &wandbase_sgtl5000_vddio_reg_config,
++ },
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct platform_device wandbase_audio_device = {
++ .name = "imx-sgtl5000",
++};
++
++/* ------------------------------------------------------------------------ */
++
++static const struct i2c_board_info wandbase_sgtl5000_i2c_data __initdata = {
++ I2C_BOARD_INFO("sgtl5000", 0x0a)
++};
++
++/* ------------------------------------------------------------------------ */
++
++static char wandbase_sgtl5000_dev_name[8] = "0-000a";
++
++extern struct mxc_audio_platform_data wand_audio_channel_data;
++
++static __init int wandbase_init_sgtl5000(void) {
++ int i2c_bus = 1; /* TODO: get this from the module. */
++
++ wandbase_sgtl5000_dev_name[0] = '0' + i2c_bus;
++ wandbase_sgtl5000_consumer_vdda.dev_name = wandbase_sgtl5000_dev_name;
++ wandbase_sgtl5000_consumer_vddio.dev_name = wandbase_sgtl5000_dev_name;
++
++ wandbase_audio_device.dev.platform_data = &wand_audio_channel_data;
++ platform_device_register(&wandbase_audio_device);
++
++ i2c_register_board_info(i2c_bus, &wandbase_sgtl5000_i2c_data, 1);
++ platform_device_register(&wandbase_sgtl5000_vdda_reg_devices);
++ platform_device_register(&wandbase_sgtl5000_vddio_reg_devices);
++ return 0;
++}
++
++
++/****************************************************************************
++ *
++ * main-function for wand baseboard
++ *
++ ****************************************************************************/
++
++static __init int wandbase_init(void) {
++ return wandbase_init_sgtl5000();
++}
++subsys_initcall(wandbase_init);
++
++static __exit void wandbase_exit(void) {
++ /* Actually, this cannot be unloaded. Or loaded as a module..? */
++}
++module_exit(wandbase_exit);
++
++MODULE_DESCRIPTION("Wand baseboard driver");
++MODULE_AUTHOR("Tapani <tapani@vmail.me>");
++MODULE_LICENSE("GPL");
+diff --git a/arch/arm/mach-mx6/board-wand.c b/arch/arm/mach-mx6/board-wand.c
+new file mode 100644
+index 0000000..7f972eb
+--- /dev/null
++++ b/arch/arm/mach-mx6/board-wand.c
+@@ -0,0 +1,972 @@
++
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/time.h>
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/fec.h>
++#include <linux/i2c.h>
++#include <linux/kernel.h>
++#include <linux/memblock.h>
++#include <linux/phy.h>
++
++#include <mach/common.h>
++//#include <mach/devices-common.h>
++#include <mach/gpio.h>
++#include <mach/iomux-mx6dl.h>
++#include <mach/iomux-v3.h>
++#include <mach/mx6.h>
++
++#include "crm_regs.h"
++#include "devices-imx6q.h"
++#include "usb.h"
++//#include "cpu_op-mx6.h"
++
++#define WAND_BT_ON IMX_GPIO_NR(3, 13)
++#define WAND_BT_WAKE IMX_GPIO_NR(3, 14)
++#define WAND_BT_HOST_WAKE IMX_GPIO_NR(3, 15)
++
++#define WAND_RGMII_INT IMX_GPIO_NR(1, 28)
++#define WAND_RGMII_RST IMX_GPIO_NR(3, 29)
++
++#define WAND_SD1_CD IMX_GPIO_NR(1, 2)
++#define WAND_SD3_CD IMX_GPIO_NR(3, 9)
++#define WAND_SD3_WP IMX_GPIO_NR(1, 10)
++
++#define WAND_USB_OTG_OC IMX_GPIO_NR(1, 9)
++#define WAND_USB_OTG_PWR IMX_GPIO_NR(3, 22)
++#define WAND_USB_H1_OC IMX_GPIO_NR(3, 30)
++
++#define WAND_WL_REF_ON IMX_GPIO_NR(2, 29)
++#define WAND_WL_RST_N IMX_GPIO_NR(5, 2)
++#define WAND_WL_REG_ON IMX_GPIO_NR(1, 26)
++#define WAND_WL_HOST_WAKE IMX_GPIO_NR(1, 29)
++#define WAND_WL_WAKE IMX_GPIO_NR(1, 30)
++
++/* Syntactic sugar for pad configuration */
++#define WAND_SETUP_PADS(p) \
++ mxc_iomux_v3_setup_multiple_pads((p), ARRAY_SIZE(p))
++
++/* See arch/arm/plat-mxc/include/mach/iomux-mx6dl.h for definitions */
++
++/****************************************************************************
++ *
++ * DMA controller init
++ *
++ ****************************************************************************/
++
++static __init void wand_init_dma(void) {
++ imx6q_add_dma();
++}
++
++
++/****************************************************************************
++ *
++ * SD init
++ *
++ * SD1 is routed to EDM connector (external SD on wand baseboard)
++ * SD2 is WiFi
++ * SD3 is boot SD on the module
++ *
++ ****************************************************************************/
++
++/* For some reason, iomux_mx6dl.h does not define multiple speeds for
++ SD1 and SD2, so these don't have any speed switching. */
++static iomux_v3_cfg_t mx6dl_sd1_pads[] = {
++ MX6DL_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM,
++ MX6DL_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM,
++ MX6DL_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM,
++ MX6DL_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM,
++ MX6DL_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM,
++ MX6DL_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM,
++};
++
++static iomux_v3_cfg_t mx6dl_sd2_pads[] = {
++ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
++ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
++ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
++ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
++ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
++ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
++};
++
++
++#define MX6DL_USDHC_PAD_SETTING(id, speed) \
++mx6dl_sd##id##_##speed##mhz[] = { \
++ MX6DL_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ, \
++ MX6DL_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ, \
++ MX6DL_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ, \
++ MX6DL_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ, \
++ MX6DL_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ, \
++ MX6DL_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ, \
++}
++
++/* 50,100, and 200 MHz are supported for SD3 in iomux_mx6dl.h */
++static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(3, 50);
++static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(3, 100);
++static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(3, 200);
++
++enum sd_pad_mode {
++ SD_PAD_MODE_LOW_SPEED,
++ SD_PAD_MODE_MED_SPEED,
++ SD_PAD_MODE_HIGH_SPEED,
++};
++
++static int plt_sd_pad_change(unsigned int index, int clock)
++{
++ /* LOW speed is the default state of SD pads */
++ static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
++
++ iomux_v3_cfg_t *sd_pads_200mhz = NULL;
++ iomux_v3_cfg_t *sd_pads_100mhz = NULL;
++ iomux_v3_cfg_t *sd_pads_50mhz = NULL;
++
++ u32 sd_pads_200mhz_cnt;
++ u32 sd_pads_100mhz_cnt;
++ u32 sd_pads_50mhz_cnt;
++
++ switch (index) {
++ case 0:
++ sd_pads_50mhz = mx6dl_sd1_pads;
++ sd_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd1_pads);
++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_50mhz, sd_pads_50mhz_cnt);
++ break;
++ case 1:
++ sd_pads_50mhz = mx6dl_sd2_pads;
++ sd_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd2_pads);
++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_50mhz, sd_pads_50mhz_cnt);
++ break;
++ case 2:
++ sd_pads_200mhz = mx6dl_sd3_200mhz;
++ sd_pads_100mhz = mx6dl_sd3_100mhz;
++ sd_pads_50mhz = mx6dl_sd3_50mhz;
++
++ sd_pads_200mhz_cnt = ARRAY_SIZE(mx6dl_sd3_200mhz);
++ sd_pads_100mhz_cnt = ARRAY_SIZE(mx6dl_sd3_100mhz);
++ sd_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd3_50mhz);
++ break;
++ default:
++ printk(KERN_ERR "no such SD host controller index %d\n", index);
++ return -EINVAL;
++ }
++
++ if (clock > 100000000) {
++ if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
++ return 0;
++ BUG_ON(!sd_pads_200mhz);
++ pad_mode = SD_PAD_MODE_HIGH_SPEED;
++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_200mhz,
++ sd_pads_200mhz_cnt);
++ } else if (clock > 52000000) {
++ if (pad_mode == SD_PAD_MODE_MED_SPEED)
++ return 0;
++ BUG_ON(!sd_pads_100mhz);
++ pad_mode = SD_PAD_MODE_MED_SPEED;
++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_100mhz,
++ sd_pads_100mhz_cnt);
++ } else {
++ if (pad_mode == SD_PAD_MODE_LOW_SPEED)
++ return 0;
++ BUG_ON(!sd_pads_50mhz);
++ pad_mode = SD_PAD_MODE_LOW_SPEED;
++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_50mhz,
++ sd_pads_50mhz_cnt);
++ }
++}
++
++
++/* ------------------------------------------------------------------------ */
++
++static const struct esdhc_platform_data wand_sd_data[3] = {
++ {
++ .cd_gpio = WAND_SD1_CD,
++ .wp_gpio =-EINVAL,
++ .keep_power_at_suspend = 1,
++ .support_8bit = 0,
++ .platform_pad_change = plt_sd_pad_change,
++ }, {
++ .cd_gpio =-EINVAL,
++ .wp_gpio =-EINVAL,
++ .keep_power_at_suspend = 1,
++ .platform_pad_change = plt_sd_pad_change,
++ }, {
++ .cd_gpio = WAND_SD3_CD,
++ .wp_gpio = WAND_SD3_WP,
++ .keep_power_at_suspend = 1,
++ .support_8bit = 0,
++ .delay_line = 0,
++ .platform_pad_change = plt_sd_pad_change,
++ }
++};
++
++/* ------------------------------------------------------------------------ */
++
++static void wand_init_sd(void) {
++ //int i;
++ /* Card Detect for SD1 & SD3, respectively */
++ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_2__GPIO_1_2);
++ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA9__GPIO_3_9);
++
++ /* Add mmc devices in reverse order, so mmc0 always is boot sd (SD3) */
++/* for (i=2; i>=0; i--) {
++ WAND_SETUP_PADS(wand_sd_pads[i][0]);
++ imx6q_add_sdhci_usdhc_imx(i, &wand_sd_data[i]);
++ } */
++
++ /* SD3 is first, speed is set to lowest to start */
++ WAND_SETUP_PADS(mx6dl_sd3_50mhz);
++ imx6q_add_sdhci_usdhc_imx(2, &wand_sd_data[2]);
++
++ WAND_SETUP_PADS(mx6dl_sd2_pads);
++ imx6q_add_sdhci_usdhc_imx(1, &wand_sd_data[1]);
++
++ WAND_SETUP_PADS(mx6dl_sd1_pads);
++ imx6q_add_sdhci_usdhc_imx(0, &wand_sd_data[0]);
++}
++
++
++/****************************************************************************
++ *
++ * I2C
++ *
++ ****************************************************************************/
++
++static iomux_v3_cfg_t wand_i2c_pads[3][2] __initdata = {
++ {
++ MX6DL_PAD_EIM_D21__I2C1_SCL,
++ MX6DL_PAD_EIM_D28__I2C1_SDA,
++ }, {
++ MX6DL_PAD_KEY_COL3__I2C2_SCL,
++ MX6DL_PAD_KEY_ROW3__I2C2_SDA,
++ }, {
++ MX6DL_PAD_GPIO_5__I2C3_SCL,
++ MX6DL_PAD_GPIO_16__I2C3_SDA
++ }
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct imxi2c_platform_data wand_i2c_data[] = {
++ { .bitrate = 100000, },
++ { .bitrate = 400000, },
++ { .bitrate = 400000, },
++};
++
++/* ------------------------------------------------------------------------ */
++
++static void __init wand_init_i2c(void) {
++ int i;
++ for (i=0; i<3; i++) {
++ WAND_SETUP_PADS(wand_i2c_pads[i]);
++ imx6q_add_imx_i2c(i, &wand_i2c_data[i]);
++ }
++}
++
++
++/****************************************************************************
++ *
++ * Initialize debug console (UART1)
++ *
++ ****************************************************************************/
++
++static __initdata iomux_v3_cfg_t wand_uart_pads[] = {
++ /* UART1 (debug console) */
++ MX6DL_PAD_CSI0_DAT10__UART1_TXD,
++ MX6DL_PAD_CSI0_DAT11__UART1_RXD,
++ MX6DL_PAD_EIM_D19__UART1_CTS,
++ MX6DL_PAD_EIM_D20__UART1_RTS,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static __init void wand_init_uart(void) {
++ WAND_SETUP_PADS(wand_uart_pads);
++
++ imx6q_add_imx_uart(0, NULL);
++}
++
++
++/****************************************************************************
++ *
++ * Initialize sound (SSI, ASRC, AUD3 channel and S/PDIF)
++ *
++ ****************************************************************************/
++
++static iomux_v3_cfg_t wand_audio_pads[] = {
++ MX6DL_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC,
++ MX6DL_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD,
++ MX6DL_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS,
++ MX6DL_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD,
++ MX6DL_PAD_GPIO_0__CCM_CLKO,
++};
++
++/* ------------------------------------------------------------------------ */
++
++extern struct mxc_audio_platform_data wand_audio_channel_data;
++
++/* This function is called as a callback from the audio channel data struct */
++static int wand_audio_clock_enable(void) {
++ struct clk *clko;
++ struct clk *new_parent;
++ int rate;
++
++ clko = clk_get(NULL, "clko_clk");
++ if (IS_ERR(clko)) return PTR_ERR(clko);
++
++ new_parent = clk_get(NULL, "ahb");
++ if (!IS_ERR(new_parent)) {
++ clk_set_parent(clko, new_parent);
++ clk_put(new_parent);
++ }
++
++ rate = clk_round_rate(clko, 16000000);
++ if (rate < 8000000 || rate > 27000000) {
++ pr_err("SGTL5000: mclk freq %d out of range!\n", rate);
++ clk_put(clko);
++ return -1;
++ }
++
++ wand_audio_channel_data.sysclk = rate;
++ clk_set_rate(clko, rate);
++ clk_enable(clko);
++
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ */
++
++/* This struct is added by the baseboard when initializing the codec */
++struct mxc_audio_platform_data wand_audio_channel_data = {
++ .ssi_num = 1,
++ .src_port = 2,
++ .ext_port = 3, /* audio channel: 3=AUD3. TODO: EDM */
++ .init = wand_audio_clock_enable,
++ .hp_gpio = -1,
++};
++EXPORT_SYMBOL_GPL(wand_audio_channel_data); /* TODO: edm naming? */
++
++/* ------------------------------------------------------------------------ */
++
++static int wand_set_spdif_clk_rate(struct clk *clk, unsigned long rate) {
++ unsigned long rate_actual;
++ rate_actual = clk_round_rate(clk, rate);
++ clk_set_rate(clk, rate_actual);
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ */
++
++static struct mxc_spdif_platform_data wand_spdif = {
++ .spdif_tx = 1, /* enable tx */
++ .spdif_rx = 1, /* enable rx */
++ .spdif_clk_44100 = 1, /* tx clk from spdif0_clk_root */
++ .spdif_clk_48000 = 1, /* tx clk from spdif0_clk_root */
++ .spdif_div_44100 = 23,
++ .spdif_div_48000 = 37,
++ .spdif_div_32000 = 37,
++ .spdif_rx_clk = 0, /* rx clk from spdif stream */
++ .spdif_clk_set_rate = wand_set_spdif_clk_rate,
++ .spdif_clk = NULL, /* spdif bus clk */
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct imx_ssi_platform_data wand_ssi_pdata = {
++ .flags = IMX_SSI_DMA | IMX_SSI_SYN,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct imx_asrc_platform_data wand_asrc_data = {
++ .channel_bits = 4,
++ .clk_map_ver = 2,
++};
++
++/* ------------------------------------------------------------------------ */
++
++void __init wand_init_audio(void) {
++ WAND_SETUP_PADS(wand_audio_pads);
++
++ /* Sample rate converter is added together with audio */
++ wand_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
++ wand_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
++ imx6q_add_asrc(&wand_asrc_data);
++
++ imx6q_add_imx_ssi(1, &wand_ssi_pdata);
++ /* Enable SPDIF */
++
++ mxc_iomux_v3_setup_pad(MX6DL_PAD_ENET_RXD0__SPDIF_OUT1);
++
++ wand_spdif.spdif_core_clk = clk_get_sys("mxc_spdif.0", NULL);
++ clk_put(wand_spdif.spdif_core_clk);
++ imx6q_add_spdif(&wand_spdif);
++ imx6q_add_spdif_dai();
++ imx6q_add_spdif_audio_device();
++}
++
++
++/*****************************************************************************
++ *
++ * Init FEC and AR8031 PHY
++ *
++ *****************************************************************************/
++
++static iomux_v3_cfg_t wand_fec_pads[] = {
++ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
++ MX6DL_PAD_ENET_MDC__ENET_MDC,
++ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
++ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
++ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
++ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
++ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
++ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
++ MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
++ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
++ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
++ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
++ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
++ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
++ MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
++ MX6DL_PAD_ENET_TX_EN__GPIO_1_28,
++ MX6DL_PAD_EIM_D29__GPIO_3_29,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static int wand_fec_phy_init(struct phy_device *phydev) {
++ unsigned short val;
++
++ /* Enable AR8031 125MHz clk */
++ phy_write(phydev, 0x0d, 0x0007); /* Set device address to 7*/
++ phy_write(phydev, 0x00, 0x8000); /* Apply by soft reset */
++ udelay(500);
++
++ phy_write(phydev, 0x0e, 0x8016); /* set mmd reg */
++ phy_write(phydev, 0x0d, 0x4007); /* apply */
++
++ val = phy_read(phydev, 0xe);
++ val &= 0xffe3;
++ val |= 0x18;
++ phy_write(phydev, 0xe, val);
++ phy_write(phydev, 0x0d, 0x4007); /* Post data */
++
++ /* Introduce random tx clock delay. Why is this needed? */
++ phy_write(phydev, 0x1d, 0x5);
++ val = phy_read(phydev, 0x1e);
++ val |= 0x0100;
++ phy_write(phydev, 0x1e, val);
++
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ */
++
++static int wand_fec_power_hibernate(struct phy_device *phydev) { return 0; }
++
++/* ------------------------------------------------------------------------ */
++
++static struct fec_platform_data wand_fec_data __initdata = {
++ .init = wand_fec_phy_init,
++ .power_hibernate = wand_fec_power_hibernate,
++ .phy = PHY_INTERFACE_MODE_RGMII,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static __init void wand_init_ethernet(void) {
++ WAND_SETUP_PADS(wand_fec_pads);
++
++ gpio_request(WAND_RGMII_RST, "rgmii reset");
++ gpio_direction_output(WAND_RGMII_RST, 0);
++#ifdef CONFIG_FEC_1588
++ mxc_iomux_set_gpr_register(1, 21, 1, 1);
++#endif
++ msleep(10);
++ gpio_set_value(WAND_RGMII_RST, 1);
++ imx6_init_fec(wand_fec_data);
++}
++
++
++/****************************************************************************
++ *
++ * USB
++ *
++ ****************************************************************************/
++
++static __initdata iomux_v3_cfg_t wand_usb_pads[] = {
++ MX6DL_PAD_GPIO_9__GPIO_1_9,
++ MX6DL_PAD_GPIO_1__USBOTG_ID,
++ MX6DL_PAD_EIM_D22__GPIO_3_22,
++ MX6DL_PAD_EIM_D30__GPIO_3_30
++};
++
++/* ------------------------------------------------------------------------ */
++
++static void wand_usbotg_vbus(bool on) {
++ gpio_set_value_cansleep(WAND_USB_OTG_PWR, !on);
++}
++
++/* ------------------------------------------------------------------------ */
++
++static __init void wand_init_usb(void) {
++ WAND_SETUP_PADS(wand_usb_pads);
++
++ gpio_request(WAND_USB_OTG_OC, "otg oc");
++ gpio_direction_input(WAND_USB_OTG_OC);
++
++ gpio_request(WAND_USB_OTG_PWR, "otg pwr");
++ gpio_direction_output(WAND_USB_OTG_PWR, 0);
++
++ imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
++ mxc_iomux_set_gpr_register(1, 13, 1, 1);
++
++ mx6_set_otghost_vbus_func(wand_usbotg_vbus);
++
++ gpio_request(WAND_USB_H1_OC, "usbh1 oc");
++ gpio_direction_input(WAND_USB_H1_OC);
++}
++
++
++/****************************************************************************
++ *
++ * IPU
++ *
++ ****************************************************************************/
++
++static struct imx_ipuv3_platform_data wand_ipu_data[] = {
++ {
++ .rev = 4,
++ .csi_clk[0] = "ccm_clk0",
++ }, {
++ .rev = 4,
++ .csi_clk[0] = "ccm_clk0",
++ },
++};
++
++/* ------------------------------------------------------------------------ */
++
++static __init void wand_init_ipu(void) {
++ imx6q_add_ipuv3(0, &wand_ipu_data[0]);
++}
++
++
++/****************************************************************************
++ *
++ * HDMI
++ *
++ ****************************************************************************/
++
++static struct ipuv3_fb_platform_data wand_hdmi_fb[] = {
++ { /* hdmi framebuffer */
++ .disp_dev = "hdmi",
++ .interface_pix_fmt = IPU_PIX_FMT_RGB32,
++ .mode_str = "1920x1080@60",
++ .default_bpp = 32,
++ .int_clk = false,
++ }
++};
++
++/* ------------------------------------------------------------------------ */
++
++static void wand_hdmi_init(int ipu_id, int disp_id) {
++ if ((unsigned)ipu_id > 1) ipu_id = 0;
++ if ((unsigned)disp_id > 1) disp_id = 0;
++
++ mxc_iomux_set_gpr_register(3, 2, 2, 2*ipu_id + disp_id);
++}
++
++/* ------------------------------------------------------------------------ */
++
++static struct fsl_mxc_hdmi_platform_data wand_hdmi_data = {
++ .init = wand_hdmi_init,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static struct fsl_mxc_hdmi_core_platform_data wand_hdmi_core_data = {
++ .ipu_id = 0,
++ .disp_id = 1,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static const struct i2c_board_info wand_hdmi_i2c_info = {
++ I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
++};
++
++/* ------------------------------------------------------------------------ */
++
++static void wand_init_hdmi(void) {
++ i2c_register_board_info(0, &wand_hdmi_i2c_info, 1);
++ imx6q_add_mxc_hdmi_core(&wand_hdmi_core_data);
++ imx6q_add_mxc_hdmi(&wand_hdmi_data);
++ imx6q_add_ipuv3fb(0, wand_hdmi_fb);
++
++ /* Enable HDMI audio */
++ imx6q_add_hdmi_soc();
++ imx6q_add_hdmi_soc_dai();
++ mxc_iomux_set_gpr_register(0, 0, 1, 1);
++}
++
++
++/****************************************************************************
++ *
++ * WiFi
++ *
++ ****************************************************************************/
++
++static __initdata iomux_v3_cfg_t wand_wifi_pads[] = {
++ /* ref_on, enable 32k clock */
++ MX6DL_PAD_EIM_EB1__GPIO_2_29,
++ /* Wifi reset (resets when low!) */
++ MX6DL_PAD_EIM_A25__GPIO_5_2,
++ /* reg on, signal to FDC6331L */
++ MX6DL_PAD_ENET_RXD1__GPIO_1_26,
++ /* host wake */
++ MX6DL_PAD_ENET_TXD1__GPIO_1_29,
++ /* wl wake - nc */
++ MX6DL_PAD_ENET_TXD0__GPIO_1_30,
++};
++
++/* ------------------------------------------------------------------------ */
++
++/* assumes SD/MMC pins are set; call after wand_init_sd() */
++static __init void wand_init_wifi(void) {
++ WAND_SETUP_PADS(wand_wifi_pads);
++
++ gpio_request(WAND_WL_RST_N, "wl_rst_n");
++ gpio_direction_output(WAND_WL_RST_N, 0);
++ msleep(11);
++ gpio_set_value(WAND_WL_RST_N, 1);
++
++ gpio_request(WAND_WL_REF_ON, "wl_ref_on");
++ gpio_direction_output(WAND_WL_REF_ON, 1);
++
++ gpio_request(WAND_WL_REG_ON, "wl_reg_on");
++ gpio_direction_output(WAND_WL_REG_ON, 1);
++
++ gpio_request(WAND_WL_WAKE, "wl_wake");
++ gpio_direction_output(WAND_WL_WAKE, 1);
++
++ gpio_request(WAND_WL_HOST_WAKE, "wl_host_wake");
++ gpio_direction_input(WAND_WL_HOST_WAKE);
++}
++
++
++/****************************************************************************
++ *
++ * Bluetooth
++ *
++ ****************************************************************************/
++
++static __initdata iomux_v3_cfg_t wand_bt_pads[] = {
++ /* BT_ON, BT_WAKE and BT_HOST_WAKE */
++ MX6DL_PAD_EIM_DA13__GPIO_3_13,
++ MX6DL_PAD_EIM_DA14__GPIO_3_14,
++ MX6DL_PAD_EIM_DA15__GPIO_3_15,
++
++ /* AUD5 channel goes to BT */
++ MX6DL_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
++ MX6DL_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
++ MX6DL_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
++ MX6DL_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
++
++ /* Bluetooth is on UART3*/
++ MX6DL_PAD_EIM_D23__UART3_CTS,
++ MX6DL_PAD_EIM_D24__UART3_TXD,
++ MX6DL_PAD_EIM_D25__UART3_RXD,
++ MX6DL_PAD_EIM_EB3__UART3_RTS,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static const struct imxuart_platform_data wand_bt_uart_data = {
++ .flags = IMXUART_HAVE_RTSCTS | IMXUART_SDMA,
++ .dma_req_tx = MX6Q_DMA_REQ_UART3_TX,
++ .dma_req_rx = MX6Q_DMA_REQ_UART3_RX,
++};
++
++/* ------------------------------------------------------------------------ */
++
++/* This assumes wifi is initialized (chip has power) */
++static __init void wand_init_bluetooth(void) {
++ WAND_SETUP_PADS(wand_bt_pads);
++
++ imx6q_add_imx_uart(2, &wand_bt_uart_data);
++
++ gpio_request(WAND_BT_ON, "bt_on");
++ gpio_direction_output(WAND_BT_ON, 0);
++ msleep(11);
++ gpio_set_value(WAND_BT_ON, 1);
++
++ gpio_request(WAND_BT_WAKE, "bt_wake");
++ gpio_direction_output(WAND_BT_WAKE, 1);
++
++ gpio_request(WAND_BT_HOST_WAKE, "bt_host_wake");
++ gpio_direction_input(WAND_BT_WAKE);
++}
++
++
++/****************************************************************************
++ *
++ * Power and thermal management
++ *
++ ****************************************************************************/
++
++extern bool enable_wait_mode;
++
++static const struct anatop_thermal_platform_data wand_thermal = {
++ .name = "anatop_thermal",
++};
++
++/* ------------------------------------------------------------------------ */
++
++static void wand_suspend_enter(void) {
++ gpio_set_value(WAND_WL_WAKE, 0);
++ gpio_set_value(WAND_BT_WAKE, 0);
++}
++
++/* ------------------------------------------------------------------------ */
++
++static void wand_suspend_exit(void) {
++ gpio_set_value(WAND_WL_WAKE, 1);
++ gpio_set_value(WAND_BT_WAKE, 1);
++}
++
++/* ------------------------------------------------------------------------ */
++
++static const struct pm_platform_data wand_pm_data = {
++ .name = "imx_pm",
++ .suspend_enter = wand_suspend_enter,
++ .suspend_exit = wand_suspend_exit,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static const struct mxc_dvfs_platform_data wand_dvfscore_data = {
++ .reg_id = "cpu_vddgp",
++ .clk1_id = "cpu_clk",
++ .clk2_id = "gpc_dvfs_clk",
++ .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
++ .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
++ .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
++ .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
++ .prediv_mask = 0x1F800,
++ .prediv_offset = 11,
++ .prediv_val = 3,
++ .div3ck_mask = 0xE0000000,
++ .div3ck_offset = 29,
++ .div3ck_val = 2,
++ .emac_val = 0x08,
++ .upthr_val = 25,
++ .dnthr_val = 9,
++ .pncthr_val = 33,
++ .upcnt_val = 10,
++ .dncnt_val = 10,
++ .delay_time = 80,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static __init void wand_init_pm(void) {
++ enable_wait_mode = false;
++ imx6q_add_anatop_thermal_imx(1, &wand_thermal);
++ imx6q_add_pm_imx(0, &wand_pm_data);
++ imx6q_add_dvfs_core(&wand_dvfscore_data);
++ imx6q_add_busfreq();
++}
++
++
++/****************************************************************************
++ *
++ * Expansion pin header GPIOs
++ *
++ ****************************************************************************/
++
++static __initdata iomux_v3_cfg_t wand_external_gpio_pads[] = {
++ MX6DL_PAD_EIM_DA11__GPIO_3_11,
++ MX6DL_PAD_EIM_D27__GPIO_3_27,
++ MX6DL_PAD_EIM_BCLK__GPIO_6_31,
++ MX6DL_PAD_ENET_RX_ER__GPIO_1_24,
++ MX6DL_PAD_SD3_RST__GPIO_7_8,
++ MX6DL_PAD_EIM_D26__GPIO_3_26,
++ MX6DL_PAD_EIM_DA8__GPIO_3_8,
++ MX6DL_PAD_GPIO_19__GPIO_4_5,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static __init void wand_init_external_gpios(void) {
++ WAND_SETUP_PADS(wand_external_gpio_pads);
++
++ gpio_request(IMX_GPIO_NR(3, 11), "external_gpio_0");
++ gpio_export(IMX_GPIO_NR(3, 11), true);
++ gpio_request(IMX_GPIO_NR(3, 27), "external_gpio_1");
++ gpio_export(IMX_GPIO_NR(3, 27), true);
++ gpio_request(IMX_GPIO_NR(6, 31), "external_gpio_2");
++ gpio_export(IMX_GPIO_NR(6, 31), true);
++ gpio_request(IMX_GPIO_NR(1, 24), "external_gpio_3");
++ gpio_export(IMX_GPIO_NR(1, 24), true);
++ gpio_request(IMX_GPIO_NR(7, 8), "external_gpio_4");
++ gpio_export(IMX_GPIO_NR(7, 8), true);
++ gpio_request(IMX_GPIO_NR(3, 26), "external_gpio_5");
++ gpio_export(IMX_GPIO_NR(3, 26), true);
++ gpio_request(IMX_GPIO_NR(3, 8), "external_gpio_6");
++ gpio_export(IMX_GPIO_NR(3, 8), true);
++ gpio_request(IMX_GPIO_NR(4, 5), "external_gpio_7");
++ gpio_export(IMX_GPIO_NR(4, 5), true);
++}
++
++
++/****************************************************************************
++ *
++ * SPI - while not used on the Wandboard, the pins are routed out
++ *
++ ****************************************************************************/
++
++static __initdata iomux_v3_cfg_t wand_spi_pads[] = {
++ MX6DL_PAD_EIM_D16__ECSPI1_SCLK,
++ MX6DL_PAD_EIM_D17__ECSPI1_MISO,
++ MX6DL_PAD_EIM_D18__ECSPI1_MOSI,
++ MX6DL_PAD_EIM_EB2__GPIO_2_30,
++
++ MX6DL_PAD_EIM_CS0__ECSPI2_SCLK,
++ MX6DL_PAD_EIM_CS1__ECSPI2_MOSI,
++ MX6DL_PAD_EIM_OE__ECSPI2_MISO,
++ MX6DL_PAD_EIM_RW__GPIO_2_26,
++ MX6DL_PAD_EIM_LBA__GPIO_2_27,
++};
++/* The choice of using gpios for chipselect is deliberate,
++ there can be issues using the dedicated mux modes for cs.
++*/
++
++/* ------------------------------------------------------------------------ */
++
++static const int wand_spi1_chipselect[] = { IMX_GPIO_NR(2, 30) };
++
++/* platform device */
++static const struct spi_imx_master wand_spi1_data = {
++ .chipselect = wand_spi1_chipselect,
++ .num_chipselect = ARRAY_SIZE(wand_spi1_chipselect),
++};
++
++/* ------------------------------------------------------------------------ */
++
++static const int wand_spi2_chipselect[] = { IMX_GPIO_NR(2, 26), IMX_GPIO_NR(2, 27) };
++
++static const struct spi_imx_master wand_spi2_data = {
++ .chipselect = wand_spi2_chipselect,
++ .num_chipselect = ARRAY_SIZE(wand_spi2_chipselect),
++};
++
++/* ------------------------------------------------------------------------ */
++
++static void __init wand_init_spi(void) {
++ WAND_SETUP_PADS(wand_spi_pads);
++
++ imx6q_add_ecspi(0, &wand_spi1_data);
++ imx6q_add_ecspi(1, &wand_spi2_data);
++}
++
++
++/****************************************************************************
++ *
++ * Vivante GPU/VPU
++ *
++ ****************************************************************************/
++
++static const __initconst struct imx_viv_gpu_data wand_gpu_data = {
++ .phys_baseaddr = 0,
++ .iobase_3d = GPU_3D_ARB_BASE_ADDR,
++ .irq_3d = MXC_INT_GPU3D_IRQ,
++ .iobase_2d = GPU_2D_ARB_BASE_ADDR,
++ .irq_2d = MXC_INT_GPU2D_IRQ,
++ .iobase_vg = OPENVG_ARB_BASE_ADDR,
++ .irq_vg = MXC_INT_OPENVG_XAQ2,
++};
++
++static struct viv_gpu_platform_data wand_gpu_pdata = {
++ .reserved_mem_size = SZ_128M + SZ_64M - SZ_16M,
++};
++
++static __init void wand_init_gpu(void) {
++ imx_add_viv_gpu(&wand_gpu_data, &wand_gpu_pdata);
++ imx6q_add_vpu();
++ imx6q_add_v4l2_output(0);
++}
++
++/*****************************************************************************
++ *
++ * Init clocks and early boot console
++ *
++ *****************************************************************************/
++
++extern void __iomem *twd_base;
++
++static void __init wand_init_timer(void) {
++ struct clk *uart_clk;
++#ifdef CONFIG_LOCAL_TIMERS
++ twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
++#endif
++ mx6_clocks_init(32768, 24000000, 0, 0);
++
++ uart_clk = clk_get_sys("imx-uart.0", NULL);
++ early_console_setup(UART1_BASE_ADDR, uart_clk);
++}
++
++/* ------------------------------------------------------------------------ */
++
++static struct sys_timer wand_timer = {
++ .init = wand_init_timer,
++};
++
++/* ------------------------------------------------------------------------ */
++
++static void __init wand_reserve(void) {
++ phys_addr_t phys;
++
++ if (wand_gpu_pdata.reserved_mem_size) {
++ phys = memblock_alloc_base(wand_gpu_pdata.reserved_mem_size, SZ_4K, SZ_512M);
++ memblock_remove(phys, wand_gpu_pdata.reserved_mem_size);
++ wand_gpu_pdata.reserved_mem_base = phys;
++ }
++}
++
++/*****************************************************************************
++ *
++ * BOARD INIT
++ *
++ *****************************************************************************/
++
++static void __init wand_board_init(void) {
++ wand_init_dma();
++ wand_init_uart();
++ wand_init_sd();
++ wand_init_i2c();
++ wand_init_audio();
++ wand_init_ethernet();
++ wand_init_usb();
++ wand_init_ipu();
++ imx6q_add_imx_snvs_rtc();
++ wand_init_hdmi();
++ wand_init_wifi();
++ wand_init_bluetooth();
++ wand_init_pm();
++ wand_init_external_gpios();
++ wand_init_spi();
++ wand_init_gpu();
++}
++
++/* ------------------------------------------------------------------------ */
++
++MACHINE_START(WANDBOARD, "Wandboard")
++ .boot_params = MX6_PHYS_OFFSET + 0x100,
++ .map_io = mx6_map_io,
++ .init_irq = mx6_init_irq,
++ .init_machine = wand_board_init,
++ .timer = &wand_timer,
++ .reserve = wand_reserve,
++MACHINE_END
++
+diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
+index 88210d9..5b4c1be 100644
+--- a/arch/arm/tools/mach-types
++++ b/arch/arm/tools/mach-types
+@@ -1119,4 +1119,5 @@ mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980
+ mx6q_arm2 MACH_MX6Q_ARM2 MX6Q_ARM2 3837
+ mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091
+ mx6sl_evk MACH_MX6SL_EVK MX6SL_EVK 4307
++wandboard MACH_WANDBOARD WANDBOARD 4412
+
+--
+1.7.9.5
+
diff --git a/recipes-kernel/linux/linux-imx-3.0.35/wandboard-dual/defconfig b/recipes-kernel/linux/linux-imx-3.0.35/wandboard-dual/defconfig
new file mode 100644
index 0000000..cbc3c34
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.0.35/wandboard-dual/defconfig
@@ -0,0 +1,2762 @@
+#
+# Automatically generated make config: don't edit
+# Linux/arm 3.0.35 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_SCHED_CLOCK=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LOCKBREAK=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FIQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-1.1.0+yocto"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_PREEMPT_RCU=y
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_BOOST is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_CGROUP_PERF is not set
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS4 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+CONFIG_IMX_HAVE_PLATFORM_DMA=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_MLB=y
+CONFIG_IMX_HAVE_PLATFORM_FEC=y
+CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
+CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
+CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
+CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
+CONFIG_IMX_HAVE_PLATFORM_AHCI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
+CONFIG_IMX_HAVE_PLATFORM_PERFMON=y
+CONFIG_IMX_HAVE_PLATFORM_LDB=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_PXP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
+CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
+
+#
+# Freescale MXC Implementations
+#
+# CONFIG_ARCH_MX1 is not set
+# CONFIG_ARCH_MX2 is not set
+# CONFIG_ARCH_MX25 is not set
+# CONFIG_ARCH_MX3 is not set
+# CONFIG_ARCH_MX503 is not set
+# CONFIG_ARCH_MX51 is not set
+CONFIG_ARCH_MX6=y
+CONFIG_ARCH_MX6Q=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_SOC_IMX6Q=y
+CONFIG_MACH_MX6Q_ARM2=y
+# CONFIG_MACH_MX6SL_ARM2 is not set
+# CONFIG_MACH_MX6SL_EVK is not set
+# CONFIG_MACH_MX6Q_SABRELITE is not set
+# CONFIG_MACH_MX6Q_SABRESD is not set
+# CONFIG_MACH_MX6Q_SABREAUTO is not set
+CONFIG_MACH_WANDBOARD=y
+CONFIG_WANDBOARD_BASE=y
+
+#
+# MX6 Options:
+#
+# CONFIG_IMX_PCIE is not set
+CONFIG_USB_EHCI_ARC_H1=y
+CONFIG_USB_FSL_ARC_OTG=y
+# CONFIG_MX6_INTER_LDO_BYPASS is not set
+# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS is not set
+CONFIG_ISP1504_MXC=y
+# CONFIG_MXC_IRQ_PRIOR is not set
+CONFIG_MXC_PWM=y
+# CONFIG_MXC_DEBUG_BOARD is not set
+CONFIG_MXC_REBOOT_MFGMODE=y
+# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
+CONFIG_ARCH_MXC_IOMUX_V3=y
+CONFIG_ARCH_MXC_AUDMUX_V2=y
+CONFIG_IRAM_ALLOC=y
+CONFIG_CLK_DEBUG=y
+CONFIG_DMA_ZONE_SIZE=184
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_742230 is not set
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+# CONFIG_ARM_ERRATA_753970 is not set
+CONFIG_ARM_ERRATA_754322=y
+# CONFIG_ARM_ERRATA_754327 is not set
+CONFIG_ARM_GIC=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+CONFIG_ARM_ERRATA_764369=y
+# CONFIG_PL310_ERRATA_769419 is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+CONFIG_LOCAL_TIMERS=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CLEANCACHE is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+# CONFIG_USE_OF is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_IMX=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_ADVANCED_DEBUG is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_APM_EMULATION=y
+CONFIG_PM_RUNTIME_CLK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+CONFIG_LLC2=y
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=y
+# CONFIG_CAN_SLCAN is not set
+CONFIG_CAN_DEV=y
+CONFIG_CAN_CALC_BITTIMING=y
+# CONFIG_CAN_MCP251X is not set
+CONFIG_HAVE_CAN_FLEXCAN=y
+CONFIG_CAN_FLEXCAN=y
+# CONFIG_CAN_SJA1000 is not set
+# CONFIG_CAN_C_CAN is not set
+
+#
+# CAN USB interfaces
+#
+# CONFIG_CAN_EMS_USB is not set
+# CONFIG_CAN_ESD_USB2 is not set
+# CONFIG_CAN_SOFTING is not set
+# CONFIG_CAN_DEBUG_DEVICES is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=y
+# CONFIG_BT_HCIUART_H4 is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+CONFIG_BT_HCIUART_ATH3K=y
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+CONFIG_BT_HCIVHCI=y
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+CONFIG_LIB80211_CRYPT_WEP=y
+CONFIG_LIB80211_CRYPT_CCMP=y
+CONFIG_LIB80211_CRYPT_TKIP=y
+# CONFIG_LIB80211_DEBUG is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_RFKILL_GPIO is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_GPMI_NAND=y
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+CONFIG_MXS_PERFMON=m
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_SATA_MV is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ARASAN_CF is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_PLATFORM is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_MICREL_PHY=y
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_FEC=y
+CONFIG_FEC_NAPI=y
+# CONFIG_FEC_1588 is not set
+# CONFIG_FTMAC100 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH6KL=m
+# CONFIG_ATH6KL_DEBUG is not set
+CONFIG_HOSTAP=y
+# CONFIG_HOSTAP_FIRMWARE is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_APMPOWER is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_IMX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+CONFIG_TOUCHSCREEN_EGALAX=y
+CONFIG_TOUCHSCREEN_ELAN=y
+CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+CONFIG_TOUCHSCREEN_MAX11801=y
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_NOVATEK is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_P1003 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+CONFIG_INPUT_ISL29023=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_AMBAKMI is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+# CONFIG_SERIAL_AMBA_PL011 is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_FSL_OTP=y
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_MXS_VIIM=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_IMX_VER_2_3=y
+CONFIG_SPI_IMX=y
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PL022 is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_BASIC_MMIO is not set
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_PL061 is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X_IRQ is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_WM8994 is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+CONFIG_SABRESD_MAX8903=y
+# CONFIG_CHARGER_GPIO is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+CONFIG_SENSORS_MAX17135=y
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_SENSORS_MAG3110=y
+# CONFIG_MXC_MMA8450 is not set
+CONFIG_MXC_MMA8451=y
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+# CONFIG_MPCORE_WATCHDOG is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_IMX2_WDT=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+CONFIG_MFD_SUPPORT=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+CONFIG_MFD_WM8994=y
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_PMIC_DIALOG is not set
+# CONFIG_MFD_MC_PMIC is not set
+# CONFIG_MFD_MC34708 is not set
+CONFIG_MFD_PFUZE=y
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65910 is not set
+CONFIG_MFD_MAX17135=y
+CONFIG_MFD_MXC_HDMI=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_WM8994 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_MC34708 is not set
+CONFIG_REGULATOR_PFUZE100=y
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+CONFIG_REGULATOR_ANATOP=y
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_MAX17135=y
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders, decoders, sensors and other helper chips
+#
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_AK881X is not set
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_VIDEO_MXC_CAMERA=m
+
+#
+# MXC Camera/V4L2 PRP Features support
+#
+CONFIG_VIDEO_MXC_IPU_CAMERA=y
+# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
+# CONFIG_MXC_CAMERA_MICRON111 is not set
+# CONFIG_MXC_CAMERA_OV2640 is not set
+CONFIG_MXC_CAMERA_OV3640=m
+CONFIG_MXC_CAMERA_OV5640=m
+CONFIG_MXC_CAMERA_OV8820_MIPI=m
+CONFIG_MXC_CAMERA_OV5642=m
+CONFIG_MXC_TVIN_ADV7180=m
+CONFIG_MXC_CAMERA_OV5640_MIPI=m
+# CONFIG_MXC_MIPI_CSI2_TVIN_ADV7280 is not set
+CONFIG_MXC_CAMERA_SENSOR_CLK=m
+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+CONFIG_MXC_IPU_PRP_ENC=m
+CONFIG_MXC_IPU_CSI_ENC=m
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
+# CONFIG_VIDEO_MXC_OPL is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+
+#
+# Graphics support
+#
+CONFIG_DRM=m
+CONFIG_DRM_VIVANTE=m
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_ARMCLCD is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+CONFIG_FB_MXC=y
+CONFIG_FB_MXC_EDID=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_MIPI_DSI=y
+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
+# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
+# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
+# CONFIG_FB_MXC_SII902X is not set
+# CONFIG_FB_MXC_CH7026 is not set
+# CONFIG_FB_MXC_TVOUT_CH7024 is not set
+# CONFIG_FB_MXC_ASYNC_PANEL is not set
+CONFIG_FB_MXC_EINK_PANEL=y
+# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set
+# CONFIG_FB_MXC_SIPIX_PANEL is not set
+# CONFIG_FB_MXC_ELCDIF_FB is not set
+CONFIG_FB_MXC_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_ARMAACI is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_CACHE_LZO is not set
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_MXC_SOC_MX2=y
+CONFIG_SND_MXC_SOC_SPDIF_DAI=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+# CONFIG_SND_SOC_IMX_WM8958 is not set
+CONFIG_SND_SOC_IMX_WM8962=y
+CONFIG_SND_SOC_IMX_CS42888=y
+# CONFIG_SND_SOC_IMX_SI4763 is not set
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_IMX_HDMI=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_MXC_HDMI=y
+CONFIG_SND_SOC_MXC_SPDIF=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_SND_SOC_CS42888=y
+CONFIG_SND_SOC_WM8962=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+# CONFIG_HID_PRODIKEYS is not set
+CONFIG_HID_CYPRESS=m
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+CONFIG_HID_EZKEY=m
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+CONFIG_HID_GYRATION=m
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIWII_FF is not set
+# CONFIG_HID_MAGICMOUSE is not set
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_ARVO is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_ROCCAT_KONEPLUS is not set
+# CONFIG_HID_ROCCAT_KOVAPLUS is not set
+# CONFIG_HID_ROCCAT_PYRA is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ARC=y
+CONFIG_USB_EHCI_ARC_OTG=y
+# CONFIG_USB_EHCI_ARC_HSIC is not set
+# CONFIG_USB_STATIC_IRAM is not set
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_EHCI_MXC is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_ARC=y
+# CONFIG_IMX_USB_CHARGER is not set
+CONFIG_USB_ARC=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_FUSB300 is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA_U2O is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_AUDIO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_FSL_UTP is not set
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_MASS_STORAGE is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MXC_OTG=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_ARMMMCI is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+
+#
+# LED Triggers
+#
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+CONFIG_RTC_DRV_SNVS=y
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+# CONFIG_AMBA_PL08X is not set
+# CONFIG_DW_DMAC is not set
+CONFIG_MXC_PXP_V2=y
+CONFIG_MXC_PXP_CLIENT_DEVICE=y
+# CONFIG_TIMB_DMA is not set
+CONFIG_IMX_SDMA=y
+CONFIG_MXS_DMA=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+
+#
+# MXC support drivers
+#
+CONFIG_MXC_IPU=y
+CONFIG_MXC_IPU_V3=y
+CONFIG_MXC_IPU_V3H=y
+
+#
+# MXC SSI support
+#
+# CONFIG_MXC_SSI is not set
+
+#
+# MXC Digital Audio Multiplexer support
+#
+# CONFIG_MXC_DAM is not set
+
+#
+# MXC PMIC support
+#
+# CONFIG_MXC_PMIC_MC13783 is not set
+# CONFIG_MXC_PMIC_MC13892 is not set
+# CONFIG_MXC_PMIC_MC34704 is not set
+# CONFIG_MXC_PMIC_MC9SDZ60 is not set
+# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
+
+#
+# MXC Security Drivers
+#
+# CONFIG_MXC_SECURITY_SCC is not set
+# CONFIG_MXC_SECURITY_RNG is not set
+
+#
+# MXC MPEG4 Encoder Kernel module support
+#
+# CONFIG_MXC_HMP4E is not set
+
+#
+# MXC HARDWARE EVENT
+#
+# CONFIG_MXC_HWEVENT is not set
+
+#
+# MXC VPU(Video Processing Unit) support
+#
+CONFIG_MXC_VPU=y
+# CONFIG_MXC_VPU_DEBUG is not set
+# CONFIG_MX6_VPU_352M is not set
+
+#
+# MXC Asynchronous Sample Rate Converter support
+#
+CONFIG_MXC_ASRC=y
+
+#
+# MXC Bluetooth support
+#
+
+#
+# Broadcom GPS ioctrl support
+#
+
+#
+# MXC Media Local Bus Driver
+#
+CONFIG_MXC_MLB=y
+CONFIG_MXC_MLB150=m
+
+#
+# i.MX ADC support
+#
+# CONFIG_IMX_ADC is not set
+
+#
+# MXC Vivante GPU support
+#
+CONFIG_MXC_GPU_VIV=y
+
+#
+# ANATOP_THERMAL
+#
+CONFIG_ANATOP_THERMAL=y
+
+#
+# MXC MIPI Support
+#
+CONFIG_MXC_MIPI_CSI2=y
+
+#
+# MXC HDMI CEC (Consumer Electronics Control) support
+#
+# CONFIG_MXC_HDMI_CEC is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_VERBOSE=y
+# CONFIG_LKDTM is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_OC_ETM=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_GF128MUL=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_TEST=m
+# CONFIG_CRYPTO_CRYPTODEV is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+CONFIG_CRYPTO_GHASH=y
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255
+CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_RATIONAL=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
diff --git a/recipes-kernel/linux/linux-imx_3.0.35.bbappend b/recipes-kernel/linux/linux-imx_3.0.35.bbappend
new file mode 100644
index 0000000..7554c66
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx_3.0.35.bbappend
@@ -0,0 +1,8 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}-${PV}:"
+
+PRINC := "${@int(PRINC) + 1}"
+
+# Wandboard-specific patches
+SRC_URI_append_wandboard-dual= " \
+ file://Initial-kernel-support-for-Wandboard.patch \
+"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [meta-fsl-arm-extra][PATCH 2/3] Add U-boot support for Wandboard Dual
2013-02-23 20:29 [meta-fsl-arm-extra][PATCH 1/3] Add kernel support for Wandboard Dual John Weber
@ 2013-02-23 20:29 ` John Weber
2013-02-26 19:24 ` Otavio Salvador
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 3/3] Add conf " John Weber
2013-02-26 19:24 ` [meta-fsl-arm-extra][PATCH 1/3] Add kernel " Otavio Salvador
2 siblings, 1 reply; 8+ messages in thread
From: John Weber @ 2013-02-23 20:29 UTC (permalink / raw)
To: meta-freescale
This patch adds U-boot-imx support for Wandboard Dual. It is
meant to patch the 2009.08 u-boot from the 1.1.0 FSL SDK.
Signed-off-by: John Weber <rjohnweber@gmail.com>
---
Upstream-Status: Pending
.../Initial-support-for-Wandboard-Dual.patch | 1773 ++++++++++++++++++++
recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend | 8 +
2 files changed, 1781 insertions(+)
create mode 100644 recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-Dual.patch
create mode 100644 recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
diff --git a/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-Dual.patch b/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-Dual.patch
new file mode 100644
index 0000000..cdb641f
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-Dual.patch
@@ -0,0 +1,1773 @@
+From eb057c5028d8f5e7243b0875d2bd299ecb376e01 Mon Sep 17 00:00:00 2001
+From: John Weber <rjohnweber@gmail.com>
+Date: Fri, 22 Feb 2013 08:49:27 -0600
+Subject: [PATCH] Initial support for Wandboard Dual
+
+ That patch adds support for Wandboard. It has been tested on
+ Wandboard-Dual. The serial port, module microSD card slot,
+ and ethernet ports were found to work. Testers welcome.
+
+ Almost all of this was ported directly from the Wandboard SDK
+ released Feb 5, 2013 and was the work of Tapani.
+
+---
+ Makefile | 3 +
+ board/freescale/wandboard/Makefile | 47 +++
+ board/freescale/wandboard/config.mk | 7 +
+ board/freescale/wandboard/flash_header.S | 572 +++++++++++++++++++++++++++++
+ board/freescale/wandboard/lowlevel_init.S | 171 +++++++++
+ board/freescale/wandboard/u-boot.lds | 74 ++++
+ board/freescale/wandboard/wandboard.c | 494 +++++++++++++++++++++++++
+ include/asm-arm/mach-types.h | 27 ++
+ include/configs/wandboard.h | 273 ++++++++++++++
+ 9 files changed, 1668 insertions(+)
+ create mode 100644 board/freescale/wandboard/Makefile
+ create mode 100644 board/freescale/wandboard/config.mk
+ create mode 100644 board/freescale/wandboard/flash_header.S
+ create mode 100644 board/freescale/wandboard/lowlevel_init.S
+ create mode 100644 board/freescale/wandboard/u-boot.lds
+ create mode 100644 board/freescale/wandboard/wandboard.c
+ create mode 100644 include/configs/wandboard.h
+
+diff --git a/Makefile b/Makefile
+index 1088794..41cca34 100644
+--- a/Makefile
++++ b/Makefile
+@@ -3387,6 +3387,9 @@ mx6sl_evk_iram_config : unconfig
+ }
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6sl_evk freescale mx6
+
++wandboard_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 wandboard freescale mx6
++
+ omap2420h4_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
+
+diff --git a/board/freescale/wandboard/Makefile b/board/freescale/wandboard/Makefile
+new file mode 100644
+index 0000000..c0b30e4
+--- /dev/null
++++ b/board/freescale/wandboard/Makefile
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2010-2011 Freescale Semiconductor, Inc.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS := $(BOARD).o
++SOBJS := lowlevel_init.o flash_header.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/freescale/wandboard/config.mk b/board/freescale/wandboard/config.mk
+new file mode 100644
+index 0000000..a0ce2a1
+--- /dev/null
++++ b/board/freescale/wandboard/config.mk
+@@ -0,0 +1,7 @@
++LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
++
++sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
++
++ifndef TEXT_BASE
++ TEXT_BASE = 0x27800000
++endif
+diff --git a/board/freescale/wandboard/flash_header.S b/board/freescale/wandboard/flash_header.S
+new file mode 100644
+index 0000000..f97d970
+--- /dev/null
++++ b/board/freescale/wandboard/flash_header.S
+@@ -0,0 +1,572 @@
++/*
++ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <asm/arch/mx6.h>
++
++#ifdef CONFIG_FLASH_HEADER
++#ifndef CONFIG_FLASH_HEADER_OFFSET
++# error "Must define the offset of flash header"
++#endif
++
++#define CPU_2_BE_32(l) \
++ ((((l) & 0x000000FF) << 24) | \
++ (((l) & 0x0000FF00) << 8) | \
++ (((l) & 0x00FF0000) >> 8) | \
++ (((l) & 0xFF000000) >> 24))
++
++#define MXC_DCD_ITEM(i, addr, val) \
++dcd_node_##i: \
++ .word CPU_2_BE_32(addr) ; \
++ .word CPU_2_BE_32(val) ; \
++
++.section ".text.flasheader", "x"
++ b _start
++ .org CONFIG_FLASH_HEADER_OFFSET
++
++ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
++app_code_jump_v: .word _start
++reserv1: .word 0x0
++dcd_ptr: .word dcd_hdr
++boot_data_ptr: .word boot_data
++self_ptr: .word ivt_header
++app_code_csf: .word 0x0
++reserv2: .word 0x0
++
++boot_data: .word TEXT_BASE
++image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
++plugin: .word 0x0
++
++#ifdef CONFIG_MX6SOLO_DDR3
++dcd_hdr: .word 0x408802D2 /* Tag=0xD2, Len=80*8 + 4 + 4, Ver=0x40 */
++write_dcd_cmd: .word 0x048402CC /* Tag=0xCC, Len=80*8 + 4, Param=0x04 */
++
++/* DCD */
++/* DDR3 initialization based on the MX6Solo Auto Reference Design (ARD) */
++/* DDR IO TYPE */
++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
++/* CLOCK */
++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
++/* ADDRESS */
++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
++/* CONTROLE */
++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x000c0030)
++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000)
++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000)
++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030)
++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030)
++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
++/* DATA STROBE */
++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000038)
++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000038)
++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000038)
++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000038)
++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000038)
++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000038)
++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000038)
++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000038)
++/* DATA */
++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
++
++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x000C0030)
++/* ZQ */
++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
++MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
++/* Write leveling */
++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x0040003c)
++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0032003e)
++
++MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x83c, 0x42350231)
++MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x840, 0x021a0218)
++MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x848, 0x4b4b4e49)
++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x850, 0x3f3f3035)
++/* Read data bit delay */
++MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
++MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
++MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
++MXC_DCD_ITEM(53, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
++MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
++MXC_DCD_ITEM(55, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
++MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
++
++/* Complete calibration by forced measurement */
++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
++MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
++
++MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
++MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x00c, 0x696d5323)
++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x030, 0x006d0e21)
++MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x000, 0x84190000)
++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
++MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
++MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
++MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
++MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
++MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x004, 0x00011006)
++MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
++
++#elif defined CONFIG_MX6DL_DDR3
++
++dcd_hdr: .word 0x40E002D2 /* Tag=0xD2, Len=91*8 + 4 + 4, Ver=0x40 */
++write_dcd_cmd: .word 0x04DC02CC /* Tag=0xCC, Len=91*8 + 4, Param=0x04 */
++
++# IOMUXC_BASE_ADDR = 0x20e0000
++# DDR IO TYPE
++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
++# Clock
++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
++# Address
++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
++# Control
++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)
++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000)
++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000)
++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030)
++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030)
++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
++# Data Strobe
++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
++
++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030)
++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030)
++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030)
++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030)
++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000030)
++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000030)
++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000030)
++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000030)
++# DATA
++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
++
++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
++
++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x00000030)
++
++# MMDC_P0_BASE_ADDR = 0x021b0000
++# MMDC_P1_BASE_ADDR = 0x021b4000
++# Calibrations
++# ZQ
++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
++MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
++# write leveling
++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
++MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
++# DQS gating, read delay, write delay calibration values
++# based on calibration compare of 0x00ffff00
++MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x420E020E)
++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x02000200)
++MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x42020202)
++MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x01720172)
++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x494C4F4C)
++MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x4A4C4C49)
++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3133)
++MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x39373F2E)
++# read data bit delay
++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
++MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
++MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
++MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
++MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
++MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
++# Complete calibration by forced measurment
++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
++MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
++# MMDC init:
++# in DDR3, 64-bit mode, only MMDC0 is initiated:
++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
++
++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
++MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
++
++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
++MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
++MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x00440e21)
++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0xc31a0000)
++
++# Initialize 2GB DDR3 - Micron MT41J128M
++# MR2
++MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
++# MR3
++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
++MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
++# MR1
++MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
++# MR0
++MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038)
++# ZQ calibration
++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
++# final DDR setup
++MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
++MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
++MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
++MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
++MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)
++MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
++
++#elif defined CONFIG_LPDDR2
++dcd_hdr: .word 0x40F003D2 /* Tag=0xD2, Len=125*8 + 4 + 4, Ver=0x40 */
++write_dcd_cmd: .word 0x04EC03CC /* Tag=0xCC, Len=125*8 + 4, Param=0x04 */
++
++/* DCD */
++MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324)
++
++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038)
++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038)
++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x524, 0x00003038)
++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x51c, 0x00003038)
++
++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x518, 0x00003038)
++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x50c, 0x00003038)
++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038)
++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038)
++
++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038)
++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x528, 0x00000038)
++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x520, 0x00000038)
++
++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x514, 0x00000038)
++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x510, 0x00000038)
++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038)
++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
++
++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x56c, 0x00000038)
++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x578, 0x00000038)
++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00000038)
++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x594, 0x00000038)
++
++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x57c, 0x00000038)
++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x590, 0x00000038)
++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x598, 0x00000038)
++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
++
++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x59c, 0x00000038)
++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038)
++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x788, 0x00000038)
++
++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x794, 0x00000038)
++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x79c, 0x00000038)
++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038)
++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038)
++
++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038)
++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
++
++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
++MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x798, 0x00080000)
++
++MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
++MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
++
++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
++
++MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000)
++MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000)
++
++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
++MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x890, 0x00400000)
++
++MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
++
++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
++MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
++
++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
++MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
++MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
++MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
++MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
++MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
++
++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
++MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333)
++MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333)
++MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333)
++MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x838, 0xf3333333)
++
++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x848, 0x49383b39)
++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x850, 0x30364738)
++MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x3e3c3846)
++MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x850, 0x4c294b35)
++
++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x840, 0x0)
++MXC_DCD_ITEM(75, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
++MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x840, 0x0)
++
++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x858, 0xf00)
++MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x858, 0xf00)
++
++MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
++MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
++
++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0xc, 0x555a61a5)
++MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x4, 0x20036)
++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x10, 0x160e83)
++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x14, 0xdd)
++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x18, 0x8174c)
++MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x2c, 0xf9f26d2)
++MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x30, 0x20e)
++MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x38, 0x200aac)
++MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x8, 0x0)
++
++MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x40, 0x5f)
++
++MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x0, 0xc3010000)
++
++MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0xc, 0x555a61a5)
++MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x4, 0x20036)
++MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x10, 0x160e83)
++MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x14, 0xdd)
++MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x18, 0x8174c)
++MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x2c, 0xf9f26d2)
++MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x30, 0x20e)
++MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x38, 0x200aac)
++MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x8, 0x0)
++
++MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x40, 0x3f)
++MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x0, 0xc3010000)
++
++MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x1c, 0x3f8030)
++MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x1c, 0xff0a8030)
++MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x1c, 0xc2018030)
++MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x1c, 0x6028030)
++MXC_DCD_ITEM(107, MMDC_P0_BASE_ADDR + 0x1c, 0x2038030)
++
++MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x1c, 0x3f8030)
++MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x1c, 0xff0a8030)
++MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x1c, 0xc2018030)
++MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x1c, 0x6028030)
++MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x1c, 0x2038030)
++
++MXC_DCD_ITEM(113, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
++MXC_DCD_ITEM(114, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
++
++MXC_DCD_ITEM(115, MMDC_P0_BASE_ADDR + 0x20, 0x7800)
++MXC_DCD_ITEM(116, MMDC_P1_BASE_ADDR + 0x20, 0x7800)
++
++MXC_DCD_ITEM(117, MMDC_P0_BASE_ADDR + 0x818, 0x0)
++MXC_DCD_ITEM(118, MMDC_P1_BASE_ADDR + 0x818, 0x0)
++
++MXC_DCD_ITEM(119, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
++MXC_DCD_ITEM(120, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
++
++MXC_DCD_ITEM(121, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
++MXC_DCD_ITEM(122, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
++
++MXC_DCD_ITEM(123, MMDC_P0_BASE_ADDR + 0x1c, 0x0)
++MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0)
++
++MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
++
++#else
++
++dcd_hdr: .word 0x40B002D2 /* Tag=0xD2, Len=85*8 + 4 + 4, Ver=0x40 */
++write_dcd_cmd: .word 0x04AC02CC /* Tag=0xCC, Len=85*8 + 4, Param=0x04 */
++
++/* DCD */
++/* DDR3 initialization based on the MX6Q Auto Reference Design (ARD) */
++
++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000028)
++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000028)
++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000028)
++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000028)
++
++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000028)
++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000028)
++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000028)
++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000028)
++
++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00000028)
++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00000028)
++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00000028)
++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00000028)
++
++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00000028)
++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00000028)
++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00000028)
++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00000028)
++
++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
++
++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00000030)
++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00000030)
++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
++
++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000028)
++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000028)
++
++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000028)
++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000028)
++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000028)
++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000028)
++
++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000028)
++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000028)
++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
++
++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
++
++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
++MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
++
++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
++MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
++MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
++MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
++
++MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
++
++MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7975)
++MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
++MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
++
++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008F0E21)
++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
++MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
++MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
++
++MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
++
++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
++MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
++
++/* Calibration values based on ARD and 528MHz */
++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0358)
++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x840, 0x033D033C)
++MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x83c, 0x03520362)
++MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x840, 0x03480318)
++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x848, 0x41383A3C)
++MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x848, 0x3F3C374A)
++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x850, 0x42434444)
++MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x850, 0x4932473A)
++
++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
++
++MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
++MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
++
++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
++MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
++
++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
++
++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
++
++#endif
++
++#endif
+diff --git a/board/freescale/wandboard/lowlevel_init.S b/board/freescale/wandboard/lowlevel_init.S
+new file mode 100644
+index 0000000..b725b66
+--- /dev/null
++++ b/board/freescale/wandboard/lowlevel_init.S
+@@ -0,0 +1,171 @@
++/*
++ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <asm/arch/mx6.h>
++
++/*
++ Disable L2Cache because ROM turn it on when uboot use plug-in.
++ If L2Cache is on default, there are cache coherence problem if kernel have
++ not config L2Cache.
++*/
++.macro init_l2cc
++ ldr r1, =0xa02000
++ ldr r0, =0x0
++ str r0, [r1, #0x100]
++.endm /* init_l2cc */
++
++/* invalidate the D-CACHE */
++.macro inv_dcache
++ mov r0,#0
++ mcr p15,2,r0,c0,c0,0 /* cache size selection register, select dcache */
++ mrc p15,1,r0,c0,c0,0 /* cache size ID register */
++ mov r0,r0,ASR #13
++ ldr r3,=0xfff
++ and r0,r0,r3
++ cmp r0,#0x7f
++ moveq r6,#0x1000
++ beq size_done
++ cmp r0,#0xff
++ moveq r6,#0x2000
++ movne r6,#0x4000
++
++size_done:
++ mov r2,#0
++ mov r3,#0x40000000
++ mov r4,#0x80000000
++ mov r5,#0xc0000000
++
++d_inv_loop:
++ mcr p15,0,r2,c7,c6,2 /* invalidate dcache by set / way */
++ mcr p15,0,r3,c7,c6,2 /* invalidate dcache by set / way */
++ mcr p15,0,r4,c7,c6,2 /* invalidate dcache by set / way */
++ mcr p15,0,r5,c7,c6,2 /* invalidate dcache by set / way */
++ add r2,r2,#0x20
++ add r3,r3,#0x20
++ add r4,r4,#0x20
++ add r5,r5,#0x20
++
++ cmp r2,r6
++ bne d_inv_loop
++.endm
++
++/* AIPS setup - Only setup MPROTx registers.
++ * The PACR default values are good.*/
++.macro init_aips
++ /*
++ * Set all MPROTx to be non-bufferable, trusted for R/W,
++ * not forced to user-mode.
++ */
++ ldr r0, =AIPS1_ON_BASE_ADDR
++ ldr r1, =0x77777777
++ str r1, [r0, #0x0]
++ str r1, [r0, #0x4]
++ ldr r1, =0x0
++ str r1, [r0, #0x40]
++ str r1, [r0, #0x44]
++ str r1, [r0, #0x48]
++ str r1, [r0, #0x4C]
++ str r1, [r0, #0x50]
++
++ ldr r0, =AIPS2_ON_BASE_ADDR
++ ldr r1, =0x77777777
++ str r1, [r0, #0x0]
++ str r1, [r0, #0x4]
++ ldr r1, =0x0
++ str r1, [r0, #0x40]
++ str r1, [r0, #0x44]
++ str r1, [r0, #0x48]
++ str r1, [r0, #0x4C]
++ str r1, [r0, #0x50]
++.endm /* init_aips */
++
++.macro setup_pll pll, freq
++.endm
++
++.macro init_clock
++
++/* PLL1, PLL2, and PLL3 are enabled by ROM */
++#ifdef CONFIG_PLL3
++ /* enable PLL3 for UART */
++ ldr r0, ANATOP_BASE_ADDR_W
++
++ /* power up PLL */
++ ldr r1, [r0, #ANATOP_USB1]
++ orr r1, r1, #0x1000
++ str r1, [r0, #ANATOP_USB1]
++
++ /* enable PLL */
++ ldr r1, [r0, #ANATOP_USB1]
++ orr r1, r1, #0x2000
++ str r1, [r0, #ANATOP_USB1]
++
++ /* wait PLL lock */
++100:
++ ldr r1, [r0, #ANATOP_USB1]
++ mov r1, r1, lsr #31
++ cmp r1, #0x1
++ bne 100b
++
++ /* clear bypass bit */
++ ldr r1, [r0, #ANATOP_USB1]
++ and r1, r1, #0xfffeffff
++ str r1, [r0, #ANATOP_USB1]
++#endif
++
++ /* Restore the default values in the Gate registers */
++ ldr r0, CCM_BASE_ADDR_W
++ ldr r1, =0xC0003F
++ str r1, [r0, #CLKCTL_CCGR0]
++ ldr r1, =0x30FC00
++ str r1, [r0, #CLKCTL_CCGR1]
++ ldr r1, =0xFFFC000
++ str r1, [r0, #CLKCTL_CCGR2]
++ ldr r1, =0x3FF00000
++ str r1, [r0, #CLKCTL_CCGR3]
++ ldr r1, =0xFFF300
++ str r1, [r0, #CLKCTL_CCGR4]
++ ldr r1, =0xF0000C3
++ str r1, [r0, #CLKCTL_CCGR5]
++#ifdef CONFIG_CMD_WEIMNOR
++ ldr r1, =0xFFC
++#else
++ ldr r1, =0x3FC
++#endif
++ str r1, [r0, #CLKCTL_CCGR6]
++.endm
++
++.section ".text.init", "x"
++
++.globl lowlevel_init
++lowlevel_init:
++
++ inv_dcache
++
++ init_l2cc
++
++ init_aips
++
++ init_clock
++
++ mov pc, lr
++
++/* Board level setting value */
++ANATOP_BASE_ADDR_W: .word ANATOP_BASE_ADDR
++CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+diff --git a/board/freescale/wandboard/u-boot.lds b/board/freescale/wandboard/u-boot.lds
+new file mode 100644
+index 0000000..650c8a8
+--- /dev/null
++++ b/board/freescale/wandboard/u-boot.lds
+@@ -0,0 +1,74 @@
++/*
++ * January 2004 - Changed to support H4 device
++ * Copyright (c) 2004 Texas Instruments
++ *
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * (C) Copyright 2011 Freescale Semiconductor, Inc.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ /* WARNING - the following is hand-optimized to fit within */
++ /* the sector layout of our flash chips! XXX FIXME XXX */
++ board/freescale/wandboard/flash_header.o (.text.flasheader)
++ cpu/arm_cortexa8/start.o
++ board/freescale/wandboard/libwandboard.a (.text)
++ lib_arm/libarm.a (.text)
++ net/libnet.a (.text)
++ drivers/mtd/libmtd.a (.text)
++ drivers/mmc/libmmc.a (.text)
++
++ . = DEFINED(env_offset) ? env_offset : .;
++ common/env_embedded.o(.text)
++
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ _end_of_copy = .; /* end_of ROM copy code here */
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff --git a/board/freescale/wandboard/wandboard.c b/board/freescale/wandboard/wandboard.c
+new file mode 100644
+index 0000000..274febb
+--- /dev/null
++++ b/board/freescale/wandboard/wandboard.c
+@@ -0,0 +1,494 @@
++/*
++ * Wandboard u-boot board-file.
++ *
++ * Copyright (C) Wandboard.org
++ * This file is a quick-mock up, to get a kernel booting.
++ *
++ * Maintainer: Tapani Utriainen <tapani at vmail me>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/mx6.h>
++#include <asm/arch/mx6_pins.h>
++#include <asm/arch/mx6dl_pins.h>
++#include <asm/arch/iomux-v3.h>
++#include <asm/errno.h>
++
++#ifdef CONFIG_MXC_FEC
++#include <miiphy.h>
++#endif
++
++#ifdef CONFIG_CMD_MMC
++#include <mmc.h>
++#include <fsl_esdhc.h>
++#endif
++
++#ifdef CONFIG_ARCH_MMU
++#include <asm/mmu.h>
++#include <asm/arch/mmu.h>
++#endif
++
++#ifdef CONFIG_CMD_CLOCK
++#include <asm/clock.h>
++#endif
++
++#ifdef CONFIG_CMD_IMXOTP
++#include <imx_otp.h>
++#endif
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static enum boot_device boot_dev;
++
++static void set_gpio_output_val(unsigned base, unsigned mask, unsigned val)
++{
++ unsigned reg = readl(base + GPIO_DR);
++ if (val & 1)
++ reg |= mask; /* set high */
++ else
++ reg &= ~mask; /* clear low */
++ writel(reg, base + GPIO_DR);
++
++ reg = readl(base + GPIO_GDIR);
++ reg |= mask; /* configure GPIO line as output */
++ writel(reg, base + GPIO_GDIR);
++}
++
++static inline void setup_boot_device(void)
++{
++ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
++ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
++ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
++
++ switch (bt_mem_ctl) {
++ case 0x0:
++ if (bt_mem_type)
++ boot_dev = ONE_NAND_BOOT;
++ else
++ boot_dev = WEIM_NOR_BOOT;
++ break;
++ case 0x2:
++ boot_dev = SATA_BOOT;
++ break;
++ case 0x3:
++ if (bt_mem_type)
++ boot_dev = I2C_BOOT;
++ else
++ boot_dev = SPI_NOR_BOOT;
++ break;
++ case 0x4:
++ case 0x5:
++ boot_dev = SD_BOOT;
++ break;
++ case 0x6:
++ case 0x7:
++ boot_dev = MMC_BOOT;
++ break;
++ case 0x8 ... 0xf:
++ boot_dev = NAND_BOOT;
++ break;
++ default:
++ boot_dev = UNKNOWN_BOOT;
++ break;
++ }
++}
++
++enum boot_device get_boot_device(void) {
++ return boot_dev;
++}
++
++u32 get_board_rev(void) {
++ return fsl_system_rev;
++}
++
++#ifdef CONFIG_ARCH_MMU
++void board_mmu_init(void)
++{
++ unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
++ unsigned long i;
++
++ /*
++ * Set the TTB register
++ */
++ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
++
++ /*
++ * Set the Domain Access Control Register
++ */
++ i = ARM_ACCESS_DACR_DEFAULT;
++ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
++
++ /*
++ * First clear all TT entries - ie Set them to Faulting
++ */
++ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
++ /* Actual Virtual Size Attributes Function */
++ /* Base Base MB cached? buffered? access permissions */
++ /* xxx00000 xxx00000 */
++ X_ARM_MMU_SECTION(0x000, 0x000, 0x001,
++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
++ ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */
++ X_ARM_MMU_SECTION(0x001, 0x001, 0x008,
++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
++ ARM_ACCESS_PERM_RW_RW); /* 8M */
++ X_ARM_MMU_SECTION(0x009, 0x009, 0x001,
++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
++ ARM_ACCESS_PERM_RW_RW); /* IRAM */
++ X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6,
++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
++ ARM_ACCESS_PERM_RW_RW); /* 246M */
++ /* 2 GB memory starting at 0x10000000, only map 1.875 GB */
++ X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
++ ARM_CACHEABLE, ARM_BUFFERABLE,
++ ARM_ACCESS_PERM_RW_RW);
++ /* uncached alias of the same 1.875 GB memory */
++ X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
++ ARM_ACCESS_PERM_RW_RW);
++
++ /* Enable MMU */
++ MMU_ON();
++}
++#endif
++
++int dram_init(void)
++{
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++ return 0;
++}
++
++static void setup_uart(void) {
++ /* UART1 TXD */
++ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT10__UART1_TXD);
++
++ /* UART1 RXD */
++ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT11__UART1_RXD);
++
++}
++
++#ifdef CONFIG_CMD_MMC
++
++/* On this board, only SD3 can support 1.8V signalling
++ * that is required for UHS-I mode of operation.
++ * Last element in struct is used to indicate 1.8V support.
++ */
++struct fsl_esdhc_cfg usdhc_cfg[4] = {
++ {USDHC1_BASE_ADDR, 1, 1, 1, 0},
++ {USDHC2_BASE_ADDR, 1, 1, 1, 0},
++ {USDHC3_BASE_ADDR, 1, 1, 1, 0},
++ {USDHC4_BASE_ADDR, 1, 1, 1, 0},
++};
++
++#ifdef CONFIG_DYNAMIC_MMC_DEVNO
++int get_mmc_env_devno(void)
++{
++ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
++
++ if (SD_BOOT == boot_dev || MMC_BOOT == boot_dev) {
++ /* BOOT_CFG2[3] and BOOT_CFG2[4] */
++ return (soc_sbmr & 0x00001800) >> 11;
++ } else
++ return -1;
++
++}
++#endif
++
++iomux_v3_cfg_t usdhc1_pads[] = {
++ MX6DL_PAD_SD1_CLK__USDHC1_CLK,
++ MX6DL_PAD_SD1_CMD__USDHC1_CMD,
++ MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
++ MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
++ MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
++ MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
++};
++
++iomux_v3_cfg_t usdhc2_pads[] = {
++ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
++ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
++ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
++ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
++ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
++ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
++};
++
++iomux_v3_cfg_t usdhc3_pads[] = {
++ MX6DL_PAD_SD3_CLK__USDHC3_CLK,
++ MX6DL_PAD_SD3_CMD__USDHC3_CMD,
++ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0,
++ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1,
++ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2,
++ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3,
++};
++
++int usdhc_pad_init(bd_t *bis) {
++ s32 status = 0;
++ u32 index = 0;
++
++ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM;
++ ++index) {
++ switch (index) {
++ case 0:
++ mxc_iomux_v3_setup_multiple_pads(usdhc1_pads,
++ ARRAY_SIZE(usdhc1_pads));
++ break;
++ case 1:
++ mxc_iomux_v3_setup_multiple_pads(usdhc2_pads,
++ ARRAY_SIZE(usdhc2_pads));
++ break;
++ case 2:
++ mxc_iomux_v3_setup_multiple_pads(usdhc3_pads,
++ ARRAY_SIZE(usdhc3_pads));
++ break;
++ default:
++ printf("Warning: you configured more USDHC controllers"
++ "(%d) then supported by the board (%d)\n",
++ index+1, CONFIG_SYS_FSL_USDHC_NUM);
++ return status;
++ }
++ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
++ }
++
++ return status;
++}
++
++int board_mmc_init(bd_t *bis) {
++ if (!usdhc_pad_init(bis))
++ return 0;
++ else
++ return -1;
++}
++
++/* For DDR mode operation, provide target delay parameter for each SD port.
++ * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
++ * is dependent on signal layout for that particular port. If the following
++ * CONFIG is not defined, then the default target delay value will be used.
++ */
++#ifdef CONFIG_GET_DDR_TARGET_DELAY
++u32 get_ddr_delay(struct fsl_esdhc_cfg *cfg) { return 0; }
++#endif
++
++#endif
++
++int board_init(void) {
++ mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
++ setup_boot_device();
++ fsl_set_system_rev();
++
++ /* board id for linux */
++ gd->bd->bi_arch_number = 4412;
++
++ /* address of boot parameters */
++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
++
++ setup_uart();
++
++ return 0;
++}
++
++extern int fec_get_mac_addr(unsigned char *mac);
++
++int board_late_init(void) {
++
++ unsigned char mac[6];
++ int i;
++
++ fec_get_mac_addr(mac);
++ printf("Got MAC = ");
++ for (i=0; i<6; i++) {
++ printf("%02X", mac[i]);
++ if (i<5) printf(":"); else printf("\n");
++ }
++
++
++ return 0;
++}
++
++#ifdef CONFIG_MXC_FEC
++static int phy_read(char *devname, unsigned char addr, unsigned char reg,
++ unsigned short *pdata)
++{
++ int ret = miiphy_read(devname, addr, reg, pdata);
++ if (ret)
++ printf("Error reading from %s PHY addr=%02x reg=%02x\n",
++ devname, addr, reg);
++ return ret;
++}
++
++static int phy_write(char *devname, unsigned char addr, unsigned char reg,
++ unsigned short value)
++{
++ int ret = miiphy_write(devname, addr, reg, value);
++ if (ret)
++ printf("Error writing to %s PHY addr=%02x reg=%02x\n", devname,
++ addr, reg);
++ return ret;
++}
++
++int mx6_rgmii_rework(char *devname, int phy_addr)
++{
++ unsigned short val;
++
++ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
++ phy_write(devname, phy_addr, 0xd, 0x7);
++ phy_write(devname, phy_addr, 0xe, 0x8016);
++ phy_write(devname, phy_addr, 0xd, 0x4007);
++ phy_read(devname, phy_addr, 0xe, &val);
++
++ val &= 0xffe3;
++ val |= 0x18;
++ phy_write(devname, phy_addr, 0xe, val);
++
++ /* introduce tx clock delay */
++ phy_write(devname, phy_addr, 0x1d, 0x5);
++ phy_read(devname, phy_addr, 0x1e, &val);
++ val |= 0x0100;
++ phy_write(devname, phy_addr, 0x1e, val);
++
++ return 0;
++}
++
++#if defined CONFIG_MX6Q
++iomux_v3_cfg_t enet_pads[] = {
++ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
++ MX6Q_PAD_ENET_MDC__ENET_MDC,
++ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
++ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
++ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
++ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
++ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
++ MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
++ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
++ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
++ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
++ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
++ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
++ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
++ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
++ MX6Q_PAD_GPIO_0__CCM_CLKO,
++ MX6Q_PAD_GPIO_3__CCM_CLKO2,
++};
++#elif defined CONFIG_MX6DL
++iomux_v3_cfg_t enet_pads[] = {
++ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
++ MX6DL_PAD_ENET_MDC__ENET_MDC,
++ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
++ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
++ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
++ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
++ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
++ MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
++ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
++ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
++ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
++ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
++ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
++ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
++ MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
++ MX6DL_PAD_GPIO_0__CCM_CLKO,
++};
++#endif
++
++void enet_board_init(void)
++{
++ unsigned int reg;
++#if defined CONFIG_MX6Q
++ iomux_v3_cfg_t enet_reset =
++ (_MX6Q_PAD_EIM_D29__GPIO_3_29 &
++ ~MUX_PAD_CTRL_MASK) |
++ MUX_PAD_CTRL(0x48);
++#elif defined CONFIG_MX6DL
++ iomux_v3_cfg_t enet_reset =
++ (MX6DL_PAD_EIM_D29__GPIO_3_29 &
++ ~MUX_PAD_CTRL_MASK) |
++ MUX_PAD_CTRL(0x48);
++#endif
++
++ mxc_iomux_v3_setup_multiple_pads(enet_pads,
++ ARRAY_SIZE(enet_pads));
++ mxc_iomux_v3_setup_pad(enet_reset);
++
++ /* PHY reset: gpio 3-29 */
++ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 29), 0);
++
++ udelay(500);
++
++ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 29), 1);
++
++}
++#endif
++
++int checkboard(void) {
++ printf("Board: %s WandBoard 0x%x [",
++ mx6_chip_name(),
++ fsl_system_rev);
++
++ switch (__REG(SRC_BASE_ADDR + 0x8)) {
++ case 0x0001:
++ printf("POR");
++ break;
++ case 0x0009:
++ printf("RST");
++ break;
++ case 0x0010:
++ case 0x0011:
++ printf("WDOG");
++ break;
++ default:
++ printf("unknown");
++ }
++ printf(" ]\n");
++
++ printf("Boot Device: ");
++ switch (get_boot_device()) {
++ case WEIM_NOR_BOOT:
++ printf("NOR\n");
++ break;
++ case ONE_NAND_BOOT:
++ printf("ONE NAND\n");
++ break;
++ case PATA_BOOT:
++ printf("PATA\n");
++ break;
++ case SATA_BOOT:
++ printf("SATA\n");
++ break;
++ case I2C_BOOT:
++ printf("I2C\n");
++ break;
++ case SPI_NOR_BOOT:
++ printf("SPI NOR\n");
++ break;
++ case SD_BOOT:
++ printf("SD\n");
++ break;
++ case MMC_BOOT:
++ printf("MMC\n");
++ break;
++ case NAND_BOOT:
++ printf("NAND\n");
++ break;
++ case UNKNOWN_BOOT:
++ default:
++ printf("UNKNOWN\n");
++ break;
++ }
++ return 0;
++}
++
+diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
+index 2630bac..e00b122 100644
+--- a/include/asm-arm/mach-types.h
++++ b/include/asm-arm/mach-types.h
+@@ -3258,6 +3258,9 @@ extern unsigned int __machine_arch_type;
+ #define MACH_TYPE_MX6Q_SABRELITE 3769
+ #define MACH_TYPE_MX6Q_ARM2 3837
+ #define MACH_TYPE_MX6Q_SABRESD 3980
++#define MACH_TYPE_EDM_SF_IMX6 4256
++#define MACH_TYPE_EDM_CF_IMX6 4257
++#define MACH_TYPE_WANDBOARD 4412
+ #define MACH_TYPE_MX6SL_ARM2 4091
+ #define MACH_TYPE_MX6SL_EVK 4307
+
+@@ -42213,6 +42216,30 @@ extern unsigned int __machine_arch_type;
+ # define machine_is_mx6sl_evk() (0)
+ #endif
+
++#ifdef CONFIG_MACH_EDM_SF_IMX6
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_EDM_SF_IMX6
++# endif
++# define machine_is_edm_sf_imx6() (machine_arch_type == MACH_TYPE_EDM_SF_IMX6)
++#else
++# define machine_is_edm_sf_imx6() (0)
++#endif
++
++#ifdef CONFIG_MACH_EDM_CF_IMX6
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_EDM_CF_IMX6
++# endif
++# define machine_is_edm_cf_imx6() (machine_arch_type == MACH_TYPE_EDM_CF_IMX6)
++#else
++# define machine_is_edm_cf_imx6() (0)
++#endif
++
+ /*
+ * These have not yet been registered
+ */
+diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
+new file mode 100644
+index 0000000..e872c6b
+--- /dev/null
++++ b/include/configs/wandboard.h
+@@ -0,0 +1,273 @@
++/*
++ * Configuration settings for the Wandboard.
++ *
++ * Copyright (C) 2013 Wandboard.org
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#include <asm/arch/mx6.h>
++
++ /* High Level Configuration Options */
++#define CONFIG_ARMV7
++#define CONFIG_MXC
++#define CONFIG_MX6DL
++#define CONFIG_WANDBOARD
++
++/* Comment this line when compiling for the Wandboard Solo */
++#define CONFIG_WANDBOARD_DUAL
++
++/* Setup memory depending if we have 512M/1G. */
++#ifdef CONFIG_WANDBOARD_DUAL
++#define CONFIG_MX6DL_DDR3
++#define CONFIG_DDR_64BIT
++#else
++#define CONFIG_MX6SOLO_DDR3
++#define CONFIG_DDR_32BIT
++#endif
++
++#define CONFIG_FLASH_HEADER
++#define CONFIG_FLASH_HEADER_OFFSET 0x400
++#define CONFIG_MX6_CLK32 32768
++
++#define CONFIG_SKIP_RELOCATE_UBOOT
++
++#define CONFIG_ARCH_CPU_INIT
++#undef CONFIG_ARCH_MMU /* disable MMU first */
++#define CONFIG_L2_OFF /* disable L2 cache first*/
++
++#define CONFIG_MX6_HCLK_FREQ 24000000
++
++#define CONFIG_DISPLAY_CPUINFO
++#define CONFIG_DISPLAY_BOARDINFO
++
++#define CONFIG_SYS_64BIT_VSPRINTF
++
++#define BOARD_LATE_INIT
++
++#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
++#define CONFIG_REVISION_TAG
++#define CONFIG_SETUP_MEMORY_TAGS
++
++/*
++ * Size of malloc() pool
++ */
++#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
++/* size in bytes reserved for initial data */
++#define CONFIG_SYS_GBL_DATA_SIZE 128
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_MXC_UART
++#define CONFIG_MXC_GPIO
++#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR
++
++/* allow to overwrite serial and ethaddr */
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_CONS_INDEX 1
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
++
++/***********************************************************
++ * Command definition
++ ***********************************************************/
++
++#define CONFIG_CMD_BDI /* bdinfo */
++#define CONFIG_CMD_CONSOLE /* coninfo */
++#define CONFIG_CMD_ECHO /* echo arguments */
++#define CONFIG_CMD_IMI /* iminfo */
++#define CONFIG_CMD_ITEST /* Integer (and string) test */
++#define CONFIG_CMD_LOADB /* loadb */
++#define CONFIG_CMD_LOADS /* loads */
++#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
++#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
++#define CONFIG_CMD_RUN /* run command in env variable */
++#define CONFIG_CMD_SAVEENV /* saveenv */
++#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
++#define CONFIG_CMD_SOURCE /* "source" command support */
++#define CONFIG_CMD_XIMG /* Load part of Multi Image */
++
++#define CONFIG_PARTITIONS 1
++
++#define CONFIG_SYS_NO_FLASH
++#define CONFIG_CMD_BOOTD /* bootd */
++
++#define CONFIG_CMD_IMXOTP
++#define CONFIG_CMD_NET
++#define CONFIG_NET_MULTI 1
++#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
++#define CONFIG_FEC0_PINMUX -1
++#define CONFIG_FEC0_MIIBASE -1
++#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
++#define CONFIG_MXC_FEC
++#define CONFIG_FEC0_PHY_ADDR 0xFF
++#define CONFIG_DISCOVER_PHY
++#define CONFIG_ETH_PRIME
++#define CONFIG_RMII
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_PING
++#define CONFIG_IPADDR 192.168.1.103
++#define CONFIG_SERVERIP 192.168.1.101
++#define CONFIG_NETMASK 255.255.255.0
++
++/* Enable below configure when supporting nand */
++#define CONFIG_CMD_MMC
++#define CONFIG_CMD_ENV
++#define CONFIG_CMD_REGUL
++
++#define CONFIG_CMD_CLOCK
++#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
++
++#undef CONFIG_CMD_IMLS
++
++#define CONFIG_CMD_IMX_DOWNLOAD_MODE
++
++#define CONFIG_BOOTDELAY 1
++
++#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
++#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "netdev=eth0\0" \
++ "uboot=u-boot.bin\0" \
++ "kernel=uImage\0" \
++ "bootargs=console=ttymxc0,115200\0" \
++ "videoargs=video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24\0" \
++ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
++ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
++ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
++ "video=${videoargs}\0" \
++ "bootcmd_net=dhcp; run bootargs_base bootargs_nfs;bootm\0" \
++ "bootargs_mmc=setenv bootargs ${bootargs} " \
++ "root=/dev/mmcblk0p2 rootwait rw " \
++ "video=${videoargs}\0" \
++ "bootcmd_mmc=run bootargs_base bootargs_mmc;mmc dev 2;" \
++ "fatload mmc 2 ${loadaddr} ${kernel};bootm\0" \
++ "bootcmd=run bootcmd_mmc\0" \
++ "upgradeu=for disk in 0 1 ; do mmc dev ${disk} ;" \
++ "for fs in fat ext2 ; do " \
++ "${fs}load mmc ${disk}:1 10008000 " \
++ "/6q_upgrade && " \
++ "source 10008000 ; " \
++ "done ; " \
++ "done\0" \
++ "bootfile=_BOOT_FILE_PATH_IN_TFTP_\0" \
++ "nfsroot=_ROOTFS_PATH_IN_NFS_\0"
++
++#define CONFIG_ARP_TIMEOUT 200UL
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CONFIG_SYS_LONGHELP /* undef to save memory */
++#define CONFIG_SYS_PROMPT "WANDBOARD U-Boot > "
++#define CONFIG_AUTO_COMPLETE
++#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
++/* Print Buffer Size */
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
++#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
++
++#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
++#define CONFIG_SYS_MEMTEST_END 0x10010000
++
++#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
++
++#define CONFIG_SYS_HZ 1000
++
++#define CONFIG_CMDLINE_EDITING
++
++/*
++ * OCOTP Configs
++ */
++#ifdef CONFIG_CMD_IMXOTP
++ #define CONFIG_IMX_OTP
++ #define IMX_OTP_BASE OCOTP_BASE_ADDR
++ #define IMX_OTP_ADDR_MAX 0x7F
++ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
++#endif
++
++/* Regulator Configs */
++#ifdef CONFIG_CMD_REGUL
++ #define CONFIG_ANATOP_REGULATOR
++ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
++ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
++#endif
++
++/*
++ * MMC Configs
++ */
++#ifdef CONFIG_CMD_MMC
++ #define CONFIG_MMC
++ #define CONFIG_GENERIC_MMC
++ #define CONFIG_IMX_MMC
++ #define CONFIG_SYS_FSL_USDHC_NUM 3
++ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
++ #define CONFIG_SYS_MMC_ENV_DEV 2
++ #define CONFIG_DOS_PARTITION 1
++ #define CONFIG_CMD_FAT 1
++ #define CONFIG_CMD_EXT2 1
++
++ /* detect whether SD1 or 3 is boot device */
++ #define CONFIG_DYNAMIC_MMC_DEVNO
++
++ /* No 8 bit MMC */
++ #define CONFIG_MMC_8BIT_PORTS 0x0
++#endif
++
++/*-----------------------------------------------------------------------
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
++
++/*-----------------------------------------------------------------------
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1
++#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
++#ifdef CONFIG_DDR_64BIT
++ #define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
++#else
++ #define PHYS_SDRAM_1_SIZE (512u * 1024 * 1024)
++#endif
++#define iomem_valid_addr(addr, size) \
++ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
++
++/*-----------------------------------------------------------------------
++ * FLASH and environment organization
++ */
++
++/* No NAND */
++#define CONFIG_SYS_NO_FLASH
++
++/* Monitor at beginning of flash */
++#define CONFIG_FSL_ENV_IN_MMC
++
++#define CONFIG_ENV_SECT_SIZE (8 * 1024)
++#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
++#define CONFIG_ENV_IS_IN_MMC 1
++#define CONFIG_ENV_OFFSET (768 * 1024)
++
++#endif /* __CONFIG_H */
+--
+1.7.9.5
+
diff --git a/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend b/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
new file mode 100644
index 0000000..0a50ccf
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
@@ -0,0 +1,8 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}"
+
+PRINC := "${@int(PRINC) + 1}"
+
+# Wandboard-specific patches
+SRC_URI_append_mx6= " \
+ file://Initial-support-for-Wandboard-Dual.patch \
+"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [meta-fsl-arm-extra][PATCH 3/3] Add conf support for Wandboard Dual
2013-02-23 20:29 [meta-fsl-arm-extra][PATCH 1/3] Add kernel support for Wandboard Dual John Weber
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 2/3] Add U-boot " John Weber
@ 2013-02-23 20:29 ` John Weber
2013-02-26 19:25 ` Otavio Salvador
2013-02-26 19:24 ` [meta-fsl-arm-extra][PATCH 1/3] Add kernel " Otavio Salvador
2 siblings, 1 reply; 8+ messages in thread
From: John Weber @ 2013-02-23 20:29 UTC (permalink / raw)
To: meta-freescale
The patch adds machine conf support for Wandboar Dual.
It is not known but is possible that it will work with
Wandboard Solo.
In the local.conf, set the MACHINE ??= 'wandboard-dual'
to use this configuration.
Signed-off-by: John Weber <rjohnweber@gmail.com>
---
Upstream-Status: Pending
conf/machine/wandboard-dual.conf | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 conf/machine/wandboard-dual.conf
diff --git a/conf/machine/wandboard-dual.conf b/conf/machine/wandboard-dual.conf
new file mode 100644
index 0000000..f827be7
--- /dev/null
+++ b/conf/machine/wandboard-dual.conf
@@ -0,0 +1,20 @@
+#@TYPE: Machine
+#@NAME: i.MX6 Wandboard Dual
+#@DESCRIPTION: Machine configuration for i.MX6 Wandboard Dual
+
+include conf/machine/include/imx-base.inc
+include conf/machine/include/tune-cortexa9.inc
+
+SOC_FAMILY = "mx6dl:mx6"
+
+KERNEL_DEVICETREE = "${S}/arch/arm/boot/dts/imx6dl-wandboard.dts"
+
+PREFERRED_PROVIDER_u-boot = "u-boot-imx"
+
+UBOOT_MACHINE = "wandboard_config"
+UBOOT_SUFFIX = "bin"
+UBOOT_PADDING = "2"
+
+SERIAL_CONSOLE = "115200 ttymxc0"
+
+MACHINE_FEATURES += " pci wifi bluetooth"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [meta-fsl-arm-extra][PATCH 1/3] Add kernel support for Wandboard Dual
2013-02-23 20:29 [meta-fsl-arm-extra][PATCH 1/3] Add kernel support for Wandboard Dual John Weber
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 2/3] Add U-boot " John Weber
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 3/3] Add conf " John Weber
@ 2013-02-26 19:24 ` Otavio Salvador
2 siblings, 0 replies; 8+ messages in thread
From: Otavio Salvador @ 2013-02-26 19:24 UTC (permalink / raw)
To: John Weber; +Cc: meta-freescale
On Sat, Feb 23, 2013 at 5:29 PM, John Weber <rjohnweber@gmail.com> wrote:
> This patch adds kernel support for Wandboard Dual. It is meant
> to be over the 1.1.0 SDK kernel from Freescale.
>
> Signed-off-by: John Weber <rjohnweber@gmail.com>
Please change short log to:
linux (3.0.35): Add Wandboard Dual support
> Upstream-Status: Pending
This doesn't bellongs here but in the patch file itself... more bellow.
> .../Initial-kernel-support-for-Wandboard.patch | 3195 ++++++++++++++++++++
> .../linux-imx-3.0.35/wandboard-dual/defconfig | 2762 +++++++++++++++++
> recipes-kernel/linux/linux-imx_3.0.35.bbappend | 8 +
> 3 files changed, 5965 insertions(+)
> create mode 100644 recipes-kernel/linux/linux-imx-3.0.35/Initial-kernel-support-for-Wandboard.patch
Please move it inside wandboard-dual directory; if it will be shared
between both wandboard please move it inside wandboard and do the
override append (as did in olinuxino board).
> create mode 100644 recipes-kernel/linux/linux-imx-3.0.35/wandboard-dual/defconfig
> create mode 100644 recipes-kernel/linux/linux-imx_3.0.35.bbappend
>
> diff --git a/recipes-kernel/linux/linux-imx-3.0.35/Initial-kernel-support-for-Wandboard.patch b/recipes-kernel/linux/linux-imx-3.0.35/Initial-kernel-support-for-Wandboard.patch
> new file mode 100644
> index 0000000..5dfbc96
> --- /dev/null
> +++ b/recipes-kernel/linux/linux-imx-3.0.35/Initial-kernel-support-for-Wandboard.patch
> @@ -0,0 +1,3195 @@
> +From f82dfc918b80905559bc1b97877a88bd85ede40f Mon Sep 17 00:00:00 2001
> +From: John Weber <rjohnweber@gmail.com>
> +Date: Fri, 22 Feb 2013 01:12:20 -0600
> +Subject: [PATCH] Initial kernel support Wandboard
> +
> + This patch adds support for Wandboard. It depends on
> + the FSL SDK 1.1.0 kernel (3.0.35). It has been minimally
> + tested on a Wandboard-Dual, rev A0. The serial port and
> + module SD card were found to work. Testers welcome!
> +
> + Most of this was lifted and ported from the Wandboard SDK
> + released Feb 2, 2013. That original work was done by Tapani.
> +
Please add:
Upstream-Status: Pending
and also add your signed-off-by as you did the patch porting.
> +diff --git a/arch/arm/configs/wandboard_defconfig b/arch/arm/configs/wandboard_defconfig
> +new file mode 100644
> +index 0000000..da75924
> +--- /dev/null
> ++++ b/arch/arm/configs/wandboard_defconfig
> +@@ -0,0 +1,1976 @@
> ++#
> ++# Automatically generated make config: don't edit
> ++# Linux/arm 3.0.35 Kernel Configuration
> ++#
> ++CONFIG_ARM=y
> ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> ++CONFIG_HAVE_SCHED_CLOCK=y
> ++CONFIG_GENERIC_GPIO=y
> ++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
> ++CONFIG_GENERIC_CLOCKEVENTS=y
> ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
> ++CONFIG_KTIME_SCALAR=y
> ++CONFIG_HAVE_PROC_CPU=y
> ++CONFIG_STACKTRACE_SUPPORT=y
> ++CONFIG_LOCKDEP_SUPPORT=y
> ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> ++CONFIG_HARDIRQS_SW_RESEND=y
> ++CONFIG_GENERIC_IRQ_PROBE=y
> ++CONFIG_GENERIC_LOCKBREAK=y
> ++CONFIG_RWSEM_GENERIC_SPINLOCK=y
> ++CONFIG_ARCH_HAS_CPUFREQ=y
> ++CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
> ++CONFIG_GENERIC_HWEIGHT=y
> ++CONFIG_GENERIC_CALIBRATE_DELAY=y
> ++CONFIG_NEED_DMA_MAP_STATE=y
> ++CONFIG_FIQ=y
> ++CONFIG_VECTORS_BASE=0xffff0000
> ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set
> ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> ++CONFIG_HAVE_IRQ_WORK=y
> ++
> ++#
> ++# General setup
> ++#
> ++CONFIG_EXPERIMENTAL=y
> ++CONFIG_INIT_ENV_ARG_LIMIT=32
> ++CONFIG_CROSS_COMPILE=""
> ++CONFIG_LOCALVERSION=""
> ++# CONFIG_LOCALVERSION_AUTO is not set
> ++CONFIG_HAVE_KERNEL_GZIP=y
> ++CONFIG_HAVE_KERNEL_LZMA=y
> ++CONFIG_HAVE_KERNEL_LZO=y
> ++# CONFIG_KERNEL_GZIP is not set
> ++CONFIG_KERNEL_LZMA=y
> ++# CONFIG_KERNEL_LZO is not set
> ++CONFIG_DEFAULT_HOSTNAME="wandboard"
> ++# CONFIG_SWAP is not set
> ++CONFIG_SYSVIPC=y
> ++CONFIG_SYSVIPC_SYSCTL=y
> ++# CONFIG_POSIX_MQUEUE is not set
> ++# CONFIG_BSD_PROCESS_ACCT is not set
> ++# CONFIG_FHANDLE is not set
> ++# CONFIG_TASKSTATS is not set
> ++# CONFIG_AUDIT is not set
> ++CONFIG_HAVE_GENERIC_HARDIRQS=y
> ++
> ++#
> ++# IRQ subsystem
> ++#
> ++CONFIG_GENERIC_HARDIRQS=y
> ++CONFIG_HAVE_SPARSE_IRQ=y
> ++CONFIG_GENERIC_IRQ_SHOW=y
> ++# CONFIG_SPARSE_IRQ is not set
> ++
> ++#
> ++# RCU Subsystem
> ++#
> ++CONFIG_TREE_PREEMPT_RCU=y
> ++CONFIG_PREEMPT_RCU=y
> ++# CONFIG_RCU_TRACE is not set
> ++CONFIG_RCU_FANOUT=32
> ++# CONFIG_RCU_FANOUT_EXACT is not set
> ++# CONFIG_TREE_RCU_TRACE is not set
> ++# CONFIG_RCU_BOOST is not set
> ++# CONFIG_IKCONFIG is not set
> ++CONFIG_LOG_BUF_SHIFT=14
> ++# CONFIG_CGROUPS is not set
> ++# CONFIG_NAMESPACES is not set
> ++# CONFIG_SCHED_AUTOGROUP is not set
> ++# CONFIG_SYSFS_DEPRECATED is not set
> ++# CONFIG_RELAY is not set
> ++# CONFIG_BLK_DEV_INITRD is not set
> ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> ++CONFIG_SYSCTL=y
> ++CONFIG_ANON_INODES=y
> ++CONFIG_PANIC_TIMEOUT=0
> ++CONFIG_EXPERT=y
> ++CONFIG_UID16=y
> ++CONFIG_SYSCTL_SYSCALL=y
> ++CONFIG_KALLSYMS=y
> ++CONFIG_HOTPLUG=y
> ++CONFIG_PRINTK=y
> ++# CONFIG_BUG is not set
> ++# CONFIG_ELF_CORE is not set
> ++CONFIG_BASE_FULL=y
> ++CONFIG_FUTEX=y
> ++CONFIG_EPOLL=y
> ++CONFIG_SIGNALFD=y
> ++CONFIG_TIMERFD=y
> ++CONFIG_EVENTFD=y
> ++# CONFIG_SHMEM is not set
> ++# CONFIG_AIO is not set
> ++CONFIG_EMBEDDED=y
> ++CONFIG_HAVE_PERF_EVENTS=y
> ++CONFIG_PERF_USE_VMALLOC=y
> ++
> ++#
> ++# Kernel Performance Events And Counters
> ++#
> ++# CONFIG_PERF_EVENTS is not set
> ++# CONFIG_PERF_COUNTERS is not set
> ++# CONFIG_VM_EVENT_COUNTERS is not set
> ++# CONFIG_SLUB_DEBUG is not set
> ++CONFIG_COMPAT_BRK=y
> ++# CONFIG_SLAB is not set
> ++CONFIG_SLUB=y
> ++# CONFIG_SLOB is not set
> ++# CONFIG_PROFILING is not set
> ++CONFIG_HAVE_OPROFILE=y
> ++# CONFIG_KPROBES is not set
> ++CONFIG_HAVE_KPROBES=y
> ++CONFIG_HAVE_KRETPROBES=y
> ++CONFIG_USE_GENERIC_SMP_HELPERS=y
> ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
> ++CONFIG_HAVE_CLK=y
> ++CONFIG_HAVE_DMA_API_DEBUG=y
> ++
> ++#
> ++# GCOV-based kernel profiling
> ++#
> ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> ++CONFIG_RT_MUTEXES=y
> ++CONFIG_BASE_SMALL=0
> ++CONFIG_MODULES=y
> ++CONFIG_MODULE_FORCE_LOAD=y
> ++CONFIG_MODULE_UNLOAD=y
> ++# CONFIG_MODULE_FORCE_UNLOAD is not set
> ++CONFIG_MODVERSIONS=y
> ++# CONFIG_MODULE_SRCVERSION_ALL is not set
> ++CONFIG_STOP_MACHINE=y
> ++CONFIG_BLOCK=y
> ++# CONFIG_LBDAF is not set
> ++# CONFIG_BLK_DEV_BSG is not set
> ++# CONFIG_BLK_DEV_INTEGRITY is not set
> ++
> ++#
> ++# IO Schedulers
> ++#
> ++CONFIG_IOSCHED_NOOP=y
> ++# CONFIG_IOSCHED_DEADLINE is not set
> ++CONFIG_IOSCHED_CFQ=y
> ++CONFIG_DEFAULT_CFQ=y
> ++# CONFIG_DEFAULT_NOOP is not set
> ++CONFIG_DEFAULT_IOSCHED="cfq"
> ++# CONFIG_INLINE_SPIN_TRYLOCK is not set
> ++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
> ++# CONFIG_INLINE_SPIN_LOCK is not set
> ++# CONFIG_INLINE_SPIN_LOCK_BH is not set
> ++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
> ++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
> ++# CONFIG_INLINE_SPIN_UNLOCK is not set
> ++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
> ++# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
> ++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
> ++# CONFIG_INLINE_READ_TRYLOCK is not set
> ++# CONFIG_INLINE_READ_LOCK is not set
> ++# CONFIG_INLINE_READ_LOCK_BH is not set
> ++# CONFIG_INLINE_READ_LOCK_IRQ is not set
> ++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
> ++# CONFIG_INLINE_READ_UNLOCK is not set
> ++# CONFIG_INLINE_READ_UNLOCK_BH is not set
> ++# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
> ++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
> ++# CONFIG_INLINE_WRITE_TRYLOCK is not set
> ++# CONFIG_INLINE_WRITE_LOCK is not set
> ++# CONFIG_INLINE_WRITE_LOCK_BH is not set
> ++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
> ++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
> ++# CONFIG_INLINE_WRITE_UNLOCK is not set
> ++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
> ++# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
> ++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
> ++CONFIG_MUTEX_SPIN_ON_OWNER=y
> ++CONFIG_FREEZER=y
> ++
> ++#
> ++# System Type
> ++#
> ++CONFIG_MMU=y
> ++# CONFIG_ARCH_INTEGRATOR is not set
> ++# CONFIG_ARCH_REALVIEW is not set
> ++# CONFIG_ARCH_VERSATILE is not set
> ++# CONFIG_ARCH_VEXPRESS is not set
> ++# CONFIG_ARCH_AT91 is not set
> ++# CONFIG_ARCH_BCMRING is not set
> ++# CONFIG_ARCH_CLPS711X is not set
> ++# CONFIG_ARCH_CNS3XXX is not set
> ++# CONFIG_ARCH_GEMINI is not set
> ++# CONFIG_ARCH_EBSA110 is not set
> ++# CONFIG_ARCH_EP93XX is not set
> ++# CONFIG_ARCH_FOOTBRIDGE is not set
> ++CONFIG_ARCH_MXC=y
> ++# CONFIG_ARCH_MXS is not set
> ++# CONFIG_ARCH_NETX is not set
> ++# CONFIG_ARCH_H720X is not set
> ++# CONFIG_ARCH_IOP13XX is not set
> ++# CONFIG_ARCH_IOP32X is not set
> ++# CONFIG_ARCH_IOP33X is not set
> ++# CONFIG_ARCH_IXP23XX is not set
> ++# CONFIG_ARCH_IXP2000 is not set
> ++# CONFIG_ARCH_IXP4XX is not set
> ++# CONFIG_ARCH_DOVE is not set
> ++# CONFIG_ARCH_KIRKWOOD is not set
> ++# CONFIG_ARCH_LOKI is not set
> ++# CONFIG_ARCH_LPC32XX is not set
> ++# CONFIG_ARCH_MV78XX0 is not set
> ++# CONFIG_ARCH_ORION5X is not set
> ++# CONFIG_ARCH_MMP is not set
> ++# CONFIG_ARCH_KS8695 is not set
> ++# CONFIG_ARCH_W90X900 is not set
> ++# CONFIG_ARCH_NUC93X is not set
> ++# CONFIG_ARCH_TEGRA is not set
> ++# CONFIG_ARCH_PNX4008 is not set
> ++# CONFIG_ARCH_PXA is not set
> ++# CONFIG_ARCH_MSM is not set
> ++# CONFIG_ARCH_SHMOBILE is not set
> ++# CONFIG_ARCH_RPC is not set
> ++# CONFIG_ARCH_SA1100 is not set
> ++# CONFIG_ARCH_S3C2410 is not set
> ++# CONFIG_ARCH_S3C64XX is not set
> ++# CONFIG_ARCH_S5P64X0 is not set
> ++# CONFIG_ARCH_S5PC100 is not set
> ++# CONFIG_ARCH_S5PV210 is not set
> ++# CONFIG_ARCH_EXYNOS4 is not set
> ++# CONFIG_ARCH_SHARK is not set
> ++# CONFIG_ARCH_TCC_926 is not set
> ++# CONFIG_ARCH_U300 is not set
> ++# CONFIG_ARCH_U8500 is not set
> ++# CONFIG_ARCH_NOMADIK is not set
> ++# CONFIG_ARCH_DAVINCI is not set
> ++# CONFIG_ARCH_OMAP is not set
> ++# CONFIG_PLAT_SPEAR is not set
> ++# CONFIG_ARCH_VT8500 is not set
> ++# CONFIG_GPIO_PCA953X is not set
> ++CONFIG_IMX_HAVE_PLATFORM_DMA=y
> ++CONFIG_IMX_HAVE_PLATFORM_FEC=y
> ++CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
> ++CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
> ++CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
> ++CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
> ++CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
> ++CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
> ++CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
> ++CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
> ++
> ++#
> ++# Freescale MXC Implementations
> ++#
> ++# CONFIG_ARCH_MX1 is not set
> ++# CONFIG_ARCH_MX2 is not set
> ++# CONFIG_ARCH_MX25 is not set
> ++# CONFIG_ARCH_MX3 is not set
> ++# CONFIG_ARCH_MX503 is not set
> ++# CONFIG_ARCH_MX51 is not set
> ++CONFIG_ARCH_MX6=y
> ++CONFIG_FORCE_MAX_ZONEORDER=14
> ++CONFIG_ARCH_MX6Q=y
> ++CONFIG_SOC_IMX6Q=y
> ++# CONFIG_MACH_MX6Q_ARM2 is not set
> ++# CONFIG_MACH_MX6SL_ARM2 is not set
> ++# CONFIG_MACH_MX6SL_EVK is not set
> ++# CONFIG_MACH_MX6Q_SABRELITE is not set
> ++# CONFIG_MACH_MX6Q_SABRESD is not set
> ++# CONFIG_MACH_MX6Q_SABREAUTO is not set
> ++CONFIG_MACH_WANDBOARD=y
> ++CONFIG_WANDBOARD_BASE=y
> ++
> ++#
> ++# MX6 Options:
> ++#
> ++# CONFIG_IMX_PCIE is not set
> ++CONFIG_USB_EHCI_ARC_H1=y
> ++CONFIG_USB_FSL_ARC_OTG=y
> ++# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS is not set
> ++# CONFIG_ISP1504_MXC is not set
> ++# CONFIG_MXC_IRQ_PRIOR is not set
> ++# CONFIG_MXC_PWM is not set
> ++# CONFIG_MXC_DEBUG_BOARD is not set
> ++# CONFIG_MXC_REBOOT_MFGMODE is not set
> ++# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
> ++CONFIG_ARCH_MXC_IOMUX_V3=y
> ++CONFIG_ARCH_MXC_AUDMUX_V2=y
> ++CONFIG_IRAM_ALLOC=y
> ++CONFIG_DMA_ZONE_SIZE=184
> ++
> ++#
> ++# System MMU
> ++#
> ++
> ++#
> ++# Processor Type
> ++#
> ++CONFIG_CPU_V7=y
> ++CONFIG_CPU_32v6K=y
> ++CONFIG_CPU_32v7=y
> ++CONFIG_CPU_ABRT_EV7=y
> ++CONFIG_CPU_PABRT_V7=y
> ++CONFIG_CPU_CACHE_V7=y
> ++CONFIG_CPU_CACHE_VIPT=y
> ++CONFIG_CPU_COPY_V6=y
> ++CONFIG_CPU_TLB_V7=y
> ++CONFIG_CPU_HAS_ASID=y
> ++CONFIG_CPU_CP15=y
> ++CONFIG_CPU_CP15_MMU=y
> ++
> ++#
> ++# Processor Features
> ++#
> ++# CONFIG_ARM_THUMB is not set
> ++# CONFIG_ARM_THUMBEE is not set
> ++# CONFIG_SWP_EMULATE is not set
> ++# CONFIG_CPU_ICACHE_DISABLE is not set
> ++# CONFIG_CPU_DCACHE_DISABLE is not set
> ++# CONFIG_CPU_BPREDICT_DISABLE is not set
> ++CONFIG_OUTER_CACHE=y
> ++CONFIG_OUTER_CACHE_SYNC=y
> ++CONFIG_CACHE_L2X0=y
> ++CONFIG_CACHE_PL310=y
> ++CONFIG_ARM_L1_CACHE_SHIFT=5
> ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
> ++CONFIG_CPU_HAS_PMU=y
> ++# CONFIG_ARM_ERRATA_430973 is not set
> ++# CONFIG_ARM_ERRATA_458693 is not set
> ++# CONFIG_ARM_ERRATA_460075 is not set
> ++# CONFIG_ARM_ERRATA_742230 is not set
> ++# CONFIG_ARM_ERRATA_742231 is not set
> ++# CONFIG_PL310_ERRATA_588369 is not set
> ++# CONFIG_ARM_ERRATA_720789 is not set
> ++# CONFIG_PL310_ERRATA_727915 is not set
> ++CONFIG_ARM_ERRATA_743622=y
> ++# CONFIG_ARM_ERRATA_751472 is not set
> ++CONFIG_ARM_ERRATA_753970=y
> ++# CONFIG_ARM_ERRATA_754322 is not set
> ++# CONFIG_ARM_ERRATA_754327 is not set
> ++CONFIG_ARM_GIC=y
> ++# CONFIG_FIQ_DEBUGGER is not set
> ++
> ++#
> ++# Bus support
> ++#
> ++CONFIG_ARM_AMBA=y
> ++# CONFIG_PCI_SYSCALL is not set
> ++# CONFIG_ARCH_SUPPORTS_MSI is not set
> ++# CONFIG_PCCARD is not set
> ++# CONFIG_ARM_ERRATA_764369 is not set
> ++# CONFIG_PL310_ERRATA_769419 is not set
> ++
> ++#
> ++# Kernel Features
> ++#
> ++CONFIG_TICK_ONESHOT=y
> ++CONFIG_NO_HZ=y
> ++CONFIG_HIGH_RES_TIMERS=y
> ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> ++CONFIG_SMP=y
> ++CONFIG_SMP_ON_UP=y
> ++CONFIG_HAVE_ARM_SCU=y
> ++CONFIG_HAVE_ARM_TWD=y
> ++# CONFIG_VMSPLIT_3G is not set
> ++CONFIG_VMSPLIT_2G=y
> ++# CONFIG_VMSPLIT_1G is not set
> ++CONFIG_PAGE_OFFSET=0x80000000
> ++CONFIG_NR_CPUS=4
> ++CONFIG_HOTPLUG_CPU=y
> ++CONFIG_LOCAL_TIMERS=y
> ++# CONFIG_PREEMPT_NONE is not set
> ++# CONFIG_PREEMPT_VOLUNTARY is not set
> ++CONFIG_PREEMPT=y
> ++CONFIG_HZ=100
> ++# CONFIG_THUMB2_KERNEL is not set
> ++CONFIG_AEABI=y
> ++# CONFIG_OABI_COMPAT is not set
> ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> ++CONFIG_HAVE_ARCH_PFN_VALID=y
> ++CONFIG_HIGHMEM=y
> ++# CONFIG_HIGHPTE is not set
> ++CONFIG_SELECT_MEMORY_MODEL=y
> ++CONFIG_FLATMEM_MANUAL=y
> ++CONFIG_FLATMEM=y
> ++CONFIG_FLAT_NODE_MEM_MAP=y
> ++CONFIG_HAVE_MEMBLOCK=y
> ++CONFIG_PAGEFLAGS_EXTENDED=y
> ++CONFIG_SPLIT_PTLOCK_CPUS=4
> ++CONFIG_COMPACTION=y
> ++CONFIG_MIGRATION=y
> ++# CONFIG_PHYS_ADDR_T_64BIT is not set
> ++CONFIG_ZONE_DMA_FLAG=0
> ++CONFIG_BOUNCE=y
> ++CONFIG_VIRT_TO_BUS=y
> ++# CONFIG_KSM is not set
> ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
> ++# CONFIG_CLEANCACHE is not set
> ++CONFIG_ALIGNMENT_TRAP=y
> ++# CONFIG_UACCESS_WITH_MEMCPY is not set
> ++# CONFIG_SECCOMP is not set
> ++# CONFIG_CC_STACKPROTECTOR is not set
> ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
> ++# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set
> ++
> ++#
> ++# Boot options
> ++#
> ++# CONFIG_USE_OF is not set
> ++CONFIG_ZBOOT_ROM_TEXT=0x0
> ++CONFIG_ZBOOT_ROM_BSS=0x0
> ++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
> ++CONFIG_CMDLINE_FROM_BOOTLOADER=y
> ++# CONFIG_CMDLINE_EXTEND is not set
> ++# CONFIG_CMDLINE_FORCE is not set
> ++# CONFIG_XIP_KERNEL is not set
> ++# CONFIG_KEXEC is not set
> ++# CONFIG_CRASH_DUMP is not set
> ++# CONFIG_AUTO_ZRELADDR is not set
> ++
> ++#
> ++# CPU Power Management
> ++#
> ++
> ++#
> ++# CPU Frequency scaling
> ++#
> ++CONFIG_CPU_FREQ=y
> ++CONFIG_CPU_FREQ_TABLE=y
> ++CONFIG_CPU_FREQ_STAT=y
> ++# CONFIG_CPU_FREQ_STAT_DETAILS is not set
> ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
> ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
> ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
> ++# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
> ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> ++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
> ++# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
> ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> ++# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set
> ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
> ++CONFIG_CPU_FREQ_IMX=y
> ++CONFIG_CPU_IDLE=y
> ++CONFIG_CPU_IDLE_GOV_LADDER=y
> ++CONFIG_CPU_IDLE_GOV_MENU=y
> ++
> ++#
> ++# Floating point emulation
> ++#
> ++
> ++#
> ++# At least one emulation must be selected
> ++#
> ++CONFIG_VFP=y
> ++CONFIG_VFPv3=y
> ++CONFIG_NEON=y
> ++
> ++#
> ++# Userspace binary formats
> ++#
> ++CONFIG_BINFMT_ELF=y
> ++CONFIG_HAVE_AOUT=y
> ++# CONFIG_BINFMT_AOUT is not set
> ++# CONFIG_BINFMT_MISC is not set
> ++
> ++#
> ++# Power management options
> ++#
> ++CONFIG_SUSPEND=y
> ++CONFIG_SUSPEND_FREEZER=y
> ++CONFIG_PM_SLEEP=y
> ++CONFIG_PM_SLEEP_SMP=y
> ++CONFIG_PM_RUNTIME=y
> ++CONFIG_PM=y
> ++# CONFIG_PM_DEBUG is not set
> ++# CONFIG_APM_EMULATION is not set
> ++CONFIG_PM_RUNTIME_CLK=y
> ++# CONFIG_SUSPEND_TIME is not set
> ++CONFIG_ARCH_SUSPEND_POSSIBLE=y
> ++CONFIG_NET=y
> ++
> ++#
> ++# Networking options
> ++#
> ++CONFIG_PACKET=y
> ++CONFIG_UNIX=y
> ++# CONFIG_NET_KEY is not set
> ++CONFIG_INET=y
> ++CONFIG_IP_MULTICAST=y
> ++# CONFIG_IP_ADVANCED_ROUTER is not set
> ++# CONFIG_IP_PNP is not set
> ++# CONFIG_NET_IPIP is not set
> ++# CONFIG_NET_IPGRE_DEMUX is not set
> ++# CONFIG_IP_MROUTE is not set
> ++# CONFIG_ARPD is not set
> ++# CONFIG_SYN_COOKIES is not set
> ++# CONFIG_INET_AH is not set
> ++# CONFIG_INET_ESP is not set
> ++# CONFIG_INET_IPCOMP is not set
> ++# CONFIG_INET_XFRM_TUNNEL is not set
> ++# CONFIG_INET_TUNNEL is not set
> ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> ++# CONFIG_INET_XFRM_MODE_BEET is not set
> ++CONFIG_INET_LRO=y
> ++# CONFIG_INET_DIAG is not set
> ++# CONFIG_TCP_CONG_ADVANCED is not set
> ++CONFIG_TCP_CONG_CUBIC=y
> ++CONFIG_DEFAULT_TCP_CONG="cubic"
> ++# CONFIG_TCP_MD5SIG is not set
> ++# CONFIG_IPV6 is not set
> ++# CONFIG_ANDROID_PARANOID_NETWORK is not set
> ++# CONFIG_NET_ACTIVITY_STATS is not set
> ++# CONFIG_NETWORK_SECMARK is not set
> ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
> ++# CONFIG_NETFILTER is not set
> ++# CONFIG_IP_DCCP is not set
> ++# CONFIG_IP_SCTP is not set
> ++# CONFIG_RDS is not set
> ++# CONFIG_TIPC is not set
> ++# CONFIG_ATM is not set
> ++# CONFIG_L2TP is not set
> ++# CONFIG_BRIDGE is not set
> ++# CONFIG_NET_DSA is not set
> ++# CONFIG_VLAN_8021Q is not set
> ++# CONFIG_DECNET is not set
> ++# CONFIG_LLC2 is not set
> ++# CONFIG_IPX is not set
> ++# CONFIG_ATALK is not set
> ++# CONFIG_X25 is not set
> ++# CONFIG_LAPB is not set
> ++# CONFIG_ECONET is not set
> ++# CONFIG_WAN_ROUTER is not set
> ++# CONFIG_PHONET is not set
> ++# CONFIG_IEEE802154 is not set
> ++# CONFIG_NET_SCHED is not set
> ++# CONFIG_DCB is not set
> ++# CONFIG_BATMAN_ADV is not set
> ++CONFIG_RPS=y
> ++CONFIG_RFS_ACCEL=y
> ++CONFIG_XPS=y
> ++
> ++#
> ++# Network testing
> ++#
> ++# CONFIG_NET_PKTGEN is not set
> ++# CONFIG_HAMRADIO is not set
> ++# CONFIG_CAN is not set
> ++# CONFIG_IRDA is not set
> ++CONFIG_BT=y
> ++CONFIG_BT_L2CAP=y
> ++CONFIG_BT_SCO=y
> ++CONFIG_BT_RFCOMM=y
> ++# CONFIG_BT_RFCOMM_TTY is not set
> ++CONFIG_BT_BNEP=y
> ++CONFIG_BT_BNEP_MC_FILTER=y
> ++# CONFIG_BT_BNEP_PROTO_FILTER is not set
> ++
> ++#
> ++# Bluetooth device drivers
> ++#
> ++# CONFIG_BT_HCIBTUSB is not set
> ++# CONFIG_BT_HCIBTSDIO is not set
> ++CONFIG_BT_HCIUART=y
> ++CONFIG_BT_HCIUART_H4=y
> ++# CONFIG_BT_HCIUART_BCSP is not set
> ++# CONFIG_BT_HCIUART_ATH3K is not set
> ++# CONFIG_BT_HCIUART_LL is not set
> ++# CONFIG_BT_HCIBCM203X is not set
> ++# CONFIG_BT_HCIBPA10X is not set
> ++# CONFIG_BT_HCIBFUSB is not set
> ++# CONFIG_BT_HCIVHCI is not set
> ++# CONFIG_BT_MRVL is not set
> ++# CONFIG_AF_RXRPC is not set
> ++CONFIG_WIRELESS=y
> ++CONFIG_WEXT_CORE=y
> ++CONFIG_WEXT_PROC=y
> ++CONFIG_CFG80211=y
> ++# CONFIG_NL80211_TESTMODE is not set
> ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
> ++# CONFIG_CFG80211_REG_DEBUG is not set
> ++# CONFIG_CFG80211_DEFAULT_PS is not set
> ++# CONFIG_CFG80211_INTERNAL_REGDB is not set
> ++CONFIG_CFG80211_WEXT=y
> ++# CONFIG_WIRELESS_EXT_SYSFS is not set
> ++# CONFIG_LIB80211 is not set
> ++# CONFIG_CFG80211_ALLOW_RECONNECT is not set
> ++# CONFIG_MAC80211 is not set
> ++# CONFIG_WIMAX is not set
> ++# CONFIG_RFKILL is not set
> ++CONFIG_RFKILL_REGULATOR=y
> ++# CONFIG_NET_9P is not set
> ++# CONFIG_CAIF is not set
> ++# CONFIG_CEPH_LIB is not set
> ++
> ++#
> ++# Device Drivers
> ++#
> ++
> ++#
> ++# Generic Driver Options
> ++#
> ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> ++# CONFIG_DEVTMPFS is not set
> ++# CONFIG_STANDALONE is not set
> ++CONFIG_PREVENT_FIRMWARE_BUILD=y
> ++CONFIG_FW_LOADER=y
> ++CONFIG_FIRMWARE_IN_KERNEL=y
> ++CONFIG_EXTRA_FIRMWARE=""
> ++# CONFIG_SYS_HYPERVISOR is not set
> ++# CONFIG_SYNC is not set
> ++# CONFIG_CONNECTOR is not set
> ++# CONFIG_MTD is not set
> ++# CONFIG_PARPORT is not set
> ++CONFIG_BLK_DEV=y
> ++# CONFIG_BLK_DEV_COW_COMMON is not set
> ++# CONFIG_BLK_DEV_LOOP is not set
> ++
> ++#
> ++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
> ++#
> ++# CONFIG_BLK_DEV_NBD is not set
> ++# CONFIG_BLK_DEV_UB is not set
> ++# CONFIG_BLK_DEV_RAM is not set
> ++# CONFIG_CDROM_PKTCDVD is not set
> ++# CONFIG_ATA_OVER_ETH is not set
> ++# CONFIG_MG_DISK is not set
> ++# CONFIG_BLK_DEV_RBD is not set
> ++# CONFIG_SENSORS_LIS3LV02D is not set
> ++# CONFIG_MISC_DEVICES is not set
> ++CONFIG_HAVE_IDE=y
> ++# CONFIG_IDE is not set
> ++
> ++#
> ++# SCSI device support
> ++#
> ++CONFIG_SCSI_MOD=y
> ++# CONFIG_RAID_ATTRS is not set
> ++CONFIG_SCSI=y
> ++CONFIG_SCSI_DMA=y
> ++# CONFIG_SCSI_TGT is not set
> ++# CONFIG_SCSI_NETLINK is not set
> ++# CONFIG_SCSI_PROC_FS is not set
> ++
> ++#
> ++# SCSI support type (disk, tape, CD-ROM)
> ++#
> ++CONFIG_BLK_DEV_SD=y
> ++# CONFIG_CHR_DEV_ST is not set
> ++# CONFIG_CHR_DEV_OSST is not set
> ++# CONFIG_BLK_DEV_SR is not set
> ++# CONFIG_CHR_DEV_SG is not set
> ++# CONFIG_CHR_DEV_SCH is not set
> ++# CONFIG_SCSI_MULTI_LUN is not set
> ++# CONFIG_SCSI_CONSTANTS is not set
> ++# CONFIG_SCSI_LOGGING is not set
> ++# CONFIG_SCSI_SCAN_ASYNC is not set
> ++# CONFIG_SCSI_WAIT_SCAN is not set
> ++
> ++#
> ++# SCSI Transports
> ++#
> ++# CONFIG_SCSI_SPI_ATTRS is not set
> ++# CONFIG_SCSI_FC_ATTRS is not set
> ++# CONFIG_SCSI_ISCSI_ATTRS is not set
> ++# CONFIG_SCSI_SAS_ATTRS is not set
> ++# CONFIG_SCSI_SAS_LIBSAS is not set
> ++# CONFIG_SCSI_SRP_ATTRS is not set
> ++# CONFIG_SCSI_LOWLEVEL is not set
> ++# CONFIG_SCSI_DH is not set
> ++# CONFIG_SCSI_OSD_INITIATOR is not set
> ++# CONFIG_ATA is not set
> ++# CONFIG_MD is not set
> ++# CONFIG_TARGET_CORE is not set
> ++CONFIG_NETDEVICES=y
> ++# CONFIG_DUMMY is not set
> ++# CONFIG_BONDING is not set
> ++# CONFIG_MACVLAN is not set
> ++# CONFIG_EQUALIZER is not set
> ++# CONFIG_TUN is not set
> ++# CONFIG_VETH is not set
> ++# CONFIG_MII is not set
> ++CONFIG_PHYLIB=y
> ++
> ++#
> ++# MII PHY device drivers
> ++#
> ++# CONFIG_MARVELL_PHY is not set
> ++# CONFIG_DAVICOM_PHY is not set
> ++# CONFIG_QSEMI_PHY is not set
> ++# CONFIG_LXT_PHY is not set
> ++# CONFIG_CICADA_PHY is not set
> ++# CONFIG_VITESSE_PHY is not set
> ++# CONFIG_SMSC_PHY is not set
> ++# CONFIG_BROADCOM_PHY is not set
> ++# CONFIG_ICPLUS_PHY is not set
> ++# CONFIG_REALTEK_PHY is not set
> ++# CONFIG_NATIONAL_PHY is not set
> ++# CONFIG_STE10XP is not set
> ++# CONFIG_LSI_ET1011C_PHY is not set
> ++# CONFIG_MICREL_PHY is not set
> ++# CONFIG_FIXED_PHY is not set
> ++# CONFIG_MDIO_BITBANG is not set
> ++CONFIG_NET_ETHERNET=y
> ++# CONFIG_AX88796 is not set
> ++# CONFIG_SMC91X is not set
> ++# CONFIG_DM9000 is not set
> ++# CONFIG_ENC28J60 is not set
> ++# CONFIG_ETHOC is not set
> ++# CONFIG_SMC911X is not set
> ++# CONFIG_SMSC911X is not set
> ++# CONFIG_DNET is not set
> ++# CONFIG_IBM_NEW_EMAC_ZMII is not set
> ++# CONFIG_IBM_NEW_EMAC_RGMII is not set
> ++# CONFIG_IBM_NEW_EMAC_TAH is not set
> ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
> ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
> ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
> ++# CONFIG_B44 is not set
> ++# CONFIG_KS8842 is not set
> ++# CONFIG_KS8851 is not set
> ++# CONFIG_KS8851_MLL is not set
> ++CONFIG_FEC=y
> ++CONFIG_FEC_NAPI=y
> ++# CONFIG_FEC_1588 is not set
> ++# CONFIG_FTMAC100 is not set
> ++# CONFIG_NETDEV_1000 is not set
> ++# CONFIG_NETDEV_10000 is not set
> ++CONFIG_WLAN=y
> ++# CONFIG_USB_ZD1201 is not set
> ++# CONFIG_USB_NET_RNDIS_WLAN is not set
> ++# CONFIG_WIFI_CONTROL_FUNC is not set
> ++# CONFIG_ATH_COMMON is not set
> ++# CONFIG_BCM4329 is not set
> ++# CONFIG_BCMDHD is not set
> ++CONFIG_BRCMUTIL=m
> ++CONFIG_BRCMFMAC=m
> ++CONFIG_BRCMFMAC_SDIO=y
> ++# CONFIG_BRCMFMAC_SDIO_OOB is not set
> ++# CONFIG_BRCMFMAC_USB is not set
> ++# CONFIG_BRCMDBG is not set
> ++# CONFIG_HOSTAP is not set
> ++# CONFIG_IWM is not set
> ++# CONFIG_LIBERTAS is not set
> ++# CONFIG_MWIFIEX is not set
> ++
> ++#
> ++# Enable WiMAX (Networking options) to see the WiMAX drivers
> ++#
> ++
> ++#
> ++# USB Network Adapters
> ++#
> ++# CONFIG_USB_CATC is not set
> ++# CONFIG_USB_KAWETH is not set
> ++# CONFIG_USB_PEGASUS is not set
> ++# CONFIG_USB_RTL8150 is not set
> ++# CONFIG_USB_USBNET is not set
> ++# CONFIG_USB_IPHETH is not set
> ++# CONFIG_WAN is not set
> ++
> ++#
> ++# CAIF transport drivers
> ++#
> ++# CONFIG_PPP is not set
> ++# CONFIG_SLIP is not set
> ++# CONFIG_NETCONSOLE is not set
> ++# CONFIG_NETPOLL is not set
> ++# CONFIG_NET_POLL_CONTROLLER is not set
> ++# CONFIG_ISDN is not set
> ++# CONFIG_PHONE is not set
> ++
> ++#
> ++# Input device support
> ++#
> ++CONFIG_INPUT=y
> ++# CONFIG_INPUT_FF_MEMLESS is not set
> ++# CONFIG_INPUT_POLLDEV is not set
> ++# CONFIG_INPUT_SPARSEKMAP is not set
> ++
> ++#
> ++# Userland interfaces
> ++#
> ++# CONFIG_INPUT_MOUSEDEV is not set
> ++# CONFIG_INPUT_JOYDEV is not set
> ++# CONFIG_INPUT_EVDEV is not set
> ++# CONFIG_INPUT_EVBUG is not set
> ++# CONFIG_INPUT_KEYRESET is not set
> ++
> ++#
> ++# Input Device Drivers
> ++#
> ++# CONFIG_INPUT_KEYBOARD is not set
> ++# CONFIG_INPUT_MOUSE is not set
> ++# CONFIG_INPUT_JOYSTICK is not set
> ++# CONFIG_INPUT_TABLET is not set
> ++# CONFIG_INPUT_TOUCHSCREEN is not set
> ++# CONFIG_INPUT_MISC is not set
> ++
> ++#
> ++# Hardware I/O ports
> ++#
> ++CONFIG_SERIO=y
> ++# CONFIG_SERIO_SERPORT is not set
> ++# CONFIG_SERIO_AMBAKMI is not set
> ++# CONFIG_SERIO_LIBPS2 is not set
> ++# CONFIG_SERIO_RAW is not set
> ++# CONFIG_SERIO_ALTERA_PS2 is not set
> ++# CONFIG_SERIO_PS2MULT is not set
> ++# CONFIG_GAMEPORT is not set
> ++
> ++#
> ++# Character devices
> ++#
> ++CONFIG_VT=y
> ++# CONFIG_CONSOLE_TRANSLATIONS is not set
> ++CONFIG_VT_CONSOLE=y
> ++CONFIG_HW_CONSOLE=y
> ++# CONFIG_VT_HW_CONSOLE_BINDING is not set
> ++CONFIG_UNIX98_PTYS=y
> ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> ++# CONFIG_LEGACY_PTYS is not set
> ++# CONFIG_SERIAL_NONSTANDARD is not set
> ++# CONFIG_N_GSM is not set
> ++# CONFIG_TRACE_SINK is not set
> ++# CONFIG_DEVMEM is not set
> ++# CONFIG_DEVKMEM is not set
> ++
> ++#
> ++# Serial drivers
> ++#
> ++# CONFIG_SERIAL_8250 is not set
> ++
> ++#
> ++# Non-8250 serial port support
> ++#
> ++# CONFIG_SERIAL_AMBA_PL010 is not set
> ++# CONFIG_SERIAL_AMBA_PL011 is not set
> ++# CONFIG_SERIAL_MAX3100 is not set
> ++# CONFIG_SERIAL_MAX3107 is not set
> ++CONFIG_SERIAL_IMX=y
> ++CONFIG_SERIAL_IMX_CONSOLE=y
> ++CONFIG_SERIAL_CORE=y
> ++CONFIG_SERIAL_CORE_CONSOLE=y
> ++# CONFIG_SERIAL_TIMBERDALE is not set
> ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
> ++# CONFIG_SERIAL_ALTERA_UART is not set
> ++# CONFIG_SERIAL_IFX6X60 is not set
> ++# CONFIG_SERIAL_XILINX_PS_UART is not set
> ++# CONFIG_TTY_PRINTK is not set
> ++# CONFIG_FSL_OTP is not set
> ++# CONFIG_HVC_DCC is not set
> ++# CONFIG_IPMI_HANDLER is not set
> ++# CONFIG_HW_RANDOM is not set
> ++# CONFIG_R3964 is not set
> ++# CONFIG_RAW_DRIVER is not set
> ++# CONFIG_TCG_TPM is not set
> ++# CONFIG_DCC_TTY is not set
> ++# CONFIG_RAMOOPS is not set
> ++# CONFIG_MXS_VIIM is not set
> ++CONFIG_I2C=y
> ++CONFIG_I2C_BOARDINFO=y
> ++# CONFIG_I2C_COMPAT is not set
> ++CONFIG_I2C_CHARDEV=y
> ++# CONFIG_I2C_MUX is not set
> ++CONFIG_I2C_HELPER_AUTO=y
> ++
> ++#
> ++# I2C Hardware Bus support
> ++#
> ++
> ++#
> ++# I2C system bus drivers (mostly embedded / system-on-chip)
> ++#
> ++# CONFIG_I2C_DESIGNWARE is not set
> ++# CONFIG_I2C_GPIO is not set
> ++CONFIG_I2C_IMX=y
> ++# CONFIG_I2C_OCORES is not set
> ++# CONFIG_I2C_PCA_PLATFORM is not set
> ++# CONFIG_I2C_PXA_PCI is not set
> ++# CONFIG_I2C_SIMTEC is not set
> ++# CONFIG_I2C_XILINX is not set
> ++
> ++#
> ++# External I2C/SMBus adapter drivers
> ++#
> ++# CONFIG_I2C_DIOLAN_U2C is not set
> ++# CONFIG_I2C_PARPORT_LIGHT is not set
> ++# CONFIG_I2C_TAOS_EVM is not set
> ++# CONFIG_I2C_TINY_USB is not set
> ++
> ++#
> ++# Other I2C/SMBus bus drivers
> ++#
> ++# CONFIG_I2C_STUB is not set
> ++# CONFIG_I2C_DEBUG_CORE is not set
> ++# CONFIG_I2C_DEBUG_ALGO is not set
> ++# CONFIG_I2C_DEBUG_BUS is not set
> ++CONFIG_SPI=y
> ++CONFIG_SPI_MASTER=y
> ++
> ++#
> ++# SPI Master Controller Drivers
> ++#
> ++# CONFIG_SPI_ALTERA is not set
> ++CONFIG_SPI_BITBANG=y
> ++# CONFIG_SPI_GPIO is not set
> ++CONFIG_SPI_IMX_VER_2_3=y
> ++CONFIG_SPI_IMX=y
> ++# CONFIG_SPI_OC_TINY is not set
> ++# CONFIG_SPI_PL022 is not set
> ++# CONFIG_SPI_PXA2XX_PCI is not set
> ++# CONFIG_SPI_XILINX is not set
> ++# CONFIG_SPI_DESIGNWARE is not set
> ++
> ++#
> ++# SPI Protocol Masters
> ++#
> ++# CONFIG_SPI_SPIDEV is not set
> ++# CONFIG_SPI_TLE62X0 is not set
> ++
> ++#
> ++# PPS support
> ++#
> ++# CONFIG_PPS is not set
> ++
> ++#
> ++# PPS generators support
> ++#
> ++
> ++#
> ++# PTP clock support
> ++#
> ++
> ++#
> ++# Enable Device Drivers -> PPS to see the PTP clock options.
> ++#
> ++CONFIG_ARCH_REQUIRE_GPIOLIB=y
> ++CONFIG_GPIOLIB=y
> ++CONFIG_GPIO_SYSFS=y
> ++
> ++#
> ++# Memory mapped GPIO drivers:
> ++#
> ++# CONFIG_GPIO_BASIC_MMIO is not set
> ++# CONFIG_GPIO_IT8761E is not set
> ++# CONFIG_GPIO_PL061 is not set
> ++
> ++#
> ++# I2C GPIO expanders:
> ++#
> ++# CONFIG_GPIO_MAX7300 is not set
> ++# CONFIG_GPIO_MAX732X is not set
> ++# CONFIG_GPIO_PCF857X is not set
> ++# CONFIG_GPIO_SX150X is not set
> ++# CONFIG_GPIO_ADP5588 is not set
> ++
> ++#
> ++# PCI GPIO expanders:
> ++#
> ++
> ++#
> ++# SPI GPIO expanders:
> ++#
> ++# CONFIG_GPIO_MAX7301 is not set
> ++# CONFIG_GPIO_MCP23S08 is not set
> ++# CONFIG_GPIO_MC33880 is not set
> ++# CONFIG_GPIO_74X164 is not set
> ++
> ++#
> ++# AC97 GPIO expanders:
> ++#
> ++
> ++#
> ++# MODULbus GPIO expanders:
> ++#
> ++# CONFIG_W1 is not set
> ++CONFIG_POWER_SUPPLY=y
> ++# CONFIG_POWER_SUPPLY_DEBUG is not set
> ++# CONFIG_PDA_POWER is not set
> ++# CONFIG_TEST_POWER is not set
> ++# CONFIG_BATTERY_DS2780 is not set
> ++# CONFIG_BATTERY_DS2782 is not set
> ++# CONFIG_BATTERY_BQ20Z75 is not set
> ++# CONFIG_BATTERY_BQ27x00 is not set
> ++# CONFIG_BATTERY_MAX17040 is not set
> ++# CONFIG_BATTERY_MAX17042 is not set
> ++# CONFIG_CHARGER_ISP1704 is not set
> ++# CONFIG_CHARGER_MAX8903 is not set
> ++# CONFIG_SABRESD_MAX8903 is not set
> ++# CONFIG_CHARGER_GPIO is not set
> ++# CONFIG_HWMON is not set
> ++CONFIG_THERMAL=y
> ++# CONFIG_WATCHDOG is not set
> ++CONFIG_SSB_POSSIBLE=y
> ++
> ++#
> ++# Sonics Silicon Backplane
> ++#
> ++# CONFIG_SSB is not set
> ++CONFIG_BCMA_POSSIBLE=y
> ++
> ++#
> ++# Broadcom specific AMBA
> ++#
> ++# CONFIG_BCMA is not set
> ++CONFIG_MFD_SUPPORT=y
> ++CONFIG_MFD_CORE=y
> ++# CONFIG_MFD_88PM860X is not set
> ++# CONFIG_MFD_SM501 is not set
> ++# CONFIG_MFD_ASIC3 is not set
> ++# CONFIG_HTC_EGPIO is not set
> ++# CONFIG_HTC_PASIC3 is not set
> ++# CONFIG_HTC_I2CPLD is not set
> ++# CONFIG_UCB1400_CORE is not set
> ++# CONFIG_TPS6105X is not set
> ++# CONFIG_TPS65010 is not set
> ++# CONFIG_TPS6507X is not set
> ++# CONFIG_MFD_TPS6586X is not set
> ++# CONFIG_TWL4030_CORE is not set
> ++# CONFIG_MFD_STMPE is not set
> ++# CONFIG_MFD_TC3589X is not set
> ++# CONFIG_MFD_TMIO is not set
> ++# CONFIG_MFD_T7L66XB is not set
> ++# CONFIG_MFD_TC6387XB is not set
> ++# CONFIG_MFD_TC6393XB is not set
> ++# CONFIG_PMIC_DA903X is not set
> ++# CONFIG_PMIC_ADP5520 is not set
> ++# CONFIG_MFD_MAX8925 is not set
> ++# CONFIG_MFD_MAX8997 is not set
> ++# CONFIG_MFD_MAX8998 is not set
> ++# CONFIG_MFD_WM8400 is not set
> ++# CONFIG_MFD_WM831X_I2C is not set
> ++# CONFIG_MFD_WM831X_SPI is not set
> ++# CONFIG_MFD_WM8350_I2C is not set
> ++# CONFIG_MFD_WM8994 is not set
> ++# CONFIG_MFD_PCF50633 is not set
> ++# CONFIG_PMIC_DIALOG is not set
> ++# CONFIG_MFD_MC_PMIC is not set
> ++# CONFIG_MFD_MC34708 is not set
> ++# CONFIG_MFD_PFUZE is not set
> ++# CONFIG_MFD_MC13XXX is not set
> ++# CONFIG_ABX500_CORE is not set
> ++# CONFIG_EZX_PCAP is not set
> ++# CONFIG_MFD_WL1273_CORE is not set
> ++# CONFIG_MFD_TPS65910 is not set
> ++# CONFIG_MFD_MAX17135 is not set
> ++CONFIG_MFD_MXC_HDMI=y
> ++CONFIG_REGULATOR=y
> ++# CONFIG_REGULATOR_DEBUG is not set
> ++CONFIG_REGULATOR_DUMMY=y
> ++CONFIG_REGULATOR_FIXED_VOLTAGE=y
> ++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
> ++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
> ++# CONFIG_REGULATOR_BQ24022 is not set
> ++# CONFIG_REGULATOR_MAX1586 is not set
> ++# CONFIG_REGULATOR_MAX8649 is not set
> ++# CONFIG_REGULATOR_MAX8660 is not set
> ++# CONFIG_REGULATOR_MAX8952 is not set
> ++# CONFIG_REGULATOR_LP3971 is not set
> ++# CONFIG_REGULATOR_LP3972 is not set
> ++# CONFIG_REGULATOR_MC34708 is not set
> ++# CONFIG_REGULATOR_TPS65023 is not set
> ++# CONFIG_REGULATOR_TPS6507X is not set
> ++# CONFIG_REGULATOR_ISL6271A is not set
> ++# CONFIG_REGULATOR_AD5398 is not set
> ++CONFIG_REGULATOR_ANATOP=y
> ++# CONFIG_REGULATOR_TPS6524X is not set
> ++CONFIG_MEDIA_SUPPORT=y
> ++
> ++#
> ++# Multimedia core support
> ++#
> ++# CONFIG_MEDIA_CONTROLLER is not set
> ++CONFIG_VIDEO_DEV=y
> ++CONFIG_VIDEO_V4L2_COMMON=y
> ++# CONFIG_DVB_CORE is not set
> ++CONFIG_VIDEO_MEDIA=y
> ++
> ++#
> ++# Multimedia drivers
> ++#
> ++# CONFIG_RC_CORE is not set
> ++# CONFIG_MEDIA_ATTACH is not set
> ++CONFIG_MEDIA_TUNER=y
> ++# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
> ++CONFIG_MEDIA_TUNER_SIMPLE=y
> ++CONFIG_MEDIA_TUNER_TDA8290=y
> ++CONFIG_MEDIA_TUNER_TDA827X=y
> ++CONFIG_MEDIA_TUNER_TDA18271=y
> ++CONFIG_MEDIA_TUNER_TDA9887=y
> ++CONFIG_MEDIA_TUNER_TEA5761=y
> ++CONFIG_MEDIA_TUNER_TEA5767=y
> ++CONFIG_MEDIA_TUNER_MT20XX=y
> ++CONFIG_MEDIA_TUNER_XC2028=y
> ++CONFIG_MEDIA_TUNER_XC5000=y
> ++CONFIG_MEDIA_TUNER_MC44S803=y
> ++CONFIG_VIDEO_V4L2=y
> ++CONFIG_VIDEOBUF_GEN=y
> ++CONFIG_VIDEOBUF_DMA_CONTIG=y
> ++CONFIG_VIDEO_CAPTURE_DRIVERS=y
> ++# CONFIG_VIDEO_ADV_DEBUG is not set
> ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
> ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
> ++
> ++#
> ++# Encoders, decoders, sensors and other helper chips
> ++#
> ++
> ++#
> ++# Audio decoders, processors and mixers
> ++#
> ++# CONFIG_VIDEO_TVAUDIO is not set
> ++# CONFIG_VIDEO_TDA7432 is not set
> ++# CONFIG_VIDEO_TDA9840 is not set
> ++# CONFIG_VIDEO_TEA6415C is not set
> ++# CONFIG_VIDEO_TEA6420 is not set
> ++# CONFIG_VIDEO_MSP3400 is not set
> ++# CONFIG_VIDEO_CS5345 is not set
> ++# CONFIG_VIDEO_CS53L32A is not set
> ++# CONFIG_VIDEO_TLV320AIC23B is not set
> ++# CONFIG_VIDEO_WM8775 is not set
> ++# CONFIG_VIDEO_WM8739 is not set
> ++# CONFIG_VIDEO_VP27SMPX is not set
> ++
> ++#
> ++# RDS decoders
> ++#
> ++# CONFIG_VIDEO_SAA6588 is not set
> ++
> ++#
> ++# Video decoders
> ++#
> ++# CONFIG_VIDEO_ADV7180 is not set
> ++# CONFIG_VIDEO_BT819 is not set
> ++# CONFIG_VIDEO_BT856 is not set
> ++# CONFIG_VIDEO_BT866 is not set
> ++# CONFIG_VIDEO_KS0127 is not set
> ++# CONFIG_VIDEO_SAA7110 is not set
> ++# CONFIG_VIDEO_SAA711X is not set
> ++# CONFIG_VIDEO_SAA7191 is not set
> ++# CONFIG_VIDEO_TVP514X is not set
> ++# CONFIG_VIDEO_TVP5150 is not set
> ++# CONFIG_VIDEO_TVP7002 is not set
> ++# CONFIG_VIDEO_VPX3220 is not set
> ++
> ++#
> ++# Video and audio decoders
> ++#
> ++# CONFIG_VIDEO_SAA717X is not set
> ++# CONFIG_VIDEO_CX25840 is not set
> ++
> ++#
> ++# MPEG video encoders
> ++#
> ++# CONFIG_VIDEO_CX2341X is not set
> ++
> ++#
> ++# Video encoders
> ++#
> ++# CONFIG_VIDEO_SAA7127 is not set
> ++# CONFIG_VIDEO_SAA7185 is not set
> ++# CONFIG_VIDEO_ADV7170 is not set
> ++# CONFIG_VIDEO_ADV7175 is not set
> ++# CONFIG_VIDEO_ADV7343 is not set
> ++# CONFIG_VIDEO_AK881X is not set
> ++
> ++#
> ++# Camera sensor devices
> ++#
> ++# CONFIG_VIDEO_OV7670 is not set
> ++# CONFIG_VIDEO_MT9V011 is not set
> ++# CONFIG_VIDEO_TCM825X is not set
> ++
> ++#
> ++# Video improvement chips
> ++#
> ++# CONFIG_VIDEO_UPD64031A is not set
> ++# CONFIG_VIDEO_UPD64083 is not set
> ++
> ++#
> ++# Miscelaneous helper chips
> ++#
> ++# CONFIG_VIDEO_THS7303 is not set
> ++# CONFIG_VIDEO_M52790 is not set
> ++# CONFIG_VIDEO_VIVI is not set
> ++# CONFIG_VIDEO_MXC_CAMERA is not set
> ++CONFIG_VIDEO_MXC_OUTPUT=y
> ++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
> ++# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
> ++# CONFIG_VIDEO_MXC_OPL is not set
> ++# CONFIG_VIDEO_CPIA2 is not set
> ++# CONFIG_VIDEO_TIMBERDALE is not set
> ++# CONFIG_VIDEO_SR030PC30 is not set
> ++# CONFIG_VIDEO_NOON010PC30 is not set
> ++# CONFIG_SOC_CAMERA is not set
> ++# CONFIG_V4L_USB_DRIVERS is not set
> ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
> ++# CONFIG_RADIO_ADAPTERS is not set
> ++
> ++#
> ++# Graphics support
> ++#
> ++# CONFIG_DRM is not set
> ++# CONFIG_ION is not set
> ++# CONFIG_VGASTATE is not set
> ++CONFIG_VIDEO_OUTPUT_CONTROL=y
> ++CONFIG_FB=y
> ++# CONFIG_FIRMWARE_EDID is not set
> ++# CONFIG_FB_DDC is not set
> ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> ++CONFIG_FB_CFB_FILLRECT=y
> ++CONFIG_FB_CFB_COPYAREA=y
> ++CONFIG_FB_CFB_IMAGEBLIT=y
> ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> ++# CONFIG_FB_SYS_FILLRECT is not set
> ++# CONFIG_FB_SYS_COPYAREA is not set
> ++# CONFIG_FB_SYS_IMAGEBLIT is not set
> ++# CONFIG_FB_FOREIGN_ENDIAN is not set
> ++# CONFIG_FB_SYS_FOPS is not set
> ++# CONFIG_FB_WMT_GE_ROPS is not set
> ++# CONFIG_FB_SVGALIB is not set
> ++# CONFIG_FB_MACMODES is not set
> ++# CONFIG_FB_BACKLIGHT is not set
> ++CONFIG_FB_MODE_HELPERS=y
> ++# CONFIG_FB_TILEBLITTING is not set
> ++
> ++#
> ++# Frame buffer hardware drivers
> ++#
> ++# CONFIG_FB_ARMCLCD is not set
> ++# CONFIG_FB_S1D13XXX is not set
> ++# CONFIG_FB_TMIO is not set
> ++# CONFIG_FB_UDL is not set
> ++# CONFIG_FB_VIRTUAL is not set
> ++# CONFIG_FB_METRONOME is not set
> ++# CONFIG_FB_BROADSHEET is not set
> ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> ++
> ++#
> ++# Display device support
> ++#
> ++CONFIG_DISPLAY_SUPPORT=y
> ++
> ++#
> ++# Display hardware drivers
> ++#
> ++CONFIG_FB_MXC=y
> ++CONFIG_FB_MXC_EDID=y
> ++CONFIG_FB_MXC_SYNC_PANEL=y
> ++# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
> ++CONFIG_FB_MXC_LDB=y
> ++# CONFIG_FB_MXC_MIPI_DSI is not set
> ++# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
> ++# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
> ++# CONFIG_FB_MXC_SII902X is not set
> ++# CONFIG_FB_MXC_CH7026 is not set
> ++# CONFIG_FB_MXC_TVOUT_CH7024 is not set
> ++# CONFIG_FB_MXC_ASYNC_PANEL is not set
> ++# CONFIG_FB_MXC_EINK_PANEL is not set
> ++# CONFIG_FB_MXC_SIPIX_PANEL is not set
> ++# CONFIG_FB_MXC_ELCDIF_FB is not set
> ++CONFIG_FB_MXC_HDMI=y
> ++
> ++#
> ++# Console display driver support
> ++#
> ++CONFIG_DUMMY_CONSOLE=y
> ++CONFIG_FRAMEBUFFER_CONSOLE=y
> ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> ++# CONFIG_FONTS is not set
> ++CONFIG_FONT_8x8=y
> ++CONFIG_FONT_8x16=y
> ++CONFIG_LOGO=y
> ++# CONFIG_LOGO_LINUX_MONO is not set
> ++# CONFIG_LOGO_LINUX_VGA16 is not set
> ++CONFIG_LOGO_LINUX_CLUT224=y
> ++CONFIG_SOUND=y
> ++# CONFIG_SOUND_OSS_CORE is not set
> ++CONFIG_SND=y
> ++CONFIG_SND_TIMER=y
> ++CONFIG_SND_PCM=y
> ++CONFIG_SND_JACK=y
> ++# CONFIG_SND_SEQUENCER is not set
> ++# CONFIG_SND_MIXER_OSS is not set
> ++# CONFIG_SND_PCM_OSS is not set
> ++# CONFIG_SND_HRTIMER is not set
> ++# CONFIG_SND_DYNAMIC_MINORS is not set
> ++# CONFIG_SND_SUPPORT_OLD_API is not set
> ++# CONFIG_SND_VERBOSE_PROCFS is not set
> ++# CONFIG_SND_VERBOSE_PRINTK is not set
> ++# CONFIG_SND_DEBUG is not set
> ++# CONFIG_SND_RAWMIDI_SEQ is not set
> ++# CONFIG_SND_OPL3_LIB_SEQ is not set
> ++# CONFIG_SND_OPL4_LIB_SEQ is not set
> ++# CONFIG_SND_SBAWE_SEQ is not set
> ++# CONFIG_SND_EMU10K1_SEQ is not set
> ++# CONFIG_SND_DRIVERS is not set
> ++# CONFIG_SND_ARM is not set
> ++# CONFIG_SND_SPI is not set
> ++# CONFIG_SND_USB is not set
> ++CONFIG_SND_SOC=y
> ++# CONFIG_SND_SOC_CACHE_LZO is not set
> ++CONFIG_SND_SOC_AC97_BUS=y
> ++CONFIG_SND_IMX_SOC=y
> ++CONFIG_SND_MXC_SOC_MX2=y
> ++CONFIG_SND_MXC_SOC_SPDIF_DAI=y
> ++CONFIG_SND_SOC_IMX_SGTL5000=y
> ++# CONFIG_SND_SOC_IMX_WM8962 is not set
> ++# CONFIG_SND_SOC_IMX_SI4763 is not set
> ++CONFIG_SND_SOC_IMX_SPDIF=y
> ++CONFIG_SND_SOC_IMX_HDMI=y
> ++CONFIG_SND_SOC_I2C_AND_SPI=y
> ++# CONFIG_SND_SOC_ALL_CODECS is not set
> ++CONFIG_SND_SOC_MXC_HDMI=y
> ++CONFIG_SND_SOC_MXC_SPDIF=y
> ++CONFIG_SND_SOC_SGTL5000=y
> ++# CONFIG_SOUND_PRIME is not set
> ++CONFIG_AC97_BUS=y
> ++# CONFIG_HID_SUPPORT is not set
> ++CONFIG_USB_SUPPORT=y
> ++CONFIG_USB_ARCH_HAS_HCD=y
> ++# CONFIG_USB_ARCH_HAS_OHCI is not set
> ++CONFIG_USB_ARCH_HAS_EHCI=y
> ++CONFIG_USB=y
> ++# CONFIG_USB_DEBUG is not set
> ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> ++
> ++#
> ++# Miscellaneous USB options
> ++#
> ++CONFIG_USB_DEVICEFS=y
> ++# CONFIG_USB_DEVICE_CLASS is not set
> ++# CONFIG_USB_DYNAMIC_MINORS is not set
> ++# CONFIG_USB_SUSPEND is not set
> ++# CONFIG_USB_OTG_WHITELIST is not set
> ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> ++# CONFIG_USB_MON is not set
> ++# CONFIG_USB_WUSB is not set
> ++# CONFIG_USB_WUSB_CBAF is not set
> ++
> ++#
> ++# USB Host Controller Drivers
> ++#
> ++# CONFIG_USB_C67X00_HCD is not set
> ++CONFIG_USB_EHCI_HCD=y
> ++CONFIG_USB_EHCI_ARC=y
> ++CONFIG_USB_EHCI_ARC_OTG=y
> ++# CONFIG_USB_EHCI_ARC_HSIC is not set
> ++# CONFIG_USB_STATIC_IRAM is not set
> ++CONFIG_USB_EHCI_ROOT_HUB_TT=y
> ++CONFIG_USB_EHCI_TT_NEWSCHED=y
> ++# CONFIG_USB_EHCI_MXC is not set
> ++# CONFIG_USB_OXU210HP_HCD is not set
> ++# CONFIG_USB_ISP116X_HCD is not set
> ++# CONFIG_USB_ISP1760_HCD is not set
> ++# CONFIG_USB_ISP1362_HCD is not set
> ++# CONFIG_USB_SL811_HCD is not set
> ++# CONFIG_USB_R8A66597_HCD is not set
> ++# CONFIG_USB_HWA_HCD is not set
> ++# CONFIG_USB_MUSB_HDRC is not set
> ++
> ++#
> ++# USB Device Class drivers
> ++#
> ++# CONFIG_USB_ACM is not set
> ++# CONFIG_USB_PRINTER is not set
> ++# CONFIG_USB_WDM is not set
> ++# CONFIG_USB_TMC is not set
> ++
> ++#
> ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
> ++#
> ++
> ++#
> ++# also be needed; see USB_STORAGE Help for more info
> ++#
> ++CONFIG_USB_STORAGE=y
> ++# CONFIG_USB_STORAGE_DEBUG is not set
> ++# CONFIG_USB_STORAGE_REALTEK is not set
> ++# CONFIG_USB_STORAGE_DATAFAB is not set
> ++# CONFIG_USB_STORAGE_FREECOM is not set
> ++# CONFIG_USB_STORAGE_ISD200 is not set
> ++# CONFIG_USB_STORAGE_USBAT is not set
> ++# CONFIG_USB_STORAGE_SDDR09 is not set
> ++# CONFIG_USB_STORAGE_SDDR55 is not set
> ++# CONFIG_USB_STORAGE_JUMPSHOT is not set
> ++# CONFIG_USB_STORAGE_ALAUDA is not set
> ++# CONFIG_USB_STORAGE_ONETOUCH is not set
> ++# CONFIG_USB_STORAGE_KARMA is not set
> ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
> ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
> ++# CONFIG_USB_UAS is not set
> ++# CONFIG_USB_LIBUSUAL is not set
> ++
> ++#
> ++# USB Imaging devices
> ++#
> ++# CONFIG_USB_MDC800 is not set
> ++# CONFIG_USB_MICROTEK is not set
> ++
> ++#
> ++# USB port drivers
> ++#
> ++# CONFIG_USB_SERIAL is not set
> ++
> ++#
> ++# USB Miscellaneous drivers
> ++#
> ++# CONFIG_USB_EMI62 is not set
> ++# CONFIG_USB_EMI26 is not set
> ++# CONFIG_USB_ADUTUX is not set
> ++# CONFIG_USB_SEVSEG is not set
> ++# CONFIG_USB_RIO500 is not set
> ++# CONFIG_USB_LEGOTOWER is not set
> ++# CONFIG_USB_LCD is not set
> ++# CONFIG_USB_LED is not set
> ++# CONFIG_USB_CYPRESS_CY7C63 is not set
> ++# CONFIG_USB_CYTHERM is not set
> ++# CONFIG_USB_IDMOUSE is not set
> ++# CONFIG_USB_FTDI_ELAN is not set
> ++# CONFIG_USB_APPLEDISPLAY is not set
> ++# CONFIG_USB_SISUSBVGA is not set
> ++# CONFIG_USB_LD is not set
> ++# CONFIG_USB_TRANCEVIBRATOR is not set
> ++# CONFIG_USB_IOWARRIOR is not set
> ++# CONFIG_USB_TEST is not set
> ++# CONFIG_USB_ISIGHTFW is not set
> ++# CONFIG_USB_YUREX is not set
> ++CONFIG_USB_GADGET=y
> ++# CONFIG_USB_GADGET_DEBUG_FILES is not set
> ++CONFIG_USB_GADGET_VBUS_DRAW=100
> ++CONFIG_USB_GADGET_SELECTED=y
> ++CONFIG_USB_GADGET_ARC=y
> ++# CONFIG_IMX_USB_CHARGER is not set
> ++CONFIG_USB_ARC=y
> ++# CONFIG_USB_GADGET_FSL_USB2 is not set
> ++# CONFIG_USB_GADGET_FUSB300 is not set
> ++# CONFIG_USB_GADGET_R8A66597 is not set
> ++# CONFIG_USB_GADGET_PXA_U2O is not set
> ++# CONFIG_USB_GADGET_M66592 is not set
> ++# CONFIG_USB_GADGET_DUMMY_HCD is not set
> ++CONFIG_USB_GADGET_DUALSPEED=y
> ++# CONFIG_USB_ZERO is not set
> ++# CONFIG_USB_AUDIO is not set
> ++# CONFIG_USB_ETH is not set
> ++# CONFIG_USB_G_NCM is not set
> ++# CONFIG_USB_GADGETFS is not set
> ++# CONFIG_USB_FUNCTIONFS is not set
> ++# CONFIG_USB_FILE_STORAGE is not set
> ++CONFIG_USB_MASS_STORAGE=y
> ++# CONFIG_USB_G_SERIAL is not set
> ++# CONFIG_USB_MIDI_GADGET is not set
> ++# CONFIG_USB_G_PRINTER is not set
> ++# CONFIG_USB_G_ANDROID is not set
> ++# CONFIG_USB_CDC_COMPOSITE is not set
> ++# CONFIG_USB_G_MULTI is not set
> ++# CONFIG_USB_G_HID is not set
> ++# CONFIG_USB_G_DBGP is not set
> ++# CONFIG_USB_G_WEBCAM is not set
> ++
> ++#
> ++# OTG and related infrastructure
> ++#
> ++CONFIG_USB_OTG_UTILS=y
> ++CONFIG_USB_GPIO_VBUS=y
> ++CONFIG_USB_ULPI=y
> ++# CONFIG_NOP_USB_XCEIV is not set
> ++# CONFIG_MXC_OTG is not set
> ++CONFIG_MMC=y
> ++# CONFIG_MMC_DEBUG is not set
> ++CONFIG_MMC_UNSAFE_RESUME=y
> ++CONFIG_MMC_CLKGATE=y
> ++# CONFIG_MMC_EMBEDDED_SDIO is not set
> ++# CONFIG_MMC_PARANOID_SD_INIT is not set
> ++
> ++#
> ++# MMC/SD/SDIO Card Drivers
> ++#
> ++CONFIG_MMC_BLOCK=y
> ++CONFIG_MMC_BLOCK_MINORS=8
> ++CONFIG_MMC_BLOCK_BOUNCE=y
> ++# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
> ++# CONFIG_SDIO_UART is not set
> ++# CONFIG_MMC_TEST is not set
> ++
> ++#
> ++# MMC/SD/SDIO Host Controller Drivers
> ++#
> ++# CONFIG_MMC_ARMMMCI is not set
> ++CONFIG_MMC_SDHCI=y
> ++CONFIG_MMC_SDHCI_IO_ACCESSORS=y
> ++CONFIG_MMC_SDHCI_PLTFM=y
> ++CONFIG_MMC_SDHCI_ESDHC_IMX=y
> ++# CONFIG_MMC_DW is not set
> ++# CONFIG_MMC_VUB300 is not set
> ++# CONFIG_MMC_USHC is not set
> ++# CONFIG_MEMSTICK is not set
> ++# CONFIG_NEW_LEDS is not set
> ++# CONFIG_NFC_DEVICES is not set
> ++CONFIG_SWITCH=y
> ++# CONFIG_SWITCH_GPIO is not set
> ++# CONFIG_ACCESSIBILITY is not set
> ++CONFIG_RTC_LIB=y
> ++# CONFIG_RTC_CLASS is not set
> ++CONFIG_DMADEVICES=y
> ++# CONFIG_DMADEVICES_DEBUG is not set
> ++
> ++#
> ++# DMA Devices
> ++#
> ++# CONFIG_AMBA_PL08X is not set
> ++# CONFIG_DW_DMAC is not set
> ++# CONFIG_MXC_PXP_V2 is not set
> ++# CONFIG_TIMB_DMA is not set
> ++CONFIG_IMX_SDMA=y
> ++# CONFIG_MXS_DMA is not set
> ++CONFIG_DMA_ENGINE=y
> ++
> ++#
> ++# DMA Clients
> ++#
> ++# CONFIG_NET_DMA is not set
> ++# CONFIG_ASYNC_TX_DMA is not set
> ++# CONFIG_DMATEST is not set
> ++# CONFIG_AUXDISPLAY is not set
> ++# CONFIG_UIO is not set
> ++CONFIG_STAGING=y
> ++# CONFIG_USBIP_CORE is not set
> ++# CONFIG_PRISM2_USB is not set
> ++# CONFIG_ECHO is not set
> ++# CONFIG_ASUS_OLED is not set
> ++# CONFIG_R8712U is not set
> ++# CONFIG_TRANZPORT is not set
> ++
> ++#
> ++# Android
> ++#
> ++# CONFIG_ANDROID is not set
> ++# CONFIG_POHMELFS is not set
> ++# CONFIG_LINE6_USB is not set
> ++# CONFIG_VT6656 is not set
> ++# CONFIG_IIO is not set
> ++# CONFIG_XVMALLOC is not set
> ++# CONFIG_ZRAM is not set
> ++# CONFIG_FB_SM7XX is not set
> ++# CONFIG_EASYCAP is not set
> ++CONFIG_MACH_NO_WESTBRIDGE=y
> ++# CONFIG_ATH6K_LEGACY is not set
> ++# CONFIG_USB_ENESTORAGE is not set
> ++# CONFIG_BCM_WIMAX is not set
> ++# CONFIG_FT1000 is not set
> ++
> ++#
> ++# Speakup console speech
> ++#
> ++# CONFIG_SPEAKUP is not set
> ++# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
> ++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
> ++
> ++#
> ++# Altera FPGA firmware download module
> ++#
> ++# CONFIG_ALTERA_STAPL is not set
> ++CONFIG_CLKDEV_LOOKUP=y
> ++CONFIG_CLKSRC_MMIO=y
> ++
> ++#
> ++# MXC support drivers
> ++#
> ++CONFIG_MXC_IPU=y
> ++CONFIG_MXC_IPU_V3=y
> ++CONFIG_MXC_IPU_V3H=y
> ++
> ++#
> ++# MXC SSI support
> ++#
> ++CONFIG_MXC_SSI=y
> ++
> ++#
> ++# MXC Digital Audio Multiplexer support
> ++#
> ++# CONFIG_MXC_DAM is not set
> ++
> ++#
> ++# MXC PMIC support
> ++#
> ++# CONFIG_MXC_PMIC_MC13783 is not set
> ++# CONFIG_MXC_PMIC_MC13892 is not set
> ++# CONFIG_MXC_PMIC_MC34704 is not set
> ++# CONFIG_MXC_PMIC_MC9SDZ60 is not set
> ++# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
> ++
> ++#
> ++# MXC Security Drivers
> ++#
> ++# CONFIG_MXC_SECURITY_SCC is not set
> ++# CONFIG_MXC_SECURITY_RNG is not set
> ++
> ++#
> ++# MXC MPEG4 Encoder Kernel module support
> ++#
> ++# CONFIG_MXC_HMP4E is not set
> ++
> ++#
> ++# MXC HARDWARE EVENT
> ++#
> ++# CONFIG_MXC_HWEVENT is not set
> ++
> ++#
> ++# MXC VPU(Video Processing Unit) support
> ++#
> ++CONFIG_MXC_VPU=y
> ++# CONFIG_MXC_VPU_DEBUG is not set
> ++# CONFIG_MX6_VPU_352M is not set
> ++
> ++#
> ++# MXC Asynchronous Sample Rate Converter support
> ++#
> ++CONFIG_MXC_ASRC=y
> ++
> ++#
> ++# MXC Bluetooth support
> ++#
> ++
> ++#
> ++# Broadcom GPS ioctrl support
> ++#
> ++
> ++#
> ++# MXC Media Local Bus Driver
> ++#
> ++# CONFIG_MXC_MLB150 is not set
> ++
> ++#
> ++# i.MX ADC support
> ++#
> ++# CONFIG_IMX_ADC is not set
> ++
> ++#
> ++# MXC Vivante GPU support
> ++#
> ++CONFIG_MXC_GPU_VIV=y
> ++
> ++#
> ++# ANATOP_THERMAL
> ++#
> ++CONFIG_ANATOP_THERMAL=y
> ++
> ++#
> ++# MXC MIPI Support
> ++#
> ++# CONFIG_MXC_MIPI_CSI2 is not set
> ++
> ++#
> ++# MXC HDMI CEC (Consumer Electronics Control) support
> ++#
> ++# CONFIG_MXC_HDMI_CEC is not set
> ++
> ++#
> ++# File systems
> ++#
> ++CONFIG_EXT2_FS=y
> ++# CONFIG_EXT2_FS_XATTR is not set
> ++# CONFIG_EXT2_FS_XIP is not set
> ++CONFIG_EXT3_FS=y
> ++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
> ++# CONFIG_EXT3_FS_XATTR is not set
> ++# CONFIG_EXT4_FS is not set
> ++CONFIG_JBD=y
> ++# CONFIG_REISERFS_FS is not set
> ++# CONFIG_JFS_FS is not set
> ++# CONFIG_XFS_FS is not set
> ++# CONFIG_BTRFS_FS is not set
> ++# CONFIG_NILFS2_FS is not set
> ++# CONFIG_FS_POSIX_ACL is not set
> ++CONFIG_FILE_LOCKING=y
> ++CONFIG_FSNOTIFY=y
> ++# CONFIG_DNOTIFY is not set
> ++CONFIG_INOTIFY_USER=y
> ++# CONFIG_FANOTIFY is not set
> ++# CONFIG_QUOTA is not set
> ++# CONFIG_QUOTACTL is not set
> ++# CONFIG_AUTOFS4_FS is not set
> ++# CONFIG_FUSE_FS is not set
> ++
> ++#
> ++# Caches
> ++#
> ++# CONFIG_FSCACHE is not set
> ++
> ++#
> ++# CD-ROM/DVD Filesystems
> ++#
> ++# CONFIG_ISO9660_FS is not set
> ++# CONFIG_UDF_FS is not set
> ++
> ++#
> ++# DOS/FAT/NT Filesystems
> ++#
> ++CONFIG_FAT_FS=y
> ++# CONFIG_MSDOS_FS is not set
> ++CONFIG_VFAT_FS=y
> ++CONFIG_FAT_DEFAULT_CODEPAGE=437
> ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> ++# CONFIG_NTFS_FS is not set
> ++
> ++#
> ++# Pseudo filesystems
> ++#
> ++CONFIG_PROC_FS=y
> ++CONFIG_PROC_SYSCTL=y
> ++# CONFIG_PROC_PAGE_MONITOR is not set
> ++CONFIG_SYSFS=y
> ++# CONFIG_HUGETLB_PAGE is not set
> ++# CONFIG_CONFIGFS_FS is not set
> ++# CONFIG_MISC_FILESYSTEMS is not set
> ++# CONFIG_NETWORK_FILESYSTEMS is not set
> ++
> ++#
> ++# Partition Types
> ++#
> ++CONFIG_PARTITION_ADVANCED=y
> ++# CONFIG_ACORN_PARTITION is not set
> ++# CONFIG_OSF_PARTITION is not set
> ++# CONFIG_AMIGA_PARTITION is not set
> ++# CONFIG_ATARI_PARTITION is not set
> ++# CONFIG_MAC_PARTITION is not set
> ++CONFIG_MSDOS_PARTITION=y
> ++# CONFIG_BSD_DISKLABEL is not set
> ++# CONFIG_MINIX_SUBPARTITION is not set
> ++# CONFIG_SOLARIS_X86_PARTITION is not set
> ++# CONFIG_UNIXWARE_DISKLABEL is not set
> ++# CONFIG_LDM_PARTITION is not set
> ++# CONFIG_SGI_PARTITION is not set
> ++# CONFIG_ULTRIX_PARTITION is not set
> ++# CONFIG_SUN_PARTITION is not set
> ++# CONFIG_KARMA_PARTITION is not set
> ++CONFIG_EFI_PARTITION=y
> ++# CONFIG_SYSV68_PARTITION is not set
> ++CONFIG_NLS=y
> ++CONFIG_NLS_DEFAULT="iso8859-1"
> ++CONFIG_NLS_CODEPAGE_437=y
> ++# CONFIG_NLS_CODEPAGE_737 is not set
> ++# CONFIG_NLS_CODEPAGE_775 is not set
> ++# CONFIG_NLS_CODEPAGE_850 is not set
> ++# CONFIG_NLS_CODEPAGE_852 is not set
> ++# CONFIG_NLS_CODEPAGE_855 is not set
> ++# CONFIG_NLS_CODEPAGE_857 is not set
> ++# CONFIG_NLS_CODEPAGE_860 is not set
> ++# CONFIG_NLS_CODEPAGE_861 is not set
> ++# CONFIG_NLS_CODEPAGE_862 is not set
> ++# CONFIG_NLS_CODEPAGE_863 is not set
> ++# CONFIG_NLS_CODEPAGE_864 is not set
> ++# CONFIG_NLS_CODEPAGE_865 is not set
> ++# CONFIG_NLS_CODEPAGE_866 is not set
> ++# CONFIG_NLS_CODEPAGE_869 is not set
> ++# CONFIG_NLS_CODEPAGE_936 is not set
> ++# CONFIG_NLS_CODEPAGE_950 is not set
> ++# CONFIG_NLS_CODEPAGE_932 is not set
> ++# CONFIG_NLS_CODEPAGE_949 is not set
> ++# CONFIG_NLS_CODEPAGE_874 is not set
> ++# CONFIG_NLS_ISO8859_8 is not set
> ++# CONFIG_NLS_CODEPAGE_1250 is not set
> ++# CONFIG_NLS_CODEPAGE_1251 is not set
> ++# CONFIG_NLS_ASCII is not set
> ++CONFIG_NLS_ISO8859_1=y
> ++# CONFIG_NLS_ISO8859_2 is not set
> ++# CONFIG_NLS_ISO8859_3 is not set
> ++# CONFIG_NLS_ISO8859_4 is not set
> ++# CONFIG_NLS_ISO8859_5 is not set
> ++# CONFIG_NLS_ISO8859_6 is not set
> ++# CONFIG_NLS_ISO8859_7 is not set
> ++# CONFIG_NLS_ISO8859_9 is not set
> ++# CONFIG_NLS_ISO8859_13 is not set
> ++# CONFIG_NLS_ISO8859_14 is not set
> ++# CONFIG_NLS_ISO8859_15 is not set
> ++# CONFIG_NLS_KOI8_R is not set
> ++# CONFIG_NLS_KOI8_U is not set
> ++# CONFIG_NLS_UTF8 is not set
> ++
> ++#
> ++# Kernel hacking
> ++#
> ++CONFIG_PRINTK_TIME=y
> ++CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
> ++CONFIG_ENABLE_WARN_DEPRECATED=y
> ++CONFIG_ENABLE_MUST_CHECK=y
> ++CONFIG_FRAME_WARN=4096
> ++# CONFIG_MAGIC_SYSRQ is not set
> ++CONFIG_STRIP_ASM_SYMS=y
> ++# CONFIG_UNUSED_SYMBOLS is not set
> ++# CONFIG_DEBUG_FS is not set
> ++# CONFIG_HEADERS_CHECK is not set
> ++# CONFIG_DEBUG_SECTION_MISMATCH is not set
> ++# CONFIG_DEBUG_KERNEL is not set
> ++# CONFIG_HARDLOCKUP_DETECTOR is not set
> ++# CONFIG_SLUB_STATS is not set
> ++# CONFIG_SPARSE_RCU_POINTER is not set
> ++CONFIG_STACKTRACE=y
> ++# CONFIG_DEBUG_MEMORY_INIT is not set
> ++CONFIG_FRAME_POINTER=y
> ++CONFIG_RCU_CPU_STALL_TIMEOUT=60
> ++CONFIG_RCU_CPU_STALL_VERBOSE=y
> ++CONFIG_SYSCTL_SYSCALL_CHECK=y
> ++CONFIG_HAVE_FUNCTION_TRACER=y
> ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
> ++CONFIG_HAVE_DYNAMIC_FTRACE=y
> ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
> ++CONFIG_HAVE_C_RECORDMCOUNT=y
> ++CONFIG_TRACING_SUPPORT=y
> ++# CONFIG_FTRACE is not set
> ++# CONFIG_DMA_API_DEBUG is not set
> ++# CONFIG_ATOMIC64_SELFTEST is not set
> ++# CONFIG_SAMPLES is not set
> ++CONFIG_HAVE_ARCH_KGDB=y
> ++# CONFIG_TEST_KSTRTOX is not set
> ++# CONFIG_STRICT_DEVMEM is not set
> ++# CONFIG_ARM_UNWIND is not set
> ++# CONFIG_DEBUG_USER is not set
> ++CONFIG_OC_ETM=y
> ++
> ++#
> ++# Security options
> ++#
> ++# CONFIG_KEYS is not set
> ++# CONFIG_SECURITY_DMESG_RESTRICT is not set
> ++# CONFIG_SECURITY is not set
> ++# CONFIG_SECURITYFS is not set
> ++CONFIG_DEFAULT_SECURITY_DAC=y
> ++CONFIG_DEFAULT_SECURITY=""
> ++CONFIG_CRYPTO=y
> ++
> ++#
> ++# Crypto core or helper
> ++#
> ++CONFIG_CRYPTO_ALGAPI=y
> ++CONFIG_CRYPTO_ALGAPI2=y
> ++CONFIG_CRYPTO_AEAD2=y
> ++CONFIG_CRYPTO_BLKCIPHER=y
> ++CONFIG_CRYPTO_BLKCIPHER2=y
> ++CONFIG_CRYPTO_HASH2=y
> ++CONFIG_CRYPTO_RNG2=y
> ++CONFIG_CRYPTO_PCOMP2=y
> ++CONFIG_CRYPTO_MANAGER=y
> ++CONFIG_CRYPTO_MANAGER2=y
> ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
> ++# CONFIG_CRYPTO_GF128MUL is not set
> ++# CONFIG_CRYPTO_NULL is not set
> ++# CONFIG_CRYPTO_PCRYPT is not set
> ++CONFIG_CRYPTO_WORKQUEUE=y
> ++# CONFIG_CRYPTO_CRYPTD is not set
> ++# CONFIG_CRYPTO_AUTHENC is not set
> ++# CONFIG_CRYPTO_TEST is not set
> ++# CONFIG_CRYPTO_CRYPTODEV is not set
> ++
> ++#
> ++# Authenticated Encryption with Associated Data
> ++#
> ++# CONFIG_CRYPTO_CCM is not set
> ++# CONFIG_CRYPTO_GCM is not set
> ++# CONFIG_CRYPTO_SEQIV is not set
> ++
> ++#
> ++# Block modes
> ++#
> ++# CONFIG_CRYPTO_CBC is not set
> ++# CONFIG_CRYPTO_CTR is not set
> ++# CONFIG_CRYPTO_CTS is not set
> ++CONFIG_CRYPTO_ECB=y
> ++# CONFIG_CRYPTO_LRW is not set
> ++# CONFIG_CRYPTO_PCBC is not set
> ++# CONFIG_CRYPTO_XTS is not set
> ++
> ++#
> ++# Hash modes
> ++#
> ++# CONFIG_CRYPTO_HMAC is not set
> ++# CONFIG_CRYPTO_XCBC is not set
> ++# CONFIG_CRYPTO_VMAC is not set
> ++
> ++#
> ++# Digest
> ++#
> ++# CONFIG_CRYPTO_CRC32C is not set
> ++# CONFIG_CRYPTO_GHASH is not set
> ++# CONFIG_CRYPTO_MD4 is not set
> ++# CONFIG_CRYPTO_MD5 is not set
> ++# CONFIG_CRYPTO_MICHAEL_MIC is not set
> ++# CONFIG_CRYPTO_RMD128 is not set
> ++# CONFIG_CRYPTO_RMD160 is not set
> ++# CONFIG_CRYPTO_RMD256 is not set
> ++# CONFIG_CRYPTO_RMD320 is not set
> ++# CONFIG_CRYPTO_SHA1 is not set
> ++# CONFIG_CRYPTO_SHA256 is not set
> ++# CONFIG_CRYPTO_SHA512 is not set
> ++# CONFIG_CRYPTO_TGR192 is not set
> ++# CONFIG_CRYPTO_WP512 is not set
> ++
> ++#
> ++# Ciphers
> ++#
> ++CONFIG_CRYPTO_AES=y
> ++# CONFIG_CRYPTO_ANUBIS is not set
> ++# CONFIG_CRYPTO_ARC4 is not set
> ++# CONFIG_CRYPTO_BLOWFISH is not set
> ++# CONFIG_CRYPTO_CAMELLIA is not set
> ++# CONFIG_CRYPTO_CAST5 is not set
> ++# CONFIG_CRYPTO_CAST6 is not set
> ++# CONFIG_CRYPTO_DES is not set
> ++# CONFIG_CRYPTO_FCRYPT is not set
> ++# CONFIG_CRYPTO_KHAZAD is not set
> ++# CONFIG_CRYPTO_SALSA20 is not set
> ++# CONFIG_CRYPTO_SEED is not set
> ++# CONFIG_CRYPTO_SERPENT is not set
> ++# CONFIG_CRYPTO_TEA is not set
> ++# CONFIG_CRYPTO_TWOFISH is not set
> ++
> ++#
> ++# Compression
> ++#
> ++# CONFIG_CRYPTO_DEFLATE is not set
> ++# CONFIG_CRYPTO_ZLIB is not set
> ++# CONFIG_CRYPTO_LZO is not set
> ++
> ++#
> ++# Random Number Generation
> ++#
> ++# CONFIG_CRYPTO_ANSI_CPRNG is not set
> ++# CONFIG_CRYPTO_USER_API_HASH is not set
> ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
> ++# CONFIG_CRYPTO_HW is not set
> ++# CONFIG_BINARY_PRINTF is not set
> ++
> ++#
> ++# Library routines
> ++#
> ++CONFIG_BITREVERSE=y
> ++CONFIG_RATIONAL=y
> ++# CONFIG_CRC_CCITT is not set
> ++CONFIG_CRC16=y
> ++# CONFIG_CRC_T10DIF is not set
> ++# CONFIG_CRC_ITU_T is not set
> ++CONFIG_CRC32=y
> ++# CONFIG_CRC7 is not set
> ++# CONFIG_LIBCRC32C is not set
> ++# CONFIG_XZ_DEC is not set
> ++# CONFIG_XZ_DEC_BCJ is not set
> ++CONFIG_GENERIC_ALLOCATOR=y
> ++CONFIG_HAS_IOMEM=y
> ++CONFIG_HAS_IOPORT=y
> ++CONFIG_HAS_DMA=y
> ++CONFIG_CPU_RMAP=y
> ++CONFIG_NLATTR=y
> ++# CONFIG_AVERAGE is not set
> +diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
> +index 2ffd90d..e49c56f 100644
> +--- a/arch/arm/mach-mx6/Kconfig
> ++++ b/arch/arm/mach-mx6/Kconfig
> +@@ -251,6 +251,47 @@ config MACH_MX6Q_SABREAUTO
> + Include support for i.MX 6Quad SABRE Auto platform. This includes specific
> + configurations for the board and its peripherals.
> +
> ++config MACH_WANDBOARD
> ++ bool "Support for the WandBoard"
> ++ select ARCH_MX6Q
> ++ select SOC_IMX6Q
> ++ select IMX_HAVE_PLATFORM_DMA if IMX_SDMA
> ++ select IMX_HAVE_PLATFORM_IMX_UART if SERIAL_IMX
> ++ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX if MMC_SDHCI_ESDHC_IMX
> ++ select IMX_HAVE_PLATFORM_IMX_I2C if I2C_IMX
> ++ select IMX_HAVE_PLATFORM_IMX_ASRC if SND_IMX_SOC
> ++ select ARCH_MXC_AUDMUX_V2 if SND_IMX_SOC
> ++ select IMX_HAVE_PLATFORM_IMX_SSI if MXC_SSI
> ++ select IMX_HAVE_PLATFORM_IMX_ESAI if MXC_SSI
> ++ select IMX_HAVE_PLATFORM_IMX_SPDIF if SND_SOC_IMX_SPDIF
> ++ select IMX_HAVE_PLATFORM_FEC if NETDEVICES
> ++ select IMX_HAVE_PLATFORM_FSL_USB2_UDC if USB
> ++ select IMX_HAVE_PLATFORM_MXC_EHCI if USB
> ++ select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP if USB
> ++ select IMX_HAVE_PLATFORM_FSL_OTG if USB_OTG
> ++ select IMX_HAVE_PLATFORM_MXC_HDMI if FB_MXC_HDMI
> ++ select IMX_HAVE_PLATFORM_IMX_IPUV3 if MXC_IPU_V3
> ++ select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL if ANATOP_THERMAL
> ++ select IMX_HAVE_PLATFORM_IMX_PM if PM
> ++ select IMX_HAVE_PLATFORM_IMX_DVFS if CPU_FREQ_IMX
> ++ select IMX_HAVE_PLATFORM_SPI_IMX if SPI
> ++ select IMX_HAVE_PLATFORM_VIV_GPU if MXC_GPU_VIV
> ++ select IMX_HAVE_PLATFORM_IMX_VPU if MXC_VPU
> ++ select IMX_HAVE_PLATFORM_IMX_MIPI_DSI if VIDEO_MXC_IPU_OUTPUT
> ++ help
> ++ Include support for the WandBoard SoM.
> ++
> ++
> ++config WANDBOARD_BASE
> ++ tristate "Support for Wand baseboard"
> ++ depends on MACH_WANDBOARD
> ++ default y
> ++ help
> ++ Include support for the devices on the default wand baseboard.
> ++
> ++ If you have a standard Wandboard, say Y.
> ++
> ++
> + comment "MX6 Options:"
> +
> + config IMX_PCIE
> +diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile
> +index 5cac9bc..3f43098 100644
> +--- a/arch/arm/mach-mx6/Makefile
> ++++ b/arch/arm/mach-mx6/Makefile
> +@@ -14,6 +14,8 @@ obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o
> + obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o
> + obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o
> + obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o
> ++obj-$(CONFIG_MACH_WANDBOARD) += board-wand.o
> ++obj-$(CONFIG_WANDBOARD_BASE) += baseboard-wand.o
> + obj-$(CONFIG_SMP) += plat_hotplug.o platsmp.o headsmp.o
> + obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
> + obj-$(CONFIG_IMX_PCIE) += pcie.o
> +diff --git a/arch/arm/mach-mx6/baseboard-wand.c b/arch/arm/mach-mx6/baseboard-wand.c
> +new file mode 100644
> +index 0000000..e9e9378
> +--- /dev/null
> ++++ b/arch/arm/mach-mx6/baseboard-wand.c
> +@@ -0,0 +1,137 @@
> ++
> ++#include <asm/mach/arch.h>
> ++
> ++#include <linux/clk.h>
> ++#include <linux/i2c.h>
> ++#include <linux/platform_device.h>
> ++#include <linux/regulator/fixed.h>
> ++#include <linux/regulator/machine.h>
> ++
> ++#include <mach/common.h>
> ++#include <mach/devices-common.h>
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * SGTL5000 Audio Codec
> ++ *
> ++ ****************************************************************************/
> ++
> ++static struct regulator_consumer_supply wandbase_sgtl5000_consumer_vdda = {
> ++ .supply = "VDDA",
> ++ .dev_name = "0-000a", /* Modified load time */
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct regulator_consumer_supply wandbase_sgtl5000_consumer_vddio = {
> ++ .supply = "VDDIO",
> ++ .dev_name = "0-000a", /* Modified load time */
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct regulator_init_data wandbase_sgtl5000_vdda_reg_initdata = {
> ++ .num_consumer_supplies = 1,
> ++ .consumer_supplies = &wandbase_sgtl5000_consumer_vdda,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct regulator_init_data wandbase_sgtl5000_vddio_reg_initdata = {
> ++ .num_consumer_supplies = 1,
> ++ .consumer_supplies = &wandbase_sgtl5000_consumer_vddio,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct fixed_voltage_config wandbase_sgtl5000_vdda_reg_config = {
> ++ .supply_name = "VDDA",
> ++ .microvolts = 2500000,
> ++ .gpio = -1,
> ++ .init_data = &wandbase_sgtl5000_vdda_reg_initdata,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct fixed_voltage_config wandbase_sgtl5000_vddio_reg_config = {
> ++ .supply_name = "VDDIO",
> ++ .microvolts = 3300000,
> ++ .gpio = -1,
> ++ .init_data = &wandbase_sgtl5000_vddio_reg_initdata,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct platform_device wandbase_sgtl5000_vdda_reg_devices = {
> ++ .name = "reg-fixed-voltage",
> ++ .id = 0,
> ++ .dev = {
> ++ .platform_data = &wandbase_sgtl5000_vdda_reg_config,
> ++ },
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct platform_device wandbase_sgtl5000_vddio_reg_devices = {
> ++ .name = "reg-fixed-voltage",
> ++ .id = 1,
> ++ .dev = {
> ++ .platform_data = &wandbase_sgtl5000_vddio_reg_config,
> ++ },
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct platform_device wandbase_audio_device = {
> ++ .name = "imx-sgtl5000",
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static const struct i2c_board_info wandbase_sgtl5000_i2c_data __initdata = {
> ++ I2C_BOARD_INFO("sgtl5000", 0x0a)
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static char wandbase_sgtl5000_dev_name[8] = "0-000a";
> ++
> ++extern struct mxc_audio_platform_data wand_audio_channel_data;
> ++
> ++static __init int wandbase_init_sgtl5000(void) {
> ++ int i2c_bus = 1; /* TODO: get this from the module. */
> ++
> ++ wandbase_sgtl5000_dev_name[0] = '0' + i2c_bus;
> ++ wandbase_sgtl5000_consumer_vdda.dev_name = wandbase_sgtl5000_dev_name;
> ++ wandbase_sgtl5000_consumer_vddio.dev_name = wandbase_sgtl5000_dev_name;
> ++
> ++ wandbase_audio_device.dev.platform_data = &wand_audio_channel_data;
> ++ platform_device_register(&wandbase_audio_device);
> ++
> ++ i2c_register_board_info(i2c_bus, &wandbase_sgtl5000_i2c_data, 1);
> ++ platform_device_register(&wandbase_sgtl5000_vdda_reg_devices);
> ++ platform_device_register(&wandbase_sgtl5000_vddio_reg_devices);
> ++ return 0;
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * main-function for wand baseboard
> ++ *
> ++ ****************************************************************************/
> ++
> ++static __init int wandbase_init(void) {
> ++ return wandbase_init_sgtl5000();
> ++}
> ++subsys_initcall(wandbase_init);
> ++
> ++static __exit void wandbase_exit(void) {
> ++ /* Actually, this cannot be unloaded. Or loaded as a module..? */
> ++}
> ++module_exit(wandbase_exit);
> ++
> ++MODULE_DESCRIPTION("Wand baseboard driver");
> ++MODULE_AUTHOR("Tapani <tapani@vmail.me>");
> ++MODULE_LICENSE("GPL");
> +diff --git a/arch/arm/mach-mx6/board-wand.c b/arch/arm/mach-mx6/board-wand.c
> +new file mode 100644
> +index 0000000..7f972eb
> +--- /dev/null
> ++++ b/arch/arm/mach-mx6/board-wand.c
> +@@ -0,0 +1,972 @@
> ++
> ++#include <asm/mach-types.h>
> ++#include <asm/mach/arch.h>
> ++#include <asm/mach/time.h>
> ++
> ++#include <linux/clk.h>
> ++#include <linux/delay.h>
> ++#include <linux/err.h>
> ++#include <linux/fec.h>
> ++#include <linux/i2c.h>
> ++#include <linux/kernel.h>
> ++#include <linux/memblock.h>
> ++#include <linux/phy.h>
> ++
> ++#include <mach/common.h>
> ++//#include <mach/devices-common.h>
> ++#include <mach/gpio.h>
> ++#include <mach/iomux-mx6dl.h>
> ++#include <mach/iomux-v3.h>
> ++#include <mach/mx6.h>
> ++
> ++#include "crm_regs.h"
> ++#include "devices-imx6q.h"
> ++#include "usb.h"
> ++//#include "cpu_op-mx6.h"
> ++
> ++#define WAND_BT_ON IMX_GPIO_NR(3, 13)
> ++#define WAND_BT_WAKE IMX_GPIO_NR(3, 14)
> ++#define WAND_BT_HOST_WAKE IMX_GPIO_NR(3, 15)
> ++
> ++#define WAND_RGMII_INT IMX_GPIO_NR(1, 28)
> ++#define WAND_RGMII_RST IMX_GPIO_NR(3, 29)
> ++
> ++#define WAND_SD1_CD IMX_GPIO_NR(1, 2)
> ++#define WAND_SD3_CD IMX_GPIO_NR(3, 9)
> ++#define WAND_SD3_WP IMX_GPIO_NR(1, 10)
> ++
> ++#define WAND_USB_OTG_OC IMX_GPIO_NR(1, 9)
> ++#define WAND_USB_OTG_PWR IMX_GPIO_NR(3, 22)
> ++#define WAND_USB_H1_OC IMX_GPIO_NR(3, 30)
> ++
> ++#define WAND_WL_REF_ON IMX_GPIO_NR(2, 29)
> ++#define WAND_WL_RST_N IMX_GPIO_NR(5, 2)
> ++#define WAND_WL_REG_ON IMX_GPIO_NR(1, 26)
> ++#define WAND_WL_HOST_WAKE IMX_GPIO_NR(1, 29)
> ++#define WAND_WL_WAKE IMX_GPIO_NR(1, 30)
> ++
> ++/* Syntactic sugar for pad configuration */
> ++#define WAND_SETUP_PADS(p) \
> ++ mxc_iomux_v3_setup_multiple_pads((p), ARRAY_SIZE(p))
> ++
> ++/* See arch/arm/plat-mxc/include/mach/iomux-mx6dl.h for definitions */
> ++
> ++/****************************************************************************
> ++ *
> ++ * DMA controller init
> ++ *
> ++ ****************************************************************************/
> ++
> ++static __init void wand_init_dma(void) {
> ++ imx6q_add_dma();
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * SD init
> ++ *
> ++ * SD1 is routed to EDM connector (external SD on wand baseboard)
> ++ * SD2 is WiFi
> ++ * SD3 is boot SD on the module
> ++ *
> ++ ****************************************************************************/
> ++
> ++/* For some reason, iomux_mx6dl.h does not define multiple speeds for
> ++ SD1 and SD2, so these don't have any speed switching. */
> ++static iomux_v3_cfg_t mx6dl_sd1_pads[] = {
> ++ MX6DL_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM,
> ++ MX6DL_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM,
> ++ MX6DL_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM,
> ++ MX6DL_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM,
> ++ MX6DL_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM,
> ++ MX6DL_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM,
> ++};
> ++
> ++static iomux_v3_cfg_t mx6dl_sd2_pads[] = {
> ++ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
> ++ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
> ++ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
> ++ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
> ++ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
> ++ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
> ++};
> ++
> ++
> ++#define MX6DL_USDHC_PAD_SETTING(id, speed) \
> ++mx6dl_sd##id##_##speed##mhz[] = { \
> ++ MX6DL_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ, \
> ++ MX6DL_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ, \
> ++ MX6DL_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ, \
> ++ MX6DL_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ, \
> ++ MX6DL_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ, \
> ++ MX6DL_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ, \
> ++}
> ++
> ++/* 50,100, and 200 MHz are supported for SD3 in iomux_mx6dl.h */
> ++static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(3, 50);
> ++static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(3, 100);
> ++static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(3, 200);
> ++
> ++enum sd_pad_mode {
> ++ SD_PAD_MODE_LOW_SPEED,
> ++ SD_PAD_MODE_MED_SPEED,
> ++ SD_PAD_MODE_HIGH_SPEED,
> ++};
> ++
> ++static int plt_sd_pad_change(unsigned int index, int clock)
> ++{
> ++ /* LOW speed is the default state of SD pads */
> ++ static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
> ++
> ++ iomux_v3_cfg_t *sd_pads_200mhz = NULL;
> ++ iomux_v3_cfg_t *sd_pads_100mhz = NULL;
> ++ iomux_v3_cfg_t *sd_pads_50mhz = NULL;
> ++
> ++ u32 sd_pads_200mhz_cnt;
> ++ u32 sd_pads_100mhz_cnt;
> ++ u32 sd_pads_50mhz_cnt;
> ++
> ++ switch (index) {
> ++ case 0:
> ++ sd_pads_50mhz = mx6dl_sd1_pads;
> ++ sd_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd1_pads);
> ++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_50mhz, sd_pads_50mhz_cnt);
> ++ break;
> ++ case 1:
> ++ sd_pads_50mhz = mx6dl_sd2_pads;
> ++ sd_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd2_pads);
> ++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_50mhz, sd_pads_50mhz_cnt);
> ++ break;
> ++ case 2:
> ++ sd_pads_200mhz = mx6dl_sd3_200mhz;
> ++ sd_pads_100mhz = mx6dl_sd3_100mhz;
> ++ sd_pads_50mhz = mx6dl_sd3_50mhz;
> ++
> ++ sd_pads_200mhz_cnt = ARRAY_SIZE(mx6dl_sd3_200mhz);
> ++ sd_pads_100mhz_cnt = ARRAY_SIZE(mx6dl_sd3_100mhz);
> ++ sd_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd3_50mhz);
> ++ break;
> ++ default:
> ++ printk(KERN_ERR "no such SD host controller index %d\n", index);
> ++ return -EINVAL;
> ++ }
> ++
> ++ if (clock > 100000000) {
> ++ if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
> ++ return 0;
> ++ BUG_ON(!sd_pads_200mhz);
> ++ pad_mode = SD_PAD_MODE_HIGH_SPEED;
> ++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_200mhz,
> ++ sd_pads_200mhz_cnt);
> ++ } else if (clock > 52000000) {
> ++ if (pad_mode == SD_PAD_MODE_MED_SPEED)
> ++ return 0;
> ++ BUG_ON(!sd_pads_100mhz);
> ++ pad_mode = SD_PAD_MODE_MED_SPEED;
> ++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_100mhz,
> ++ sd_pads_100mhz_cnt);
> ++ } else {
> ++ if (pad_mode == SD_PAD_MODE_LOW_SPEED)
> ++ return 0;
> ++ BUG_ON(!sd_pads_50mhz);
> ++ pad_mode = SD_PAD_MODE_LOW_SPEED;
> ++ return mxc_iomux_v3_setup_multiple_pads(sd_pads_50mhz,
> ++ sd_pads_50mhz_cnt);
> ++ }
> ++}
> ++
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static const struct esdhc_platform_data wand_sd_data[3] = {
> ++ {
> ++ .cd_gpio = WAND_SD1_CD,
> ++ .wp_gpio =-EINVAL,
> ++ .keep_power_at_suspend = 1,
> ++ .support_8bit = 0,
> ++ .platform_pad_change = plt_sd_pad_change,
> ++ }, {
> ++ .cd_gpio =-EINVAL,
> ++ .wp_gpio =-EINVAL,
> ++ .keep_power_at_suspend = 1,
> ++ .platform_pad_change = plt_sd_pad_change,
> ++ }, {
> ++ .cd_gpio = WAND_SD3_CD,
> ++ .wp_gpio = WAND_SD3_WP,
> ++ .keep_power_at_suspend = 1,
> ++ .support_8bit = 0,
> ++ .delay_line = 0,
> ++ .platform_pad_change = plt_sd_pad_change,
> ++ }
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void wand_init_sd(void) {
> ++ //int i;
> ++ /* Card Detect for SD1 & SD3, respectively */
> ++ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_2__GPIO_1_2);
> ++ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA9__GPIO_3_9);
> ++
> ++ /* Add mmc devices in reverse order, so mmc0 always is boot sd (SD3) */
> ++/* for (i=2; i>=0; i--) {
> ++ WAND_SETUP_PADS(wand_sd_pads[i][0]);
> ++ imx6q_add_sdhci_usdhc_imx(i, &wand_sd_data[i]);
> ++ } */
> ++
> ++ /* SD3 is first, speed is set to lowest to start */
> ++ WAND_SETUP_PADS(mx6dl_sd3_50mhz);
> ++ imx6q_add_sdhci_usdhc_imx(2, &wand_sd_data[2]);
> ++
> ++ WAND_SETUP_PADS(mx6dl_sd2_pads);
> ++ imx6q_add_sdhci_usdhc_imx(1, &wand_sd_data[1]);
> ++
> ++ WAND_SETUP_PADS(mx6dl_sd1_pads);
> ++ imx6q_add_sdhci_usdhc_imx(0, &wand_sd_data[0]);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * I2C
> ++ *
> ++ ****************************************************************************/
> ++
> ++static iomux_v3_cfg_t wand_i2c_pads[3][2] __initdata = {
> ++ {
> ++ MX6DL_PAD_EIM_D21__I2C1_SCL,
> ++ MX6DL_PAD_EIM_D28__I2C1_SDA,
> ++ }, {
> ++ MX6DL_PAD_KEY_COL3__I2C2_SCL,
> ++ MX6DL_PAD_KEY_ROW3__I2C2_SDA,
> ++ }, {
> ++ MX6DL_PAD_GPIO_5__I2C3_SCL,
> ++ MX6DL_PAD_GPIO_16__I2C3_SDA
> ++ }
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct imxi2c_platform_data wand_i2c_data[] = {
> ++ { .bitrate = 100000, },
> ++ { .bitrate = 400000, },
> ++ { .bitrate = 400000, },
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void __init wand_init_i2c(void) {
> ++ int i;
> ++ for (i=0; i<3; i++) {
> ++ WAND_SETUP_PADS(wand_i2c_pads[i]);
> ++ imx6q_add_imx_i2c(i, &wand_i2c_data[i]);
> ++ }
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * Initialize debug console (UART1)
> ++ *
> ++ ****************************************************************************/
> ++
> ++static __initdata iomux_v3_cfg_t wand_uart_pads[] = {
> ++ /* UART1 (debug console) */
> ++ MX6DL_PAD_CSI0_DAT10__UART1_TXD,
> ++ MX6DL_PAD_CSI0_DAT11__UART1_RXD,
> ++ MX6DL_PAD_EIM_D19__UART1_CTS,
> ++ MX6DL_PAD_EIM_D20__UART1_RTS,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static __init void wand_init_uart(void) {
> ++ WAND_SETUP_PADS(wand_uart_pads);
> ++
> ++ imx6q_add_imx_uart(0, NULL);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * Initialize sound (SSI, ASRC, AUD3 channel and S/PDIF)
> ++ *
> ++ ****************************************************************************/
> ++
> ++static iomux_v3_cfg_t wand_audio_pads[] = {
> ++ MX6DL_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC,
> ++ MX6DL_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD,
> ++ MX6DL_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS,
> ++ MX6DL_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD,
> ++ MX6DL_PAD_GPIO_0__CCM_CLKO,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++extern struct mxc_audio_platform_data wand_audio_channel_data;
> ++
> ++/* This function is called as a callback from the audio channel data struct */
> ++static int wand_audio_clock_enable(void) {
> ++ struct clk *clko;
> ++ struct clk *new_parent;
> ++ int rate;
> ++
> ++ clko = clk_get(NULL, "clko_clk");
> ++ if (IS_ERR(clko)) return PTR_ERR(clko);
> ++
> ++ new_parent = clk_get(NULL, "ahb");
> ++ if (!IS_ERR(new_parent)) {
> ++ clk_set_parent(clko, new_parent);
> ++ clk_put(new_parent);
> ++ }
> ++
> ++ rate = clk_round_rate(clko, 16000000);
> ++ if (rate < 8000000 || rate > 27000000) {
> ++ pr_err("SGTL5000: mclk freq %d out of range!\n", rate);
> ++ clk_put(clko);
> ++ return -1;
> ++ }
> ++
> ++ wand_audio_channel_data.sysclk = rate;
> ++ clk_set_rate(clko, rate);
> ++ clk_enable(clko);
> ++
> ++ return 0;
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++/* This struct is added by the baseboard when initializing the codec */
> ++struct mxc_audio_platform_data wand_audio_channel_data = {
> ++ .ssi_num = 1,
> ++ .src_port = 2,
> ++ .ext_port = 3, /* audio channel: 3=AUD3. TODO: EDM */
> ++ .init = wand_audio_clock_enable,
> ++ .hp_gpio = -1,
> ++};
> ++EXPORT_SYMBOL_GPL(wand_audio_channel_data); /* TODO: edm naming? */
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static int wand_set_spdif_clk_rate(struct clk *clk, unsigned long rate) {
> ++ unsigned long rate_actual;
> ++ rate_actual = clk_round_rate(clk, rate);
> ++ clk_set_rate(clk, rate_actual);
> ++ return 0;
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct mxc_spdif_platform_data wand_spdif = {
> ++ .spdif_tx = 1, /* enable tx */
> ++ .spdif_rx = 1, /* enable rx */
> ++ .spdif_clk_44100 = 1, /* tx clk from spdif0_clk_root */
> ++ .spdif_clk_48000 = 1, /* tx clk from spdif0_clk_root */
> ++ .spdif_div_44100 = 23,
> ++ .spdif_div_48000 = 37,
> ++ .spdif_div_32000 = 37,
> ++ .spdif_rx_clk = 0, /* rx clk from spdif stream */
> ++ .spdif_clk_set_rate = wand_set_spdif_clk_rate,
> ++ .spdif_clk = NULL, /* spdif bus clk */
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct imx_ssi_platform_data wand_ssi_pdata = {
> ++ .flags = IMX_SSI_DMA | IMX_SSI_SYN,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct imx_asrc_platform_data wand_asrc_data = {
> ++ .channel_bits = 4,
> ++ .clk_map_ver = 2,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++void __init wand_init_audio(void) {
> ++ WAND_SETUP_PADS(wand_audio_pads);
> ++
> ++ /* Sample rate converter is added together with audio */
> ++ wand_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
> ++ wand_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
> ++ imx6q_add_asrc(&wand_asrc_data);
> ++
> ++ imx6q_add_imx_ssi(1, &wand_ssi_pdata);
> ++ /* Enable SPDIF */
> ++
> ++ mxc_iomux_v3_setup_pad(MX6DL_PAD_ENET_RXD0__SPDIF_OUT1);
> ++
> ++ wand_spdif.spdif_core_clk = clk_get_sys("mxc_spdif.0", NULL);
> ++ clk_put(wand_spdif.spdif_core_clk);
> ++ imx6q_add_spdif(&wand_spdif);
> ++ imx6q_add_spdif_dai();
> ++ imx6q_add_spdif_audio_device();
> ++}
> ++
> ++
> ++/*****************************************************************************
> ++ *
> ++ * Init FEC and AR8031 PHY
> ++ *
> ++ *****************************************************************************/
> ++
> ++static iomux_v3_cfg_t wand_fec_pads[] = {
> ++ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
> ++ MX6DL_PAD_ENET_MDC__ENET_MDC,
> ++ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
> ++ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
> ++ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
> ++ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
> ++ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
> ++ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
> ++ MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
> ++ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
> ++ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
> ++ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
> ++ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
> ++ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
> ++ MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
> ++ MX6DL_PAD_ENET_TX_EN__GPIO_1_28,
> ++ MX6DL_PAD_EIM_D29__GPIO_3_29,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static int wand_fec_phy_init(struct phy_device *phydev) {
> ++ unsigned short val;
> ++
> ++ /* Enable AR8031 125MHz clk */
> ++ phy_write(phydev, 0x0d, 0x0007); /* Set device address to 7*/
> ++ phy_write(phydev, 0x00, 0x8000); /* Apply by soft reset */
> ++ udelay(500);
> ++
> ++ phy_write(phydev, 0x0e, 0x8016); /* set mmd reg */
> ++ phy_write(phydev, 0x0d, 0x4007); /* apply */
> ++
> ++ val = phy_read(phydev, 0xe);
> ++ val &= 0xffe3;
> ++ val |= 0x18;
> ++ phy_write(phydev, 0xe, val);
> ++ phy_write(phydev, 0x0d, 0x4007); /* Post data */
> ++
> ++ /* Introduce random tx clock delay. Why is this needed? */
> ++ phy_write(phydev, 0x1d, 0x5);
> ++ val = phy_read(phydev, 0x1e);
> ++ val |= 0x0100;
> ++ phy_write(phydev, 0x1e, val);
> ++
> ++ return 0;
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static int wand_fec_power_hibernate(struct phy_device *phydev) { return 0; }
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct fec_platform_data wand_fec_data __initdata = {
> ++ .init = wand_fec_phy_init,
> ++ .power_hibernate = wand_fec_power_hibernate,
> ++ .phy = PHY_INTERFACE_MODE_RGMII,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static __init void wand_init_ethernet(void) {
> ++ WAND_SETUP_PADS(wand_fec_pads);
> ++
> ++ gpio_request(WAND_RGMII_RST, "rgmii reset");
> ++ gpio_direction_output(WAND_RGMII_RST, 0);
> ++#ifdef CONFIG_FEC_1588
> ++ mxc_iomux_set_gpr_register(1, 21, 1, 1);
> ++#endif
> ++ msleep(10);
> ++ gpio_set_value(WAND_RGMII_RST, 1);
> ++ imx6_init_fec(wand_fec_data);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * USB
> ++ *
> ++ ****************************************************************************/
> ++
> ++static __initdata iomux_v3_cfg_t wand_usb_pads[] = {
> ++ MX6DL_PAD_GPIO_9__GPIO_1_9,
> ++ MX6DL_PAD_GPIO_1__USBOTG_ID,
> ++ MX6DL_PAD_EIM_D22__GPIO_3_22,
> ++ MX6DL_PAD_EIM_D30__GPIO_3_30
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void wand_usbotg_vbus(bool on) {
> ++ gpio_set_value_cansleep(WAND_USB_OTG_PWR, !on);
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static __init void wand_init_usb(void) {
> ++ WAND_SETUP_PADS(wand_usb_pads);
> ++
> ++ gpio_request(WAND_USB_OTG_OC, "otg oc");
> ++ gpio_direction_input(WAND_USB_OTG_OC);
> ++
> ++ gpio_request(WAND_USB_OTG_PWR, "otg pwr");
> ++ gpio_direction_output(WAND_USB_OTG_PWR, 0);
> ++
> ++ imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
> ++ mxc_iomux_set_gpr_register(1, 13, 1, 1);
> ++
> ++ mx6_set_otghost_vbus_func(wand_usbotg_vbus);
> ++
> ++ gpio_request(WAND_USB_H1_OC, "usbh1 oc");
> ++ gpio_direction_input(WAND_USB_H1_OC);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * IPU
> ++ *
> ++ ****************************************************************************/
> ++
> ++static struct imx_ipuv3_platform_data wand_ipu_data[] = {
> ++ {
> ++ .rev = 4,
> ++ .csi_clk[0] = "ccm_clk0",
> ++ }, {
> ++ .rev = 4,
> ++ .csi_clk[0] = "ccm_clk0",
> ++ },
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static __init void wand_init_ipu(void) {
> ++ imx6q_add_ipuv3(0, &wand_ipu_data[0]);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * HDMI
> ++ *
> ++ ****************************************************************************/
> ++
> ++static struct ipuv3_fb_platform_data wand_hdmi_fb[] = {
> ++ { /* hdmi framebuffer */
> ++ .disp_dev = "hdmi",
> ++ .interface_pix_fmt = IPU_PIX_FMT_RGB32,
> ++ .mode_str = "1920x1080@60",
> ++ .default_bpp = 32,
> ++ .int_clk = false,
> ++ }
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void wand_hdmi_init(int ipu_id, int disp_id) {
> ++ if ((unsigned)ipu_id > 1) ipu_id = 0;
> ++ if ((unsigned)disp_id > 1) disp_id = 0;
> ++
> ++ mxc_iomux_set_gpr_register(3, 2, 2, 2*ipu_id + disp_id);
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct fsl_mxc_hdmi_platform_data wand_hdmi_data = {
> ++ .init = wand_hdmi_init,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct fsl_mxc_hdmi_core_platform_data wand_hdmi_core_data = {
> ++ .ipu_id = 0,
> ++ .disp_id = 1,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static const struct i2c_board_info wand_hdmi_i2c_info = {
> ++ I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void wand_init_hdmi(void) {
> ++ i2c_register_board_info(0, &wand_hdmi_i2c_info, 1);
> ++ imx6q_add_mxc_hdmi_core(&wand_hdmi_core_data);
> ++ imx6q_add_mxc_hdmi(&wand_hdmi_data);
> ++ imx6q_add_ipuv3fb(0, wand_hdmi_fb);
> ++
> ++ /* Enable HDMI audio */
> ++ imx6q_add_hdmi_soc();
> ++ imx6q_add_hdmi_soc_dai();
> ++ mxc_iomux_set_gpr_register(0, 0, 1, 1);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * WiFi
> ++ *
> ++ ****************************************************************************/
> ++
> ++static __initdata iomux_v3_cfg_t wand_wifi_pads[] = {
> ++ /* ref_on, enable 32k clock */
> ++ MX6DL_PAD_EIM_EB1__GPIO_2_29,
> ++ /* Wifi reset (resets when low!) */
> ++ MX6DL_PAD_EIM_A25__GPIO_5_2,
> ++ /* reg on, signal to FDC6331L */
> ++ MX6DL_PAD_ENET_RXD1__GPIO_1_26,
> ++ /* host wake */
> ++ MX6DL_PAD_ENET_TXD1__GPIO_1_29,
> ++ /* wl wake - nc */
> ++ MX6DL_PAD_ENET_TXD0__GPIO_1_30,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++/* assumes SD/MMC pins are set; call after wand_init_sd() */
> ++static __init void wand_init_wifi(void) {
> ++ WAND_SETUP_PADS(wand_wifi_pads);
> ++
> ++ gpio_request(WAND_WL_RST_N, "wl_rst_n");
> ++ gpio_direction_output(WAND_WL_RST_N, 0);
> ++ msleep(11);
> ++ gpio_set_value(WAND_WL_RST_N, 1);
> ++
> ++ gpio_request(WAND_WL_REF_ON, "wl_ref_on");
> ++ gpio_direction_output(WAND_WL_REF_ON, 1);
> ++
> ++ gpio_request(WAND_WL_REG_ON, "wl_reg_on");
> ++ gpio_direction_output(WAND_WL_REG_ON, 1);
> ++
> ++ gpio_request(WAND_WL_WAKE, "wl_wake");
> ++ gpio_direction_output(WAND_WL_WAKE, 1);
> ++
> ++ gpio_request(WAND_WL_HOST_WAKE, "wl_host_wake");
> ++ gpio_direction_input(WAND_WL_HOST_WAKE);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * Bluetooth
> ++ *
> ++ ****************************************************************************/
> ++
> ++static __initdata iomux_v3_cfg_t wand_bt_pads[] = {
> ++ /* BT_ON, BT_WAKE and BT_HOST_WAKE */
> ++ MX6DL_PAD_EIM_DA13__GPIO_3_13,
> ++ MX6DL_PAD_EIM_DA14__GPIO_3_14,
> ++ MX6DL_PAD_EIM_DA15__GPIO_3_15,
> ++
> ++ /* AUD5 channel goes to BT */
> ++ MX6DL_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
> ++ MX6DL_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
> ++ MX6DL_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
> ++ MX6DL_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
> ++
> ++ /* Bluetooth is on UART3*/
> ++ MX6DL_PAD_EIM_D23__UART3_CTS,
> ++ MX6DL_PAD_EIM_D24__UART3_TXD,
> ++ MX6DL_PAD_EIM_D25__UART3_RXD,
> ++ MX6DL_PAD_EIM_EB3__UART3_RTS,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static const struct imxuart_platform_data wand_bt_uart_data = {
> ++ .flags = IMXUART_HAVE_RTSCTS | IMXUART_SDMA,
> ++ .dma_req_tx = MX6Q_DMA_REQ_UART3_TX,
> ++ .dma_req_rx = MX6Q_DMA_REQ_UART3_RX,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++/* This assumes wifi is initialized (chip has power) */
> ++static __init void wand_init_bluetooth(void) {
> ++ WAND_SETUP_PADS(wand_bt_pads);
> ++
> ++ imx6q_add_imx_uart(2, &wand_bt_uart_data);
> ++
> ++ gpio_request(WAND_BT_ON, "bt_on");
> ++ gpio_direction_output(WAND_BT_ON, 0);
> ++ msleep(11);
> ++ gpio_set_value(WAND_BT_ON, 1);
> ++
> ++ gpio_request(WAND_BT_WAKE, "bt_wake");
> ++ gpio_direction_output(WAND_BT_WAKE, 1);
> ++
> ++ gpio_request(WAND_BT_HOST_WAKE, "bt_host_wake");
> ++ gpio_direction_input(WAND_BT_WAKE);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * Power and thermal management
> ++ *
> ++ ****************************************************************************/
> ++
> ++extern bool enable_wait_mode;
> ++
> ++static const struct anatop_thermal_platform_data wand_thermal = {
> ++ .name = "anatop_thermal",
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void wand_suspend_enter(void) {
> ++ gpio_set_value(WAND_WL_WAKE, 0);
> ++ gpio_set_value(WAND_BT_WAKE, 0);
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void wand_suspend_exit(void) {
> ++ gpio_set_value(WAND_WL_WAKE, 1);
> ++ gpio_set_value(WAND_BT_WAKE, 1);
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static const struct pm_platform_data wand_pm_data = {
> ++ .name = "imx_pm",
> ++ .suspend_enter = wand_suspend_enter,
> ++ .suspend_exit = wand_suspend_exit,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static const struct mxc_dvfs_platform_data wand_dvfscore_data = {
> ++ .reg_id = "cpu_vddgp",
> ++ .clk1_id = "cpu_clk",
> ++ .clk2_id = "gpc_dvfs_clk",
> ++ .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
> ++ .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
> ++ .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
> ++ .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
> ++ .prediv_mask = 0x1F800,
> ++ .prediv_offset = 11,
> ++ .prediv_val = 3,
> ++ .div3ck_mask = 0xE0000000,
> ++ .div3ck_offset = 29,
> ++ .div3ck_val = 2,
> ++ .emac_val = 0x08,
> ++ .upthr_val = 25,
> ++ .dnthr_val = 9,
> ++ .pncthr_val = 33,
> ++ .upcnt_val = 10,
> ++ .dncnt_val = 10,
> ++ .delay_time = 80,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static __init void wand_init_pm(void) {
> ++ enable_wait_mode = false;
> ++ imx6q_add_anatop_thermal_imx(1, &wand_thermal);
> ++ imx6q_add_pm_imx(0, &wand_pm_data);
> ++ imx6q_add_dvfs_core(&wand_dvfscore_data);
> ++ imx6q_add_busfreq();
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * Expansion pin header GPIOs
> ++ *
> ++ ****************************************************************************/
> ++
> ++static __initdata iomux_v3_cfg_t wand_external_gpio_pads[] = {
> ++ MX6DL_PAD_EIM_DA11__GPIO_3_11,
> ++ MX6DL_PAD_EIM_D27__GPIO_3_27,
> ++ MX6DL_PAD_EIM_BCLK__GPIO_6_31,
> ++ MX6DL_PAD_ENET_RX_ER__GPIO_1_24,
> ++ MX6DL_PAD_SD3_RST__GPIO_7_8,
> ++ MX6DL_PAD_EIM_D26__GPIO_3_26,
> ++ MX6DL_PAD_EIM_DA8__GPIO_3_8,
> ++ MX6DL_PAD_GPIO_19__GPIO_4_5,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static __init void wand_init_external_gpios(void) {
> ++ WAND_SETUP_PADS(wand_external_gpio_pads);
> ++
> ++ gpio_request(IMX_GPIO_NR(3, 11), "external_gpio_0");
> ++ gpio_export(IMX_GPIO_NR(3, 11), true);
> ++ gpio_request(IMX_GPIO_NR(3, 27), "external_gpio_1");
> ++ gpio_export(IMX_GPIO_NR(3, 27), true);
> ++ gpio_request(IMX_GPIO_NR(6, 31), "external_gpio_2");
> ++ gpio_export(IMX_GPIO_NR(6, 31), true);
> ++ gpio_request(IMX_GPIO_NR(1, 24), "external_gpio_3");
> ++ gpio_export(IMX_GPIO_NR(1, 24), true);
> ++ gpio_request(IMX_GPIO_NR(7, 8), "external_gpio_4");
> ++ gpio_export(IMX_GPIO_NR(7, 8), true);
> ++ gpio_request(IMX_GPIO_NR(3, 26), "external_gpio_5");
> ++ gpio_export(IMX_GPIO_NR(3, 26), true);
> ++ gpio_request(IMX_GPIO_NR(3, 8), "external_gpio_6");
> ++ gpio_export(IMX_GPIO_NR(3, 8), true);
> ++ gpio_request(IMX_GPIO_NR(4, 5), "external_gpio_7");
> ++ gpio_export(IMX_GPIO_NR(4, 5), true);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * SPI - while not used on the Wandboard, the pins are routed out
> ++ *
> ++ ****************************************************************************/
> ++
> ++static __initdata iomux_v3_cfg_t wand_spi_pads[] = {
> ++ MX6DL_PAD_EIM_D16__ECSPI1_SCLK,
> ++ MX6DL_PAD_EIM_D17__ECSPI1_MISO,
> ++ MX6DL_PAD_EIM_D18__ECSPI1_MOSI,
> ++ MX6DL_PAD_EIM_EB2__GPIO_2_30,
> ++
> ++ MX6DL_PAD_EIM_CS0__ECSPI2_SCLK,
> ++ MX6DL_PAD_EIM_CS1__ECSPI2_MOSI,
> ++ MX6DL_PAD_EIM_OE__ECSPI2_MISO,
> ++ MX6DL_PAD_EIM_RW__GPIO_2_26,
> ++ MX6DL_PAD_EIM_LBA__GPIO_2_27,
> ++};
> ++/* The choice of using gpios for chipselect is deliberate,
> ++ there can be issues using the dedicated mux modes for cs.
> ++*/
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static const int wand_spi1_chipselect[] = { IMX_GPIO_NR(2, 30) };
> ++
> ++/* platform device */
> ++static const struct spi_imx_master wand_spi1_data = {
> ++ .chipselect = wand_spi1_chipselect,
> ++ .num_chipselect = ARRAY_SIZE(wand_spi1_chipselect),
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static const int wand_spi2_chipselect[] = { IMX_GPIO_NR(2, 26), IMX_GPIO_NR(2, 27) };
> ++
> ++static const struct spi_imx_master wand_spi2_data = {
> ++ .chipselect = wand_spi2_chipselect,
> ++ .num_chipselect = ARRAY_SIZE(wand_spi2_chipselect),
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void __init wand_init_spi(void) {
> ++ WAND_SETUP_PADS(wand_spi_pads);
> ++
> ++ imx6q_add_ecspi(0, &wand_spi1_data);
> ++ imx6q_add_ecspi(1, &wand_spi2_data);
> ++}
> ++
> ++
> ++/****************************************************************************
> ++ *
> ++ * Vivante GPU/VPU
> ++ *
> ++ ****************************************************************************/
> ++
> ++static const __initconst struct imx_viv_gpu_data wand_gpu_data = {
> ++ .phys_baseaddr = 0,
> ++ .iobase_3d = GPU_3D_ARB_BASE_ADDR,
> ++ .irq_3d = MXC_INT_GPU3D_IRQ,
> ++ .iobase_2d = GPU_2D_ARB_BASE_ADDR,
> ++ .irq_2d = MXC_INT_GPU2D_IRQ,
> ++ .iobase_vg = OPENVG_ARB_BASE_ADDR,
> ++ .irq_vg = MXC_INT_OPENVG_XAQ2,
> ++};
> ++
> ++static struct viv_gpu_platform_data wand_gpu_pdata = {
> ++ .reserved_mem_size = SZ_128M + SZ_64M - SZ_16M,
> ++};
> ++
> ++static __init void wand_init_gpu(void) {
> ++ imx_add_viv_gpu(&wand_gpu_data, &wand_gpu_pdata);
> ++ imx6q_add_vpu();
> ++ imx6q_add_v4l2_output(0);
> ++}
> ++
> ++/*****************************************************************************
> ++ *
> ++ * Init clocks and early boot console
> ++ *
> ++ *****************************************************************************/
> ++
> ++extern void __iomem *twd_base;
> ++
> ++static void __init wand_init_timer(void) {
> ++ struct clk *uart_clk;
> ++#ifdef CONFIG_LOCAL_TIMERS
> ++ twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
> ++#endif
> ++ mx6_clocks_init(32768, 24000000, 0, 0);
> ++
> ++ uart_clk = clk_get_sys("imx-uart.0", NULL);
> ++ early_console_setup(UART1_BASE_ADDR, uart_clk);
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static struct sys_timer wand_timer = {
> ++ .init = wand_init_timer,
> ++};
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++static void __init wand_reserve(void) {
> ++ phys_addr_t phys;
> ++
> ++ if (wand_gpu_pdata.reserved_mem_size) {
> ++ phys = memblock_alloc_base(wand_gpu_pdata.reserved_mem_size, SZ_4K, SZ_512M);
> ++ memblock_remove(phys, wand_gpu_pdata.reserved_mem_size);
> ++ wand_gpu_pdata.reserved_mem_base = phys;
> ++ }
> ++}
> ++
> ++/*****************************************************************************
> ++ *
> ++ * BOARD INIT
> ++ *
> ++ *****************************************************************************/
> ++
> ++static void __init wand_board_init(void) {
> ++ wand_init_dma();
> ++ wand_init_uart();
> ++ wand_init_sd();
> ++ wand_init_i2c();
> ++ wand_init_audio();
> ++ wand_init_ethernet();
> ++ wand_init_usb();
> ++ wand_init_ipu();
> ++ imx6q_add_imx_snvs_rtc();
> ++ wand_init_hdmi();
> ++ wand_init_wifi();
> ++ wand_init_bluetooth();
> ++ wand_init_pm();
> ++ wand_init_external_gpios();
> ++ wand_init_spi();
> ++ wand_init_gpu();
> ++}
> ++
> ++/* ------------------------------------------------------------------------ */
> ++
> ++MACHINE_START(WANDBOARD, "Wandboard")
> ++ .boot_params = MX6_PHYS_OFFSET + 0x100,
> ++ .map_io = mx6_map_io,
> ++ .init_irq = mx6_init_irq,
> ++ .init_machine = wand_board_init,
> ++ .timer = &wand_timer,
> ++ .reserve = wand_reserve,
> ++MACHINE_END
> ++
> +diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
> +index 88210d9..5b4c1be 100644
> +--- a/arch/arm/tools/mach-types
> ++++ b/arch/arm/tools/mach-types
> +@@ -1119,4 +1119,5 @@ mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980
> + mx6q_arm2 MACH_MX6Q_ARM2 MX6Q_ARM2 3837
> + mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091
> + mx6sl_evk MACH_MX6SL_EVK MX6SL_EVK 4307
> ++wandboard MACH_WANDBOARD WANDBOARD 4412
> +
> +--
> +1.7.9.5
> +
> diff --git a/recipes-kernel/linux/linux-imx-3.0.35/wandboard-dual/defconfig b/recipes-kernel/linux/linux-imx-3.0.35/wandboard-dual/defconfig
> new file mode 100644
> index 0000000..cbc3c34
> --- /dev/null
> +++ b/recipes-kernel/linux/linux-imx-3.0.35/wandboard-dual/defconfig
> @@ -0,0 +1,2762 @@
> +#
> +# Automatically generated make config: don't edit
> +# Linux/arm 3.0.35 Kernel Configuration
> +#
> +CONFIG_ARM=y
> +CONFIG_HAVE_PWM=y
> +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> +CONFIG_HAVE_SCHED_CLOCK=y
> +CONFIG_GENERIC_GPIO=y
> +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
> +CONFIG_GENERIC_CLOCKEVENTS=y
> +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
> +CONFIG_KTIME_SCALAR=y
> +CONFIG_HAVE_PROC_CPU=y
> +CONFIG_STACKTRACE_SUPPORT=y
> +CONFIG_LOCKDEP_SUPPORT=y
> +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> +CONFIG_HARDIRQS_SW_RESEND=y
> +CONFIG_GENERIC_IRQ_PROBE=y
> +CONFIG_GENERIC_LOCKBREAK=y
> +CONFIG_RWSEM_GENERIC_SPINLOCK=y
> +CONFIG_ARCH_HAS_CPUFREQ=y
> +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
> +CONFIG_GENERIC_HWEIGHT=y
> +CONFIG_GENERIC_CALIBRATE_DELAY=y
> +CONFIG_ZONE_DMA=y
> +CONFIG_NEED_DMA_MAP_STATE=y
> +CONFIG_FIQ=y
> +CONFIG_VECTORS_BASE=0xffff0000
> +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
> +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> +CONFIG_HAVE_IRQ_WORK=y
> +CONFIG_IRQ_WORK=y
> +
> +#
> +# General setup
> +#
> +CONFIG_EXPERIMENTAL=y
> +CONFIG_INIT_ENV_ARG_LIMIT=32
> +CONFIG_CROSS_COMPILE=""
> +CONFIG_LOCALVERSION="-1.1.0+yocto"
> +CONFIG_LOCALVERSION_AUTO=y
> +CONFIG_HAVE_KERNEL_GZIP=y
> +CONFIG_HAVE_KERNEL_LZMA=y
> +CONFIG_HAVE_KERNEL_LZO=y
> +CONFIG_KERNEL_GZIP=y
> +# CONFIG_KERNEL_LZMA is not set
> +# CONFIG_KERNEL_LZO is not set
> +CONFIG_DEFAULT_HOSTNAME="(none)"
> +CONFIG_SWAP=y
> +CONFIG_SYSVIPC=y
> +CONFIG_SYSVIPC_SYSCTL=y
> +# CONFIG_POSIX_MQUEUE is not set
> +# CONFIG_BSD_PROCESS_ACCT is not set
> +# CONFIG_FHANDLE is not set
> +# CONFIG_TASKSTATS is not set
> +# CONFIG_AUDIT is not set
> +CONFIG_HAVE_GENERIC_HARDIRQS=y
> +
> +#
> +# IRQ subsystem
> +#
> +CONFIG_GENERIC_HARDIRQS=y
> +CONFIG_HAVE_SPARSE_IRQ=y
> +CONFIG_GENERIC_IRQ_SHOW=y
> +# CONFIG_SPARSE_IRQ is not set
> +
> +#
> +# RCU Subsystem
> +#
> +CONFIG_TREE_PREEMPT_RCU=y
> +CONFIG_PREEMPT_RCU=y
> +# CONFIG_RCU_TRACE is not set
> +CONFIG_RCU_FANOUT=32
> +# CONFIG_RCU_FANOUT_EXACT is not set
> +# CONFIG_TREE_RCU_TRACE is not set
> +# CONFIG_RCU_BOOST is not set
> +CONFIG_IKCONFIG=y
> +CONFIG_IKCONFIG_PROC=y
> +CONFIG_LOG_BUF_SHIFT=14
> +CONFIG_CGROUPS=y
> +# CONFIG_CGROUP_DEBUG is not set
> +# CONFIG_CGROUP_FREEZER is not set
> +# CONFIG_CGROUP_DEVICE is not set
> +# CONFIG_CPUSETS is not set
> +# CONFIG_CGROUP_CPUACCT is not set
> +# CONFIG_RESOURCE_COUNTERS is not set
> +# CONFIG_CGROUP_PERF is not set
> +# CONFIG_CGROUP_SCHED is not set
> +# CONFIG_BLK_CGROUP is not set
> +# CONFIG_NAMESPACES is not set
> +# CONFIG_SCHED_AUTOGROUP is not set
> +# CONFIG_SYSFS_DEPRECATED is not set
> +# CONFIG_RELAY is not set
> +# CONFIG_BLK_DEV_INITRD is not set
> +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
> +CONFIG_SYSCTL=y
> +CONFIG_ANON_INODES=y
> +CONFIG_EXPERT=y
> +CONFIG_UID16=y
> +CONFIG_SYSCTL_SYSCALL=y
> +CONFIG_KALLSYMS=y
> +CONFIG_HOTPLUG=y
> +CONFIG_PRINTK=y
> +CONFIG_BUG=y
> +CONFIG_ELF_CORE=y
> +CONFIG_BASE_FULL=y
> +CONFIG_FUTEX=y
> +CONFIG_EPOLL=y
> +CONFIG_SIGNALFD=y
> +CONFIG_TIMERFD=y
> +CONFIG_EVENTFD=y
> +CONFIG_SHMEM=y
> +CONFIG_AIO=y
> +CONFIG_EMBEDDED=y
> +CONFIG_HAVE_PERF_EVENTS=y
> +CONFIG_PERF_USE_VMALLOC=y
> +
> +#
> +# Kernel Performance Events And Counters
> +#
> +CONFIG_PERF_EVENTS=y
> +# CONFIG_PERF_COUNTERS is not set
> +CONFIG_VM_EVENT_COUNTERS=y
> +CONFIG_SLUB_DEBUG=y
> +CONFIG_COMPAT_BRK=y
> +# CONFIG_SLAB is not set
> +CONFIG_SLUB=y
> +# CONFIG_SLOB is not set
> +# CONFIG_PROFILING is not set
> +CONFIG_HAVE_OPROFILE=y
> +# CONFIG_KPROBES is not set
> +CONFIG_HAVE_KPROBES=y
> +CONFIG_HAVE_KRETPROBES=y
> +CONFIG_USE_GENERIC_SMP_HELPERS=y
> +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
> +CONFIG_HAVE_CLK=y
> +CONFIG_HAVE_DMA_API_DEBUG=y
> +CONFIG_HAVE_HW_BREAKPOINT=y
> +
> +#
> +# GCOV-based kernel profiling
> +#
> +# CONFIG_GCOV_KERNEL is not set
> +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> +CONFIG_SLABINFO=y
> +CONFIG_RT_MUTEXES=y
> +CONFIG_BASE_SMALL=0
> +CONFIG_MODULES=y
> +# CONFIG_MODULE_FORCE_LOAD is not set
> +CONFIG_MODULE_UNLOAD=y
> +CONFIG_MODULE_FORCE_UNLOAD=y
> +CONFIG_MODVERSIONS=y
> +# CONFIG_MODULE_SRCVERSION_ALL is not set
> +CONFIG_STOP_MACHINE=y
> +CONFIG_BLOCK=y
> +CONFIG_LBDAF=y
> +# CONFIG_BLK_DEV_BSG is not set
> +# CONFIG_BLK_DEV_INTEGRITY is not set
> +
> +#
> +# IO Schedulers
> +#
> +CONFIG_IOSCHED_NOOP=y
> +CONFIG_IOSCHED_DEADLINE=y
> +CONFIG_IOSCHED_CFQ=y
> +# CONFIG_DEFAULT_DEADLINE is not set
> +CONFIG_DEFAULT_CFQ=y
> +# CONFIG_DEFAULT_NOOP is not set
> +CONFIG_DEFAULT_IOSCHED="cfq"
> +# CONFIG_INLINE_SPIN_TRYLOCK is not set
> +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
> +# CONFIG_INLINE_SPIN_LOCK is not set
> +# CONFIG_INLINE_SPIN_LOCK_BH is not set
> +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
> +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
> +# CONFIG_INLINE_SPIN_UNLOCK is not set
> +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
> +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
> +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
> +# CONFIG_INLINE_READ_TRYLOCK is not set
> +# CONFIG_INLINE_READ_LOCK is not set
> +# CONFIG_INLINE_READ_LOCK_BH is not set
> +# CONFIG_INLINE_READ_LOCK_IRQ is not set
> +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
> +# CONFIG_INLINE_READ_UNLOCK is not set
> +# CONFIG_INLINE_READ_UNLOCK_BH is not set
> +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
> +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
> +# CONFIG_INLINE_WRITE_TRYLOCK is not set
> +# CONFIG_INLINE_WRITE_LOCK is not set
> +# CONFIG_INLINE_WRITE_LOCK_BH is not set
> +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
> +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
> +# CONFIG_INLINE_WRITE_UNLOCK is not set
> +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
> +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
> +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
> +CONFIG_MUTEX_SPIN_ON_OWNER=y
> +CONFIG_FREEZER=y
> +
> +#
> +# System Type
> +#
> +CONFIG_MMU=y
> +# CONFIG_ARCH_INTEGRATOR is not set
> +# CONFIG_ARCH_REALVIEW is not set
> +# CONFIG_ARCH_VERSATILE is not set
> +# CONFIG_ARCH_VEXPRESS is not set
> +# CONFIG_ARCH_AT91 is not set
> +# CONFIG_ARCH_BCMRING is not set
> +# CONFIG_ARCH_CLPS711X is not set
> +# CONFIG_ARCH_CNS3XXX is not set
> +# CONFIG_ARCH_GEMINI is not set
> +# CONFIG_ARCH_EBSA110 is not set
> +# CONFIG_ARCH_EP93XX is not set
> +# CONFIG_ARCH_FOOTBRIDGE is not set
> +CONFIG_ARCH_MXC=y
> +# CONFIG_ARCH_MXS is not set
> +# CONFIG_ARCH_NETX is not set
> +# CONFIG_ARCH_H720X is not set
> +# CONFIG_ARCH_IOP13XX is not set
> +# CONFIG_ARCH_IOP32X is not set
> +# CONFIG_ARCH_IOP33X is not set
> +# CONFIG_ARCH_IXP23XX is not set
> +# CONFIG_ARCH_IXP2000 is not set
> +# CONFIG_ARCH_IXP4XX is not set
> +# CONFIG_ARCH_DOVE is not set
> +# CONFIG_ARCH_KIRKWOOD is not set
> +# CONFIG_ARCH_LOKI is not set
> +# CONFIG_ARCH_LPC32XX is not set
> +# CONFIG_ARCH_MV78XX0 is not set
> +# CONFIG_ARCH_ORION5X is not set
> +# CONFIG_ARCH_MMP is not set
> +# CONFIG_ARCH_KS8695 is not set
> +# CONFIG_ARCH_W90X900 is not set
> +# CONFIG_ARCH_NUC93X is not set
> +# CONFIG_ARCH_TEGRA is not set
> +# CONFIG_ARCH_PNX4008 is not set
> +# CONFIG_ARCH_PXA is not set
> +# CONFIG_ARCH_MSM is not set
> +# CONFIG_ARCH_SHMOBILE is not set
> +# CONFIG_ARCH_RPC is not set
> +# CONFIG_ARCH_SA1100 is not set
> +# CONFIG_ARCH_S3C2410 is not set
> +# CONFIG_ARCH_S3C64XX is not set
> +# CONFIG_ARCH_S5P64X0 is not set
> +# CONFIG_ARCH_S5PC100 is not set
> +# CONFIG_ARCH_S5PV210 is not set
> +# CONFIG_ARCH_EXYNOS4 is not set
> +# CONFIG_ARCH_SHARK is not set
> +# CONFIG_ARCH_TCC_926 is not set
> +# CONFIG_ARCH_U300 is not set
> +# CONFIG_ARCH_U8500 is not set
> +# CONFIG_ARCH_NOMADIK is not set
> +# CONFIG_ARCH_DAVINCI is not set
> +# CONFIG_ARCH_OMAP is not set
> +# CONFIG_PLAT_SPEAR is not set
> +# CONFIG_ARCH_VT8500 is not set
> +CONFIG_GPIO_PCA953X=y
> +# CONFIG_KEYBOARD_GPIO_POLLED is not set
> +CONFIG_IMX_HAVE_PLATFORM_DMA=y
> +CONFIG_IMX_HAVE_PLATFORM_MXC_MLB=y
> +CONFIG_IMX_HAVE_PLATFORM_FEC=y
> +CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
> +CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
> +CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
> +CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
> +CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
> +CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
> +CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
> +CONFIG_IMX_HAVE_PLATFORM_AHCI=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
> +CONFIG_IMX_HAVE_PLATFORM_PERFMON=y
> +CONFIG_IMX_HAVE_PLATFORM_LDB=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_PXP=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
> +CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
> +CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
> +CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
> +CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y
> +CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
> +
> +#
> +# Freescale MXC Implementations
> +#
> +# CONFIG_ARCH_MX1 is not set
> +# CONFIG_ARCH_MX2 is not set
> +# CONFIG_ARCH_MX25 is not set
> +# CONFIG_ARCH_MX3 is not set
> +# CONFIG_ARCH_MX503 is not set
> +# CONFIG_ARCH_MX51 is not set
> +CONFIG_ARCH_MX6=y
> +CONFIG_ARCH_MX6Q=y
> +CONFIG_FORCE_MAX_ZONEORDER=14
> +CONFIG_SOC_IMX6Q=y
> +CONFIG_MACH_MX6Q_ARM2=y
> +# CONFIG_MACH_MX6SL_ARM2 is not set
> +# CONFIG_MACH_MX6SL_EVK is not set
> +# CONFIG_MACH_MX6Q_SABRELITE is not set
> +# CONFIG_MACH_MX6Q_SABRESD is not set
> +# CONFIG_MACH_MX6Q_SABREAUTO is not set
> +CONFIG_MACH_WANDBOARD=y
> +CONFIG_WANDBOARD_BASE=y
> +
> +#
> +# MX6 Options:
> +#
> +# CONFIG_IMX_PCIE is not set
> +CONFIG_USB_EHCI_ARC_H1=y
> +CONFIG_USB_FSL_ARC_OTG=y
> +# CONFIG_MX6_INTER_LDO_BYPASS is not set
> +# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS is not set
> +CONFIG_ISP1504_MXC=y
> +# CONFIG_MXC_IRQ_PRIOR is not set
> +CONFIG_MXC_PWM=y
> +# CONFIG_MXC_DEBUG_BOARD is not set
> +CONFIG_MXC_REBOOT_MFGMODE=y
> +# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
> +CONFIG_ARCH_MXC_IOMUX_V3=y
> +CONFIG_ARCH_MXC_AUDMUX_V2=y
> +CONFIG_IRAM_ALLOC=y
> +CONFIG_CLK_DEBUG=y
> +CONFIG_DMA_ZONE_SIZE=184
> +
> +#
> +# System MMU
> +#
> +
> +#
> +# Processor Type
> +#
> +CONFIG_CPU_V7=y
> +CONFIG_CPU_32v6K=y
> +CONFIG_CPU_32v7=y
> +CONFIG_CPU_ABRT_EV7=y
> +CONFIG_CPU_PABRT_V7=y
> +CONFIG_CPU_CACHE_V7=y
> +CONFIG_CPU_CACHE_VIPT=y
> +CONFIG_CPU_COPY_V6=y
> +CONFIG_CPU_TLB_V7=y
> +CONFIG_CPU_HAS_ASID=y
> +CONFIG_CPU_CP15=y
> +CONFIG_CPU_CP15_MMU=y
> +
> +#
> +# Processor Features
> +#
> +CONFIG_ARM_THUMB=y
> +# CONFIG_ARM_THUMBEE is not set
> +# CONFIG_SWP_EMULATE is not set
> +# CONFIG_CPU_ICACHE_DISABLE is not set
> +# CONFIG_CPU_DCACHE_DISABLE is not set
> +# CONFIG_CPU_BPREDICT_DISABLE is not set
> +CONFIG_OUTER_CACHE=y
> +CONFIG_OUTER_CACHE_SYNC=y
> +CONFIG_CACHE_L2X0=y
> +CONFIG_CACHE_PL310=y
> +CONFIG_ARM_L1_CACHE_SHIFT=5
> +CONFIG_ARM_DMA_MEM_BUFFERABLE=y
> +CONFIG_CPU_HAS_PMU=y
> +# CONFIG_ARM_ERRATA_430973 is not set
> +# CONFIG_ARM_ERRATA_458693 is not set
> +# CONFIG_ARM_ERRATA_460075 is not set
> +# CONFIG_ARM_ERRATA_742230 is not set
> +# CONFIG_ARM_ERRATA_742231 is not set
> +# CONFIG_PL310_ERRATA_588369 is not set
> +# CONFIG_ARM_ERRATA_720789 is not set
> +# CONFIG_PL310_ERRATA_727915 is not set
> +CONFIG_ARM_ERRATA_743622=y
> +CONFIG_ARM_ERRATA_751472=y
> +# CONFIG_ARM_ERRATA_753970 is not set
> +CONFIG_ARM_ERRATA_754322=y
> +# CONFIG_ARM_ERRATA_754327 is not set
> +CONFIG_ARM_GIC=y
> +
> +#
> +# Bus support
> +#
> +CONFIG_ARM_AMBA=y
> +# CONFIG_PCI_SYSCALL is not set
> +# CONFIG_ARCH_SUPPORTS_MSI is not set
> +# CONFIG_PCCARD is not set
> +CONFIG_ARM_ERRATA_764369=y
> +# CONFIG_PL310_ERRATA_769419 is not set
> +
> +#
> +# Kernel Features
> +#
> +CONFIG_TICK_ONESHOT=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> +CONFIG_SMP=y
> +CONFIG_SMP_ON_UP=y
> +CONFIG_HAVE_ARM_SCU=y
> +CONFIG_HAVE_ARM_TWD=y
> +# CONFIG_VMSPLIT_3G is not set
> +CONFIG_VMSPLIT_2G=y
> +# CONFIG_VMSPLIT_1G is not set
> +CONFIG_PAGE_OFFSET=0x80000000
> +CONFIG_NR_CPUS=4
> +CONFIG_HOTPLUG_CPU=y
> +CONFIG_LOCAL_TIMERS=y
> +# CONFIG_PREEMPT_NONE is not set
> +# CONFIG_PREEMPT_VOLUNTARY is not set
> +CONFIG_PREEMPT=y
> +CONFIG_HZ=100
> +# CONFIG_THUMB2_KERNEL is not set
> +CONFIG_AEABI=y
> +# CONFIG_OABI_COMPAT is not set
> +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> +CONFIG_HAVE_ARCH_PFN_VALID=y
> +CONFIG_HIGHMEM=y
> +# CONFIG_HIGHPTE is not set
> +CONFIG_HW_PERF_EVENTS=y
> +CONFIG_SELECT_MEMORY_MODEL=y
> +CONFIG_FLATMEM_MANUAL=y
> +CONFIG_FLATMEM=y
> +CONFIG_FLAT_NODE_MEM_MAP=y
> +CONFIG_HAVE_MEMBLOCK=y
> +CONFIG_PAGEFLAGS_EXTENDED=y
> +CONFIG_SPLIT_PTLOCK_CPUS=4
> +CONFIG_COMPACTION=y
> +CONFIG_MIGRATION=y
> +# CONFIG_PHYS_ADDR_T_64BIT is not set
> +CONFIG_ZONE_DMA_FLAG=1
> +CONFIG_BOUNCE=y
> +CONFIG_VIRT_TO_BUS=y
> +CONFIG_KSM=y
> +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
> +# CONFIG_CLEANCACHE is not set
> +CONFIG_ALIGNMENT_TRAP=y
> +# CONFIG_UACCESS_WITH_MEMCPY is not set
> +# CONFIG_SECCOMP is not set
> +# CONFIG_CC_STACKPROTECTOR is not set
> +# CONFIG_DEPRECATED_PARAM_STRUCT is not set
> +
> +#
> +# Boot options
> +#
> +# CONFIG_USE_OF is not set
> +CONFIG_ZBOOT_ROM_TEXT=0x0
> +CONFIG_ZBOOT_ROM_BSS=0x0
> +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
> +CONFIG_CMDLINE_FROM_BOOTLOADER=y
> +# CONFIG_CMDLINE_EXTEND is not set
> +# CONFIG_CMDLINE_FORCE is not set
> +# CONFIG_XIP_KERNEL is not set
> +# CONFIG_KEXEC is not set
> +# CONFIG_CRASH_DUMP is not set
> +# CONFIG_AUTO_ZRELADDR is not set
> +
> +#
> +# CPU Power Management
> +#
> +
> +#
> +# CPU Frequency scaling
> +#
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_TABLE=y
> +CONFIG_CPU_FREQ_STAT=y
> +# CONFIG_CPU_FREQ_STAT_DETAILS is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
> +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
> +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> +CONFIG_CPU_FREQ_GOV_USERSPACE=y
> +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
> +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
> +CONFIG_CPU_FREQ_IMX=y
> +# CONFIG_CPU_IDLE is not set
> +
> +#
> +# Floating point emulation
> +#
> +
> +#
> +# At least one emulation must be selected
> +#
> +CONFIG_VFP=y
> +CONFIG_VFPv3=y
> +CONFIG_NEON=y
> +
> +#
> +# Userspace binary formats
> +#
> +CONFIG_BINFMT_ELF=y
> +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> +CONFIG_HAVE_AOUT=y
> +# CONFIG_BINFMT_AOUT is not set
> +# CONFIG_BINFMT_MISC is not set
> +
> +#
> +# Power management options
> +#
> +CONFIG_SUSPEND=y
> +# CONFIG_PM_TEST_SUSPEND is not set
> +CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
> +CONFIG_SUSPEND_FREEZER=y
> +CONFIG_PM_SLEEP=y
> +CONFIG_PM_SLEEP_SMP=y
> +CONFIG_PM_RUNTIME=y
> +CONFIG_PM=y
> +CONFIG_PM_DEBUG=y
> +# CONFIG_PM_ADVANCED_DEBUG is not set
> +CONFIG_CAN_PM_TRACE=y
> +CONFIG_APM_EMULATION=y
> +CONFIG_PM_RUNTIME_CLK=y
> +CONFIG_ARCH_SUSPEND_POSSIBLE=y
> +CONFIG_NET=y
> +
> +#
> +# Networking options
> +#
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_XFRM=y
> +# CONFIG_XFRM_USER is not set
> +# CONFIG_XFRM_SUB_POLICY is not set
> +# CONFIG_XFRM_MIGRATE is not set
> +# CONFIG_XFRM_STATISTICS is not set
> +# CONFIG_NET_KEY is not set
> +CONFIG_INET=y
> +CONFIG_IP_MULTICAST=y
> +# CONFIG_IP_ADVANCED_ROUTER is not set
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
> +# CONFIG_IP_PNP_RARP is not set
> +# CONFIG_NET_IPIP is not set
> +# CONFIG_NET_IPGRE_DEMUX is not set
> +# CONFIG_IP_MROUTE is not set
> +# CONFIG_ARPD is not set
> +# CONFIG_SYN_COOKIES is not set
> +# CONFIG_INET_AH is not set
> +# CONFIG_INET_ESP is not set
> +# CONFIG_INET_IPCOMP is not set
> +# CONFIG_INET_XFRM_TUNNEL is not set
> +# CONFIG_INET_TUNNEL is not set
> +CONFIG_INET_XFRM_MODE_TRANSPORT=y
> +CONFIG_INET_XFRM_MODE_TUNNEL=y
> +CONFIG_INET_XFRM_MODE_BEET=y
> +# CONFIG_INET_LRO is not set
> +CONFIG_INET_DIAG=y
> +CONFIG_INET_TCP_DIAG=y
> +# CONFIG_TCP_CONG_ADVANCED is not set
> +CONFIG_TCP_CONG_CUBIC=y
> +CONFIG_DEFAULT_TCP_CONG="cubic"
> +# CONFIG_TCP_MD5SIG is not set
> +# CONFIG_IPV6 is not set
> +# CONFIG_NETWORK_SECMARK is not set
> +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
> +CONFIG_NETFILTER=y
> +# CONFIG_NETFILTER_DEBUG is not set
> +CONFIG_NETFILTER_ADVANCED=y
> +
> +#
> +# Core Netfilter Configuration
> +#
> +# CONFIG_NETFILTER_NETLINK_QUEUE is not set
> +# CONFIG_NETFILTER_NETLINK_LOG is not set
> +# CONFIG_NF_CONNTRACK is not set
> +# CONFIG_NETFILTER_XTABLES is not set
> +# CONFIG_IP_VS is not set
> +
> +#
> +# IP: Netfilter Configuration
> +#
> +# CONFIG_NF_DEFRAG_IPV4 is not set
> +# CONFIG_IP_NF_QUEUE is not set
> +# CONFIG_IP_NF_IPTABLES is not set
> +# CONFIG_IP_NF_ARPTABLES is not set
> +# CONFIG_IP_DCCP is not set
> +# CONFIG_IP_SCTP is not set
> +# CONFIG_RDS is not set
> +# CONFIG_TIPC is not set
> +# CONFIG_ATM is not set
> +# CONFIG_L2TP is not set
> +# CONFIG_BRIDGE is not set
> +# CONFIG_NET_DSA is not set
> +# CONFIG_VLAN_8021Q is not set
> +# CONFIG_DECNET is not set
> +CONFIG_LLC=y
> +CONFIG_LLC2=y
> +# CONFIG_IPX is not set
> +# CONFIG_ATALK is not set
> +# CONFIG_X25 is not set
> +# CONFIG_LAPB is not set
> +# CONFIG_ECONET is not set
> +# CONFIG_WAN_ROUTER is not set
> +# CONFIG_PHONET is not set
> +# CONFIG_IEEE802154 is not set
> +# CONFIG_NET_SCHED is not set
> +# CONFIG_DCB is not set
> +# CONFIG_BATMAN_ADV is not set
> +CONFIG_RPS=y
> +CONFIG_RFS_ACCEL=y
> +CONFIG_XPS=y
> +
> +#
> +# Network testing
> +#
> +# CONFIG_NET_PKTGEN is not set
> +# CONFIG_HAMRADIO is not set
> +CONFIG_CAN=y
> +CONFIG_CAN_RAW=y
> +CONFIG_CAN_BCM=y
> +
> +#
> +# CAN Device Drivers
> +#
> +CONFIG_CAN_VCAN=y
> +# CONFIG_CAN_SLCAN is not set
> +CONFIG_CAN_DEV=y
> +CONFIG_CAN_CALC_BITTIMING=y
> +# CONFIG_CAN_MCP251X is not set
> +CONFIG_HAVE_CAN_FLEXCAN=y
> +CONFIG_CAN_FLEXCAN=y
> +# CONFIG_CAN_SJA1000 is not set
> +# CONFIG_CAN_C_CAN is not set
> +
> +#
> +# CAN USB interfaces
> +#
> +# CONFIG_CAN_EMS_USB is not set
> +# CONFIG_CAN_ESD_USB2 is not set
> +# CONFIG_CAN_SOFTING is not set
> +# CONFIG_CAN_DEBUG_DEVICES is not set
> +# CONFIG_IRDA is not set
> +CONFIG_BT=y
> +CONFIG_BT_L2CAP=y
> +CONFIG_BT_SCO=y
> +CONFIG_BT_RFCOMM=y
> +CONFIG_BT_RFCOMM_TTY=y
> +CONFIG_BT_BNEP=y
> +CONFIG_BT_BNEP_MC_FILTER=y
> +CONFIG_BT_BNEP_PROTO_FILTER=y
> +CONFIG_BT_HIDP=y
> +
> +#
> +# Bluetooth device drivers
> +#
> +CONFIG_BT_HCIBTUSB=y
> +# CONFIG_BT_HCIBTSDIO is not set
> +CONFIG_BT_HCIUART=y
> +# CONFIG_BT_HCIUART_H4 is not set
> +# CONFIG_BT_HCIUART_BCSP is not set
> +CONFIG_BT_HCIUART_ATH3K=y
> +# CONFIG_BT_HCIUART_LL is not set
> +# CONFIG_BT_HCIBCM203X is not set
> +# CONFIG_BT_HCIBPA10X is not set
> +# CONFIG_BT_HCIBFUSB is not set
> +CONFIG_BT_HCIVHCI=y
> +# CONFIG_BT_MRVL is not set
> +# CONFIG_BT_ATH3K is not set
> +# CONFIG_AF_RXRPC is not set
> +CONFIG_WIRELESS=y
> +CONFIG_WIRELESS_EXT=y
> +CONFIG_WEXT_CORE=y
> +CONFIG_WEXT_PROC=y
> +CONFIG_WEXT_SPY=y
> +CONFIG_WEXT_PRIV=y
> +CONFIG_CFG80211=y
> +# CONFIG_NL80211_TESTMODE is not set
> +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
> +# CONFIG_CFG80211_REG_DEBUG is not set
> +CONFIG_CFG80211_DEFAULT_PS=y
> +# CONFIG_CFG80211_DEBUGFS is not set
> +# CONFIG_CFG80211_INTERNAL_REGDB is not set
> +CONFIG_CFG80211_WEXT=y
> +CONFIG_WIRELESS_EXT_SYSFS=y
> +CONFIG_LIB80211=y
> +CONFIG_LIB80211_CRYPT_WEP=y
> +CONFIG_LIB80211_CRYPT_CCMP=y
> +CONFIG_LIB80211_CRYPT_TKIP=y
> +# CONFIG_LIB80211_DEBUG is not set
> +# CONFIG_MAC80211 is not set
> +# CONFIG_WIMAX is not set
> +CONFIG_RFKILL=y
> +CONFIG_RFKILL_LEDS=y
> +CONFIG_RFKILL_INPUT=y
> +# CONFIG_RFKILL_REGULATOR is not set
> +# CONFIG_RFKILL_GPIO is not set
> +# CONFIG_NET_9P is not set
> +# CONFIG_CAIF is not set
> +# CONFIG_CEPH_LIB is not set
> +
> +#
> +# Device Drivers
> +#
> +
> +#
> +# Generic Driver Options
> +#
> +CONFIG_UEVENT_HELPER_PATH=""
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +CONFIG_STANDALONE=y
> +CONFIG_PREVENT_FIRMWARE_BUILD=y
> +CONFIG_FW_LOADER=y
> +CONFIG_FIRMWARE_IN_KERNEL=y
> +CONFIG_EXTRA_FIRMWARE=""
> +# CONFIG_SYS_HYPERVISOR is not set
> +CONFIG_CONNECTOR=y
> +CONFIG_PROC_EVENTS=y
> +CONFIG_MTD=y
> +# CONFIG_MTD_DEBUG is not set
> +# CONFIG_MTD_TESTS is not set
> +# CONFIG_MTD_REDBOOT_PARTS is not set
> +CONFIG_MTD_CMDLINE_PARTS=y
> +# CONFIG_MTD_AFS_PARTS is not set
> +# CONFIG_MTD_AR7_PARTS is not set
> +
> +#
> +# User Modules And Translation Layers
> +#
> +CONFIG_MTD_CHAR=y
> +CONFIG_MTD_BLKDEVS=y
> +CONFIG_MTD_BLOCK=y
> +# CONFIG_FTL is not set
> +# CONFIG_NFTL is not set
> +# CONFIG_INFTL is not set
> +# CONFIG_RFD_FTL is not set
> +# CONFIG_SSFDC is not set
> +# CONFIG_SM_FTL is not set
> +# CONFIG_MTD_OOPS is not set
> +# CONFIG_MTD_SWAP is not set
> +
> +#
> +# RAM/ROM/Flash chip drivers
> +#
> +CONFIG_MTD_CFI=y
> +# CONFIG_MTD_JEDECPROBE is not set
> +CONFIG_MTD_GEN_PROBE=y
> +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
> +CONFIG_MTD_MAP_BANK_WIDTH_1=y
> +CONFIG_MTD_MAP_BANK_WIDTH_2=y
> +CONFIG_MTD_MAP_BANK_WIDTH_4=y
> +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> +CONFIG_MTD_CFI_I1=y
> +CONFIG_MTD_CFI_I2=y
> +# CONFIG_MTD_CFI_I4 is not set
> +# CONFIG_MTD_CFI_I8 is not set
> +# CONFIG_MTD_CFI_INTELEXT is not set
> +CONFIG_MTD_CFI_AMDSTD=y
> +# CONFIG_MTD_CFI_STAA is not set
> +CONFIG_MTD_CFI_UTIL=y
> +# CONFIG_MTD_RAM is not set
> +# CONFIG_MTD_ROM is not set
> +# CONFIG_MTD_ABSENT is not set
> +
> +#
> +# Mapping drivers for chip access
> +#
> +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> +CONFIG_MTD_PHYSMAP=y
> +# CONFIG_MTD_PHYSMAP_COMPAT is not set
> +# CONFIG_MTD_ARM_INTEGRATOR is not set
> +# CONFIG_MTD_PLATRAM is not set
> +
> +#
> +# Self-contained MTD device drivers
> +#
> +# CONFIG_MTD_DATAFLASH is not set
> +CONFIG_MTD_M25P80=y
> +CONFIG_M25PXX_USE_FAST_READ=y
> +# CONFIG_MTD_SST25L is not set
> +# CONFIG_MTD_SLRAM is not set
> +# CONFIG_MTD_PHRAM is not set
> +# CONFIG_MTD_MTDRAM is not set
> +# CONFIG_MTD_BLOCK2MTD is not set
> +
> +#
> +# Disk-On-Chip Device Drivers
> +#
> +# CONFIG_MTD_DOC2000 is not set
> +# CONFIG_MTD_DOC2001 is not set
> +# CONFIG_MTD_DOC2001PLUS is not set
> +CONFIG_MTD_NAND_ECC=y
> +# CONFIG_MTD_NAND_ECC_SMC is not set
> +CONFIG_MTD_NAND=y
> +# CONFIG_MTD_NAND_VERIFY_WRITE is not set
> +# CONFIG_MTD_NAND_ECC_BCH is not set
> +# CONFIG_MTD_SM_COMMON is not set
> +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
> +# CONFIG_MTD_NAND_GPIO is not set
> +CONFIG_MTD_NAND_IDS=y
> +# CONFIG_MTD_NAND_DISKONCHIP is not set
> +# CONFIG_MTD_NAND_NANDSIM is not set
> +CONFIG_MTD_NAND_GPMI_NAND=y
> +# CONFIG_MTD_NAND_PLATFORM is not set
> +# CONFIG_MTD_ALAUDA is not set
> +# CONFIG_MTD_ONENAND is not set
> +
> +#
> +# LPDDR flash memory drivers
> +#
> +# CONFIG_MTD_LPDDR is not set
> +CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_WL_THRESHOLD=4096
> +CONFIG_MTD_UBI_BEB_RESERVE=1
> +# CONFIG_MTD_UBI_GLUEBI is not set
> +# CONFIG_MTD_UBI_DEBUG is not set
> +# CONFIG_PARPORT is not set
> +CONFIG_BLK_DEV=y
> +# CONFIG_BLK_DEV_COW_COMMON is not set
> +CONFIG_BLK_DEV_LOOP=y
> +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> +# CONFIG_BLK_DEV_DRBD is not set
> +# CONFIG_BLK_DEV_NBD is not set
> +# CONFIG_BLK_DEV_UB is not set
> +# CONFIG_BLK_DEV_RAM is not set
> +# CONFIG_CDROM_PKTCDVD is not set
> +# CONFIG_ATA_OVER_ETH is not set
> +# CONFIG_MG_DISK is not set
> +# CONFIG_BLK_DEV_RBD is not set
> +# CONFIG_SENSORS_LIS3LV02D is not set
> +CONFIG_MISC_DEVICES=y
> +# CONFIG_AD525X_DPOT is not set
> +# CONFIG_INTEL_MID_PTI is not set
> +# CONFIG_ICS932S401 is not set
> +# CONFIG_ENCLOSURE_SERVICES is not set
> +# CONFIG_APDS9802ALS is not set
> +# CONFIG_ISL29003 is not set
> +# CONFIG_ISL29020 is not set
> +# CONFIG_SENSORS_TSL2550 is not set
> +# CONFIG_SENSORS_BH1780 is not set
> +# CONFIG_SENSORS_BH1770 is not set
> +# CONFIG_SENSORS_APDS990X is not set
> +# CONFIG_HMC6352 is not set
> +# CONFIG_DS1682 is not set
> +# CONFIG_TI_DAC7512 is not set
> +# CONFIG_BMP085 is not set
> +CONFIG_MXS_PERFMON=m
> +# CONFIG_C2PORT is not set
> +
> +#
> +# EEPROM support
> +#
> +# CONFIG_EEPROM_AT24 is not set
> +# CONFIG_EEPROM_AT25 is not set
> +# CONFIG_EEPROM_LEGACY is not set
> +# CONFIG_EEPROM_MAX6875 is not set
> +# CONFIG_EEPROM_93CX6 is not set
> +# CONFIG_IWMC3200TOP is not set
> +
> +#
> +# Texas Instruments shared transport line discipline
> +#
> +# CONFIG_TI_ST is not set
> +# CONFIG_SENSORS_LIS3_SPI is not set
> +# CONFIG_SENSORS_LIS3_I2C is not set
> +CONFIG_HAVE_IDE=y
> +# CONFIG_IDE is not set
> +
> +#
> +# SCSI device support
> +#
> +CONFIG_SCSI_MOD=y
> +# CONFIG_RAID_ATTRS is not set
> +CONFIG_SCSI=y
> +CONFIG_SCSI_DMA=y
> +# CONFIG_SCSI_TGT is not set
> +# CONFIG_SCSI_NETLINK is not set
> +CONFIG_SCSI_PROC_FS=y
> +
> +#
> +# SCSI support type (disk, tape, CD-ROM)
> +#
> +CONFIG_BLK_DEV_SD=y
> +# CONFIG_CHR_DEV_ST is not set
> +# CONFIG_CHR_DEV_OSST is not set
> +# CONFIG_BLK_DEV_SR is not set
> +# CONFIG_CHR_DEV_SG is not set
> +# CONFIG_CHR_DEV_SCH is not set
> +CONFIG_SCSI_MULTI_LUN=y
> +# CONFIG_SCSI_CONSTANTS is not set
> +# CONFIG_SCSI_LOGGING is not set
> +# CONFIG_SCSI_SCAN_ASYNC is not set
> +CONFIG_SCSI_WAIT_SCAN=m
> +
> +#
> +# SCSI Transports
> +#
> +# CONFIG_SCSI_SPI_ATTRS is not set
> +# CONFIG_SCSI_FC_ATTRS is not set
> +# CONFIG_SCSI_ISCSI_ATTRS is not set
> +# CONFIG_SCSI_SAS_ATTRS is not set
> +# CONFIG_SCSI_SAS_LIBSAS is not set
> +# CONFIG_SCSI_SRP_ATTRS is not set
> +CONFIG_SCSI_LOWLEVEL=y
> +# CONFIG_ISCSI_TCP is not set
> +# CONFIG_ISCSI_BOOT_SYSFS is not set
> +# CONFIG_LIBFC is not set
> +# CONFIG_LIBFCOE is not set
> +# CONFIG_SCSI_DEBUG is not set
> +# CONFIG_SCSI_DH is not set
> +# CONFIG_SCSI_OSD_INITIATOR is not set
> +CONFIG_ATA=y
> +# CONFIG_ATA_NONSTANDARD is not set
> +CONFIG_ATA_VERBOSE_ERROR=y
> +# CONFIG_SATA_PMP is not set
> +
> +#
> +# Controllers with non-SFF native interface
> +#
> +CONFIG_SATA_AHCI_PLATFORM=y
> +CONFIG_ATA_SFF=y
> +
> +#
> +# SFF controllers with custom DMA interface
> +#
> +CONFIG_ATA_BMDMA=y
> +
> +#
> +# SATA SFF controllers with BMDMA
> +#
> +# CONFIG_SATA_MV is not set
> +
> +#
> +# PATA SFF controllers with BMDMA
> +#
> +# CONFIG_PATA_ARASAN_CF is not set
> +
> +#
> +# PIO-only SFF controllers
> +#
> +# CONFIG_PATA_PLATFORM is not set
> +
> +#
> +# Generic fallback / legacy drivers
> +#
> +# CONFIG_MD is not set
> +# CONFIG_TARGET_CORE is not set
> +CONFIG_NETDEVICES=y
> +# CONFIG_DUMMY is not set
> +# CONFIG_BONDING is not set
> +# CONFIG_MACVLAN is not set
> +# CONFIG_EQUALIZER is not set
> +# CONFIG_TUN is not set
> +# CONFIG_VETH is not set
> +CONFIG_MII=y
> +CONFIG_PHYLIB=y
> +
> +#
> +# MII PHY device drivers
> +#
> +# CONFIG_MARVELL_PHY is not set
> +# CONFIG_DAVICOM_PHY is not set
> +# CONFIG_QSEMI_PHY is not set
> +# CONFIG_LXT_PHY is not set
> +# CONFIG_CICADA_PHY is not set
> +# CONFIG_VITESSE_PHY is not set
> +# CONFIG_SMSC_PHY is not set
> +# CONFIG_BROADCOM_PHY is not set
> +# CONFIG_ICPLUS_PHY is not set
> +# CONFIG_REALTEK_PHY is not set
> +# CONFIG_NATIONAL_PHY is not set
> +# CONFIG_STE10XP is not set
> +# CONFIG_LSI_ET1011C_PHY is not set
> +CONFIG_MICREL_PHY=y
> +# CONFIG_FIXED_PHY is not set
> +# CONFIG_MDIO_BITBANG is not set
> +CONFIG_NET_ETHERNET=y
> +# CONFIG_AX88796 is not set
> +# CONFIG_SMC91X is not set
> +# CONFIG_DM9000 is not set
> +# CONFIG_ENC28J60 is not set
> +# CONFIG_ETHOC is not set
> +# CONFIG_SMC911X is not set
> +CONFIG_SMSC911X=y
> +# CONFIG_SMSC911X_ARCH_HOOKS is not set
> +# CONFIG_DNET is not set
> +# CONFIG_IBM_NEW_EMAC_ZMII is not set
> +# CONFIG_IBM_NEW_EMAC_RGMII is not set
> +# CONFIG_IBM_NEW_EMAC_TAH is not set
> +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
> +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
> +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
> +# CONFIG_B44 is not set
> +# CONFIG_KS8842 is not set
> +# CONFIG_KS8851 is not set
> +# CONFIG_KS8851_MLL is not set
> +CONFIG_FEC=y
> +CONFIG_FEC_NAPI=y
> +# CONFIG_FEC_1588 is not set
> +# CONFIG_FTMAC100 is not set
> +# CONFIG_NETDEV_1000 is not set
> +# CONFIG_NETDEV_10000 is not set
> +CONFIG_WLAN=y
> +# CONFIG_USB_ZD1201 is not set
> +# CONFIG_USB_NET_RNDIS_WLAN is not set
> +CONFIG_ATH_COMMON=m
> +# CONFIG_ATH_DEBUG is not set
> +CONFIG_ATH6KL=m
> +# CONFIG_ATH6KL_DEBUG is not set
> +CONFIG_HOSTAP=y
> +# CONFIG_HOSTAP_FIRMWARE is not set
> +# CONFIG_IWM is not set
> +# CONFIG_LIBERTAS is not set
> +# CONFIG_MWIFIEX is not set
> +
> +#
> +# Enable WiMAX (Networking options) to see the WiMAX drivers
> +#
> +
> +#
> +# USB Network Adapters
> +#
> +# CONFIG_USB_CATC is not set
> +# CONFIG_USB_KAWETH is not set
> +# CONFIG_USB_PEGASUS is not set
> +# CONFIG_USB_RTL8150 is not set
> +# CONFIG_USB_USBNET is not set
> +# CONFIG_USB_HSO is not set
> +# CONFIG_USB_IPHETH is not set
> +# CONFIG_WAN is not set
> +
> +#
> +# CAIF transport drivers
> +#
> +# CONFIG_PPP is not set
> +# CONFIG_SLIP is not set
> +# CONFIG_NETCONSOLE is not set
> +# CONFIG_NETPOLL is not set
> +# CONFIG_NET_POLL_CONTROLLER is not set
> +# CONFIG_ISDN is not set
> +# CONFIG_PHONE is not set
> +
> +#
> +# Input device support
> +#
> +CONFIG_INPUT=y
> +# CONFIG_INPUT_FF_MEMLESS is not set
> +CONFIG_INPUT_POLLDEV=y
> +# CONFIG_INPUT_SPARSEKMAP is not set
> +
> +#
> +# Userland interfaces
> +#
> +CONFIG_INPUT_MOUSEDEV=y
> +CONFIG_INPUT_MOUSEDEV_PSAUX=y
> +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> +# CONFIG_INPUT_JOYDEV is not set
> +CONFIG_INPUT_EVDEV=y
> +# CONFIG_INPUT_EVBUG is not set
> +# CONFIG_INPUT_APMPOWER is not set
> +
> +#
> +# Input Device Drivers
> +#
> +CONFIG_INPUT_KEYBOARD=y
> +# CONFIG_KEYBOARD_ADP5588 is not set
> +# CONFIG_KEYBOARD_ADP5589 is not set
> +CONFIG_KEYBOARD_ATKBD=y
> +# CONFIG_KEYBOARD_QT1070 is not set
> +# CONFIG_KEYBOARD_QT2160 is not set
> +# CONFIG_KEYBOARD_LKKBD is not set
> +CONFIG_KEYBOARD_GPIO=y
> +# CONFIG_KEYBOARD_TCA6416 is not set
> +# CONFIG_KEYBOARD_MATRIX is not set
> +# CONFIG_KEYBOARD_LM8323 is not set
> +# CONFIG_KEYBOARD_MAX7359 is not set
> +# CONFIG_KEYBOARD_MCS is not set
> +# CONFIG_KEYBOARD_MPR121 is not set
> +# CONFIG_KEYBOARD_IMX is not set
> +# CONFIG_KEYBOARD_NEWTON is not set
> +# CONFIG_KEYBOARD_OPENCORES is not set
> +# CONFIG_KEYBOARD_STOWAWAY is not set
> +# CONFIG_KEYBOARD_SUNKBD is not set
> +# CONFIG_KEYBOARD_XTKBD is not set
> +# CONFIG_INPUT_MOUSE is not set
> +# CONFIG_INPUT_JOYSTICK is not set
> +# CONFIG_INPUT_TABLET is not set
> +CONFIG_INPUT_TOUCHSCREEN=y
> +# CONFIG_TOUCHSCREEN_ADS7846 is not set
> +# CONFIG_TOUCHSCREEN_AD7877 is not set
> +# CONFIG_TOUCHSCREEN_AD7879 is not set
> +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
> +# CONFIG_TOUCHSCREEN_BU21013 is not set
> +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
> +# CONFIG_TOUCHSCREEN_DYNAPRO is not set
> +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
> +# CONFIG_TOUCHSCREEN_EETI is not set
> +CONFIG_TOUCHSCREEN_EGALAX=y
> +CONFIG_TOUCHSCREEN_ELAN=y
> +CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH=y
> +# CONFIG_TOUCHSCREEN_FUJITSU is not set
> +# CONFIG_TOUCHSCREEN_GUNZE is not set
> +# CONFIG_TOUCHSCREEN_ELO is not set
> +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> +CONFIG_TOUCHSCREEN_MAX11801=y
> +# CONFIG_TOUCHSCREEN_MCS5000 is not set
> +# CONFIG_TOUCHSCREEN_MTOUCH is not set
> +# CONFIG_TOUCHSCREEN_INEXIO is not set
> +# CONFIG_TOUCHSCREEN_MK712 is not set
> +# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> +# CONFIG_TOUCHSCREEN_WM97XX is not set
> +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> +# CONFIG_TOUCHSCREEN_NOVATEK is not set
> +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> +# CONFIG_TOUCHSCREEN_TSC2005 is not set
> +# CONFIG_TOUCHSCREEN_TSC2007 is not set
> +# CONFIG_TOUCHSCREEN_W90X900 is not set
> +# CONFIG_TOUCHSCREEN_ST1232 is not set
> +# CONFIG_TOUCHSCREEN_P1003 is not set
> +# CONFIG_TOUCHSCREEN_TPS6507X is not set
> +CONFIG_INPUT_MISC=y
> +# CONFIG_INPUT_AD714X is not set
> +# CONFIG_INPUT_ATI_REMOTE is not set
> +# CONFIG_INPUT_ATI_REMOTE2 is not set
> +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
> +# CONFIG_INPUT_POWERMATE is not set
> +# CONFIG_INPUT_YEALINK is not set
> +# CONFIG_INPUT_CM109 is not set
> +CONFIG_INPUT_UINPUT=y
> +# CONFIG_INPUT_PCF8574 is not set
> +# CONFIG_INPUT_PWM_BEEPER is not set
> +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
> +# CONFIG_INPUT_ADXL34X is not set
> +# CONFIG_INPUT_CMA3000 is not set
> +CONFIG_INPUT_ISL29023=y
> +
> +#
> +# Hardware I/O ports
> +#
> +CONFIG_SERIO=y
> +CONFIG_SERIO_SERPORT=y
> +# CONFIG_SERIO_AMBAKMI is not set
> +CONFIG_SERIO_LIBPS2=y
> +# CONFIG_SERIO_RAW is not set
> +# CONFIG_SERIO_ALTERA_PS2 is not set
> +# CONFIG_SERIO_PS2MULT is not set
> +# CONFIG_GAMEPORT is not set
> +
> +#
> +# Character devices
> +#
> +CONFIG_VT=y
> +CONFIG_CONSOLE_TRANSLATIONS=y
> +CONFIG_VT_CONSOLE=y
> +CONFIG_HW_CONSOLE=y
> +CONFIG_VT_HW_CONSOLE_BINDING=y
> +CONFIG_UNIX98_PTYS=y
> +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> +CONFIG_LEGACY_PTYS=y
> +CONFIG_LEGACY_PTY_COUNT=256
> +# CONFIG_SERIAL_NONSTANDARD is not set
> +# CONFIG_N_GSM is not set
> +# CONFIG_TRACE_SINK is not set
> +CONFIG_DEVKMEM=y
> +
> +#
> +# Serial drivers
> +#
> +# CONFIG_SERIAL_8250 is not set
> +
> +#
> +# Non-8250 serial port support
> +#
> +# CONFIG_SERIAL_AMBA_PL010 is not set
> +# CONFIG_SERIAL_AMBA_PL011 is not set
> +# CONFIG_SERIAL_MAX3100 is not set
> +# CONFIG_SERIAL_MAX3107 is not set
> +CONFIG_SERIAL_IMX=y
> +CONFIG_SERIAL_IMX_CONSOLE=y
> +CONFIG_SERIAL_CORE=y
> +CONFIG_SERIAL_CORE_CONSOLE=y
> +# CONFIG_SERIAL_TIMBERDALE is not set
> +# CONFIG_SERIAL_ALTERA_JTAGUART is not set
> +# CONFIG_SERIAL_ALTERA_UART is not set
> +# CONFIG_SERIAL_IFX6X60 is not set
> +# CONFIG_SERIAL_XILINX_PS_UART is not set
> +# CONFIG_TTY_PRINTK is not set
> +CONFIG_FSL_OTP=y
> +# CONFIG_HVC_DCC is not set
> +# CONFIG_IPMI_HANDLER is not set
> +CONFIG_HW_RANDOM=y
> +# CONFIG_HW_RANDOM_TIMERIOMEM is not set
> +# CONFIG_R3964 is not set
> +# CONFIG_RAW_DRIVER is not set
> +# CONFIG_TCG_TPM is not set
> +# CONFIG_RAMOOPS is not set
> +CONFIG_MXS_VIIM=y
> +CONFIG_I2C=y
> +CONFIG_I2C_BOARDINFO=y
> +CONFIG_I2C_COMPAT=y
> +CONFIG_I2C_CHARDEV=y
> +# CONFIG_I2C_MUX is not set
> +CONFIG_I2C_HELPER_AUTO=y
> +CONFIG_I2C_ALGOBIT=m
> +
> +#
> +# I2C Hardware Bus support
> +#
> +
> +#
> +# I2C system bus drivers (mostly embedded / system-on-chip)
> +#
> +# CONFIG_I2C_DESIGNWARE is not set
> +# CONFIG_I2C_GPIO is not set
> +CONFIG_I2C_IMX=y
> +# CONFIG_I2C_OCORES is not set
> +# CONFIG_I2C_PCA_PLATFORM is not set
> +# CONFIG_I2C_PXA_PCI is not set
> +# CONFIG_I2C_SIMTEC is not set
> +# CONFIG_I2C_XILINX is not set
> +
> +#
> +# External I2C/SMBus adapter drivers
> +#
> +# CONFIG_I2C_DIOLAN_U2C is not set
> +# CONFIG_I2C_PARPORT_LIGHT is not set
> +# CONFIG_I2C_TAOS_EVM is not set
> +# CONFIG_I2C_TINY_USB is not set
> +
> +#
> +# Other I2C/SMBus bus drivers
> +#
> +# CONFIG_I2C_STUB is not set
> +# CONFIG_I2C_DEBUG_CORE is not set
> +# CONFIG_I2C_DEBUG_ALGO is not set
> +# CONFIG_I2C_DEBUG_BUS is not set
> +CONFIG_SPI=y
> +CONFIG_SPI_MASTER=y
> +
> +#
> +# SPI Master Controller Drivers
> +#
> +# CONFIG_SPI_ALTERA is not set
> +CONFIG_SPI_BITBANG=y
> +# CONFIG_SPI_GPIO is not set
> +CONFIG_SPI_IMX_VER_2_3=y
> +CONFIG_SPI_IMX=y
> +# CONFIG_SPI_OC_TINY is not set
> +# CONFIG_SPI_PL022 is not set
> +# CONFIG_SPI_PXA2XX_PCI is not set
> +# CONFIG_SPI_XILINX is not set
> +# CONFIG_SPI_DESIGNWARE is not set
> +
> +#
> +# SPI Protocol Masters
> +#
> +# CONFIG_SPI_SPIDEV is not set
> +# CONFIG_SPI_TLE62X0 is not set
> +
> +#
> +# PPS support
> +#
> +# CONFIG_PPS is not set
> +
> +#
> +# PPS generators support
> +#
> +
> +#
> +# PTP clock support
> +#
> +
> +#
> +# Enable Device Drivers -> PPS to see the PTP clock options.
> +#
> +CONFIG_ARCH_REQUIRE_GPIOLIB=y
> +CONFIG_GPIOLIB=y
> +CONFIG_GPIO_SYSFS=y
> +
> +#
> +# Memory mapped GPIO drivers:
> +#
> +# CONFIG_GPIO_BASIC_MMIO is not set
> +# CONFIG_GPIO_IT8761E is not set
> +# CONFIG_GPIO_PL061 is not set
> +
> +#
> +# I2C GPIO expanders:
> +#
> +# CONFIG_GPIO_MAX7300 is not set
> +# CONFIG_GPIO_MAX732X is not set
> +# CONFIG_GPIO_PCA953X_IRQ is not set
> +# CONFIG_GPIO_PCF857X is not set
> +# CONFIG_GPIO_SX150X is not set
> +# CONFIG_GPIO_WM8994 is not set
> +# CONFIG_GPIO_ADP5588 is not set
> +
> +#
> +# PCI GPIO expanders:
> +#
> +
> +#
> +# SPI GPIO expanders:
> +#
> +# CONFIG_GPIO_MAX7301 is not set
> +# CONFIG_GPIO_MCP23S08 is not set
> +# CONFIG_GPIO_MC33880 is not set
> +# CONFIG_GPIO_74X164 is not set
> +
> +#
> +# AC97 GPIO expanders:
> +#
> +
> +#
> +# MODULbus GPIO expanders:
> +#
> +# CONFIG_W1 is not set
> +CONFIG_POWER_SUPPLY=y
> +# CONFIG_POWER_SUPPLY_DEBUG is not set
> +# CONFIG_PDA_POWER is not set
> +# CONFIG_APM_POWER is not set
> +# CONFIG_TEST_POWER is not set
> +# CONFIG_BATTERY_DS2780 is not set
> +# CONFIG_BATTERY_DS2782 is not set
> +# CONFIG_BATTERY_BQ20Z75 is not set
> +# CONFIG_BATTERY_BQ27x00 is not set
> +# CONFIG_BATTERY_MAX17040 is not set
> +# CONFIG_BATTERY_MAX17042 is not set
> +# CONFIG_CHARGER_ISP1704 is not set
> +# CONFIG_CHARGER_MAX8903 is not set
> +CONFIG_SABRESD_MAX8903=y
> +# CONFIG_CHARGER_GPIO is not set
> +CONFIG_HWMON=y
> +# CONFIG_HWMON_VID is not set
> +# CONFIG_HWMON_DEBUG_CHIP is not set
> +
> +#
> +# Native drivers
> +#
> +# CONFIG_SENSORS_AD7414 is not set
> +# CONFIG_SENSORS_AD7418 is not set
> +# CONFIG_SENSORS_ADCXX is not set
> +# CONFIG_SENSORS_ADM1021 is not set
> +# CONFIG_SENSORS_ADM1025 is not set
> +# CONFIG_SENSORS_ADM1026 is not set
> +# CONFIG_SENSORS_ADM1029 is not set
> +# CONFIG_SENSORS_ADM1031 is not set
> +# CONFIG_SENSORS_ADM9240 is not set
> +# CONFIG_SENSORS_ADT7411 is not set
> +# CONFIG_SENSORS_ADT7462 is not set
> +# CONFIG_SENSORS_ADT7470 is not set
> +# CONFIG_SENSORS_ADT7475 is not set
> +# CONFIG_SENSORS_ASC7621 is not set
> +# CONFIG_SENSORS_ATXP1 is not set
> +# CONFIG_SENSORS_DS620 is not set
> +# CONFIG_SENSORS_DS1621 is not set
> +# CONFIG_SENSORS_F71805F is not set
> +# CONFIG_SENSORS_F71882FG is not set
> +# CONFIG_SENSORS_F75375S is not set
> +# CONFIG_SENSORS_G760A is not set
> +# CONFIG_SENSORS_GL518SM is not set
> +# CONFIG_SENSORS_GL520SM is not set
> +# CONFIG_SENSORS_GPIO_FAN is not set
> +# CONFIG_SENSORS_IT87 is not set
> +# CONFIG_SENSORS_JC42 is not set
> +# CONFIG_SENSORS_LINEAGE is not set
> +# CONFIG_SENSORS_LM63 is not set
> +# CONFIG_SENSORS_LM70 is not set
> +# CONFIG_SENSORS_LM73 is not set
> +# CONFIG_SENSORS_LM75 is not set
> +# CONFIG_SENSORS_LM77 is not set
> +# CONFIG_SENSORS_LM78 is not set
> +# CONFIG_SENSORS_LM80 is not set
> +# CONFIG_SENSORS_LM83 is not set
> +# CONFIG_SENSORS_LM85 is not set
> +# CONFIG_SENSORS_LM87 is not set
> +# CONFIG_SENSORS_LM90 is not set
> +# CONFIG_SENSORS_LM92 is not set
> +# CONFIG_SENSORS_LM93 is not set
> +# CONFIG_SENSORS_LTC4151 is not set
> +# CONFIG_SENSORS_LTC4215 is not set
> +# CONFIG_SENSORS_LTC4245 is not set
> +# CONFIG_SENSORS_LTC4261 is not set
> +# CONFIG_SENSORS_LM95241 is not set
> +# CONFIG_SENSORS_MAX1111 is not set
> +# CONFIG_SENSORS_MAX16065 is not set
> +# CONFIG_SENSORS_MAX1619 is not set
> +# CONFIG_SENSORS_MAX6639 is not set
> +# CONFIG_SENSORS_MAX6642 is not set
> +CONFIG_SENSORS_MAX17135=y
> +# CONFIG_SENSORS_MAX6650 is not set
> +# CONFIG_SENSORS_PC87360 is not set
> +# CONFIG_SENSORS_PC87427 is not set
> +# CONFIG_SENSORS_PCF8591 is not set
> +# CONFIG_PMBUS is not set
> +# CONFIG_SENSORS_SHT15 is not set
> +# CONFIG_SENSORS_SHT21 is not set
> +# CONFIG_SENSORS_SMM665 is not set
> +# CONFIG_SENSORS_DME1737 is not set
> +# CONFIG_SENSORS_EMC1403 is not set
> +# CONFIG_SENSORS_EMC2103 is not set
> +# CONFIG_SENSORS_EMC6W201 is not set
> +# CONFIG_SENSORS_SMSC47M1 is not set
> +# CONFIG_SENSORS_SMSC47M192 is not set
> +# CONFIG_SENSORS_SMSC47B397 is not set
> +# CONFIG_SENSORS_SCH5627 is not set
> +# CONFIG_SENSORS_ADS1015 is not set
> +# CONFIG_SENSORS_ADS7828 is not set
> +# CONFIG_SENSORS_ADS7871 is not set
> +# CONFIG_SENSORS_AMC6821 is not set
> +# CONFIG_SENSORS_THMC50 is not set
> +# CONFIG_SENSORS_TMP102 is not set
> +# CONFIG_SENSORS_TMP401 is not set
> +# CONFIG_SENSORS_TMP421 is not set
> +# CONFIG_SENSORS_VT1211 is not set
> +# CONFIG_SENSORS_W83781D is not set
> +# CONFIG_SENSORS_W83791D is not set
> +# CONFIG_SENSORS_W83792D is not set
> +# CONFIG_SENSORS_W83793 is not set
> +# CONFIG_SENSORS_W83795 is not set
> +# CONFIG_SENSORS_W83L785TS is not set
> +# CONFIG_SENSORS_W83L786NG is not set
> +# CONFIG_SENSORS_W83627HF is not set
> +# CONFIG_SENSORS_W83627EHF is not set
> +CONFIG_SENSORS_MAG3110=y
> +# CONFIG_MXC_MMA8450 is not set
> +CONFIG_MXC_MMA8451=y
> +CONFIG_THERMAL=y
> +# CONFIG_THERMAL_HWMON is not set
> +CONFIG_WATCHDOG=y
> +CONFIG_WATCHDOG_NOWAYOUT=y
> +
> +#
> +# Watchdog Device Drivers
> +#
> +# CONFIG_SOFT_WATCHDOG is not set
> +# CONFIG_ARM_SP805_WATCHDOG is not set
> +# CONFIG_MPCORE_WATCHDOG is not set
> +# CONFIG_MAX63XX_WATCHDOG is not set
> +CONFIG_IMX2_WDT=y
> +
> +#
> +# USB-based Watchdog Cards
> +#
> +# CONFIG_USBPCWATCHDOG is not set
> +CONFIG_SSB_POSSIBLE=y
> +
> +#
> +# Sonics Silicon Backplane
> +#
> +# CONFIG_SSB is not set
> +CONFIG_BCMA_POSSIBLE=y
> +
> +#
> +# Broadcom specific AMBA
> +#
> +# CONFIG_BCMA is not set
> +CONFIG_MFD_SUPPORT=y
> +CONFIG_MFD_CORE=y
> +# CONFIG_MFD_88PM860X is not set
> +# CONFIG_MFD_SM501 is not set
> +# CONFIG_MFD_ASIC3 is not set
> +# CONFIG_HTC_EGPIO is not set
> +# CONFIG_HTC_PASIC3 is not set
> +# CONFIG_HTC_I2CPLD is not set
> +# CONFIG_UCB1400_CORE is not set
> +# CONFIG_TPS6105X is not set
> +# CONFIG_TPS65010 is not set
> +# CONFIG_TPS6507X is not set
> +# CONFIG_MFD_TPS6586X is not set
> +# CONFIG_TWL4030_CORE is not set
> +# CONFIG_MFD_STMPE is not set
> +# CONFIG_MFD_TC3589X is not set
> +# CONFIG_MFD_TMIO is not set
> +# CONFIG_MFD_T7L66XB is not set
> +# CONFIG_MFD_TC6387XB is not set
> +# CONFIG_MFD_TC6393XB is not set
> +# CONFIG_PMIC_DA903X is not set
> +# CONFIG_PMIC_ADP5520 is not set
> +# CONFIG_MFD_MAX8925 is not set
> +# CONFIG_MFD_MAX8997 is not set
> +# CONFIG_MFD_MAX8998 is not set
> +# CONFIG_MFD_WM8400 is not set
> +# CONFIG_MFD_WM831X_I2C is not set
> +# CONFIG_MFD_WM831X_SPI is not set
> +# CONFIG_MFD_WM8350_I2C is not set
> +CONFIG_MFD_WM8994=y
> +# CONFIG_MFD_PCF50633 is not set
> +# CONFIG_PMIC_DIALOG is not set
> +# CONFIG_MFD_MC_PMIC is not set
> +# CONFIG_MFD_MC34708 is not set
> +CONFIG_MFD_PFUZE=y
> +# CONFIG_MFD_MC13XXX is not set
> +# CONFIG_ABX500_CORE is not set
> +# CONFIG_EZX_PCAP is not set
> +# CONFIG_MFD_WL1273_CORE is not set
> +# CONFIG_MFD_TPS65910 is not set
> +CONFIG_MFD_MAX17135=y
> +CONFIG_MFD_MXC_HDMI=y
> +CONFIG_REGULATOR=y
> +# CONFIG_REGULATOR_DEBUG is not set
> +# CONFIG_REGULATOR_DUMMY is not set
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
> +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
> +# CONFIG_REGULATOR_BQ24022 is not set
> +# CONFIG_REGULATOR_MAX1586 is not set
> +# CONFIG_REGULATOR_MAX8649 is not set
> +# CONFIG_REGULATOR_MAX8660 is not set
> +# CONFIG_REGULATOR_MAX8952 is not set
> +# CONFIG_REGULATOR_WM8994 is not set
> +# CONFIG_REGULATOR_LP3971 is not set
> +# CONFIG_REGULATOR_LP3972 is not set
> +# CONFIG_REGULATOR_MC34708 is not set
> +CONFIG_REGULATOR_PFUZE100=y
> +# CONFIG_REGULATOR_TPS65023 is not set
> +# CONFIG_REGULATOR_TPS6507X is not set
> +# CONFIG_REGULATOR_ISL6271A is not set
> +# CONFIG_REGULATOR_AD5398 is not set
> +CONFIG_REGULATOR_ANATOP=y
> +# CONFIG_REGULATOR_TPS6524X is not set
> +CONFIG_REGULATOR_MAX17135=y
> +CONFIG_MEDIA_SUPPORT=y
> +
> +#
> +# Multimedia core support
> +#
> +# CONFIG_MEDIA_CONTROLLER is not set
> +CONFIG_VIDEO_DEV=y
> +CONFIG_VIDEO_V4L2_COMMON=y
> +# CONFIG_DVB_CORE is not set
> +CONFIG_VIDEO_MEDIA=y
> +
> +#
> +# Multimedia drivers
> +#
> +# CONFIG_RC_CORE is not set
> +# CONFIG_MEDIA_ATTACH is not set
> +CONFIG_MEDIA_TUNER=y
> +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
> +CONFIG_MEDIA_TUNER_SIMPLE=y
> +CONFIG_MEDIA_TUNER_TDA8290=y
> +CONFIG_MEDIA_TUNER_TDA827X=y
> +CONFIG_MEDIA_TUNER_TDA18271=y
> +CONFIG_MEDIA_TUNER_TDA9887=y
> +CONFIG_MEDIA_TUNER_TEA5761=y
> +CONFIG_MEDIA_TUNER_TEA5767=y
> +CONFIG_MEDIA_TUNER_MT20XX=y
> +CONFIG_MEDIA_TUNER_XC2028=y
> +CONFIG_MEDIA_TUNER_XC5000=y
> +CONFIG_MEDIA_TUNER_MC44S803=y
> +CONFIG_VIDEO_V4L2=y
> +CONFIG_VIDEOBUF_GEN=y
> +CONFIG_VIDEOBUF_DMA_CONTIG=y
> +CONFIG_VIDEO_CAPTURE_DRIVERS=y
> +# CONFIG_VIDEO_ADV_DEBUG is not set
> +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
> +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
> +
> +#
> +# Encoders, decoders, sensors and other helper chips
> +#
> +
> +#
> +# Audio decoders, processors and mixers
> +#
> +# CONFIG_VIDEO_TVAUDIO is not set
> +# CONFIG_VIDEO_TDA7432 is not set
> +# CONFIG_VIDEO_TDA9840 is not set
> +# CONFIG_VIDEO_TEA6415C is not set
> +# CONFIG_VIDEO_TEA6420 is not set
> +# CONFIG_VIDEO_MSP3400 is not set
> +# CONFIG_VIDEO_CS5345 is not set
> +# CONFIG_VIDEO_CS53L32A is not set
> +# CONFIG_VIDEO_TLV320AIC23B is not set
> +# CONFIG_VIDEO_WM8775 is not set
> +# CONFIG_VIDEO_WM8739 is not set
> +# CONFIG_VIDEO_VP27SMPX is not set
> +
> +#
> +# RDS decoders
> +#
> +# CONFIG_VIDEO_SAA6588 is not set
> +
> +#
> +# Video decoders
> +#
> +# CONFIG_VIDEO_ADV7180 is not set
> +# CONFIG_VIDEO_BT819 is not set
> +# CONFIG_VIDEO_BT856 is not set
> +# CONFIG_VIDEO_BT866 is not set
> +# CONFIG_VIDEO_KS0127 is not set
> +# CONFIG_VIDEO_SAA7110 is not set
> +# CONFIG_VIDEO_SAA711X is not set
> +# CONFIG_VIDEO_SAA7191 is not set
> +# CONFIG_VIDEO_TVP514X is not set
> +# CONFIG_VIDEO_TVP5150 is not set
> +# CONFIG_VIDEO_TVP7002 is not set
> +# CONFIG_VIDEO_VPX3220 is not set
> +
> +#
> +# Video and audio decoders
> +#
> +# CONFIG_VIDEO_SAA717X is not set
> +# CONFIG_VIDEO_CX25840 is not set
> +
> +#
> +# MPEG video encoders
> +#
> +# CONFIG_VIDEO_CX2341X is not set
> +
> +#
> +# Video encoders
> +#
> +# CONFIG_VIDEO_SAA7127 is not set
> +# CONFIG_VIDEO_SAA7185 is not set
> +# CONFIG_VIDEO_ADV7170 is not set
> +# CONFIG_VIDEO_ADV7175 is not set
> +# CONFIG_VIDEO_ADV7343 is not set
> +# CONFIG_VIDEO_AK881X is not set
> +
> +#
> +# Camera sensor devices
> +#
> +# CONFIG_VIDEO_OV7670 is not set
> +# CONFIG_VIDEO_MT9V011 is not set
> +# CONFIG_VIDEO_TCM825X is not set
> +
> +#
> +# Video improvement chips
> +#
> +# CONFIG_VIDEO_UPD64031A is not set
> +# CONFIG_VIDEO_UPD64083 is not set
> +
> +#
> +# Miscelaneous helper chips
> +#
> +# CONFIG_VIDEO_THS7303 is not set
> +# CONFIG_VIDEO_M52790 is not set
> +# CONFIG_VIDEO_VIVI is not set
> +CONFIG_VIDEO_MXC_CAMERA=m
> +
> +#
> +# MXC Camera/V4L2 PRP Features support
> +#
> +CONFIG_VIDEO_MXC_IPU_CAMERA=y
> +# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
> +# CONFIG_MXC_CAMERA_MICRON111 is not set
> +# CONFIG_MXC_CAMERA_OV2640 is not set
> +CONFIG_MXC_CAMERA_OV3640=m
> +CONFIG_MXC_CAMERA_OV5640=m
> +CONFIG_MXC_CAMERA_OV8820_MIPI=m
> +CONFIG_MXC_CAMERA_OV5642=m
> +CONFIG_MXC_TVIN_ADV7180=m
> +CONFIG_MXC_CAMERA_OV5640_MIPI=m
> +# CONFIG_MXC_MIPI_CSI2_TVIN_ADV7280 is not set
> +CONFIG_MXC_CAMERA_SENSOR_CLK=m
> +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
> +CONFIG_MXC_IPU_PRP_ENC=m
> +CONFIG_MXC_IPU_CSI_ENC=m
> +CONFIG_VIDEO_MXC_OUTPUT=y
> +CONFIG_VIDEO_MXC_IPU_OUTPUT=y
> +# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
> +# CONFIG_VIDEO_MXC_OPL is not set
> +# CONFIG_VIDEO_CPIA2 is not set
> +# CONFIG_VIDEO_TIMBERDALE is not set
> +# CONFIG_VIDEO_SR030PC30 is not set
> +# CONFIG_VIDEO_NOON010PC30 is not set
> +# CONFIG_SOC_CAMERA is not set
> +CONFIG_V4L_USB_DRIVERS=y
> +CONFIG_USB_VIDEO_CLASS=m
> +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
> +CONFIG_USB_GSPCA=m
> +# CONFIG_USB_M5602 is not set
> +# CONFIG_USB_STV06XX is not set
> +# CONFIG_USB_GL860 is not set
> +# CONFIG_USB_GSPCA_BENQ is not set
> +# CONFIG_USB_GSPCA_CONEX is not set
> +# CONFIG_USB_GSPCA_CPIA1 is not set
> +# CONFIG_USB_GSPCA_ETOMS is not set
> +# CONFIG_USB_GSPCA_FINEPIX is not set
> +# CONFIG_USB_GSPCA_JEILINJ is not set
> +# CONFIG_USB_GSPCA_KINECT is not set
> +# CONFIG_USB_GSPCA_KONICA is not set
> +# CONFIG_USB_GSPCA_MARS is not set
> +# CONFIG_USB_GSPCA_MR97310A is not set
> +# CONFIG_USB_GSPCA_NW80X is not set
> +# CONFIG_USB_GSPCA_OV519 is not set
> +# CONFIG_USB_GSPCA_OV534 is not set
> +# CONFIG_USB_GSPCA_OV534_9 is not set
> +# CONFIG_USB_GSPCA_PAC207 is not set
> +# CONFIG_USB_GSPCA_PAC7302 is not set
> +# CONFIG_USB_GSPCA_PAC7311 is not set
> +# CONFIG_USB_GSPCA_SN9C2028 is not set
> +# CONFIG_USB_GSPCA_SN9C20X is not set
> +# CONFIG_USB_GSPCA_SONIXB is not set
> +# CONFIG_USB_GSPCA_SONIXJ is not set
> +# CONFIG_USB_GSPCA_SPCA500 is not set
> +# CONFIG_USB_GSPCA_SPCA501 is not set
> +# CONFIG_USB_GSPCA_SPCA505 is not set
> +# CONFIG_USB_GSPCA_SPCA506 is not set
> +# CONFIG_USB_GSPCA_SPCA508 is not set
> +# CONFIG_USB_GSPCA_SPCA561 is not set
> +# CONFIG_USB_GSPCA_SPCA1528 is not set
> +# CONFIG_USB_GSPCA_SQ905 is not set
> +# CONFIG_USB_GSPCA_SQ905C is not set
> +# CONFIG_USB_GSPCA_SQ930X is not set
> +# CONFIG_USB_GSPCA_STK014 is not set
> +# CONFIG_USB_GSPCA_STV0680 is not set
> +# CONFIG_USB_GSPCA_SUNPLUS is not set
> +# CONFIG_USB_GSPCA_T613 is not set
> +# CONFIG_USB_GSPCA_TV8532 is not set
> +# CONFIG_USB_GSPCA_VC032X is not set
> +# CONFIG_USB_GSPCA_VICAM is not set
> +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
> +# CONFIG_USB_GSPCA_ZC3XX is not set
> +# CONFIG_VIDEO_PVRUSB2 is not set
> +# CONFIG_VIDEO_HDPVR is not set
> +# CONFIG_VIDEO_USBVISION is not set
> +# CONFIG_USB_ET61X251 is not set
> +# CONFIG_USB_SN9C102 is not set
> +# CONFIG_USB_PWC is not set
> +# CONFIG_USB_ZR364XX is not set
> +# CONFIG_USB_STKWEBCAM is not set
> +# CONFIG_USB_S2255 is not set
> +# CONFIG_V4L_MEM2MEM_DRIVERS is not set
> +# CONFIG_RADIO_ADAPTERS is not set
> +
> +#
> +# Graphics support
> +#
> +CONFIG_DRM=m
> +CONFIG_DRM_VIVANTE=m
> +# CONFIG_VGASTATE is not set
> +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> +CONFIG_FB=y
> +# CONFIG_FIRMWARE_EDID is not set
> +# CONFIG_FB_DDC is not set
> +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> +CONFIG_FB_CFB_FILLRECT=y
> +CONFIG_FB_CFB_COPYAREA=y
> +CONFIG_FB_CFB_IMAGEBLIT=y
> +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> +# CONFIG_FB_SYS_FILLRECT is not set
> +# CONFIG_FB_SYS_COPYAREA is not set
> +# CONFIG_FB_SYS_IMAGEBLIT is not set
> +# CONFIG_FB_FOREIGN_ENDIAN is not set
> +# CONFIG_FB_SYS_FOPS is not set
> +# CONFIG_FB_WMT_GE_ROPS is not set
> +CONFIG_FB_DEFERRED_IO=y
> +# CONFIG_FB_SVGALIB is not set
> +# CONFIG_FB_MACMODES is not set
> +# CONFIG_FB_BACKLIGHT is not set
> +CONFIG_FB_MODE_HELPERS=y
> +# CONFIG_FB_TILEBLITTING is not set
> +
> +#
> +# Frame buffer hardware drivers
> +#
> +# CONFIG_FB_ARMCLCD is not set
> +# CONFIG_FB_UVESA is not set
> +# CONFIG_FB_S1D13XXX is not set
> +# CONFIG_FB_TMIO is not set
> +# CONFIG_FB_UDL is not set
> +# CONFIG_FB_VIRTUAL is not set
> +# CONFIG_FB_METRONOME is not set
> +# CONFIG_FB_BROADSHEET is not set
> +CONFIG_BACKLIGHT_LCD_SUPPORT=y
> +# CONFIG_LCD_CLASS_DEVICE is not set
> +CONFIG_BACKLIGHT_CLASS_DEVICE=y
> +# CONFIG_BACKLIGHT_GENERIC is not set
> +CONFIG_BACKLIGHT_PWM=y
> +# CONFIG_BACKLIGHT_ADP8860 is not set
> +# CONFIG_BACKLIGHT_ADP8870 is not set
> +
> +#
> +# Display device support
> +#
> +# CONFIG_DISPLAY_SUPPORT is not set
> +CONFIG_FB_MXC=y
> +CONFIG_FB_MXC_EDID=y
> +CONFIG_FB_MXC_SYNC_PANEL=y
> +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
> +CONFIG_FB_MXC_LDB=y
> +CONFIG_FB_MXC_MIPI_DSI=y
> +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
> +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
> +# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
> +# CONFIG_FB_MXC_SII902X is not set
> +# CONFIG_FB_MXC_CH7026 is not set
> +# CONFIG_FB_MXC_TVOUT_CH7024 is not set
> +# CONFIG_FB_MXC_ASYNC_PANEL is not set
> +CONFIG_FB_MXC_EINK_PANEL=y
> +# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set
> +# CONFIG_FB_MXC_SIPIX_PANEL is not set
> +# CONFIG_FB_MXC_ELCDIF_FB is not set
> +CONFIG_FB_MXC_HDMI=y
> +
> +#
> +# Console display driver support
> +#
> +CONFIG_DUMMY_CONSOLE=y
> +CONFIG_FRAMEBUFFER_CONSOLE=y
> +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> +CONFIG_FONTS=y
> +# CONFIG_FONT_8x8 is not set
> +CONFIG_FONT_8x16=y
> +# CONFIG_FONT_6x11 is not set
> +# CONFIG_FONT_7x14 is not set
> +# CONFIG_FONT_PEARL_8x8 is not set
> +# CONFIG_FONT_ACORN_8x8 is not set
> +# CONFIG_FONT_MINI_4x6 is not set
> +# CONFIG_FONT_SUN8x16 is not set
> +# CONFIG_FONT_SUN12x22 is not set
> +# CONFIG_FONT_10x18 is not set
> +CONFIG_LOGO=y
> +CONFIG_LOGO_LINUX_MONO=y
> +CONFIG_LOGO_LINUX_VGA16=y
> +CONFIG_LOGO_LINUX_CLUT224=y
> +CONFIG_SOUND=y
> +# CONFIG_SOUND_OSS_CORE is not set
> +CONFIG_SND=y
> +CONFIG_SND_TIMER=y
> +CONFIG_SND_PCM=y
> +CONFIG_SND_HWDEP=y
> +CONFIG_SND_RAWMIDI=y
> +CONFIG_SND_JACK=y
> +# CONFIG_SND_SEQUENCER is not set
> +# CONFIG_SND_MIXER_OSS is not set
> +# CONFIG_SND_PCM_OSS is not set
> +# CONFIG_SND_HRTIMER is not set
> +# CONFIG_SND_DYNAMIC_MINORS is not set
> +CONFIG_SND_SUPPORT_OLD_API=y
> +CONFIG_SND_VERBOSE_PROCFS=y
> +# CONFIG_SND_VERBOSE_PRINTK is not set
> +# CONFIG_SND_DEBUG is not set
> +# CONFIG_SND_RAWMIDI_SEQ is not set
> +# CONFIG_SND_OPL3_LIB_SEQ is not set
> +# CONFIG_SND_OPL4_LIB_SEQ is not set
> +# CONFIG_SND_SBAWE_SEQ is not set
> +# CONFIG_SND_EMU10K1_SEQ is not set
> +CONFIG_SND_DRIVERS=y
> +# CONFIG_SND_DUMMY is not set
> +# CONFIG_SND_ALOOP is not set
> +# CONFIG_SND_MTPAV is not set
> +# CONFIG_SND_SERIAL_U16550 is not set
> +# CONFIG_SND_MPU401 is not set
> +CONFIG_SND_ARM=y
> +# CONFIG_SND_ARMAACI is not set
> +CONFIG_SND_SPI=y
> +CONFIG_SND_USB=y
> +CONFIG_SND_USB_AUDIO=y
> +# CONFIG_SND_USB_UA101 is not set
> +# CONFIG_SND_USB_CAIAQ is not set
> +# CONFIG_SND_USB_6FIRE is not set
> +CONFIG_SND_SOC=y
> +# CONFIG_SND_SOC_CACHE_LZO is not set
> +CONFIG_SND_SOC_AC97_BUS=y
> +CONFIG_SND_IMX_SOC=y
> +CONFIG_SND_MXC_SOC_MX2=y
> +CONFIG_SND_MXC_SOC_SPDIF_DAI=y
> +CONFIG_SND_SOC_IMX_SGTL5000=y
> +# CONFIG_SND_SOC_IMX_WM8958 is not set
> +CONFIG_SND_SOC_IMX_WM8962=y
> +CONFIG_SND_SOC_IMX_CS42888=y
> +# CONFIG_SND_SOC_IMX_SI4763 is not set
> +CONFIG_SND_SOC_IMX_SPDIF=y
> +CONFIG_SND_SOC_IMX_HDMI=y
> +CONFIG_SND_SOC_I2C_AND_SPI=y
> +# CONFIG_SND_SOC_ALL_CODECS is not set
> +CONFIG_SND_SOC_MXC_HDMI=y
> +CONFIG_SND_SOC_MXC_SPDIF=y
> +CONFIG_SND_SOC_SGTL5000=y
> +CONFIG_SND_SOC_CS42888=y
> +CONFIG_SND_SOC_WM8962=y
> +# CONFIG_SOUND_PRIME is not set
> +CONFIG_AC97_BUS=y
> +CONFIG_HID_SUPPORT=y
> +CONFIG_HID=y
> +CONFIG_HIDRAW=y
> +
> +#
> +# USB Input Devices
> +#
> +CONFIG_USB_HID=y
> +# CONFIG_HID_PID is not set
> +# CONFIG_USB_HIDDEV is not set
> +
> +#
> +# Special HID drivers
> +#
> +CONFIG_HID_A4TECH=m
> +# CONFIG_HID_ACRUX is not set
> +CONFIG_HID_APPLE=m
> +CONFIG_HID_BELKIN=m
> +CONFIG_HID_CHERRY=m
> +CONFIG_HID_CHICONY=m
> +# CONFIG_HID_PRODIKEYS is not set
> +CONFIG_HID_CYPRESS=m
> +# CONFIG_HID_DRAGONRISE is not set
> +# CONFIG_HID_EMS_FF is not set
> +# CONFIG_HID_ELECOM is not set
> +CONFIG_HID_EZKEY=m
> +# CONFIG_HID_KEYTOUCH is not set
> +# CONFIG_HID_KYE is not set
> +# CONFIG_HID_UCLOGIC is not set
> +# CONFIG_HID_WALTOP is not set
> +CONFIG_HID_GYRATION=m
> +# CONFIG_HID_TWINHAN is not set
> +# CONFIG_HID_KENSINGTON is not set
> +# CONFIG_HID_LCPOWER is not set
> +CONFIG_HID_LOGITECH=m
> +# CONFIG_LOGITECH_FF is not set
> +# CONFIG_LOGIRUMBLEPAD2_FF is not set
> +# CONFIG_LOGIG940_FF is not set
> +# CONFIG_LOGIWII_FF is not set
> +# CONFIG_HID_MAGICMOUSE is not set
> +CONFIG_HID_MICROSOFT=m
> +CONFIG_HID_MONTEREY=m
> +# CONFIG_HID_MULTITOUCH is not set
> +# CONFIG_HID_NTRIG is not set
> +# CONFIG_HID_ORTEK is not set
> +CONFIG_HID_PANTHERLORD=m
> +# CONFIG_PANTHERLORD_FF is not set
> +CONFIG_HID_PETALYNX=m
> +# CONFIG_HID_PICOLCD is not set
> +# CONFIG_HID_QUANTA is not set
> +# CONFIG_HID_ROCCAT is not set
> +# CONFIG_HID_ROCCAT_ARVO is not set
> +# CONFIG_HID_ROCCAT_KONE is not set
> +# CONFIG_HID_ROCCAT_KONEPLUS is not set
> +# CONFIG_HID_ROCCAT_KOVAPLUS is not set
> +# CONFIG_HID_ROCCAT_PYRA is not set
> +CONFIG_HID_SAMSUNG=m
> +CONFIG_HID_SONY=m
> +CONFIG_HID_SUNPLUS=m
> +# CONFIG_HID_GREENASIA is not set
> +# CONFIG_HID_SMARTJOYPLUS is not set
> +# CONFIG_HID_TOPSEED is not set
> +# CONFIG_HID_THRUSTMASTER is not set
> +# CONFIG_HID_WACOM is not set
> +# CONFIG_HID_ZEROPLUS is not set
> +# CONFIG_HID_ZYDACRON is not set
> +CONFIG_USB_SUPPORT=y
> +CONFIG_USB_ARCH_HAS_HCD=y
> +# CONFIG_USB_ARCH_HAS_OHCI is not set
> +CONFIG_USB_ARCH_HAS_EHCI=y
> +CONFIG_USB=y
> +# CONFIG_USB_DEBUG is not set
> +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> +
> +#
> +# Miscellaneous USB options
> +#
> +# CONFIG_USB_DEVICEFS is not set
> +# CONFIG_USB_DEVICE_CLASS is not set
> +# CONFIG_USB_DYNAMIC_MINORS is not set
> +CONFIG_USB_SUSPEND=y
> +CONFIG_USB_OTG=y
> +# CONFIG_USB_OTG_WHITELIST is not set
> +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> +# CONFIG_USB_MON is not set
> +# CONFIG_USB_WUSB is not set
> +# CONFIG_USB_WUSB_CBAF is not set
> +
> +#
> +# USB Host Controller Drivers
> +#
> +# CONFIG_USB_C67X00_HCD is not set
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_ARC=y
> +CONFIG_USB_EHCI_ARC_OTG=y
> +# CONFIG_USB_EHCI_ARC_HSIC is not set
> +# CONFIG_USB_STATIC_IRAM is not set
> +CONFIG_USB_EHCI_ROOT_HUB_TT=y
> +# CONFIG_USB_EHCI_TT_NEWSCHED is not set
> +# CONFIG_USB_EHCI_MXC is not set
> +# CONFIG_USB_OXU210HP_HCD is not set
> +# CONFIG_USB_ISP116X_HCD is not set
> +# CONFIG_USB_ISP1760_HCD is not set
> +# CONFIG_USB_ISP1362_HCD is not set
> +# CONFIG_USB_SL811_HCD is not set
> +# CONFIG_USB_R8A66597_HCD is not set
> +# CONFIG_USB_HWA_HCD is not set
> +# CONFIG_USB_MUSB_HDRC is not set
> +
> +#
> +# USB Device Class drivers
> +#
> +# CONFIG_USB_ACM is not set
> +# CONFIG_USB_PRINTER is not set
> +# CONFIG_USB_WDM is not set
> +# CONFIG_USB_TMC is not set
> +
> +#
> +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
> +#
> +
> +#
> +# also be needed; see USB_STORAGE Help for more info
> +#
> +CONFIG_USB_STORAGE=y
> +# CONFIG_USB_STORAGE_DEBUG is not set
> +# CONFIG_USB_STORAGE_REALTEK is not set
> +# CONFIG_USB_STORAGE_DATAFAB is not set
> +# CONFIG_USB_STORAGE_FREECOM is not set
> +# CONFIG_USB_STORAGE_ISD200 is not set
> +# CONFIG_USB_STORAGE_USBAT is not set
> +# CONFIG_USB_STORAGE_SDDR09 is not set
> +# CONFIG_USB_STORAGE_SDDR55 is not set
> +# CONFIG_USB_STORAGE_JUMPSHOT is not set
> +# CONFIG_USB_STORAGE_ALAUDA is not set
> +# CONFIG_USB_STORAGE_ONETOUCH is not set
> +# CONFIG_USB_STORAGE_KARMA is not set
> +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
> +# CONFIG_USB_STORAGE_ENE_UB6250 is not set
> +# CONFIG_USB_UAS is not set
> +# CONFIG_USB_LIBUSUAL is not set
> +
> +#
> +# USB Imaging devices
> +#
> +# CONFIG_USB_MDC800 is not set
> +# CONFIG_USB_MICROTEK is not set
> +
> +#
> +# USB port drivers
> +#
> +# CONFIG_USB_SERIAL is not set
> +
> +#
> +# USB Miscellaneous drivers
> +#
> +# CONFIG_USB_EMI62 is not set
> +# CONFIG_USB_EMI26 is not set
> +# CONFIG_USB_ADUTUX is not set
> +# CONFIG_USB_SEVSEG is not set
> +# CONFIG_USB_RIO500 is not set
> +# CONFIG_USB_LEGOTOWER is not set
> +# CONFIG_USB_LCD is not set
> +# CONFIG_USB_LED is not set
> +# CONFIG_USB_CYPRESS_CY7C63 is not set
> +# CONFIG_USB_CYTHERM is not set
> +# CONFIG_USB_IDMOUSE is not set
> +# CONFIG_USB_FTDI_ELAN is not set
> +# CONFIG_USB_APPLEDISPLAY is not set
> +# CONFIG_USB_SISUSBVGA is not set
> +# CONFIG_USB_LD is not set
> +# CONFIG_USB_TRANCEVIBRATOR is not set
> +# CONFIG_USB_IOWARRIOR is not set
> +# CONFIG_USB_TEST is not set
> +# CONFIG_USB_ISIGHTFW is not set
> +# CONFIG_USB_YUREX is not set
> +CONFIG_USB_GADGET=y
> +# CONFIG_USB_GADGET_DEBUG_FILES is not set
> +# CONFIG_USB_GADGET_DEBUG_FS is not set
> +CONFIG_USB_GADGET_VBUS_DRAW=2
> +CONFIG_USB_GADGET_SELECTED=y
> +CONFIG_USB_GADGET_ARC=y
> +# CONFIG_IMX_USB_CHARGER is not set
> +CONFIG_USB_ARC=y
> +# CONFIG_USB_GADGET_FSL_USB2 is not set
> +# CONFIG_USB_GADGET_FUSB300 is not set
> +# CONFIG_USB_GADGET_R8A66597 is not set
> +# CONFIG_USB_GADGET_PXA_U2O is not set
> +# CONFIG_USB_GADGET_M66592 is not set
> +# CONFIG_USB_GADGET_DUMMY_HCD is not set
> +CONFIG_USB_GADGET_DUALSPEED=y
> +# CONFIG_USB_ZERO is not set
> +CONFIG_USB_AUDIO=m
> +CONFIG_USB_ETH=m
> +CONFIG_USB_ETH_RNDIS=y
> +# CONFIG_USB_ETH_EEM is not set
> +# CONFIG_USB_G_NCM is not set
> +# CONFIG_USB_GADGETFS is not set
> +# CONFIG_USB_FUNCTIONFS is not set
> +CONFIG_USB_FILE_STORAGE=m
> +# CONFIG_FSL_UTP is not set
> +# CONFIG_USB_FILE_STORAGE_TEST is not set
> +# CONFIG_USB_MASS_STORAGE is not set
> +CONFIG_USB_G_SERIAL=m
> +# CONFIG_USB_MIDI_GADGET is not set
> +# CONFIG_USB_G_PRINTER is not set
> +# CONFIG_USB_CDC_COMPOSITE is not set
> +# CONFIG_USB_G_MULTI is not set
> +# CONFIG_USB_G_HID is not set
> +# CONFIG_USB_G_DBGP is not set
> +# CONFIG_USB_G_WEBCAM is not set
> +
> +#
> +# OTG and related infrastructure
> +#
> +CONFIG_USB_OTG_UTILS=y
> +# CONFIG_USB_GPIO_VBUS is not set
> +# CONFIG_USB_ULPI is not set
> +# CONFIG_NOP_USB_XCEIV is not set
> +CONFIG_MXC_OTG=y
> +CONFIG_MMC=y
> +# CONFIG_MMC_DEBUG is not set
> +CONFIG_MMC_UNSAFE_RESUME=y
> +# CONFIG_MMC_CLKGATE is not set
> +
> +#
> +# MMC/SD/SDIO Card Drivers
> +#
> +CONFIG_MMC_BLOCK=y
> +CONFIG_MMC_BLOCK_MINORS=8
> +CONFIG_MMC_BLOCK_BOUNCE=y
> +# CONFIG_SDIO_UART is not set
> +# CONFIG_MMC_TEST is not set
> +
> +#
> +# MMC/SD/SDIO Host Controller Drivers
> +#
> +# CONFIG_MMC_ARMMMCI is not set
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_IO_ACCESSORS=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_ESDHC_IMX=y
> +# CONFIG_MMC_DW is not set
> +# CONFIG_MMC_VUB300 is not set
> +# CONFIG_MMC_USHC is not set
> +# CONFIG_MEMSTICK is not set
> +CONFIG_NEW_LEDS=y
> +CONFIG_LEDS_CLASS=y
> +
> +#
> +# LED drivers
> +#
> +# CONFIG_LEDS_LM3530 is not set
> +# CONFIG_LEDS_PCA9532 is not set
> +CONFIG_LEDS_GPIO=y
> +CONFIG_LEDS_GPIO_PLATFORM=y
> +# CONFIG_LEDS_LP3944 is not set
> +# CONFIG_LEDS_LP5521 is not set
> +# CONFIG_LEDS_LP5523 is not set
> +# CONFIG_LEDS_PCA955X is not set
> +# CONFIG_LEDS_DAC124S085 is not set
> +# CONFIG_LEDS_PWM is not set
> +# CONFIG_LEDS_REGULATOR is not set
> +# CONFIG_LEDS_BD2802 is not set
> +# CONFIG_LEDS_LT3593 is not set
> +CONFIG_LEDS_TRIGGERS=y
> +
> +#
> +# LED Triggers
> +#
> +# CONFIG_LEDS_TRIGGER_TIMER is not set
> +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
> +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
> +CONFIG_LEDS_TRIGGER_GPIO=y
> +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> +
> +#
> +# iptables trigger is under Netfilter config (LED target)
> +#
> +
> +#
> +# LED Triggers
> +#
> +# CONFIG_NFC_DEVICES is not set
> +# CONFIG_ACCESSIBILITY is not set
> +CONFIG_RTC_LIB=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_HCTOSYS=y
> +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> +# CONFIG_RTC_DEBUG is not set
> +
> +#
> +# RTC interfaces
> +#
> +CONFIG_RTC_INTF_SYSFS=y
> +CONFIG_RTC_INTF_PROC=y
> +CONFIG_RTC_INTF_DEV=y
> +CONFIG_RTC_INTF_DEV_UIE_EMUL=y
> +# CONFIG_RTC_DRV_TEST is not set
> +
> +#
> +# I2C RTC drivers
> +#
> +# CONFIG_RTC_DRV_DS1307 is not set
> +# CONFIG_RTC_DRV_DS1374 is not set
> +# CONFIG_RTC_DRV_DS1672 is not set
> +# CONFIG_RTC_DRV_DS3232 is not set
> +# CONFIG_RTC_DRV_MAX6900 is not set
> +# CONFIG_RTC_DRV_RS5C372 is not set
> +# CONFIG_RTC_DRV_ISL1208 is not set
> +# CONFIG_RTC_DRV_ISL12022 is not set
> +# CONFIG_RTC_DRV_X1205 is not set
> +# CONFIG_RTC_DRV_PCF8563 is not set
> +# CONFIG_RTC_DRV_PCF8583 is not set
> +# CONFIG_RTC_DRV_M41T80 is not set
> +# CONFIG_RTC_DRV_BQ32K is not set
> +# CONFIG_RTC_DRV_S35390A is not set
> +# CONFIG_RTC_DRV_FM3130 is not set
> +# CONFIG_RTC_DRV_RX8581 is not set
> +# CONFIG_RTC_DRV_RX8025 is not set
> +# CONFIG_RTC_DRV_EM3027 is not set
> +# CONFIG_RTC_DRV_RV3029C2 is not set
> +
> +#
> +# SPI RTC drivers
> +#
> +# CONFIG_RTC_DRV_M41T93 is not set
> +# CONFIG_RTC_DRV_M41T94 is not set
> +# CONFIG_RTC_DRV_DS1305 is not set
> +# CONFIG_RTC_DRV_DS1390 is not set
> +# CONFIG_RTC_DRV_MAX6902 is not set
> +# CONFIG_RTC_DRV_R9701 is not set
> +# CONFIG_RTC_DRV_RS5C348 is not set
> +# CONFIG_RTC_DRV_DS3234 is not set
> +# CONFIG_RTC_DRV_PCF2123 is not set
> +
> +#
> +# Platform RTC drivers
> +#
> +# CONFIG_RTC_DRV_CMOS is not set
> +# CONFIG_RTC_DRV_DS1286 is not set
> +# CONFIG_RTC_DRV_DS1511 is not set
> +# CONFIG_RTC_DRV_DS1553 is not set
> +# CONFIG_RTC_DRV_DS1742 is not set
> +# CONFIG_RTC_DRV_STK17TA8 is not set
> +# CONFIG_RTC_DRV_M48T86 is not set
> +# CONFIG_RTC_DRV_M48T35 is not set
> +# CONFIG_RTC_DRV_M48T59 is not set
> +# CONFIG_RTC_DRV_MSM6242 is not set
> +# CONFIG_RTC_MXC is not set
> +# CONFIG_RTC_DRV_MXC_V2 is not set
> +CONFIG_RTC_DRV_SNVS=y
> +# CONFIG_RTC_DRV_BQ4802 is not set
> +# CONFIG_RTC_DRV_RP5C01 is not set
> +# CONFIG_RTC_DRV_V3020 is not set
> +
> +#
> +# on-CPU RTC drivers
> +#
> +# CONFIG_RTC_DRV_PL030 is not set
> +# CONFIG_RTC_DRV_PL031 is not set
> +CONFIG_DMADEVICES=y
> +# CONFIG_DMADEVICES_DEBUG is not set
> +
> +#
> +# DMA Devices
> +#
> +# CONFIG_AMBA_PL08X is not set
> +# CONFIG_DW_DMAC is not set
> +CONFIG_MXC_PXP_V2=y
> +CONFIG_MXC_PXP_CLIENT_DEVICE=y
> +# CONFIG_TIMB_DMA is not set
> +CONFIG_IMX_SDMA=y
> +CONFIG_MXS_DMA=y
> +CONFIG_DMA_ENGINE=y
> +
> +#
> +# DMA Clients
> +#
> +# CONFIG_NET_DMA is not set
> +# CONFIG_ASYNC_TX_DMA is not set
> +# CONFIG_DMATEST is not set
> +# CONFIG_AUXDISPLAY is not set
> +# CONFIG_UIO is not set
> +# CONFIG_STAGING is not set
> +CONFIG_CLKDEV_LOOKUP=y
> +CONFIG_CLKSRC_MMIO=y
> +
> +#
> +# MXC support drivers
> +#
> +CONFIG_MXC_IPU=y
> +CONFIG_MXC_IPU_V3=y
> +CONFIG_MXC_IPU_V3H=y
> +
> +#
> +# MXC SSI support
> +#
> +# CONFIG_MXC_SSI is not set
> +
> +#
> +# MXC Digital Audio Multiplexer support
> +#
> +# CONFIG_MXC_DAM is not set
> +
> +#
> +# MXC PMIC support
> +#
> +# CONFIG_MXC_PMIC_MC13783 is not set
> +# CONFIG_MXC_PMIC_MC13892 is not set
> +# CONFIG_MXC_PMIC_MC34704 is not set
> +# CONFIG_MXC_PMIC_MC9SDZ60 is not set
> +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
> +
> +#
> +# MXC Security Drivers
> +#
> +# CONFIG_MXC_SECURITY_SCC is not set
> +# CONFIG_MXC_SECURITY_RNG is not set
> +
> +#
> +# MXC MPEG4 Encoder Kernel module support
> +#
> +# CONFIG_MXC_HMP4E is not set
> +
> +#
> +# MXC HARDWARE EVENT
> +#
> +# CONFIG_MXC_HWEVENT is not set
> +
> +#
> +# MXC VPU(Video Processing Unit) support
> +#
> +CONFIG_MXC_VPU=y
> +# CONFIG_MXC_VPU_DEBUG is not set
> +# CONFIG_MX6_VPU_352M is not set
> +
> +#
> +# MXC Asynchronous Sample Rate Converter support
> +#
> +CONFIG_MXC_ASRC=y
> +
> +#
> +# MXC Bluetooth support
> +#
> +
> +#
> +# Broadcom GPS ioctrl support
> +#
> +
> +#
> +# MXC Media Local Bus Driver
> +#
> +CONFIG_MXC_MLB=y
> +CONFIG_MXC_MLB150=m
> +
> +#
> +# i.MX ADC support
> +#
> +# CONFIG_IMX_ADC is not set
> +
> +#
> +# MXC Vivante GPU support
> +#
> +CONFIG_MXC_GPU_VIV=y
> +
> +#
> +# ANATOP_THERMAL
> +#
> +CONFIG_ANATOP_THERMAL=y
> +
> +#
> +# MXC MIPI Support
> +#
> +CONFIG_MXC_MIPI_CSI2=y
> +
> +#
> +# MXC HDMI CEC (Consumer Electronics Control) support
> +#
> +# CONFIG_MXC_HDMI_CEC is not set
> +
> +#
> +# File systems
> +#
> +CONFIG_EXT2_FS=y
> +# CONFIG_EXT2_FS_XATTR is not set
> +# CONFIG_EXT2_FS_XIP is not set
> +CONFIG_EXT3_FS=y
> +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
> +CONFIG_EXT3_FS_XATTR=y
> +# CONFIG_EXT3_FS_POSIX_ACL is not set
> +# CONFIG_EXT3_FS_SECURITY is not set
> +CONFIG_EXT4_FS=y
> +CONFIG_EXT4_FS_XATTR=y
> +# CONFIG_EXT4_FS_POSIX_ACL is not set
> +# CONFIG_EXT4_FS_SECURITY is not set
> +# CONFIG_EXT4_DEBUG is not set
> +CONFIG_JBD=y
> +# CONFIG_JBD_DEBUG is not set
> +CONFIG_JBD2=y
> +# CONFIG_JBD2_DEBUG is not set
> +CONFIG_FS_MBCACHE=y
> +# CONFIG_REISERFS_FS is not set
> +# CONFIG_JFS_FS is not set
> +# CONFIG_XFS_FS is not set
> +# CONFIG_GFS2_FS is not set
> +# CONFIG_BTRFS_FS is not set
> +# CONFIG_NILFS2_FS is not set
> +# CONFIG_FS_POSIX_ACL is not set
> +CONFIG_FILE_LOCKING=y
> +CONFIG_FSNOTIFY=y
> +CONFIG_DNOTIFY=y
> +CONFIG_INOTIFY_USER=y
> +# CONFIG_FANOTIFY is not set
> +# CONFIG_QUOTA is not set
> +# CONFIG_QUOTACTL is not set
> +CONFIG_AUTOFS4_FS=m
> +# CONFIG_FUSE_FS is not set
> +
> +#
> +# Caches
> +#
> +# CONFIG_FSCACHE is not set
> +
> +#
> +# CD-ROM/DVD Filesystems
> +#
> +# CONFIG_ISO9660_FS is not set
> +# CONFIG_UDF_FS is not set
> +
> +#
> +# DOS/FAT/NT Filesystems
> +#
> +CONFIG_FAT_FS=y
> +CONFIG_MSDOS_FS=y
> +CONFIG_VFAT_FS=y
> +CONFIG_FAT_DEFAULT_CODEPAGE=437
> +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> +# CONFIG_NTFS_FS is not set
> +
> +#
> +# Pseudo filesystems
> +#
> +CONFIG_PROC_FS=y
> +CONFIG_PROC_SYSCTL=y
> +CONFIG_PROC_PAGE_MONITOR=y
> +CONFIG_SYSFS=y
> +CONFIG_TMPFS=y
> +# CONFIG_TMPFS_POSIX_ACL is not set
> +# CONFIG_TMPFS_XATTR is not set
> +# CONFIG_HUGETLB_PAGE is not set
> +# CONFIG_CONFIGFS_FS is not set
> +CONFIG_MISC_FILESYSTEMS=y
> +# CONFIG_ADFS_FS is not set
> +# CONFIG_AFFS_FS is not set
> +# CONFIG_HFS_FS is not set
> +# CONFIG_HFSPLUS_FS is not set
> +# CONFIG_BEFS_FS is not set
> +# CONFIG_BFS_FS is not set
> +# CONFIG_EFS_FS is not set
> +CONFIG_JFFS2_FS=y
> +CONFIG_JFFS2_FS_DEBUG=0
> +CONFIG_JFFS2_FS_WRITEBUFFER=y
> +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> +# CONFIG_JFFS2_SUMMARY is not set
> +# CONFIG_JFFS2_FS_XATTR is not set
> +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> +CONFIG_JFFS2_ZLIB=y
> +# CONFIG_JFFS2_LZO is not set
> +CONFIG_JFFS2_RTIME=y
> +# CONFIG_JFFS2_RUBIN is not set
> +CONFIG_UBIFS_FS=y
> +# CONFIG_UBIFS_FS_XATTR is not set
> +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
> +CONFIG_UBIFS_FS_LZO=y
> +CONFIG_UBIFS_FS_ZLIB=y
> +# CONFIG_UBIFS_FS_DEBUG is not set
> +# CONFIG_LOGFS is not set
> +CONFIG_CRAMFS=y
> +# CONFIG_SQUASHFS is not set
> +# CONFIG_VXFS_FS is not set
> +# CONFIG_MINIX_FS is not set
> +# CONFIG_OMFS_FS is not set
> +# CONFIG_HPFS_FS is not set
> +# CONFIG_QNX4FS_FS is not set
> +# CONFIG_ROMFS_FS is not set
> +# CONFIG_PSTORE is not set
> +# CONFIG_SYSV_FS is not set
> +# CONFIG_UFS_FS is not set
> +CONFIG_NETWORK_FILESYSTEMS=y
> +CONFIG_NFS_FS=y
> +CONFIG_NFS_V3=y
> +# CONFIG_NFS_V3_ACL is not set
> +# CONFIG_NFS_V4 is not set
> +CONFIG_ROOT_NFS=y
> +# CONFIG_NFSD is not set
> +CONFIG_LOCKD=y
> +CONFIG_LOCKD_V4=y
> +CONFIG_NFS_COMMON=y
> +CONFIG_SUNRPC=y
> +# CONFIG_CEPH_FS is not set
> +# CONFIG_CIFS is not set
> +# CONFIG_NCP_FS is not set
> +# CONFIG_CODA_FS is not set
> +# CONFIG_AFS_FS is not set
> +
> +#
> +# Partition Types
> +#
> +CONFIG_PARTITION_ADVANCED=y
> +# CONFIG_ACORN_PARTITION is not set
> +# CONFIG_OSF_PARTITION is not set
> +# CONFIG_AMIGA_PARTITION is not set
> +# CONFIG_ATARI_PARTITION is not set
> +# CONFIG_MAC_PARTITION is not set
> +CONFIG_MSDOS_PARTITION=y
> +# CONFIG_BSD_DISKLABEL is not set
> +# CONFIG_MINIX_SUBPARTITION is not set
> +# CONFIG_SOLARIS_X86_PARTITION is not set
> +# CONFIG_UNIXWARE_DISKLABEL is not set
> +# CONFIG_LDM_PARTITION is not set
> +# CONFIG_SGI_PARTITION is not set
> +# CONFIG_ULTRIX_PARTITION is not set
> +# CONFIG_SUN_PARTITION is not set
> +# CONFIG_KARMA_PARTITION is not set
> +CONFIG_EFI_PARTITION=y
> +# CONFIG_SYSV68_PARTITION is not set
> +CONFIG_NLS=y
> +CONFIG_NLS_DEFAULT="iso8859-1"
> +CONFIG_NLS_CODEPAGE_437=y
> +# CONFIG_NLS_CODEPAGE_737 is not set
> +# CONFIG_NLS_CODEPAGE_775 is not set
> +# CONFIG_NLS_CODEPAGE_850 is not set
> +# CONFIG_NLS_CODEPAGE_852 is not set
> +# CONFIG_NLS_CODEPAGE_855 is not set
> +# CONFIG_NLS_CODEPAGE_857 is not set
> +# CONFIG_NLS_CODEPAGE_860 is not set
> +# CONFIG_NLS_CODEPAGE_861 is not set
> +# CONFIG_NLS_CODEPAGE_862 is not set
> +# CONFIG_NLS_CODEPAGE_863 is not set
> +# CONFIG_NLS_CODEPAGE_864 is not set
> +# CONFIG_NLS_CODEPAGE_865 is not set
> +# CONFIG_NLS_CODEPAGE_866 is not set
> +# CONFIG_NLS_CODEPAGE_869 is not set
> +# CONFIG_NLS_CODEPAGE_936 is not set
> +# CONFIG_NLS_CODEPAGE_950 is not set
> +# CONFIG_NLS_CODEPAGE_932 is not set
> +# CONFIG_NLS_CODEPAGE_949 is not set
> +# CONFIG_NLS_CODEPAGE_874 is not set
> +# CONFIG_NLS_ISO8859_8 is not set
> +# CONFIG_NLS_CODEPAGE_1250 is not set
> +# CONFIG_NLS_CODEPAGE_1251 is not set
> +CONFIG_NLS_ASCII=m
> +CONFIG_NLS_ISO8859_1=y
> +# CONFIG_NLS_ISO8859_2 is not set
> +# CONFIG_NLS_ISO8859_3 is not set
> +# CONFIG_NLS_ISO8859_4 is not set
> +# CONFIG_NLS_ISO8859_5 is not set
> +# CONFIG_NLS_ISO8859_6 is not set
> +# CONFIG_NLS_ISO8859_7 is not set
> +# CONFIG_NLS_ISO8859_9 is not set
> +# CONFIG_NLS_ISO8859_13 is not set
> +# CONFIG_NLS_ISO8859_14 is not set
> +# CONFIG_NLS_ISO8859_15 is not set
> +# CONFIG_NLS_KOI8_R is not set
> +# CONFIG_NLS_KOI8_U is not set
> +CONFIG_NLS_UTF8=m
> +
> +#
> +# Kernel hacking
> +#
> +# CONFIG_PRINTK_TIME is not set
> +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
> +CONFIG_ENABLE_WARN_DEPRECATED=y
> +CONFIG_ENABLE_MUST_CHECK=y
> +CONFIG_FRAME_WARN=1024
> +CONFIG_MAGIC_SYSRQ=y
> +# CONFIG_STRIP_ASM_SYMS is not set
> +# CONFIG_UNUSED_SYMBOLS is not set
> +CONFIG_DEBUG_FS=y
> +# CONFIG_HEADERS_CHECK is not set
> +# CONFIG_DEBUG_SECTION_MISMATCH is not set
> +# CONFIG_DEBUG_KERNEL is not set
> +# CONFIG_HARDLOCKUP_DETECTOR is not set
> +# CONFIG_SLUB_DEBUG_ON is not set
> +# CONFIG_SLUB_STATS is not set
> +# CONFIG_SPARSE_RCU_POINTER is not set
> +CONFIG_DEBUG_BUGVERBOSE=y
> +# CONFIG_DEBUG_MEMORY_INIT is not set
> +CONFIG_RCU_CPU_STALL_TIMEOUT=60
> +CONFIG_RCU_CPU_STALL_VERBOSE=y
> +# CONFIG_LKDTM is not set
> +CONFIG_SYSCTL_SYSCALL_CHECK=y
> +CONFIG_HAVE_FUNCTION_TRACER=y
> +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
> +CONFIG_HAVE_DYNAMIC_FTRACE=y
> +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
> +CONFIG_HAVE_C_RECORDMCOUNT=y
> +CONFIG_TRACING_SUPPORT=y
> +# CONFIG_FTRACE is not set
> +# CONFIG_DYNAMIC_DEBUG is not set
> +# CONFIG_DMA_API_DEBUG is not set
> +# CONFIG_ATOMIC64_SELFTEST is not set
> +# CONFIG_SAMPLES is not set
> +CONFIG_HAVE_ARCH_KGDB=y
> +# CONFIG_TEST_KSTRTOX is not set
> +# CONFIG_STRICT_DEVMEM is not set
> +CONFIG_ARM_UNWIND=y
> +# CONFIG_DEBUG_USER is not set
> +CONFIG_OC_ETM=y
> +
> +#
> +# Security options
> +#
> +# CONFIG_KEYS is not set
> +# CONFIG_SECURITY_DMESG_RESTRICT is not set
> +# CONFIG_SECURITY is not set
> +# CONFIG_SECURITYFS is not set
> +CONFIG_DEFAULT_SECURITY_DAC=y
> +CONFIG_DEFAULT_SECURITY=""
> +CONFIG_CRYPTO=y
> +
> +#
> +# Crypto core or helper
> +#
> +CONFIG_CRYPTO_ALGAPI=y
> +CONFIG_CRYPTO_ALGAPI2=y
> +CONFIG_CRYPTO_AEAD=y
> +CONFIG_CRYPTO_AEAD2=y
> +CONFIG_CRYPTO_BLKCIPHER=y
> +CONFIG_CRYPTO_BLKCIPHER2=y
> +CONFIG_CRYPTO_HASH=y
> +CONFIG_CRYPTO_HASH2=y
> +CONFIG_CRYPTO_RNG=y
> +CONFIG_CRYPTO_RNG2=y
> +CONFIG_CRYPTO_PCOMP2=y
> +CONFIG_CRYPTO_MANAGER=y
> +CONFIG_CRYPTO_MANAGER2=y
> +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
> +CONFIG_CRYPTO_GF128MUL=y
> +# CONFIG_CRYPTO_NULL is not set
> +# CONFIG_CRYPTO_PCRYPT is not set
> +CONFIG_CRYPTO_WORKQUEUE=y
> +# CONFIG_CRYPTO_CRYPTD is not set
> +CONFIG_CRYPTO_AUTHENC=y
> +CONFIG_CRYPTO_TEST=m
> +# CONFIG_CRYPTO_CRYPTODEV is not set
> +
> +#
> +# Authenticated Encryption with Associated Data
> +#
> +CONFIG_CRYPTO_CCM=y
> +CONFIG_CRYPTO_GCM=y
> +CONFIG_CRYPTO_SEQIV=y
> +
> +#
> +# Block modes
> +#
> +CONFIG_CRYPTO_CBC=y
> +CONFIG_CRYPTO_CTR=y
> +CONFIG_CRYPTO_CTS=y
> +CONFIG_CRYPTO_ECB=y
> +CONFIG_CRYPTO_LRW=y
> +CONFIG_CRYPTO_PCBC=y
> +CONFIG_CRYPTO_XTS=y
> +
> +#
> +# Hash modes
> +#
> +# CONFIG_CRYPTO_HMAC is not set
> +# CONFIG_CRYPTO_XCBC is not set
> +# CONFIG_CRYPTO_VMAC is not set
> +
> +#
> +# Digest
> +#
> +# CONFIG_CRYPTO_CRC32C is not set
> +CONFIG_CRYPTO_GHASH=y
> +# CONFIG_CRYPTO_MD4 is not set
> +# CONFIG_CRYPTO_MD5 is not set
> +CONFIG_CRYPTO_MICHAEL_MIC=y
> +# CONFIG_CRYPTO_RMD128 is not set
> +# CONFIG_CRYPTO_RMD160 is not set
> +# CONFIG_CRYPTO_RMD256 is not set
> +# CONFIG_CRYPTO_RMD320 is not set
> +# CONFIG_CRYPTO_SHA1 is not set
> +# CONFIG_CRYPTO_SHA256 is not set
> +# CONFIG_CRYPTO_SHA512 is not set
> +# CONFIG_CRYPTO_TGR192 is not set
> +# CONFIG_CRYPTO_WP512 is not set
> +
> +#
> +# Ciphers
> +#
> +CONFIG_CRYPTO_AES=y
> +# CONFIG_CRYPTO_ANUBIS is not set
> +CONFIG_CRYPTO_ARC4=y
> +# CONFIG_CRYPTO_BLOWFISH is not set
> +# CONFIG_CRYPTO_CAMELLIA is not set
> +# CONFIG_CRYPTO_CAST5 is not set
> +# CONFIG_CRYPTO_CAST6 is not set
> +CONFIG_CRYPTO_DES=y
> +# CONFIG_CRYPTO_FCRYPT is not set
> +# CONFIG_CRYPTO_KHAZAD is not set
> +# CONFIG_CRYPTO_SALSA20 is not set
> +# CONFIG_CRYPTO_SEED is not set
> +# CONFIG_CRYPTO_SERPENT is not set
> +# CONFIG_CRYPTO_TEA is not set
> +# CONFIG_CRYPTO_TWOFISH is not set
> +
> +#
> +# Compression
> +#
> +CONFIG_CRYPTO_DEFLATE=y
> +# CONFIG_CRYPTO_ZLIB is not set
> +CONFIG_CRYPTO_LZO=y
> +
> +#
> +# Random Number Generation
> +#
> +# CONFIG_CRYPTO_ANSI_CPRNG is not set
> +# CONFIG_CRYPTO_USER_API_HASH is not set
> +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
> +CONFIG_CRYPTO_HW=y
> +CONFIG_CRYPTO_DEV_FSL_CAAM=y
> +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y
> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255
> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048
> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
> +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
> +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
> +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7
> +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
> +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
> +# CONFIG_BINARY_PRINTF is not set
> +
> +#
> +# Library routines
> +#
> +CONFIG_BITREVERSE=y
> +CONFIG_RATIONAL=y
> +CONFIG_CRC_CCITT=m
> +CONFIG_CRC16=y
> +# CONFIG_CRC_T10DIF is not set
> +# CONFIG_CRC_ITU_T is not set
> +CONFIG_CRC32=y
> +# CONFIG_CRC7 is not set
> +# CONFIG_LIBCRC32C is not set
> +CONFIG_ZLIB_INFLATE=y
> +CONFIG_ZLIB_DEFLATE=y
> +CONFIG_LZO_COMPRESS=y
> +CONFIG_LZO_DECOMPRESS=y
> +# CONFIG_XZ_DEC is not set
> +# CONFIG_XZ_DEC_BCJ is not set
> +CONFIG_GENERIC_ALLOCATOR=y
> +CONFIG_HAS_IOMEM=y
> +CONFIG_HAS_IOPORT=y
> +CONFIG_HAS_DMA=y
> +CONFIG_CPU_RMAP=y
> +CONFIG_NLATTR=y
> +# CONFIG_AVERAGE is not set
> diff --git a/recipes-kernel/linux/linux-imx_3.0.35.bbappend b/recipes-kernel/linux/linux-imx_3.0.35.bbappend
> new file mode 100644
> index 0000000..7554c66
> --- /dev/null
> +++ b/recipes-kernel/linux/linux-imx_3.0.35.bbappend
> @@ -0,0 +1,8 @@
> +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}-${PV}:"
> +
> +PRINC := "${@int(PRINC) + 1}"
> +
> +# Wandboard-specific patches
> +SRC_URI_append_wandboard-dual= " \
> + file://Initial-kernel-support-for-Wandboard.patch \
> +"
> --
> 1.7.9.5
>
> _______________________________________________
> meta-freescale mailing list
> meta-freescale@yoctoproject.org
> https://lists.yoctoproject.org/listinfo/meta-freescale
--
Otavio Salvador O.S. Systems
E-mail: otavio@ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [meta-fsl-arm-extra][PATCH 2/3] Add U-boot support for Wandboard Dual
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 2/3] Add U-boot " John Weber
@ 2013-02-26 19:24 ` Otavio Salvador
2013-02-26 20:11 ` John Weber
0 siblings, 1 reply; 8+ messages in thread
From: Otavio Salvador @ 2013-02-26 19:24 UTC (permalink / raw)
To: John Weber; +Cc: meta-freescale
On Sat, Feb 23, 2013 at 5:29 PM, John Weber <rjohnweber@gmail.com> wrote:
> This patch adds U-boot-imx support for Wandboard Dual. It is
> meant to patch the 2009.08 u-boot from the 1.1.0 FSL SDK.
Same comments as done in the kernel patch.
> Signed-off-by: John Weber <rjohnweber@gmail.com>
> ---
> Upstream-Status: Pending
> .../Initial-support-for-Wandboard-Dual.patch | 1773 ++++++++++++++++++++
> recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend | 8 +
> 2 files changed, 1781 insertions(+)
> create mode 100644 recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-Dual.patch
> create mode 100644 recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
>
> diff --git a/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-Dual.patch b/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-Dual.patch
> new file mode 100644
> index 0000000..cdb641f
> --- /dev/null
> +++ b/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-Dual.patch
> @@ -0,0 +1,1773 @@
> +From eb057c5028d8f5e7243b0875d2bd299ecb376e01 Mon Sep 17 00:00:00 2001
> +From: John Weber <rjohnweber@gmail.com>
> +Date: Fri, 22 Feb 2013 08:49:27 -0600
> +Subject: [PATCH] Initial support for Wandboard Dual
> +
> + That patch adds support for Wandboard. It has been tested on
> + Wandboard-Dual. The serial port, module microSD card slot,
> + and ethernet ports were found to work. Testers welcome.
> +
> + Almost all of this was ported directly from the Wandboard SDK
> + released Feb 5, 2013 and was the work of Tapani.
> +
> +---
> + Makefile | 3 +
> + board/freescale/wandboard/Makefile | 47 +++
> + board/freescale/wandboard/config.mk | 7 +
> + board/freescale/wandboard/flash_header.S | 572 +++++++++++++++++++++++++++++
> + board/freescale/wandboard/lowlevel_init.S | 171 +++++++++
> + board/freescale/wandboard/u-boot.lds | 74 ++++
> + board/freescale/wandboard/wandboard.c | 494 +++++++++++++++++++++++++
> + include/asm-arm/mach-types.h | 27 ++
> + include/configs/wandboard.h | 273 ++++++++++++++
> + 9 files changed, 1668 insertions(+)
> + create mode 100644 board/freescale/wandboard/Makefile
> + create mode 100644 board/freescale/wandboard/config.mk
> + create mode 100644 board/freescale/wandboard/flash_header.S
> + create mode 100644 board/freescale/wandboard/lowlevel_init.S
> + create mode 100644 board/freescale/wandboard/u-boot.lds
> + create mode 100644 board/freescale/wandboard/wandboard.c
> + create mode 100644 include/configs/wandboard.h
> +
> +diff --git a/Makefile b/Makefile
> +index 1088794..41cca34 100644
> +--- a/Makefile
> ++++ b/Makefile
> +@@ -3387,6 +3387,9 @@ mx6sl_evk_iram_config : unconfig
> + }
> + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6sl_evk freescale mx6
> +
> ++wandboard_config : unconfig
> ++ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 wandboard freescale mx6
> ++
> + omap2420h4_config : unconfig
> + @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
> +
> +diff --git a/board/freescale/wandboard/Makefile b/board/freescale/wandboard/Makefile
> +new file mode 100644
> +index 0000000..c0b30e4
> +--- /dev/null
> ++++ b/board/freescale/wandboard/Makefile
> +@@ -0,0 +1,47 @@
> ++#
> ++# (C) Copyright 2010-2011 Freescale Semiconductor, Inc.
> ++#
> ++# This program is free software; you can redistribute it and/or
> ++# modify it under the terms of the GNU General Public License as
> ++# published by the Free Software Foundation; either version 2 of
> ++# the License, or (at your option) any later version.
> ++#
> ++# This program is distributed in the hope that it will be useful,
> ++# but WITHOUT ANY WARRANTY; without even the implied warranty of
> ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> ++# GNU General Public License for more details.
> ++#
> ++# You should have received a copy of the GNU General Public License
> ++# along with this program; if not, write to the Free Software
> ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> ++# MA 02111-1307 USA
> ++#
> ++
> ++include $(TOPDIR)/config.mk
> ++
> ++LIB = $(obj)lib$(BOARD).a
> ++
> ++COBJS := $(BOARD).o
> ++SOBJS := lowlevel_init.o flash_header.o
> ++
> ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> ++OBJS := $(addprefix $(obj),$(COBJS))
> ++SOBJS := $(addprefix $(obj),$(SOBJS))
> ++
> ++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> ++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> ++
> ++clean:
> ++ rm -f $(SOBJS) $(OBJS)
> ++
> ++distclean: clean
> ++ rm -f $(LIB) core *.bak .depend
> ++
> ++#########################################################################
> ++
> ++# defines $(obj).depend target
> ++include $(SRCTREE)/rules.mk
> ++
> ++sinclude $(obj).depend
> ++
> ++#########################################################################
> +diff --git a/board/freescale/wandboard/config.mk b/board/freescale/wandboard/config.mk
> +new file mode 100644
> +index 0000000..a0ce2a1
> +--- /dev/null
> ++++ b/board/freescale/wandboard/config.mk
> +@@ -0,0 +1,7 @@
> ++LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
> ++
> ++sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
> ++
> ++ifndef TEXT_BASE
> ++ TEXT_BASE = 0x27800000
> ++endif
> +diff --git a/board/freescale/wandboard/flash_header.S b/board/freescale/wandboard/flash_header.S
> +new file mode 100644
> +index 0000000..f97d970
> +--- /dev/null
> ++++ b/board/freescale/wandboard/flash_header.S
> +@@ -0,0 +1,572 @@
> ++/*
> ++ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
> ++ *
> ++ * This program is free software; you can redistribute it and/or
> ++ * modify it under the terms of the GNU General Public License as
> ++ * published by the Free Software Foundation; either version 2 of
> ++ * the License, or (at your option) any later version.
> ++ *
> ++ * This program is distributed in the hope that it will be useful,
> ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> ++ * GNU General Public License for more details.
> ++ *
> ++ * You should have received a copy of the GNU General Public License
> ++ * along with this program; if not, write to the Free Software
> ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> ++ * MA 02111-1307 USA
> ++ */
> ++
> ++#include <config.h>
> ++#include <asm/arch/mx6.h>
> ++
> ++#ifdef CONFIG_FLASH_HEADER
> ++#ifndef CONFIG_FLASH_HEADER_OFFSET
> ++# error "Must define the offset of flash header"
> ++#endif
> ++
> ++#define CPU_2_BE_32(l) \
> ++ ((((l) & 0x000000FF) << 24) | \
> ++ (((l) & 0x0000FF00) << 8) | \
> ++ (((l) & 0x00FF0000) >> 8) | \
> ++ (((l) & 0xFF000000) >> 24))
> ++
> ++#define MXC_DCD_ITEM(i, addr, val) \
> ++dcd_node_##i: \
> ++ .word CPU_2_BE_32(addr) ; \
> ++ .word CPU_2_BE_32(val) ; \
> ++
> ++.section ".text.flasheader", "x"
> ++ b _start
> ++ .org CONFIG_FLASH_HEADER_OFFSET
> ++
> ++ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
> ++app_code_jump_v: .word _start
> ++reserv1: .word 0x0
> ++dcd_ptr: .word dcd_hdr
> ++boot_data_ptr: .word boot_data
> ++self_ptr: .word ivt_header
> ++app_code_csf: .word 0x0
> ++reserv2: .word 0x0
> ++
> ++boot_data: .word TEXT_BASE
> ++image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
> ++plugin: .word 0x0
> ++
> ++#ifdef CONFIG_MX6SOLO_DDR3
> ++dcd_hdr: .word 0x408802D2 /* Tag=0xD2, Len=80*8 + 4 + 4, Ver=0x40 */
> ++write_dcd_cmd: .word 0x048402CC /* Tag=0xCC, Len=80*8 + 4, Param=0x04 */
> ++
> ++/* DCD */
> ++/* DDR3 initialization based on the MX6Solo Auto Reference Design (ARD) */
> ++/* DDR IO TYPE */
> ++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
> ++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
> ++/* CLOCK */
> ++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
> ++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
> ++/* ADDRESS */
> ++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
> ++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
> ++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
> ++/* CONTROLE */
> ++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x000c0030)
> ++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000)
> ++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000)
> ++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
> ++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030)
> ++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030)
> ++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
> ++/* DATA STROBE */
> ++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
> ++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000038)
> ++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000038)
> ++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000038)
> ++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000038)
> ++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000038)
> ++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000038)
> ++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000038)
> ++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000038)
> ++/* DATA */
> ++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
> ++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
> ++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
> ++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
> ++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
> ++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
> ++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
> ++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
> ++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
> ++
> ++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
> ++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
> ++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
> ++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
> ++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
> ++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
> ++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
> ++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x000C0030)
> ++/* ZQ */
> ++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
> ++MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
> ++/* Write leveling */
> ++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x0040003c)
> ++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0032003e)
> ++
> ++MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x83c, 0x42350231)
> ++MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x840, 0x021a0218)
> ++MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x848, 0x4b4b4e49)
> ++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x850, 0x3f3f3035)
> ++/* Read data bit delay */
> ++MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
> ++MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
> ++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
> ++MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
> ++MXC_DCD_ITEM(53, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
> ++MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
> ++MXC_DCD_ITEM(55, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
> ++MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
> ++
> ++/* Complete calibration by forced measurement */
> ++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
> ++MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
> ++
> ++MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
> ++MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
> ++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x00c, 0x696d5323)
> ++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
> ++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
> ++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
> ++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
> ++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
> ++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x030, 0x006d0e21)
> ++MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
> ++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x000, 0x84190000)
> ++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
> ++MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
> ++MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
> ++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
> ++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
> ++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
> ++MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
> ++MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
> ++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
> ++MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x004, 0x00011006)
> ++MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
> ++
> ++#elif defined CONFIG_MX6DL_DDR3
> ++
> ++dcd_hdr: .word 0x40E002D2 /* Tag=0xD2, Len=91*8 + 4 + 4, Ver=0x40 */
> ++write_dcd_cmd: .word 0x04DC02CC /* Tag=0xCC, Len=91*8 + 4, Param=0x04 */
> ++
> ++# IOMUXC_BASE_ADDR = 0x20e0000
> ++# DDR IO TYPE
> ++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
> ++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
> ++# Clock
> ++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
> ++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
> ++# Address
> ++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
> ++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
> ++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
> ++# Control
> ++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)
> ++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000)
> ++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000)
> ++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
> ++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030)
> ++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030)
> ++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
> ++# Data Strobe
> ++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
> ++
> ++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030)
> ++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030)
> ++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030)
> ++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030)
> ++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000030)
> ++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000030)
> ++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000030)
> ++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000030)
> ++# DATA
> ++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
> ++
> ++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
> ++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
> ++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
> ++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
> ++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
> ++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
> ++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
> ++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
> ++
> ++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
> ++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
> ++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
> ++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
> ++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
> ++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
> ++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
> ++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x00000030)
> ++
> ++# MMDC_P0_BASE_ADDR = 0x021b0000
> ++# MMDC_P1_BASE_ADDR = 0x021b4000
> ++# Calibrations
> ++# ZQ
> ++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
> ++MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
> ++# write leveling
> ++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
> ++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
> ++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
> ++MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
> ++# DQS gating, read delay, write delay calibration values
> ++# based on calibration compare of 0x00ffff00
> ++MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x420E020E)
> ++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x02000200)
> ++MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x42020202)
> ++MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x01720172)
> ++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x494C4F4C)
> ++MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x4A4C4C49)
> ++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3133)
> ++MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x39373F2E)
> ++# read data bit delay
> ++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
> ++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
> ++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
> ++MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
> ++MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
> ++MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
> ++MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
> ++MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
> ++# Complete calibration by forced measurment
> ++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
> ++MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
> ++# MMDC init:
> ++# in DDR3, 64-bit mode, only MMDC0 is initiated:
> ++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
> ++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
> ++
> ++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
> ++MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
> ++
> ++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
> ++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
> ++MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
> ++MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
> ++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x00440e21)
> ++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
> ++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0xc31a0000)
> ++
> ++# Initialize 2GB DDR3 - Micron MT41J128M
> ++# MR2
> ++MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
> ++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
> ++# MR3
> ++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
> ++MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
> ++# MR1
> ++MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
> ++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
> ++# MR0
> ++MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
> ++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038)
> ++# ZQ calibration
> ++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
> ++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
> ++# final DDR setup
> ++MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
> ++MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
> ++MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
> ++MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
> ++MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)
> ++MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
> ++
> ++#elif defined CONFIG_LPDDR2
> ++dcd_hdr: .word 0x40F003D2 /* Tag=0xD2, Len=125*8 + 4 + 4, Ver=0x40 */
> ++write_dcd_cmd: .word 0x04EC03CC /* Tag=0xCC, Len=125*8 + 4, Param=0x04 */
> ++
> ++/* DCD */
> ++MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324)
> ++
> ++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038)
> ++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038)
> ++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x524, 0x00003038)
> ++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x51c, 0x00003038)
> ++
> ++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x518, 0x00003038)
> ++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x50c, 0x00003038)
> ++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038)
> ++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038)
> ++
> ++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
> ++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038)
> ++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x528, 0x00000038)
> ++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x520, 0x00000038)
> ++
> ++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x514, 0x00000038)
> ++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x510, 0x00000038)
> ++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038)
> ++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
> ++
> ++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x56c, 0x00000038)
> ++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x578, 0x00000038)
> ++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00000038)
> ++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x594, 0x00000038)
> ++
> ++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x57c, 0x00000038)
> ++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x590, 0x00000038)
> ++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x598, 0x00000038)
> ++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
> ++
> ++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x59c, 0x00000038)
> ++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038)
> ++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
> ++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x788, 0x00000038)
> ++
> ++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x794, 0x00000038)
> ++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x79c, 0x00000038)
> ++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038)
> ++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038)
> ++
> ++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038)
> ++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
> ++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
> ++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
> ++
> ++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
> ++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
> ++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
> ++MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x798, 0x00080000)
> ++
> ++MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
> ++MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
> ++
> ++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
> ++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
> ++
> ++MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000)
> ++MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000)
> ++
> ++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
> ++MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x890, 0x00400000)
> ++
> ++MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
> ++
> ++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
> ++MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
> ++
> ++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
> ++MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
> ++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
> ++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
> ++MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
> ++MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
> ++MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
> ++MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
> ++
> ++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
> ++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
> ++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
> ++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
> ++MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333)
> ++MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333)
> ++MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333)
> ++MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x838, 0xf3333333)
> ++
> ++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x848, 0x49383b39)
> ++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x850, 0x30364738)
> ++MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x3e3c3846)
> ++MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x850, 0x4c294b35)
> ++
> ++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
> ++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x840, 0x0)
> ++MXC_DCD_ITEM(75, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
> ++MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x840, 0x0)
> ++
> ++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x858, 0xf00)
> ++MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x858, 0xf00)
> ++
> ++MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
> ++MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
> ++
> ++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0xc, 0x555a61a5)
> ++MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x4, 0x20036)
> ++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x10, 0x160e83)
> ++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x14, 0xdd)
> ++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x18, 0x8174c)
> ++MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x2c, 0xf9f26d2)
> ++MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x30, 0x20e)
> ++MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x38, 0x200aac)
> ++MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x8, 0x0)
> ++
> ++MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x40, 0x5f)
> ++
> ++MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x0, 0xc3010000)
> ++
> ++MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0xc, 0x555a61a5)
> ++MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x4, 0x20036)
> ++MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x10, 0x160e83)
> ++MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x14, 0xdd)
> ++MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x18, 0x8174c)
> ++MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x2c, 0xf9f26d2)
> ++MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x30, 0x20e)
> ++MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x38, 0x200aac)
> ++MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x8, 0x0)
> ++
> ++MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x40, 0x3f)
> ++MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x0, 0xc3010000)
> ++
> ++MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x1c, 0x3f8030)
> ++MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x1c, 0xff0a8030)
> ++MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x1c, 0xc2018030)
> ++MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x1c, 0x6028030)
> ++MXC_DCD_ITEM(107, MMDC_P0_BASE_ADDR + 0x1c, 0x2038030)
> ++
> ++MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x1c, 0x3f8030)
> ++MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x1c, 0xff0a8030)
> ++MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x1c, 0xc2018030)
> ++MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x1c, 0x6028030)
> ++MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x1c, 0x2038030)
> ++
> ++MXC_DCD_ITEM(113, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
> ++MXC_DCD_ITEM(114, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
> ++
> ++MXC_DCD_ITEM(115, MMDC_P0_BASE_ADDR + 0x20, 0x7800)
> ++MXC_DCD_ITEM(116, MMDC_P1_BASE_ADDR + 0x20, 0x7800)
> ++
> ++MXC_DCD_ITEM(117, MMDC_P0_BASE_ADDR + 0x818, 0x0)
> ++MXC_DCD_ITEM(118, MMDC_P1_BASE_ADDR + 0x818, 0x0)
> ++
> ++MXC_DCD_ITEM(119, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
> ++MXC_DCD_ITEM(120, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
> ++
> ++MXC_DCD_ITEM(121, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
> ++MXC_DCD_ITEM(122, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
> ++
> ++MXC_DCD_ITEM(123, MMDC_P0_BASE_ADDR + 0x1c, 0x0)
> ++MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0)
> ++
> ++MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
> ++
> ++#else
> ++
> ++dcd_hdr: .word 0x40B002D2 /* Tag=0xD2, Len=85*8 + 4 + 4, Ver=0x40 */
> ++write_dcd_cmd: .word 0x04AC02CC /* Tag=0xCC, Len=85*8 + 4, Param=0x04 */
> ++
> ++/* DCD */
> ++/* DDR3 initialization based on the MX6Q Auto Reference Design (ARD) */
> ++
> ++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000028)
> ++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000028)
> ++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000028)
> ++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000028)
> ++
> ++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000028)
> ++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000028)
> ++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000028)
> ++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000028)
> ++
> ++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00000028)
> ++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00000028)
> ++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00000028)
> ++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00000028)
> ++
> ++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00000028)
> ++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00000028)
> ++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00000028)
> ++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00000028)
> ++
> ++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
> ++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
> ++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
> ++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
> ++
> ++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
> ++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00000030)
> ++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00000030)
> ++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
> ++
> ++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
> ++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
> ++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000028)
> ++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000028)
> ++
> ++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000028)
> ++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000028)
> ++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000028)
> ++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000028)
> ++
> ++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000028)
> ++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000028)
> ++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
> ++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
> ++
> ++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
> ++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
> ++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
> ++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
> ++
> ++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
> ++MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
> ++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
> ++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
> ++
> ++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
> ++MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
> ++MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
> ++MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
> ++
> ++MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
> ++
> ++MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
> ++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7975)
> ++MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
> ++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
> ++MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
> ++
> ++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008F0E21)
> ++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
> ++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
> ++MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
> ++MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
> ++
> ++MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
> ++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
> ++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
> ++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
> ++
> ++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
> ++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
> ++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
> ++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
> ++MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
> ++
> ++/* Calibration values based on ARD and 528MHz */
> ++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0358)
> ++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x840, 0x033D033C)
> ++MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x83c, 0x03520362)
> ++MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x840, 0x03480318)
> ++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x848, 0x41383A3C)
> ++MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x848, 0x3F3C374A)
> ++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x850, 0x42434444)
> ++MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x850, 0x4932473A)
> ++
> ++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
> ++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
> ++
> ++MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
> ++MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
> ++
> ++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
> ++MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
> ++
> ++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
> ++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
> ++
> ++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
> ++
> ++#endif
> ++
> ++#endif
> +diff --git a/board/freescale/wandboard/lowlevel_init.S b/board/freescale/wandboard/lowlevel_init.S
> +new file mode 100644
> +index 0000000..b725b66
> +--- /dev/null
> ++++ b/board/freescale/wandboard/lowlevel_init.S
> +@@ -0,0 +1,171 @@
> ++/*
> ++ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
> ++ *
> ++ * This program is free software; you can redistribute it and/or
> ++ * modify it under the terms of the GNU General Public License as
> ++ * published by the Free Software Foundation; either version 2 of
> ++ * the License, or (at your option) any later version.
> ++ *
> ++ * This program is distributed in the hope that it will be useful,
> ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> ++ * GNU General Public License for more details.
> ++ *
> ++ * You should have received a copy of the GNU General Public License
> ++ * along with this program; if not, write to the Free Software
> ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> ++ * MA 02111-1307 USA
> ++ */
> ++
> ++#include <config.h>
> ++#include <asm/arch/mx6.h>
> ++
> ++/*
> ++ Disable L2Cache because ROM turn it on when uboot use plug-in.
> ++ If L2Cache is on default, there are cache coherence problem if kernel have
> ++ not config L2Cache.
> ++*/
> ++.macro init_l2cc
> ++ ldr r1, =0xa02000
> ++ ldr r0, =0x0
> ++ str r0, [r1, #0x100]
> ++.endm /* init_l2cc */
> ++
> ++/* invalidate the D-CACHE */
> ++.macro inv_dcache
> ++ mov r0,#0
> ++ mcr p15,2,r0,c0,c0,0 /* cache size selection register, select dcache */
> ++ mrc p15,1,r0,c0,c0,0 /* cache size ID register */
> ++ mov r0,r0,ASR #13
> ++ ldr r3,=0xfff
> ++ and r0,r0,r3
> ++ cmp r0,#0x7f
> ++ moveq r6,#0x1000
> ++ beq size_done
> ++ cmp r0,#0xff
> ++ moveq r6,#0x2000
> ++ movne r6,#0x4000
> ++
> ++size_done:
> ++ mov r2,#0
> ++ mov r3,#0x40000000
> ++ mov r4,#0x80000000
> ++ mov r5,#0xc0000000
> ++
> ++d_inv_loop:
> ++ mcr p15,0,r2,c7,c6,2 /* invalidate dcache by set / way */
> ++ mcr p15,0,r3,c7,c6,2 /* invalidate dcache by set / way */
> ++ mcr p15,0,r4,c7,c6,2 /* invalidate dcache by set / way */
> ++ mcr p15,0,r5,c7,c6,2 /* invalidate dcache by set / way */
> ++ add r2,r2,#0x20
> ++ add r3,r3,#0x20
> ++ add r4,r4,#0x20
> ++ add r5,r5,#0x20
> ++
> ++ cmp r2,r6
> ++ bne d_inv_loop
> ++.endm
> ++
> ++/* AIPS setup - Only setup MPROTx registers.
> ++ * The PACR default values are good.*/
> ++.macro init_aips
> ++ /*
> ++ * Set all MPROTx to be non-bufferable, trusted for R/W,
> ++ * not forced to user-mode.
> ++ */
> ++ ldr r0, =AIPS1_ON_BASE_ADDR
> ++ ldr r1, =0x77777777
> ++ str r1, [r0, #0x0]
> ++ str r1, [r0, #0x4]
> ++ ldr r1, =0x0
> ++ str r1, [r0, #0x40]
> ++ str r1, [r0, #0x44]
> ++ str r1, [r0, #0x48]
> ++ str r1, [r0, #0x4C]
> ++ str r1, [r0, #0x50]
> ++
> ++ ldr r0, =AIPS2_ON_BASE_ADDR
> ++ ldr r1, =0x77777777
> ++ str r1, [r0, #0x0]
> ++ str r1, [r0, #0x4]
> ++ ldr r1, =0x0
> ++ str r1, [r0, #0x40]
> ++ str r1, [r0, #0x44]
> ++ str r1, [r0, #0x48]
> ++ str r1, [r0, #0x4C]
> ++ str r1, [r0, #0x50]
> ++.endm /* init_aips */
> ++
> ++.macro setup_pll pll, freq
> ++.endm
> ++
> ++.macro init_clock
> ++
> ++/* PLL1, PLL2, and PLL3 are enabled by ROM */
> ++#ifdef CONFIG_PLL3
> ++ /* enable PLL3 for UART */
> ++ ldr r0, ANATOP_BASE_ADDR_W
> ++
> ++ /* power up PLL */
> ++ ldr r1, [r0, #ANATOP_USB1]
> ++ orr r1, r1, #0x1000
> ++ str r1, [r0, #ANATOP_USB1]
> ++
> ++ /* enable PLL */
> ++ ldr r1, [r0, #ANATOP_USB1]
> ++ orr r1, r1, #0x2000
> ++ str r1, [r0, #ANATOP_USB1]
> ++
> ++ /* wait PLL lock */
> ++100:
> ++ ldr r1, [r0, #ANATOP_USB1]
> ++ mov r1, r1, lsr #31
> ++ cmp r1, #0x1
> ++ bne 100b
> ++
> ++ /* clear bypass bit */
> ++ ldr r1, [r0, #ANATOP_USB1]
> ++ and r1, r1, #0xfffeffff
> ++ str r1, [r0, #ANATOP_USB1]
> ++#endif
> ++
> ++ /* Restore the default values in the Gate registers */
> ++ ldr r0, CCM_BASE_ADDR_W
> ++ ldr r1, =0xC0003F
> ++ str r1, [r0, #CLKCTL_CCGR0]
> ++ ldr r1, =0x30FC00
> ++ str r1, [r0, #CLKCTL_CCGR1]
> ++ ldr r1, =0xFFFC000
> ++ str r1, [r0, #CLKCTL_CCGR2]
> ++ ldr r1, =0x3FF00000
> ++ str r1, [r0, #CLKCTL_CCGR3]
> ++ ldr r1, =0xFFF300
> ++ str r1, [r0, #CLKCTL_CCGR4]
> ++ ldr r1, =0xF0000C3
> ++ str r1, [r0, #CLKCTL_CCGR5]
> ++#ifdef CONFIG_CMD_WEIMNOR
> ++ ldr r1, =0xFFC
> ++#else
> ++ ldr r1, =0x3FC
> ++#endif
> ++ str r1, [r0, #CLKCTL_CCGR6]
> ++.endm
> ++
> ++.section ".text.init", "x"
> ++
> ++.globl lowlevel_init
> ++lowlevel_init:
> ++
> ++ inv_dcache
> ++
> ++ init_l2cc
> ++
> ++ init_aips
> ++
> ++ init_clock
> ++
> ++ mov pc, lr
> ++
> ++/* Board level setting value */
> ++ANATOP_BASE_ADDR_W: .word ANATOP_BASE_ADDR
> ++CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
> +diff --git a/board/freescale/wandboard/u-boot.lds b/board/freescale/wandboard/u-boot.lds
> +new file mode 100644
> +index 0000000..650c8a8
> +--- /dev/null
> ++++ b/board/freescale/wandboard/u-boot.lds
> +@@ -0,0 +1,74 @@
> ++/*
> ++ * January 2004 - Changed to support H4 device
> ++ * Copyright (c) 2004 Texas Instruments
> ++ *
> ++ * (C) Copyright 2002
> ++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> ++ *
> ++ * (C) Copyright 2011 Freescale Semiconductor, Inc.
> ++ *
> ++ * See file CREDITS for list of people who contributed to this
> ++ * project.
> ++ *
> ++ * This program is free software; you can redistribute it and/or
> ++ * modify it under the terms of the GNU General Public License as
> ++ * published by the Free Software Foundation; either version 2 of
> ++ * the License, or (at your option) any later version.
> ++ *
> ++ * This program is distributed in the hope that it will be useful,
> ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> ++ * GNU General Public License for more details.
> ++ *
> ++ * You should have received a copy of the GNU General Public License
> ++ * along with this program; if not, write to the Free Software
> ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> ++ * MA 02111-1307 USA
> ++ */
> ++
> ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> ++OUTPUT_ARCH(arm)
> ++ENTRY(_start)
> ++SECTIONS
> ++{
> ++ . = 0x00000000;
> ++
> ++ . = ALIGN(4);
> ++ .text :
> ++ {
> ++ /* WARNING - the following is hand-optimized to fit within */
> ++ /* the sector layout of our flash chips! XXX FIXME XXX */
> ++ board/freescale/wandboard/flash_header.o (.text.flasheader)
> ++ cpu/arm_cortexa8/start.o
> ++ board/freescale/wandboard/libwandboard.a (.text)
> ++ lib_arm/libarm.a (.text)
> ++ net/libnet.a (.text)
> ++ drivers/mtd/libmtd.a (.text)
> ++ drivers/mmc/libmmc.a (.text)
> ++
> ++ . = DEFINED(env_offset) ? env_offset : .;
> ++ common/env_embedded.o(.text)
> ++
> ++ *(.text)
> ++ }
> ++
> ++ . = ALIGN(4);
> ++ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
> ++
> ++ . = ALIGN(4);
> ++ .data : { *(.data) }
> ++
> ++ . = ALIGN(4);
> ++ .got : { *(.got) }
> ++
> ++ . = .;
> ++ __u_boot_cmd_start = .;
> ++ .u_boot_cmd : { *(.u_boot_cmd) }
> ++ __u_boot_cmd_end = .;
> ++
> ++ . = ALIGN(4);
> ++ _end_of_copy = .; /* end_of ROM copy code here */
> ++ __bss_start = .;
> ++ .bss : { *(.bss) }
> ++ _end = .;
> ++}
> +diff --git a/board/freescale/wandboard/wandboard.c b/board/freescale/wandboard/wandboard.c
> +new file mode 100644
> +index 0000000..274febb
> +--- /dev/null
> ++++ b/board/freescale/wandboard/wandboard.c
> +@@ -0,0 +1,494 @@
> ++/*
> ++ * Wandboard u-boot board-file.
> ++ *
> ++ * Copyright (C) Wandboard.org
> ++ * This file is a quick-mock up, to get a kernel booting.
> ++ *
> ++ * Maintainer: Tapani Utriainen <tapani at vmail me>
> ++ *
> ++ * This program is free software; you can redistribute it and/or
> ++ * modify it under the terms of the GNU General Public License as
> ++ * published by the Free Software Foundation; either version 2 of
> ++ * the License, or (at your option) any later version.
> ++ *
> ++ * This program is distributed in the hope that it will be useful,
> ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> ++ * GNU General Public License for more details.
> ++ *
> ++ * You should have received a copy of the GNU General Public License
> ++ * along with this program; if not, write to the Free Software
> ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> ++ * MA 02111-1307 USA
> ++ */
> ++
> ++#include <common.h>
> ++#include <asm/io.h>
> ++#include <asm/arch/mx6.h>
> ++#include <asm/arch/mx6_pins.h>
> ++#include <asm/arch/mx6dl_pins.h>
> ++#include <asm/arch/iomux-v3.h>
> ++#include <asm/errno.h>
> ++
> ++#ifdef CONFIG_MXC_FEC
> ++#include <miiphy.h>
> ++#endif
> ++
> ++#ifdef CONFIG_CMD_MMC
> ++#include <mmc.h>
> ++#include <fsl_esdhc.h>
> ++#endif
> ++
> ++#ifdef CONFIG_ARCH_MMU
> ++#include <asm/mmu.h>
> ++#include <asm/arch/mmu.h>
> ++#endif
> ++
> ++#ifdef CONFIG_CMD_CLOCK
> ++#include <asm/clock.h>
> ++#endif
> ++
> ++#ifdef CONFIG_CMD_IMXOTP
> ++#include <imx_otp.h>
> ++#endif
> ++
> ++DECLARE_GLOBAL_DATA_PTR;
> ++
> ++static enum boot_device boot_dev;
> ++
> ++static void set_gpio_output_val(unsigned base, unsigned mask, unsigned val)
> ++{
> ++ unsigned reg = readl(base + GPIO_DR);
> ++ if (val & 1)
> ++ reg |= mask; /* set high */
> ++ else
> ++ reg &= ~mask; /* clear low */
> ++ writel(reg, base + GPIO_DR);
> ++
> ++ reg = readl(base + GPIO_GDIR);
> ++ reg |= mask; /* configure GPIO line as output */
> ++ writel(reg, base + GPIO_GDIR);
> ++}
> ++
> ++static inline void setup_boot_device(void)
> ++{
> ++ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
> ++ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
> ++ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
> ++
> ++ switch (bt_mem_ctl) {
> ++ case 0x0:
> ++ if (bt_mem_type)
> ++ boot_dev = ONE_NAND_BOOT;
> ++ else
> ++ boot_dev = WEIM_NOR_BOOT;
> ++ break;
> ++ case 0x2:
> ++ boot_dev = SATA_BOOT;
> ++ break;
> ++ case 0x3:
> ++ if (bt_mem_type)
> ++ boot_dev = I2C_BOOT;
> ++ else
> ++ boot_dev = SPI_NOR_BOOT;
> ++ break;
> ++ case 0x4:
> ++ case 0x5:
> ++ boot_dev = SD_BOOT;
> ++ break;
> ++ case 0x6:
> ++ case 0x7:
> ++ boot_dev = MMC_BOOT;
> ++ break;
> ++ case 0x8 ... 0xf:
> ++ boot_dev = NAND_BOOT;
> ++ break;
> ++ default:
> ++ boot_dev = UNKNOWN_BOOT;
> ++ break;
> ++ }
> ++}
> ++
> ++enum boot_device get_boot_device(void) {
> ++ return boot_dev;
> ++}
> ++
> ++u32 get_board_rev(void) {
> ++ return fsl_system_rev;
> ++}
> ++
> ++#ifdef CONFIG_ARCH_MMU
> ++void board_mmu_init(void)
> ++{
> ++ unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
> ++ unsigned long i;
> ++
> ++ /*
> ++ * Set the TTB register
> ++ */
> ++ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
> ++
> ++ /*
> ++ * Set the Domain Access Control Register
> ++ */
> ++ i = ARM_ACCESS_DACR_DEFAULT;
> ++ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
> ++
> ++ /*
> ++ * First clear all TT entries - ie Set them to Faulting
> ++ */
> ++ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
> ++ /* Actual Virtual Size Attributes Function */
> ++ /* Base Base MB cached? buffered? access permissions */
> ++ /* xxx00000 xxx00000 */
> ++ X_ARM_MMU_SECTION(0x000, 0x000, 0x001,
> ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> ++ ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */
> ++ X_ARM_MMU_SECTION(0x001, 0x001, 0x008,
> ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> ++ ARM_ACCESS_PERM_RW_RW); /* 8M */
> ++ X_ARM_MMU_SECTION(0x009, 0x009, 0x001,
> ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> ++ ARM_ACCESS_PERM_RW_RW); /* IRAM */
> ++ X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6,
> ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> ++ ARM_ACCESS_PERM_RW_RW); /* 246M */
> ++ /* 2 GB memory starting at 0x10000000, only map 1.875 GB */
> ++ X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
> ++ ARM_CACHEABLE, ARM_BUFFERABLE,
> ++ ARM_ACCESS_PERM_RW_RW);
> ++ /* uncached alias of the same 1.875 GB memory */
> ++ X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
> ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> ++ ARM_ACCESS_PERM_RW_RW);
> ++
> ++ /* Enable MMU */
> ++ MMU_ON();
> ++}
> ++#endif
> ++
> ++int dram_init(void)
> ++{
> ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> ++ return 0;
> ++}
> ++
> ++static void setup_uart(void) {
> ++ /* UART1 TXD */
> ++ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT10__UART1_TXD);
> ++
> ++ /* UART1 RXD */
> ++ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT11__UART1_RXD);
> ++
> ++}
> ++
> ++#ifdef CONFIG_CMD_MMC
> ++
> ++/* On this board, only SD3 can support 1.8V signalling
> ++ * that is required for UHS-I mode of operation.
> ++ * Last element in struct is used to indicate 1.8V support.
> ++ */
> ++struct fsl_esdhc_cfg usdhc_cfg[4] = {
> ++ {USDHC1_BASE_ADDR, 1, 1, 1, 0},
> ++ {USDHC2_BASE_ADDR, 1, 1, 1, 0},
> ++ {USDHC3_BASE_ADDR, 1, 1, 1, 0},
> ++ {USDHC4_BASE_ADDR, 1, 1, 1, 0},
> ++};
> ++
> ++#ifdef CONFIG_DYNAMIC_MMC_DEVNO
> ++int get_mmc_env_devno(void)
> ++{
> ++ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
> ++
> ++ if (SD_BOOT == boot_dev || MMC_BOOT == boot_dev) {
> ++ /* BOOT_CFG2[3] and BOOT_CFG2[4] */
> ++ return (soc_sbmr & 0x00001800) >> 11;
> ++ } else
> ++ return -1;
> ++
> ++}
> ++#endif
> ++
> ++iomux_v3_cfg_t usdhc1_pads[] = {
> ++ MX6DL_PAD_SD1_CLK__USDHC1_CLK,
> ++ MX6DL_PAD_SD1_CMD__USDHC1_CMD,
> ++ MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
> ++ MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
> ++ MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
> ++ MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
> ++};
> ++
> ++iomux_v3_cfg_t usdhc2_pads[] = {
> ++ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
> ++ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
> ++ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
> ++ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
> ++ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
> ++ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
> ++};
> ++
> ++iomux_v3_cfg_t usdhc3_pads[] = {
> ++ MX6DL_PAD_SD3_CLK__USDHC3_CLK,
> ++ MX6DL_PAD_SD3_CMD__USDHC3_CMD,
> ++ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0,
> ++ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1,
> ++ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2,
> ++ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3,
> ++};
> ++
> ++int usdhc_pad_init(bd_t *bis) {
> ++ s32 status = 0;
> ++ u32 index = 0;
> ++
> ++ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM;
> ++ ++index) {
> ++ switch (index) {
> ++ case 0:
> ++ mxc_iomux_v3_setup_multiple_pads(usdhc1_pads,
> ++ ARRAY_SIZE(usdhc1_pads));
> ++ break;
> ++ case 1:
> ++ mxc_iomux_v3_setup_multiple_pads(usdhc2_pads,
> ++ ARRAY_SIZE(usdhc2_pads));
> ++ break;
> ++ case 2:
> ++ mxc_iomux_v3_setup_multiple_pads(usdhc3_pads,
> ++ ARRAY_SIZE(usdhc3_pads));
> ++ break;
> ++ default:
> ++ printf("Warning: you configured more USDHC controllers"
> ++ "(%d) then supported by the board (%d)\n",
> ++ index+1, CONFIG_SYS_FSL_USDHC_NUM);
> ++ return status;
> ++ }
> ++ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
> ++ }
> ++
> ++ return status;
> ++}
> ++
> ++int board_mmc_init(bd_t *bis) {
> ++ if (!usdhc_pad_init(bis))
> ++ return 0;
> ++ else
> ++ return -1;
> ++}
> ++
> ++/* For DDR mode operation, provide target delay parameter for each SD port.
> ++ * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
> ++ * is dependent on signal layout for that particular port. If the following
> ++ * CONFIG is not defined, then the default target delay value will be used.
> ++ */
> ++#ifdef CONFIG_GET_DDR_TARGET_DELAY
> ++u32 get_ddr_delay(struct fsl_esdhc_cfg *cfg) { return 0; }
> ++#endif
> ++
> ++#endif
> ++
> ++int board_init(void) {
> ++ mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
> ++ setup_boot_device();
> ++ fsl_set_system_rev();
> ++
> ++ /* board id for linux */
> ++ gd->bd->bi_arch_number = 4412;
> ++
> ++ /* address of boot parameters */
> ++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> ++
> ++ setup_uart();
> ++
> ++ return 0;
> ++}
> ++
> ++extern int fec_get_mac_addr(unsigned char *mac);
> ++
> ++int board_late_init(void) {
> ++
> ++ unsigned char mac[6];
> ++ int i;
> ++
> ++ fec_get_mac_addr(mac);
> ++ printf("Got MAC = ");
> ++ for (i=0; i<6; i++) {
> ++ printf("%02X", mac[i]);
> ++ if (i<5) printf(":"); else printf("\n");
> ++ }
> ++
> ++
> ++ return 0;
> ++}
> ++
> ++#ifdef CONFIG_MXC_FEC
> ++static int phy_read(char *devname, unsigned char addr, unsigned char reg,
> ++ unsigned short *pdata)
> ++{
> ++ int ret = miiphy_read(devname, addr, reg, pdata);
> ++ if (ret)
> ++ printf("Error reading from %s PHY addr=%02x reg=%02x\n",
> ++ devname, addr, reg);
> ++ return ret;
> ++}
> ++
> ++static int phy_write(char *devname, unsigned char addr, unsigned char reg,
> ++ unsigned short value)
> ++{
> ++ int ret = miiphy_write(devname, addr, reg, value);
> ++ if (ret)
> ++ printf("Error writing to %s PHY addr=%02x reg=%02x\n", devname,
> ++ addr, reg);
> ++ return ret;
> ++}
> ++
> ++int mx6_rgmii_rework(char *devname, int phy_addr)
> ++{
> ++ unsigned short val;
> ++
> ++ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
> ++ phy_write(devname, phy_addr, 0xd, 0x7);
> ++ phy_write(devname, phy_addr, 0xe, 0x8016);
> ++ phy_write(devname, phy_addr, 0xd, 0x4007);
> ++ phy_read(devname, phy_addr, 0xe, &val);
> ++
> ++ val &= 0xffe3;
> ++ val |= 0x18;
> ++ phy_write(devname, phy_addr, 0xe, val);
> ++
> ++ /* introduce tx clock delay */
> ++ phy_write(devname, phy_addr, 0x1d, 0x5);
> ++ phy_read(devname, phy_addr, 0x1e, &val);
> ++ val |= 0x0100;
> ++ phy_write(devname, phy_addr, 0x1e, val);
> ++
> ++ return 0;
> ++}
> ++
> ++#if defined CONFIG_MX6Q
> ++iomux_v3_cfg_t enet_pads[] = {
> ++ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
> ++ MX6Q_PAD_ENET_MDC__ENET_MDC,
> ++ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
> ++ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
> ++ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
> ++ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
> ++ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
> ++ MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
> ++ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
> ++ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
> ++ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
> ++ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
> ++ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
> ++ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
> ++ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
> ++ MX6Q_PAD_GPIO_0__CCM_CLKO,
> ++ MX6Q_PAD_GPIO_3__CCM_CLKO2,
> ++};
> ++#elif defined CONFIG_MX6DL
> ++iomux_v3_cfg_t enet_pads[] = {
> ++ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
> ++ MX6DL_PAD_ENET_MDC__ENET_MDC,
> ++ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
> ++ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
> ++ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
> ++ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
> ++ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
> ++ MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
> ++ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
> ++ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
> ++ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
> ++ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
> ++ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
> ++ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
> ++ MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
> ++ MX6DL_PAD_GPIO_0__CCM_CLKO,
> ++};
> ++#endif
> ++
> ++void enet_board_init(void)
> ++{
> ++ unsigned int reg;
> ++#if defined CONFIG_MX6Q
> ++ iomux_v3_cfg_t enet_reset =
> ++ (_MX6Q_PAD_EIM_D29__GPIO_3_29 &
> ++ ~MUX_PAD_CTRL_MASK) |
> ++ MUX_PAD_CTRL(0x48);
> ++#elif defined CONFIG_MX6DL
> ++ iomux_v3_cfg_t enet_reset =
> ++ (MX6DL_PAD_EIM_D29__GPIO_3_29 &
> ++ ~MUX_PAD_CTRL_MASK) |
> ++ MUX_PAD_CTRL(0x48);
> ++#endif
> ++
> ++ mxc_iomux_v3_setup_multiple_pads(enet_pads,
> ++ ARRAY_SIZE(enet_pads));
> ++ mxc_iomux_v3_setup_pad(enet_reset);
> ++
> ++ /* PHY reset: gpio 3-29 */
> ++ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 29), 0);
> ++
> ++ udelay(500);
> ++
> ++ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 29), 1);
> ++
> ++}
> ++#endif
> ++
> ++int checkboard(void) {
> ++ printf("Board: %s WandBoard 0x%x [",
> ++ mx6_chip_name(),
> ++ fsl_system_rev);
> ++
> ++ switch (__REG(SRC_BASE_ADDR + 0x8)) {
> ++ case 0x0001:
> ++ printf("POR");
> ++ break;
> ++ case 0x0009:
> ++ printf("RST");
> ++ break;
> ++ case 0x0010:
> ++ case 0x0011:
> ++ printf("WDOG");
> ++ break;
> ++ default:
> ++ printf("unknown");
> ++ }
> ++ printf(" ]\n");
> ++
> ++ printf("Boot Device: ");
> ++ switch (get_boot_device()) {
> ++ case WEIM_NOR_BOOT:
> ++ printf("NOR\n");
> ++ break;
> ++ case ONE_NAND_BOOT:
> ++ printf("ONE NAND\n");
> ++ break;
> ++ case PATA_BOOT:
> ++ printf("PATA\n");
> ++ break;
> ++ case SATA_BOOT:
> ++ printf("SATA\n");
> ++ break;
> ++ case I2C_BOOT:
> ++ printf("I2C\n");
> ++ break;
> ++ case SPI_NOR_BOOT:
> ++ printf("SPI NOR\n");
> ++ break;
> ++ case SD_BOOT:
> ++ printf("SD\n");
> ++ break;
> ++ case MMC_BOOT:
> ++ printf("MMC\n");
> ++ break;
> ++ case NAND_BOOT:
> ++ printf("NAND\n");
> ++ break;
> ++ case UNKNOWN_BOOT:
> ++ default:
> ++ printf("UNKNOWN\n");
> ++ break;
> ++ }
> ++ return 0;
> ++}
> ++
> +diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
> +index 2630bac..e00b122 100644
> +--- a/include/asm-arm/mach-types.h
> ++++ b/include/asm-arm/mach-types.h
> +@@ -3258,6 +3258,9 @@ extern unsigned int __machine_arch_type;
> + #define MACH_TYPE_MX6Q_SABRELITE 3769
> + #define MACH_TYPE_MX6Q_ARM2 3837
> + #define MACH_TYPE_MX6Q_SABRESD 3980
> ++#define MACH_TYPE_EDM_SF_IMX6 4256
> ++#define MACH_TYPE_EDM_CF_IMX6 4257
> ++#define MACH_TYPE_WANDBOARD 4412
> + #define MACH_TYPE_MX6SL_ARM2 4091
> + #define MACH_TYPE_MX6SL_EVK 4307
> +
> +@@ -42213,6 +42216,30 @@ extern unsigned int __machine_arch_type;
> + # define machine_is_mx6sl_evk() (0)
> + #endif
> +
> ++#ifdef CONFIG_MACH_EDM_SF_IMX6
> ++# ifdef machine_arch_type
> ++# undef machine_arch_type
> ++# define machine_arch_type __machine_arch_type
> ++# else
> ++# define machine_arch_type MACH_TYPE_EDM_SF_IMX6
> ++# endif
> ++# define machine_is_edm_sf_imx6() (machine_arch_type == MACH_TYPE_EDM_SF_IMX6)
> ++#else
> ++# define machine_is_edm_sf_imx6() (0)
> ++#endif
> ++
> ++#ifdef CONFIG_MACH_EDM_CF_IMX6
> ++# ifdef machine_arch_type
> ++# undef machine_arch_type
> ++# define machine_arch_type __machine_arch_type
> ++# else
> ++# define machine_arch_type MACH_TYPE_EDM_CF_IMX6
> ++# endif
> ++# define machine_is_edm_cf_imx6() (machine_arch_type == MACH_TYPE_EDM_CF_IMX6)
> ++#else
> ++# define machine_is_edm_cf_imx6() (0)
> ++#endif
> ++
> + /*
> + * These have not yet been registered
> + */
> +diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
> +new file mode 100644
> +index 0000000..e872c6b
> +--- /dev/null
> ++++ b/include/configs/wandboard.h
> +@@ -0,0 +1,273 @@
> ++/*
> ++ * Configuration settings for the Wandboard.
> ++ *
> ++ * Copyright (C) 2013 Wandboard.org
> ++ *
> ++ * This program is free software; you can redistribute it and/or
> ++ * modify it under the terms of the GNU General Public License as
> ++ * published by the Free Software Foundation; either version 2 of
> ++ * the License, or (at your option) any later version.
> ++ *
> ++ * This program is distributed in the hope that it will be useful,
> ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> ++ * GNU General Public License for more details.
> ++ *
> ++ * You should have received a copy of the GNU General Public License
> ++ * along with this program; if not, write to the Free Software
> ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> ++ * MA 02111-1307 USA
> ++ */
> ++
> ++#ifndef __CONFIG_H
> ++#define __CONFIG_H
> ++
> ++#include <asm/arch/mx6.h>
> ++
> ++ /* High Level Configuration Options */
> ++#define CONFIG_ARMV7
> ++#define CONFIG_MXC
> ++#define CONFIG_MX6DL
> ++#define CONFIG_WANDBOARD
> ++
> ++/* Comment this line when compiling for the Wandboard Solo */
> ++#define CONFIG_WANDBOARD_DUAL
> ++
> ++/* Setup memory depending if we have 512M/1G. */
> ++#ifdef CONFIG_WANDBOARD_DUAL
> ++#define CONFIG_MX6DL_DDR3
> ++#define CONFIG_DDR_64BIT
> ++#else
> ++#define CONFIG_MX6SOLO_DDR3
> ++#define CONFIG_DDR_32BIT
> ++#endif
> ++
> ++#define CONFIG_FLASH_HEADER
> ++#define CONFIG_FLASH_HEADER_OFFSET 0x400
> ++#define CONFIG_MX6_CLK32 32768
> ++
> ++#define CONFIG_SKIP_RELOCATE_UBOOT
> ++
> ++#define CONFIG_ARCH_CPU_INIT
> ++#undef CONFIG_ARCH_MMU /* disable MMU first */
> ++#define CONFIG_L2_OFF /* disable L2 cache first*/
> ++
> ++#define CONFIG_MX6_HCLK_FREQ 24000000
> ++
> ++#define CONFIG_DISPLAY_CPUINFO
> ++#define CONFIG_DISPLAY_BOARDINFO
> ++
> ++#define CONFIG_SYS_64BIT_VSPRINTF
> ++
> ++#define BOARD_LATE_INIT
> ++
> ++#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> ++#define CONFIG_REVISION_TAG
> ++#define CONFIG_SETUP_MEMORY_TAGS
> ++
> ++/*
> ++ * Size of malloc() pool
> ++ */
> ++#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
> ++/* size in bytes reserved for initial data */
> ++#define CONFIG_SYS_GBL_DATA_SIZE 128
> ++
> ++/*
> ++ * Hardware drivers
> ++ */
> ++#define CONFIG_MXC_UART
> ++#define CONFIG_MXC_GPIO
> ++#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR
> ++
> ++/* allow to overwrite serial and ethaddr */
> ++#define CONFIG_ENV_OVERWRITE
> ++#define CONFIG_CONS_INDEX 1
> ++#define CONFIG_BAUDRATE 115200
> ++#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
> ++
> ++/***********************************************************
> ++ * Command definition
> ++ ***********************************************************/
> ++
> ++#define CONFIG_CMD_BDI /* bdinfo */
> ++#define CONFIG_CMD_CONSOLE /* coninfo */
> ++#define CONFIG_CMD_ECHO /* echo arguments */
> ++#define CONFIG_CMD_IMI /* iminfo */
> ++#define CONFIG_CMD_ITEST /* Integer (and string) test */
> ++#define CONFIG_CMD_LOADB /* loadb */
> ++#define CONFIG_CMD_LOADS /* loads */
> ++#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
> ++#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
> ++#define CONFIG_CMD_RUN /* run command in env variable */
> ++#define CONFIG_CMD_SAVEENV /* saveenv */
> ++#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
> ++#define CONFIG_CMD_SOURCE /* "source" command support */
> ++#define CONFIG_CMD_XIMG /* Load part of Multi Image */
> ++
> ++#define CONFIG_PARTITIONS 1
> ++
> ++#define CONFIG_SYS_NO_FLASH
> ++#define CONFIG_CMD_BOOTD /* bootd */
> ++
> ++#define CONFIG_CMD_IMXOTP
> ++#define CONFIG_CMD_NET
> ++#define CONFIG_NET_MULTI 1
> ++#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
> ++#define CONFIG_FEC0_PINMUX -1
> ++#define CONFIG_FEC0_MIIBASE -1
> ++#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
> ++#define CONFIG_MXC_FEC
> ++#define CONFIG_FEC0_PHY_ADDR 0xFF
> ++#define CONFIG_DISCOVER_PHY
> ++#define CONFIG_ETH_PRIME
> ++#define CONFIG_RMII
> ++#define CONFIG_CMD_MII
> ++#define CONFIG_CMD_DHCP
> ++#define CONFIG_CMD_PING
> ++#define CONFIG_IPADDR 192.168.1.103
> ++#define CONFIG_SERVERIP 192.168.1.101
> ++#define CONFIG_NETMASK 255.255.255.0
> ++
> ++/* Enable below configure when supporting nand */
> ++#define CONFIG_CMD_MMC
> ++#define CONFIG_CMD_ENV
> ++#define CONFIG_CMD_REGUL
> ++
> ++#define CONFIG_CMD_CLOCK
> ++#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
> ++
> ++#undef CONFIG_CMD_IMLS
> ++
> ++#define CONFIG_CMD_IMX_DOWNLOAD_MODE
> ++
> ++#define CONFIG_BOOTDELAY 1
> ++
> ++#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
> ++#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
> ++
> ++#define CONFIG_EXTRA_ENV_SETTINGS \
> ++ "netdev=eth0\0" \
> ++ "uboot=u-boot.bin\0" \
> ++ "kernel=uImage\0" \
> ++ "bootargs=console=ttymxc0,115200\0" \
> ++ "videoargs=video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24\0" \
> ++ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
> ++ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
> ++ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
> ++ "video=${videoargs}\0" \
> ++ "bootcmd_net=dhcp; run bootargs_base bootargs_nfs;bootm\0" \
> ++ "bootargs_mmc=setenv bootargs ${bootargs} " \
> ++ "root=/dev/mmcblk0p2 rootwait rw " \
> ++ "video=${videoargs}\0" \
> ++ "bootcmd_mmc=run bootargs_base bootargs_mmc;mmc dev 2;" \
> ++ "fatload mmc 2 ${loadaddr} ${kernel};bootm\0" \
> ++ "bootcmd=run bootcmd_mmc\0" \
> ++ "upgradeu=for disk in 0 1 ; do mmc dev ${disk} ;" \
> ++ "for fs in fat ext2 ; do " \
> ++ "${fs}load mmc ${disk}:1 10008000 " \
> ++ "/6q_upgrade && " \
> ++ "source 10008000 ; " \
> ++ "done ; " \
> ++ "done\0" \
> ++ "bootfile=_BOOT_FILE_PATH_IN_TFTP_\0" \
> ++ "nfsroot=_ROOTFS_PATH_IN_NFS_\0"
> ++
> ++#define CONFIG_ARP_TIMEOUT 200UL
> ++
> ++/*
> ++ * Miscellaneous configurable options
> ++ */
> ++#define CONFIG_SYS_LONGHELP /* undef to save memory */
> ++#define CONFIG_SYS_PROMPT "WANDBOARD U-Boot > "
> ++#define CONFIG_AUTO_COMPLETE
> ++#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> ++/* Print Buffer Size */
> ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> ++#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> ++
> ++#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
> ++#define CONFIG_SYS_MEMTEST_END 0x10010000
> ++
> ++#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
> ++
> ++#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> ++
> ++#define CONFIG_SYS_HZ 1000
> ++
> ++#define CONFIG_CMDLINE_EDITING
> ++
> ++/*
> ++ * OCOTP Configs
> ++ */
> ++#ifdef CONFIG_CMD_IMXOTP
> ++ #define CONFIG_IMX_OTP
> ++ #define IMX_OTP_BASE OCOTP_BASE_ADDR
> ++ #define IMX_OTP_ADDR_MAX 0x7F
> ++ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
> ++#endif
> ++
> ++/* Regulator Configs */
> ++#ifdef CONFIG_CMD_REGUL
> ++ #define CONFIG_ANATOP_REGULATOR
> ++ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
> ++ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
> ++#endif
> ++
> ++/*
> ++ * MMC Configs
> ++ */
> ++#ifdef CONFIG_CMD_MMC
> ++ #define CONFIG_MMC
> ++ #define CONFIG_GENERIC_MMC
> ++ #define CONFIG_IMX_MMC
> ++ #define CONFIG_SYS_FSL_USDHC_NUM 3
> ++ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
> ++ #define CONFIG_SYS_MMC_ENV_DEV 2
> ++ #define CONFIG_DOS_PARTITION 1
> ++ #define CONFIG_CMD_FAT 1
> ++ #define CONFIG_CMD_EXT2 1
> ++
> ++ /* detect whether SD1 or 3 is boot device */
> ++ #define CONFIG_DYNAMIC_MMC_DEVNO
> ++
> ++ /* No 8 bit MMC */
> ++ #define CONFIG_MMC_8BIT_PORTS 0x0
> ++#endif
> ++
> ++/*-----------------------------------------------------------------------
> ++ * Stack sizes
> ++ *
> ++ * The stack sizes are set up in start.S using the settings below
> ++ */
> ++#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
> ++
> ++/*-----------------------------------------------------------------------
> ++ * Physical Memory Map
> ++ */
> ++#define CONFIG_NR_DRAM_BANKS 1
> ++#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
> ++#ifdef CONFIG_DDR_64BIT
> ++ #define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
> ++#else
> ++ #define PHYS_SDRAM_1_SIZE (512u * 1024 * 1024)
> ++#endif
> ++#define iomem_valid_addr(addr, size) \
> ++ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
> ++
> ++/*-----------------------------------------------------------------------
> ++ * FLASH and environment organization
> ++ */
> ++
> ++/* No NAND */
> ++#define CONFIG_SYS_NO_FLASH
> ++
> ++/* Monitor at beginning of flash */
> ++#define CONFIG_FSL_ENV_IN_MMC
> ++
> ++#define CONFIG_ENV_SECT_SIZE (8 * 1024)
> ++#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> ++#define CONFIG_ENV_IS_IN_MMC 1
> ++#define CONFIG_ENV_OFFSET (768 * 1024)
> ++
> ++#endif /* __CONFIG_H */
> +--
> +1.7.9.5
> +
> diff --git a/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend b/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
> new file mode 100644
> index 0000000..0a50ccf
> --- /dev/null
> +++ b/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
> @@ -0,0 +1,8 @@
> +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}"
> +
> +PRINC := "${@int(PRINC) + 1}"
> +
> +# Wandboard-specific patches
> +SRC_URI_append_mx6= " \
> + file://Initial-support-for-Wandboard-Dual.patch \
> +"
> --
> 1.7.9.5
>
> _______________________________________________
> meta-freescale mailing list
> meta-freescale@yoctoproject.org
> https://lists.yoctoproject.org/listinfo/meta-freescale
--
Otavio Salvador O.S. Systems
E-mail: otavio@ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [meta-fsl-arm-extra][PATCH 3/3] Add conf support for Wandboard Dual
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 3/3] Add conf " John Weber
@ 2013-02-26 19:25 ` Otavio Salvador
0 siblings, 0 replies; 8+ messages in thread
From: Otavio Salvador @ 2013-02-26 19:25 UTC (permalink / raw)
To: John Weber; +Cc: meta-freescale
On Sat, Feb 23, 2013 at 5:29 PM, John Weber <rjohnweber@gmail.com> wrote:
> The patch adds machine conf support for Wandboar Dual.
> It is not known but is possible that it will work with
> Wandboard Solo.
>
> In the local.conf, set the MACHINE ??= 'wandboard-dual'
> to use this configuration.
Shortlog ought to be:
wandboard-dual: Add machine definition
> Signed-off-by: John Weber <rjohnweber@gmail.com>
> ---
> Upstream-Status: Pending
> conf/machine/wandboard-dual.conf | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> create mode 100644 conf/machine/wandboard-dual.conf
>
> diff --git a/conf/machine/wandboard-dual.conf b/conf/machine/wandboard-dual.conf
> new file mode 100644
> index 0000000..f827be7
> --- /dev/null
> +++ b/conf/machine/wandboard-dual.conf
> @@ -0,0 +1,20 @@
> +#@TYPE: Machine
> +#@NAME: i.MX6 Wandboard Dual
> +#@DESCRIPTION: Machine configuration for i.MX6 Wandboard Dual
> +
> +include conf/machine/include/imx-base.inc
> +include conf/machine/include/tune-cortexa9.inc
> +
> +SOC_FAMILY = "mx6dl:mx6"
> +
> +KERNEL_DEVICETREE = "${S}/arch/arm/boot/dts/imx6dl-wandboard.dts"
> +
> +PREFERRED_PROVIDER_u-boot = "u-boot-imx"
> +
> +UBOOT_MACHINE = "wandboard_config"
> +UBOOT_SUFFIX = "bin"
> +UBOOT_PADDING = "2"
> +
> +SERIAL_CONSOLE = "115200 ttymxc0"
> +
> +MACHINE_FEATURES += " pci wifi bluetooth"
> --
> 1.7.9.5
>
> _______________________________________________
> meta-freescale mailing list
> meta-freescale@yoctoproject.org
> https://lists.yoctoproject.org/listinfo/meta-freescale
--
Otavio Salvador O.S. Systems
E-mail: otavio@ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [meta-fsl-arm-extra][PATCH 2/3] Add U-boot support for Wandboard Dual
2013-02-26 19:24 ` Otavio Salvador
@ 2013-02-26 20:11 ` John Weber
2013-02-26 20:17 ` Otavio Salvador
0 siblings, 1 reply; 8+ messages in thread
From: John Weber @ 2013-02-26 20:11 UTC (permalink / raw)
To: 'Otavio Salvador'; +Cc: meta-freescale
Hi Otavio -
The U-boot recipe, I've had problems using SRC_URI_apppend_<machine name> to
target patches to a particular machine. What I've done below is target them
to i.mx6 and then bitbake ties this to u-boot. I can put the wandboard-dual
specific patch into a subdirectory, as show below:
FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}"
PRINC := "${@int(PRINC) + 1}"
# Wandboard-specific patches
SRC_URI_append_mx6= " \
file://wandboard-dual/Initial-support-for-Wandboard-Dual.patch \
"
But, if I do SRC_URI_append_wandboard-dual = "..." , this does not work.
John
> -----Original Message-----
> From: otavio.salvador@gmail.com [mailto:otavio.salvador@gmail.com] On
> Behalf Of Otavio Salvador
> Sent: Tuesday, February 26, 2013 1:25 PM
> To: John Weber
> Cc: meta-freescale@yoctoproject.org
> Subject: Re: [meta-freescale] [meta-fsl-arm-extra][PATCH 2/3] Add U-boot
> support for Wandboard Dual
>
> On Sat, Feb 23, 2013 at 5:29 PM, John Weber <rjohnweber@gmail.com> wrote:
> > This patch adds U-boot-imx support for Wandboard Dual. It is
> > meant to patch the 2009.08 u-boot from the 1.1.0 FSL SDK.
>
> Same comments as done in the kernel patch.
>
> > Signed-off-by: John Weber <rjohnweber@gmail.com>
> > ---
> > Upstream-Status: Pending
> > .../Initial-support-for-Wandboard-Dual.patch | 1773
> ++++++++++++++++++++
> > recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend | 8 +
> > 2 files changed, 1781 insertions(+)
> > create mode 100644 recipes-bsp/u-boot/u-boot-imx/Initial-support-for-
> Wandboard-Dual.patch
> > create mode 100644 recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
> >
> > diff --git a/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-
> Wandboard-Dual.patch b/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-
> Wandboard-Dual.patch
> > new file mode 100644
> > index 0000000..cdb641f
> > --- /dev/null
> > +++ b/recipes-bsp/u-boot/u-boot-imx/Initial-support-for-Wandboard-
> Dual.patch
> > @@ -0,0 +1,1773 @@
> > +From eb057c5028d8f5e7243b0875d2bd299ecb376e01 Mon Sep 17 00:00:00 2001
> > +From: John Weber <rjohnweber@gmail.com>
> > +Date: Fri, 22 Feb 2013 08:49:27 -0600
> > +Subject: [PATCH] Initial support for Wandboard Dual
> > +
> > + That patch adds support for Wandboard. It has been tested on
> > + Wandboard-Dual. The serial port, module microSD card slot,
> > + and ethernet ports were found to work. Testers welcome.
> > +
> > + Almost all of this was ported directly from the Wandboard SDK
> > + released Feb 5, 2013 and was the work of Tapani.
> > +
> > +---
> > + Makefile | 3 +
> > + board/freescale/wandboard/Makefile | 47 +++
> > + board/freescale/wandboard/config.mk | 7 +
> > + board/freescale/wandboard/flash_header.S | 572
> +++++++++++++++++++++++++++++
> > + board/freescale/wandboard/lowlevel_init.S | 171 +++++++++
> > + board/freescale/wandboard/u-boot.lds | 74 ++++
> > + board/freescale/wandboard/wandboard.c | 494
> +++++++++++++++++++++++++
> > + include/asm-arm/mach-types.h | 27 ++
> > + include/configs/wandboard.h | 273 ++++++++++++++
> > + 9 files changed, 1668 insertions(+)
> > + create mode 100644 board/freescale/wandboard/Makefile
> > + create mode 100644 board/freescale/wandboard/config.mk
> > + create mode 100644 board/freescale/wandboard/flash_header.S
> > + create mode 100644 board/freescale/wandboard/lowlevel_init.S
> > + create mode 100644 board/freescale/wandboard/u-boot.lds
> > + create mode 100644 board/freescale/wandboard/wandboard.c
> > + create mode 100644 include/configs/wandboard.h
> > +
> > +diff --git a/Makefile b/Makefile
> > +index 1088794..41cca34 100644
> > +--- a/Makefile
> > ++++ b/Makefile
> > +@@ -3387,6 +3387,9 @@ mx6sl_evk_iram_config : unconfig
> > + }
> > + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6sl_evk freescale
> mx6
> > +
> > ++wandboard_config : unconfig
> > ++ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 wandboard freescale
> mx6
> > ++
> > + omap2420h4_config : unconfig
> > + @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
> > +
> > +diff --git a/board/freescale/wandboard/Makefile
> b/board/freescale/wandboard/Makefile
> > +new file mode 100644
> > +index 0000000..c0b30e4
> > +--- /dev/null
> > ++++ b/board/freescale/wandboard/Makefile
> > +@@ -0,0 +1,47 @@
> > ++#
> > ++# (C) Copyright 2010-2011 Freescale Semiconductor, Inc.
> > ++#
> > ++# This program is free software; you can redistribute it and/or
> > ++# modify it under the terms of the GNU General Public License as
> > ++# published by the Free Software Foundation; either version 2 of
> > ++# the License, or (at your option) any later version.
> > ++#
> > ++# This program is distributed in the hope that it will be useful,
> > ++# but WITHOUT ANY WARRANTY; without even the implied warranty of
> > ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > ++# GNU General Public License for more details.
> > ++#
> > ++# You should have received a copy of the GNU General Public License
> > ++# along with this program; if not, write to the Free Software
> > ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > ++# MA 02111-1307 USA
> > ++#
> > ++
> > ++include $(TOPDIR)/config.mk
> > ++
> > ++LIB = $(obj)lib$(BOARD).a
> > ++
> > ++COBJS := $(BOARD).o
> > ++SOBJS := lowlevel_init.o flash_header.o
> > ++
> > ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> > ++OBJS := $(addprefix $(obj),$(COBJS))
> > ++SOBJS := $(addprefix $(obj),$(SOBJS))
> > ++
> > ++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> > ++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> > ++
> > ++clean:
> > ++ rm -f $(SOBJS) $(OBJS)
> > ++
> > ++distclean: clean
> > ++ rm -f $(LIB) core *.bak .depend
> > ++
> >
> ++#######################################################################
> ##
> > ++
> > ++# defines $(obj).depend target
> > ++include $(SRCTREE)/rules.mk
> > ++
> > ++sinclude $(obj).depend
> > ++
> >
> ++#######################################################################
> ##
> > +diff --git a/board/freescale/wandboard/config.mk
> b/board/freescale/wandboard/config.mk
> > +new file mode 100644
> > +index 0000000..a0ce2a1
> > +--- /dev/null
> > ++++ b/board/freescale/wandboard/config.mk
> > +@@ -0,0 +1,7 @@
> > ++LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
> > ++
> > ++sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
> > ++
> > ++ifndef TEXT_BASE
> > ++ TEXT_BASE = 0x27800000
> > ++endif
> > +diff --git a/board/freescale/wandboard/flash_header.S
> b/board/freescale/wandboard/flash_header.S
> > +new file mode 100644
> > +index 0000000..f97d970
> > +--- /dev/null
> > ++++ b/board/freescale/wandboard/flash_header.S
> > +@@ -0,0 +1,572 @@
> > ++/*
> > ++ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
> > ++ *
> > ++ * This program is free software; you can redistribute it and/or
> > ++ * modify it under the terms of the GNU General Public License as
> > ++ * published by the Free Software Foundation; either version 2 of
> > ++ * the License, or (at your option) any later version.
> > ++ *
> > ++ * This program is distributed in the hope that it will be useful,
> > ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > ++ * GNU General Public License for more details.
> > ++ *
> > ++ * You should have received a copy of the GNU General Public License
> > ++ * along with this program; if not, write to the Free Software
> > ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > ++ * MA 02111-1307 USA
> > ++ */
> > ++
> > ++#include <config.h>
> > ++#include <asm/arch/mx6.h>
> > ++
> > ++#ifdef CONFIG_FLASH_HEADER
> > ++#ifndef CONFIG_FLASH_HEADER_OFFSET
> > ++# error "Must define the offset of flash header"
> > ++#endif
> > ++
> > ++#define CPU_2_BE_32(l) \
> > ++ ((((l) & 0x000000FF) << 24) | \
> > ++ (((l) & 0x0000FF00) << 8) | \
> > ++ (((l) & 0x00FF0000) >> 8) | \
> > ++ (((l) & 0xFF000000) >> 24))
> > ++
> > ++#define MXC_DCD_ITEM(i, addr, val) \
> > ++dcd_node_##i: \
> > ++ .word CPU_2_BE_32(addr) ; \
> > ++ .word CPU_2_BE_32(val) ; \
> > ++
> > ++.section ".text.flasheader", "x"
> > ++ b _start
> > ++ .org CONFIG_FLASH_HEADER_OFFSET
> > ++
> > ++ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40
> */
> > ++app_code_jump_v: .word _start
> > ++reserv1: .word 0x0
> > ++dcd_ptr: .word dcd_hdr
> > ++boot_data_ptr: .word boot_data
> > ++self_ptr: .word ivt_header
> > ++app_code_csf: .word 0x0
> > ++reserv2: .word 0x0
> > ++
> > ++boot_data: .word TEXT_BASE
> > ++image_len: .word _end_of_copy - TEXT_BASE +
> CONFIG_FLASH_HEADER_OFFSET
> > ++plugin: .word 0x0
> > ++
> > ++#ifdef CONFIG_MX6SOLO_DDR3
> > ++dcd_hdr: .word 0x408802D2 /* Tag=0xD2, Len=80*8 + 4 + 4,
> Ver=0x40 */
> > ++write_dcd_cmd: .word 0x048402CC /* Tag=0xCC, Len=80*8 + 4,
> Param=0x04 */
> > ++
> > ++/* DCD */
> > ++/* DDR3 initialization based on the MX6Solo Auto Reference Design
> (ARD) */
> > ++/* DDR IO TYPE */
> > ++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
> > ++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
> > ++/* CLOCK */
> > ++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
> > ++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
> > ++/* ADDRESS */
> > ++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
> > ++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
> > ++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
> > ++/* CONTROLE */
> > ++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x000c0030)
> > ++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000)
> > ++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000)
> > ++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
> > ++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030)
> > ++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030)
> > ++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
> > ++/* DATA STROBE */
> > ++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
> > ++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000038)
> > ++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000038)
> > ++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000038)
> > ++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000038)
> > ++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000038)
> > ++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000038)
> > ++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000038)
> > ++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000038)
> > ++/* DATA */
> > ++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
> > ++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
> > ++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
> > ++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
> > ++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
> > ++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
> > ++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
> > ++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
> > ++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
> > ++
> > ++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
> > ++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
> > ++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
> > ++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
> > ++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
> > ++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
> > ++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
> > ++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x000C0030)
> > ++/* ZQ */
> > ++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
> > ++MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
> > ++/* Write leveling */
> > ++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x0040003c)
> > ++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0032003e)
> > ++
> > ++MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x83c, 0x42350231)
> > ++MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x840, 0x021a0218)
> > ++MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x848, 0x4b4b4e49)
> > ++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x850, 0x3f3f3035)
> > ++/* Read data bit delay */
> > ++MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
> > ++MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
> > ++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
> > ++MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
> > ++MXC_DCD_ITEM(53, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
> > ++MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
> > ++MXC_DCD_ITEM(55, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
> > ++MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
> > ++
> > ++/* Complete calibration by forced measurement */
> > ++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
> > ++MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
> > ++
> > ++MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
> > ++MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
> > ++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x00c, 0x696d5323)
> > ++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
> > ++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
> > ++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
> > ++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
> > ++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
> > ++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x030, 0x006d0e21)
> > ++MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
> > ++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x000, 0x84190000)
> > ++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
> > ++MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
> > ++MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
> > ++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
> > ++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
> > ++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
> > ++MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
> > ++MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
> > ++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
> > ++MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x004, 0x00011006)
> > ++MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
> > ++
> > ++#elif defined CONFIG_MX6DL_DDR3
> > ++
> > ++dcd_hdr: .word 0x40E002D2 /* Tag=0xD2, Len=91*8 + 4 + 4,
> Ver=0x40 */
> > ++write_dcd_cmd: .word 0x04DC02CC /* Tag=0xCC, Len=91*8 + 4,
> Param=0x04 */
> > ++
> > ++# IOMUXC_BASE_ADDR = 0x20e0000
> > ++# DDR IO TYPE
> > ++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
> > ++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
> > ++# Clock
> > ++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
> > ++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
> > ++# Address
> > ++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
> > ++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
> > ++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
> > ++# Control
> > ++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)
> > ++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000)
> > ++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000)
> > ++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
> > ++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030)
> > ++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030)
> > ++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
> > ++# Data Strobe
> > ++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
> > ++
> > ++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030)
> > ++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030)
> > ++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030)
> > ++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030)
> > ++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000030)
> > ++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000030)
> > ++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000030)
> > ++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000030)
> > ++# DATA
> > ++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
> > ++
> > ++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
> > ++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
> > ++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
> > ++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
> > ++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
> > ++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
> > ++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
> > ++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
> > ++
> > ++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
> > ++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
> > ++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
> > ++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
> > ++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
> > ++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
> > ++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
> > ++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x00000030)
> > ++
> > ++# MMDC_P0_BASE_ADDR = 0x021b0000
> > ++# MMDC_P1_BASE_ADDR = 0x021b4000
> > ++# Calibrations
> > ++# ZQ
> > ++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
> > ++MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
> > ++# write leveling
> > ++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
> > ++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
> > ++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
> > ++MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
> > ++# DQS gating, read delay, write delay calibration values
> > ++# based on calibration compare of 0x00ffff00
> > ++MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x420E020E)
> > ++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x02000200)
> > ++MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x42020202)
> > ++MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x01720172)
> > ++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x494C4F4C)
> > ++MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x4A4C4C49)
> > ++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3133)
> > ++MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x39373F2E)
> > ++# read data bit delay
> > ++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
> > ++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
> > ++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
> > ++MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
> > ++MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
> > ++MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
> > ++MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
> > ++MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
> > ++# Complete calibration by forced measurment
> > ++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
> > ++MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
> > ++# MMDC init:
> > ++# in DDR3, 64-bit mode, only MMDC0 is initiated:
> > ++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
> > ++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
> > ++
> > ++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
> > ++MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
> > ++
> > ++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
> > ++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
> > ++MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
> > ++MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
> > ++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x00440e21)
> > ++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
> > ++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0xc31a0000)
> > ++
> > ++# Initialize 2GB DDR3 - Micron MT41J128M
> > ++# MR2
> > ++MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
> > ++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
> > ++# MR3
> > ++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
> > ++MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
> > ++# MR1
> > ++MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
> > ++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
> > ++# MR0
> > ++MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
> > ++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038)
> > ++# ZQ calibration
> > ++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
> > ++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
> > ++# final DDR setup
> > ++MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
> > ++MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
> > ++MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
> > ++MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
> > ++MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)
> > ++MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
> > ++
> > ++#elif defined CONFIG_LPDDR2
> > ++dcd_hdr: .word 0x40F003D2 /* Tag=0xD2, Len=125*8 + 4 + 4,
> Ver=0x40 */
> > ++write_dcd_cmd: .word 0x04EC03CC /* Tag=0xCC, Len=125*8 + 4,
> Param=0x04 */
> > ++
> > ++/* DCD */
> > ++MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324)
> > ++
> > ++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038)
> > ++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038)
> > ++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x524, 0x00003038)
> > ++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x51c, 0x00003038)
> > ++
> > ++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x518, 0x00003038)
> > ++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x50c, 0x00003038)
> > ++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038)
> > ++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038)
> > ++
> > ++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
> > ++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038)
> > ++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x528, 0x00000038)
> > ++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x520, 0x00000038)
> > ++
> > ++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x514, 0x00000038)
> > ++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x510, 0x00000038)
> > ++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038)
> > ++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
> > ++
> > ++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x56c, 0x00000038)
> > ++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x578, 0x00000038)
> > ++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00000038)
> > ++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x594, 0x00000038)
> > ++
> > ++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x57c, 0x00000038)
> > ++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x590, 0x00000038)
> > ++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x598, 0x00000038)
> > ++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
> > ++
> > ++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x59c, 0x00000038)
> > ++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038)
> > ++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
> > ++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x788, 0x00000038)
> > ++
> > ++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x794, 0x00000038)
> > ++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x79c, 0x00000038)
> > ++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038)
> > ++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038)
> > ++
> > ++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038)
> > ++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
> > ++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
> > ++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
> > ++
> > ++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
> > ++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
> > ++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
> > ++MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x798, 0x00080000)
> > ++
> > ++MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
> > ++MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
> > ++
> > ++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
> > ++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
> > ++
> > ++MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000)
> > ++MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000)
> > ++
> > ++MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
> > ++MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x890, 0x00400000)
> > ++
> > ++MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
> > ++
> > ++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
> > ++MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
> > ++
> > ++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
> > ++MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
> > ++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
> > ++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
> > ++MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
> > ++MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
> > ++MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
> > ++MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
> > ++
> > ++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
> > ++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
> > ++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
> > ++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
> > ++MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333)
> > ++MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333)
> > ++MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333)
> > ++MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x838, 0xf3333333)
> > ++
> > ++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x848, 0x49383b39)
> > ++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x850, 0x30364738)
> > ++MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x3e3c3846)
> > ++MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x850, 0x4c294b35)
> > ++
> > ++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
> > ++MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x840, 0x0)
> > ++MXC_DCD_ITEM(75, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
> > ++MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x840, 0x0)
> > ++
> > ++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x858, 0xf00)
> > ++MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x858, 0xf00)
> > ++
> > ++MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
> > ++MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
> > ++
> > ++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0xc, 0x555a61a5)
> > ++MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x4, 0x20036)
> > ++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x10, 0x160e83)
> > ++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x14, 0xdd)
> > ++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x18, 0x8174c)
> > ++MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x2c, 0xf9f26d2)
> > ++MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x30, 0x20e)
> > ++MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x38, 0x200aac)
> > ++MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x8, 0x0)
> > ++
> > ++MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x40, 0x5f)
> > ++
> > ++MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x0, 0xc3010000)
> > ++
> > ++MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0xc, 0x555a61a5)
> > ++MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x4, 0x20036)
> > ++MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x10, 0x160e83)
> > ++MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x14, 0xdd)
> > ++MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x18, 0x8174c)
> > ++MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x2c, 0xf9f26d2)
> > ++MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x30, 0x20e)
> > ++MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x38, 0x200aac)
> > ++MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x8, 0x0)
> > ++
> > ++MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x40, 0x3f)
> > ++MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x0, 0xc3010000)
> > ++
> > ++MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x1c, 0x3f8030)
> > ++MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x1c, 0xff0a8030)
> > ++MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x1c, 0xc2018030)
> > ++MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x1c, 0x6028030)
> > ++MXC_DCD_ITEM(107, MMDC_P0_BASE_ADDR + 0x1c, 0x2038030)
> > ++
> > ++MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x1c, 0x3f8030)
> > ++MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x1c, 0xff0a8030)
> > ++MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x1c, 0xc2018030)
> > ++MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x1c, 0x6028030)
> > ++MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x1c, 0x2038030)
> > ++
> > ++MXC_DCD_ITEM(113, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
> > ++MXC_DCD_ITEM(114, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
> > ++
> > ++MXC_DCD_ITEM(115, MMDC_P0_BASE_ADDR + 0x20, 0x7800)
> > ++MXC_DCD_ITEM(116, MMDC_P1_BASE_ADDR + 0x20, 0x7800)
> > ++
> > ++MXC_DCD_ITEM(117, MMDC_P0_BASE_ADDR + 0x818, 0x0)
> > ++MXC_DCD_ITEM(118, MMDC_P1_BASE_ADDR + 0x818, 0x0)
> > ++
> > ++MXC_DCD_ITEM(119, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
> > ++MXC_DCD_ITEM(120, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
> > ++
> > ++MXC_DCD_ITEM(121, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
> > ++MXC_DCD_ITEM(122, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
> > ++
> > ++MXC_DCD_ITEM(123, MMDC_P0_BASE_ADDR + 0x1c, 0x0)
> > ++MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0)
> > ++
> > ++MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
> > ++
> > ++#else
> > ++
> > ++dcd_hdr: .word 0x40B002D2 /* Tag=0xD2, Len=85*8 + 4 + 4,
> Ver=0x40 */
> > ++write_dcd_cmd: .word 0x04AC02CC /* Tag=0xCC, Len=85*8 + 4,
> Param=0x04 */
> > ++
> > ++/* DCD */
> > ++/* DDR3 initialization based on the MX6Q Auto Reference Design (ARD)
> */
> > ++
> > ++MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000028)
> > ++MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000028)
> > ++MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000028)
> > ++MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000028)
> > ++
> > ++MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000028)
> > ++MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000028)
> > ++MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000028)
> > ++MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000028)
> > ++
> > ++MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00000028)
> > ++MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00000028)
> > ++MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00000028)
> > ++MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00000028)
> > ++
> > ++MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00000028)
> > ++MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00000028)
> > ++MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00000028)
> > ++MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00000028)
> > ++
> > ++MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
> > ++MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
> > ++MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
> > ++MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
> > ++
> > ++MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
> > ++MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00000030)
> > ++MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00000030)
> > ++MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
> > ++
> > ++MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
> > ++MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
> > ++MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000028)
> > ++MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000028)
> > ++
> > ++MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000028)
> > ++MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000028)
> > ++MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000028)
> > ++MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000028)
> > ++
> > ++MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000028)
> > ++MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000028)
> > ++MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
> > ++MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
> > ++
> > ++MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
> > ++MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
> > ++MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
> > ++MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
> > ++
> > ++MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
> > ++MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
> > ++MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
> > ++MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
> > ++
> > ++MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
> > ++MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
> > ++MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
> > ++MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
> > ++
> > ++MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
> > ++
> > ++MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
> > ++MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7975)
> > ++MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
> > ++MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
> > ++MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
> > ++
> > ++MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008F0E21)
> > ++MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
> > ++MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
> > ++MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
> > ++MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
> > ++
> > ++MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
> > ++MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
> > ++MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
> > ++MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
> > ++
> > ++MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
> > ++MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
> > ++MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
> > ++MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
> > ++MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
> > ++
> > ++/* Calibration values based on ARD and 528MHz */
> > ++MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0358)
> > ++MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x840, 0x033D033C)
> > ++MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x83c, 0x03520362)
> > ++MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x840, 0x03480318)
> > ++MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x848, 0x41383A3C)
> > ++MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x848, 0x3F3C374A)
> > ++MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x850, 0x42434444)
> > ++MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x850, 0x4932473A)
> > ++
> > ++MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
> > ++MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
> > ++
> > ++MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
> > ++MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
> > ++
> > ++MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
> > ++MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
> > ++
> > ++MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
> > ++MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
> > ++
> > ++MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
> > ++
> > ++#endif
> > ++
> > ++#endif
> > +diff --git a/board/freescale/wandboard/lowlevel_init.S
> b/board/freescale/wandboard/lowlevel_init.S
> > +new file mode 100644
> > +index 0000000..b725b66
> > +--- /dev/null
> > ++++ b/board/freescale/wandboard/lowlevel_init.S
> > +@@ -0,0 +1,171 @@
> > ++/*
> > ++ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
> > ++ *
> > ++ * This program is free software; you can redistribute it and/or
> > ++ * modify it under the terms of the GNU General Public License as
> > ++ * published by the Free Software Foundation; either version 2 of
> > ++ * the License, or (at your option) any later version.
> > ++ *
> > ++ * This program is distributed in the hope that it will be useful,
> > ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > ++ * GNU General Public License for more details.
> > ++ *
> > ++ * You should have received a copy of the GNU General Public License
> > ++ * along with this program; if not, write to the Free Software
> > ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > ++ * MA 02111-1307 USA
> > ++ */
> > ++
> > ++#include <config.h>
> > ++#include <asm/arch/mx6.h>
> > ++
> > ++/*
> > ++ Disable L2Cache because ROM turn it on when uboot use plug-in.
> > ++ If L2Cache is on default, there are cache coherence problem if
> kernel have
> > ++ not config L2Cache.
> > ++*/
> > ++.macro init_l2cc
> > ++ ldr r1, =0xa02000
> > ++ ldr r0, =0x0
> > ++ str r0, [r1, #0x100]
> > ++.endm /* init_l2cc */
> > ++
> > ++/* invalidate the D-CACHE */
> > ++.macro inv_dcache
> > ++ mov r0,#0
> > ++ mcr p15,2,r0,c0,c0,0 /* cache size selection register,
> select dcache */
> > ++ mrc p15,1,r0,c0,c0,0 /* cache size ID register */
> > ++ mov r0,r0,ASR #13
> > ++ ldr r3,=0xfff
> > ++ and r0,r0,r3
> > ++ cmp r0,#0x7f
> > ++ moveq r6,#0x1000
> > ++ beq size_done
> > ++ cmp r0,#0xff
> > ++ moveq r6,#0x2000
> > ++ movne r6,#0x4000
> > ++
> > ++size_done:
> > ++ mov r2,#0
> > ++ mov r3,#0x40000000
> > ++ mov r4,#0x80000000
> > ++ mov r5,#0xc0000000
> > ++
> > ++d_inv_loop:
> > ++ mcr p15,0,r2,c7,c6,2 /* invalidate dcache by set / way */
> > ++ mcr p15,0,r3,c7,c6,2 /* invalidate dcache by set / way */
> > ++ mcr p15,0,r4,c7,c6,2 /* invalidate dcache by set / way */
> > ++ mcr p15,0,r5,c7,c6,2 /* invalidate dcache by set / way */
> > ++ add r2,r2,#0x20
> > ++ add r3,r3,#0x20
> > ++ add r4,r4,#0x20
> > ++ add r5,r5,#0x20
> > ++
> > ++ cmp r2,r6
> > ++ bne d_inv_loop
> > ++.endm
> > ++
> > ++/* AIPS setup - Only setup MPROTx registers.
> > ++ * The PACR default values are good.*/
> > ++.macro init_aips
> > ++ /*
> > ++ * Set all MPROTx to be non-bufferable, trusted for R/W,
> > ++ * not forced to user-mode.
> > ++ */
> > ++ ldr r0, =AIPS1_ON_BASE_ADDR
> > ++ ldr r1, =0x77777777
> > ++ str r1, [r0, #0x0]
> > ++ str r1, [r0, #0x4]
> > ++ ldr r1, =0x0
> > ++ str r1, [r0, #0x40]
> > ++ str r1, [r0, #0x44]
> > ++ str r1, [r0, #0x48]
> > ++ str r1, [r0, #0x4C]
> > ++ str r1, [r0, #0x50]
> > ++
> > ++ ldr r0, =AIPS2_ON_BASE_ADDR
> > ++ ldr r1, =0x77777777
> > ++ str r1, [r0, #0x0]
> > ++ str r1, [r0, #0x4]
> > ++ ldr r1, =0x0
> > ++ str r1, [r0, #0x40]
> > ++ str r1, [r0, #0x44]
> > ++ str r1, [r0, #0x48]
> > ++ str r1, [r0, #0x4C]
> > ++ str r1, [r0, #0x50]
> > ++.endm /* init_aips */
> > ++
> > ++.macro setup_pll pll, freq
> > ++.endm
> > ++
> > ++.macro init_clock
> > ++
> > ++/* PLL1, PLL2, and PLL3 are enabled by ROM */
> > ++#ifdef CONFIG_PLL3
> > ++ /* enable PLL3 for UART */
> > ++ ldr r0, ANATOP_BASE_ADDR_W
> > ++
> > ++ /* power up PLL */
> > ++ ldr r1, [r0, #ANATOP_USB1]
> > ++ orr r1, r1, #0x1000
> > ++ str r1, [r0, #ANATOP_USB1]
> > ++
> > ++ /* enable PLL */
> > ++ ldr r1, [r0, #ANATOP_USB1]
> > ++ orr r1, r1, #0x2000
> > ++ str r1, [r0, #ANATOP_USB1]
> > ++
> > ++ /* wait PLL lock */
> > ++100:
> > ++ ldr r1, [r0, #ANATOP_USB1]
> > ++ mov r1, r1, lsr #31
> > ++ cmp r1, #0x1
> > ++ bne 100b
> > ++
> > ++ /* clear bypass bit */
> > ++ ldr r1, [r0, #ANATOP_USB1]
> > ++ and r1, r1, #0xfffeffff
> > ++ str r1, [r0, #ANATOP_USB1]
> > ++#endif
> > ++
> > ++ /* Restore the default values in the Gate registers */
> > ++ ldr r0, CCM_BASE_ADDR_W
> > ++ ldr r1, =0xC0003F
> > ++ str r1, [r0, #CLKCTL_CCGR0]
> > ++ ldr r1, =0x30FC00
> > ++ str r1, [r0, #CLKCTL_CCGR1]
> > ++ ldr r1, =0xFFFC000
> > ++ str r1, [r0, #CLKCTL_CCGR2]
> > ++ ldr r1, =0x3FF00000
> > ++ str r1, [r0, #CLKCTL_CCGR3]
> > ++ ldr r1, =0xFFF300
> > ++ str r1, [r0, #CLKCTL_CCGR4]
> > ++ ldr r1, =0xF0000C3
> > ++ str r1, [r0, #CLKCTL_CCGR5]
> > ++#ifdef CONFIG_CMD_WEIMNOR
> > ++ ldr r1, =0xFFC
> > ++#else
> > ++ ldr r1, =0x3FC
> > ++#endif
> > ++ str r1, [r0, #CLKCTL_CCGR6]
> > ++.endm
> > ++
> > ++.section ".text.init", "x"
> > ++
> > ++.globl lowlevel_init
> > ++lowlevel_init:
> > ++
> > ++ inv_dcache
> > ++
> > ++ init_l2cc
> > ++
> > ++ init_aips
> > ++
> > ++ init_clock
> > ++
> > ++ mov pc, lr
> > ++
> > ++/* Board level setting value */
> > ++ANATOP_BASE_ADDR_W: .word ANATOP_BASE_ADDR
> > ++CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
> > +diff --git a/board/freescale/wandboard/u-boot.lds
> b/board/freescale/wandboard/u-boot.lds
> > +new file mode 100644
> > +index 0000000..650c8a8
> > +--- /dev/null
> > ++++ b/board/freescale/wandboard/u-boot.lds
> > +@@ -0,0 +1,74 @@
> > ++/*
> > ++ * January 2004 - Changed to support H4 device
> > ++ * Copyright (c) 2004 Texas Instruments
> > ++ *
> > ++ * (C) Copyright 2002
> > ++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> > ++ *
> > ++ * (C) Copyright 2011 Freescale Semiconductor, Inc.
> > ++ *
> > ++ * See file CREDITS for list of people who contributed to this
> > ++ * project.
> > ++ *
> > ++ * This program is free software; you can redistribute it and/or
> > ++ * modify it under the terms of the GNU General Public License as
> > ++ * published by the Free Software Foundation; either version 2 of
> > ++ * the License, or (at your option) any later version.
> > ++ *
> > ++ * This program is distributed in the hope that it will be useful,
> > ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
> the
> > ++ * GNU General Public License for more details.
> > ++ *
> > ++ * You should have received a copy of the GNU General Public License
> > ++ * along with this program; if not, write to the Free Software
> > ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > ++ * MA 02111-1307 USA
> > ++ */
> > ++
> > ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-
> littlearm")
> > ++OUTPUT_ARCH(arm)
> > ++ENTRY(_start)
> > ++SECTIONS
> > ++{
> > ++ . = 0x00000000;
> > ++
> > ++ . = ALIGN(4);
> > ++ .text :
> > ++ {
> > ++ /* WARNING - the following is hand-optimized to fit within
> */
> > ++ /* the sector layout of our flash chips! XXX FIXME XXX
> */
> > ++ board/freescale/wandboard/flash_header.o
> (.text.flasheader)
> > ++ cpu/arm_cortexa8/start.o
> > ++ board/freescale/wandboard/libwandboard.a (.text)
> > ++ lib_arm/libarm.a (.text)
> > ++ net/libnet.a (.text)
> > ++ drivers/mtd/libmtd.a (.text)
> > ++ drivers/mmc/libmmc.a (.text)
> > ++
> > ++ . = DEFINED(env_offset) ? env_offset : .;
> > ++ common/env_embedded.o(.text)
> > ++
> > ++ *(.text)
> > ++ }
> > ++
> > ++ . = ALIGN(4);
> > ++ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
> > ++
> > ++ . = ALIGN(4);
> > ++ .data : { *(.data) }
> > ++
> > ++ . = ALIGN(4);
> > ++ .got : { *(.got) }
> > ++
> > ++ . = .;
> > ++ __u_boot_cmd_start = .;
> > ++ .u_boot_cmd : { *(.u_boot_cmd) }
> > ++ __u_boot_cmd_end = .;
> > ++
> > ++ . = ALIGN(4);
> > ++ _end_of_copy = .; /* end_of ROM copy code here */
> > ++ __bss_start = .;
> > ++ .bss : { *(.bss) }
> > ++ _end = .;
> > ++}
> > +diff --git a/board/freescale/wandboard/wandboard.c
> b/board/freescale/wandboard/wandboard.c
> > +new file mode 100644
> > +index 0000000..274febb
> > +--- /dev/null
> > ++++ b/board/freescale/wandboard/wandboard.c
> > +@@ -0,0 +1,494 @@
> > ++/*
> > ++ * Wandboard u-boot board-file.
> > ++ *
> > ++ * Copyright (C) Wandboard.org
> > ++ * This file is a quick-mock up, to get a kernel booting.
> > ++ *
> > ++ * Maintainer: Tapani Utriainen <tapani at vmail me>
> > ++ *
> > ++ * This program is free software; you can redistribute it and/or
> > ++ * modify it under the terms of the GNU General Public License as
> > ++ * published by the Free Software Foundation; either version 2 of
> > ++ * the License, or (at your option) any later version.
> > ++ *
> > ++ * This program is distributed in the hope that it will be useful,
> > ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > ++ * GNU General Public License for more details.
> > ++ *
> > ++ * You should have received a copy of the GNU General Public License
> > ++ * along with this program; if not, write to the Free Software
> > ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > ++ * MA 02111-1307 USA
> > ++ */
> > ++
> > ++#include <common.h>
> > ++#include <asm/io.h>
> > ++#include <asm/arch/mx6.h>
> > ++#include <asm/arch/mx6_pins.h>
> > ++#include <asm/arch/mx6dl_pins.h>
> > ++#include <asm/arch/iomux-v3.h>
> > ++#include <asm/errno.h>
> > ++
> > ++#ifdef CONFIG_MXC_FEC
> > ++#include <miiphy.h>
> > ++#endif
> > ++
> > ++#ifdef CONFIG_CMD_MMC
> > ++#include <mmc.h>
> > ++#include <fsl_esdhc.h>
> > ++#endif
> > ++
> > ++#ifdef CONFIG_ARCH_MMU
> > ++#include <asm/mmu.h>
> > ++#include <asm/arch/mmu.h>
> > ++#endif
> > ++
> > ++#ifdef CONFIG_CMD_CLOCK
> > ++#include <asm/clock.h>
> > ++#endif
> > ++
> > ++#ifdef CONFIG_CMD_IMXOTP
> > ++#include <imx_otp.h>
> > ++#endif
> > ++
> > ++DECLARE_GLOBAL_DATA_PTR;
> > ++
> > ++static enum boot_device boot_dev;
> > ++
> > ++static void set_gpio_output_val(unsigned base, unsigned mask,
> unsigned val)
> > ++{
> > ++ unsigned reg = readl(base + GPIO_DR);
> > ++ if (val & 1)
> > ++ reg |= mask; /* set high */
> > ++ else
> > ++ reg &= ~mask; /* clear low */
> > ++ writel(reg, base + GPIO_DR);
> > ++
> > ++ reg = readl(base + GPIO_GDIR);
> > ++ reg |= mask; /* configure GPIO line as output */
> > ++ writel(reg, base + GPIO_GDIR);
> > ++}
> > ++
> > ++static inline void setup_boot_device(void)
> > ++{
> > ++ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
> > ++ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
> > ++ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
> > ++
> > ++ switch (bt_mem_ctl) {
> > ++ case 0x0:
> > ++ if (bt_mem_type)
> > ++ boot_dev = ONE_NAND_BOOT;
> > ++ else
> > ++ boot_dev = WEIM_NOR_BOOT;
> > ++ break;
> > ++ case 0x2:
> > ++ boot_dev = SATA_BOOT;
> > ++ break;
> > ++ case 0x3:
> > ++ if (bt_mem_type)
> > ++ boot_dev = I2C_BOOT;
> > ++ else
> > ++ boot_dev = SPI_NOR_BOOT;
> > ++ break;
> > ++ case 0x4:
> > ++ case 0x5:
> > ++ boot_dev = SD_BOOT;
> > ++ break;
> > ++ case 0x6:
> > ++ case 0x7:
> > ++ boot_dev = MMC_BOOT;
> > ++ break;
> > ++ case 0x8 ... 0xf:
> > ++ boot_dev = NAND_BOOT;
> > ++ break;
> > ++ default:
> > ++ boot_dev = UNKNOWN_BOOT;
> > ++ break;
> > ++ }
> > ++}
> > ++
> > ++enum boot_device get_boot_device(void) {
> > ++ return boot_dev;
> > ++}
> > ++
> > ++u32 get_board_rev(void) {
> > ++ return fsl_system_rev;
> > ++}
> > ++
> > ++#ifdef CONFIG_ARCH_MMU
> > ++void board_mmu_init(void)
> > ++{
> > ++ unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
> > ++ unsigned long i;
> > ++
> > ++ /*
> > ++ * Set the TTB register
> > ++ */
> > ++ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
> > ++
> > ++ /*
> > ++ * Set the Domain Access Control Register
> > ++ */
> > ++ i = ARM_ACCESS_DACR_DEFAULT;
> > ++ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
> > ++
> > ++ /*
> > ++ * First clear all TT entries - ie Set them to Faulting
> > ++ */
> > ++ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
> > ++ /* Actual Virtual Size Attributes Function */
> > ++ /* Base Base MB cached? buffered? access
> permissions */
> > ++ /* xxx00000 xxx00000 */
> > ++ X_ARM_MMU_SECTION(0x000, 0x000, 0x001,
> > ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> > ++ ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */
> > ++ X_ARM_MMU_SECTION(0x001, 0x001, 0x008,
> > ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> > ++ ARM_ACCESS_PERM_RW_RW); /* 8M */
> > ++ X_ARM_MMU_SECTION(0x009, 0x009, 0x001,
> > ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> > ++ ARM_ACCESS_PERM_RW_RW); /* IRAM */
> > ++ X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6,
> > ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> > ++ ARM_ACCESS_PERM_RW_RW); /* 246M */
> > ++ /* 2 GB memory starting at 0x10000000, only map 1.875 GB */
> > ++ X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
> > ++ ARM_CACHEABLE, ARM_BUFFERABLE,
> > ++ ARM_ACCESS_PERM_RW_RW);
> > ++ /* uncached alias of the same 1.875 GB memory */
> > ++ X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
> > ++ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
> > ++ ARM_ACCESS_PERM_RW_RW);
> > ++
> > ++ /* Enable MMU */
> > ++ MMU_ON();
> > ++}
> > ++#endif
> > ++
> > ++int dram_init(void)
> > ++{
> > ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> > ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> > ++ return 0;
> > ++}
> > ++
> > ++static void setup_uart(void) {
> > ++ /* UART1 TXD */
> > ++ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT10__UART1_TXD);
> > ++
> > ++ /* UART1 RXD */
> > ++ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT11__UART1_RXD);
> > ++
> > ++}
> > ++
> > ++#ifdef CONFIG_CMD_MMC
> > ++
> > ++/* On this board, only SD3 can support 1.8V signalling
> > ++ * that is required for UHS-I mode of operation.
> > ++ * Last element in struct is used to indicate 1.8V support.
> > ++ */
> > ++struct fsl_esdhc_cfg usdhc_cfg[4] = {
> > ++ {USDHC1_BASE_ADDR, 1, 1, 1, 0},
> > ++ {USDHC2_BASE_ADDR, 1, 1, 1, 0},
> > ++ {USDHC3_BASE_ADDR, 1, 1, 1, 0},
> > ++ {USDHC4_BASE_ADDR, 1, 1, 1, 0},
> > ++};
> > ++
> > ++#ifdef CONFIG_DYNAMIC_MMC_DEVNO
> > ++int get_mmc_env_devno(void)
> > ++{
> > ++ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
> > ++
> > ++ if (SD_BOOT == boot_dev || MMC_BOOT == boot_dev) {
> > ++ /* BOOT_CFG2[3] and BOOT_CFG2[4] */
> > ++ return (soc_sbmr & 0x00001800) >> 11;
> > ++ } else
> > ++ return -1;
> > ++
> > ++}
> > ++#endif
> > ++
> > ++iomux_v3_cfg_t usdhc1_pads[] = {
> > ++ MX6DL_PAD_SD1_CLK__USDHC1_CLK,
> > ++ MX6DL_PAD_SD1_CMD__USDHC1_CMD,
> > ++ MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
> > ++ MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
> > ++ MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
> > ++ MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
> > ++};
> > ++
> > ++iomux_v3_cfg_t usdhc2_pads[] = {
> > ++ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
> > ++ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
> > ++ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
> > ++ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
> > ++ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
> > ++ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
> > ++};
> > ++
> > ++iomux_v3_cfg_t usdhc3_pads[] = {
> > ++ MX6DL_PAD_SD3_CLK__USDHC3_CLK,
> > ++ MX6DL_PAD_SD3_CMD__USDHC3_CMD,
> > ++ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0,
> > ++ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1,
> > ++ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2,
> > ++ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3,
> > ++};
> > ++
> > ++int usdhc_pad_init(bd_t *bis) {
> > ++ s32 status = 0;
> > ++ u32 index = 0;
> > ++
> > ++ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM;
> > ++ ++index) {
> > ++ switch (index) {
> > ++ case 0:
> > ++ mxc_iomux_v3_setup_multiple_pads(usdhc1_pads,
> > ++
> ARRAY_SIZE(usdhc1_pads));
> > ++ break;
> > ++ case 1:
> > ++ mxc_iomux_v3_setup_multiple_pads(usdhc2_pads,
> > ++
> ARRAY_SIZE(usdhc2_pads));
> > ++ break;
> > ++ case 2:
> > ++ mxc_iomux_v3_setup_multiple_pads(usdhc3_pads,
> > ++
> ARRAY_SIZE(usdhc3_pads));
> > ++ break;
> > ++ default:
> > ++ printf("Warning: you configured more USDHC
> controllers"
> > ++ "(%d) then supported by the board
> (%d)\n",
> > ++ index+1, CONFIG_SYS_FSL_USDHC_NUM);
> > ++ return status;
> > ++ }
> > ++ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
> > ++ }
> > ++
> > ++ return status;
> > ++}
> > ++
> > ++int board_mmc_init(bd_t *bis) {
> > ++ if (!usdhc_pad_init(bis))
> > ++ return 0;
> > ++ else
> > ++ return -1;
> > ++}
> > ++
> > ++/* For DDR mode operation, provide target delay parameter for each SD
> port.
> > ++ * Use cfg->esdhc_base to distinguish the SD port #. The delay for
> each port
> > ++ * is dependent on signal layout for that particular port. If the
> following
> > ++ * CONFIG is not defined, then the default target delay value will be
> used.
> > ++ */
> > ++#ifdef CONFIG_GET_DDR_TARGET_DELAY
> > ++u32 get_ddr_delay(struct fsl_esdhc_cfg *cfg) { return 0; }
> > ++#endif
> > ++
> > ++#endif
> > ++
> > ++int board_init(void) {
> > ++ mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
> > ++ setup_boot_device();
> > ++ fsl_set_system_rev();
> > ++
> > ++ /* board id for linux */
> > ++ gd->bd->bi_arch_number = 4412;
> > ++
> > ++ /* address of boot parameters */
> > ++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> > ++
> > ++ setup_uart();
> > ++
> > ++ return 0;
> > ++}
> > ++
> > ++extern int fec_get_mac_addr(unsigned char *mac);
> > ++
> > ++int board_late_init(void) {
> > ++
> > ++ unsigned char mac[6];
> > ++ int i;
> > ++
> > ++ fec_get_mac_addr(mac);
> > ++ printf("Got MAC = ");
> > ++ for (i=0; i<6; i++) {
> > ++ printf("%02X", mac[i]);
> > ++ if (i<5) printf(":"); else printf("\n");
> > ++ }
> > ++
> > ++
> > ++ return 0;
> > ++}
> > ++
> > ++#ifdef CONFIG_MXC_FEC
> > ++static int phy_read(char *devname, unsigned char addr, unsigned char
> reg,
> > ++ unsigned short *pdata)
> > ++{
> > ++ int ret = miiphy_read(devname, addr, reg, pdata);
> > ++ if (ret)
> > ++ printf("Error reading from %s PHY addr=%02x
> reg=%02x\n",
> > ++ devname, addr, reg);
> > ++ return ret;
> > ++}
> > ++
> > ++static int phy_write(char *devname, unsigned char addr, unsigned char
> reg,
> > ++ unsigned short value)
> > ++{
> > ++ int ret = miiphy_write(devname, addr, reg, value);
> > ++ if (ret)
> > ++ printf("Error writing to %s PHY addr=%02x reg=%02x\n",
> devname,
> > ++ addr, reg);
> > ++ return ret;
> > ++}
> > ++
> > ++int mx6_rgmii_rework(char *devname, int phy_addr)
> > ++{
> > ++ unsigned short val;
> > ++
> > ++ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
> > ++ phy_write(devname, phy_addr, 0xd, 0x7);
> > ++ phy_write(devname, phy_addr, 0xe, 0x8016);
> > ++ phy_write(devname, phy_addr, 0xd, 0x4007);
> > ++ phy_read(devname, phy_addr, 0xe, &val);
> > ++
> > ++ val &= 0xffe3;
> > ++ val |= 0x18;
> > ++ phy_write(devname, phy_addr, 0xe, val);
> > ++
> > ++ /* introduce tx clock delay */
> > ++ phy_write(devname, phy_addr, 0x1d, 0x5);
> > ++ phy_read(devname, phy_addr, 0x1e, &val);
> > ++ val |= 0x0100;
> > ++ phy_write(devname, phy_addr, 0x1e, val);
> > ++
> > ++ return 0;
> > ++}
> > ++
> > ++#if defined CONFIG_MX6Q
> > ++iomux_v3_cfg_t enet_pads[] = {
> > ++ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
> > ++ MX6Q_PAD_ENET_MDC__ENET_MDC,
> > ++ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
> > ++ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
> > ++ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
> > ++ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
> > ++ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
> > ++ MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
> > ++ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
> > ++ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
> > ++ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
> > ++ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
> > ++ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
> > ++ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
> > ++ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
> > ++ MX6Q_PAD_GPIO_0__CCM_CLKO,
> > ++ MX6Q_PAD_GPIO_3__CCM_CLKO2,
> > ++};
> > ++#elif defined CONFIG_MX6DL
> > ++iomux_v3_cfg_t enet_pads[] = {
> > ++ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
> > ++ MX6DL_PAD_ENET_MDC__ENET_MDC,
> > ++ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
> > ++ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
> > ++ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
> > ++ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
> > ++ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
> > ++ MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
> > ++ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
> > ++ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
> > ++ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
> > ++ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
> > ++ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
> > ++ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
> > ++ MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
> > ++ MX6DL_PAD_GPIO_0__CCM_CLKO,
> > ++};
> > ++#endif
> > ++
> > ++void enet_board_init(void)
> > ++{
> > ++ unsigned int reg;
> > ++#if defined CONFIG_MX6Q
> > ++ iomux_v3_cfg_t enet_reset =
> > ++ (_MX6Q_PAD_EIM_D29__GPIO_3_29 &
> > ++ ~MUX_PAD_CTRL_MASK) |
> > ++ MUX_PAD_CTRL(0x48);
> > ++#elif defined CONFIG_MX6DL
> > ++ iomux_v3_cfg_t enet_reset =
> > ++ (MX6DL_PAD_EIM_D29__GPIO_3_29 &
> > ++ ~MUX_PAD_CTRL_MASK) |
> > ++ MUX_PAD_CTRL(0x48);
> > ++#endif
> > ++
> > ++ mxc_iomux_v3_setup_multiple_pads(enet_pads,
> > ++ ARRAY_SIZE(enet_pads));
> > ++ mxc_iomux_v3_setup_pad(enet_reset);
> > ++
> > ++ /* PHY reset: gpio 3-29 */
> > ++ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 29), 0);
> > ++
> > ++ udelay(500);
> > ++
> > ++ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 29), 1);
> > ++
> > ++}
> > ++#endif
> > ++
> > ++int checkboard(void) {
> > ++ printf("Board: %s WandBoard 0x%x [",
> > ++ mx6_chip_name(),
> > ++ fsl_system_rev);
> > ++
> > ++ switch (__REG(SRC_BASE_ADDR + 0x8)) {
> > ++ case 0x0001:
> > ++ printf("POR");
> > ++ break;
> > ++ case 0x0009:
> > ++ printf("RST");
> > ++ break;
> > ++ case 0x0010:
> > ++ case 0x0011:
> > ++ printf("WDOG");
> > ++ break;
> > ++ default:
> > ++ printf("unknown");
> > ++ }
> > ++ printf(" ]\n");
> > ++
> > ++ printf("Boot Device: ");
> > ++ switch (get_boot_device()) {
> > ++ case WEIM_NOR_BOOT:
> > ++ printf("NOR\n");
> > ++ break;
> > ++ case ONE_NAND_BOOT:
> > ++ printf("ONE NAND\n");
> > ++ break;
> > ++ case PATA_BOOT:
> > ++ printf("PATA\n");
> > ++ break;
> > ++ case SATA_BOOT:
> > ++ printf("SATA\n");
> > ++ break;
> > ++ case I2C_BOOT:
> > ++ printf("I2C\n");
> > ++ break;
> > ++ case SPI_NOR_BOOT:
> > ++ printf("SPI NOR\n");
> > ++ break;
> > ++ case SD_BOOT:
> > ++ printf("SD\n");
> > ++ break;
> > ++ case MMC_BOOT:
> > ++ printf("MMC\n");
> > ++ break;
> > ++ case NAND_BOOT:
> > ++ printf("NAND\n");
> > ++ break;
> > ++ case UNKNOWN_BOOT:
> > ++ default:
> > ++ printf("UNKNOWN\n");
> > ++ break;
> > ++ }
> > ++ return 0;
> > ++}
> > ++
> > +diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-
> types.h
> > +index 2630bac..e00b122 100644
> > +--- a/include/asm-arm/mach-types.h
> > ++++ b/include/asm-arm/mach-types.h
> > +@@ -3258,6 +3258,9 @@ extern unsigned int __machine_arch_type;
> > + #define MACH_TYPE_MX6Q_SABRELITE 3769
> > + #define MACH_TYPE_MX6Q_ARM2 3837
> > + #define MACH_TYPE_MX6Q_SABRESD 3980
> > ++#define MACH_TYPE_EDM_SF_IMX6 4256
> > ++#define MACH_TYPE_EDM_CF_IMX6 4257
> > ++#define MACH_TYPE_WANDBOARD 4412
> > + #define MACH_TYPE_MX6SL_ARM2 4091
> > + #define MACH_TYPE_MX6SL_EVK 4307
> > +
> > +@@ -42213,6 +42216,30 @@ extern unsigned int __machine_arch_type;
> > + # define machine_is_mx6sl_evk() (0)
> > + #endif
> > +
> > ++#ifdef CONFIG_MACH_EDM_SF_IMX6
> > ++# ifdef machine_arch_type
> > ++# undef machine_arch_type
> > ++# define machine_arch_type __machine_arch_type
> > ++# else
> > ++# define machine_arch_type MACH_TYPE_EDM_SF_IMX6
> > ++# endif
> > ++# define machine_is_edm_sf_imx6() (machine_arch_type ==
> MACH_TYPE_EDM_SF_IMX6)
> > ++#else
> > ++# define machine_is_edm_sf_imx6() (0)
> > ++#endif
> > ++
> > ++#ifdef CONFIG_MACH_EDM_CF_IMX6
> > ++# ifdef machine_arch_type
> > ++# undef machine_arch_type
> > ++# define machine_arch_type __machine_arch_type
> > ++# else
> > ++# define machine_arch_type MACH_TYPE_EDM_CF_IMX6
> > ++# endif
> > ++# define machine_is_edm_cf_imx6() (machine_arch_type ==
> MACH_TYPE_EDM_CF_IMX6)
> > ++#else
> > ++# define machine_is_edm_cf_imx6() (0)
> > ++#endif
> > ++
> > + /*
> > + * These have not yet been registered
> > + */
> > +diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
> > +new file mode 100644
> > +index 0000000..e872c6b
> > +--- /dev/null
> > ++++ b/include/configs/wandboard.h
> > +@@ -0,0 +1,273 @@
> > ++/*
> > ++ * Configuration settings for the Wandboard.
> > ++ *
> > ++ * Copyright (C) 2013 Wandboard.org
> > ++ *
> > ++ * This program is free software; you can redistribute it and/or
> > ++ * modify it under the terms of the GNU General Public License as
> > ++ * published by the Free Software Foundation; either version 2 of
> > ++ * the License, or (at your option) any later version.
> > ++ *
> > ++ * This program is distributed in the hope that it will be useful,
> > ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
> the
> > ++ * GNU General Public License for more details.
> > ++ *
> > ++ * You should have received a copy of the GNU General Public License
> > ++ * along with this program; if not, write to the Free Software
> > ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > ++ * MA 02111-1307 USA
> > ++ */
> > ++
> > ++#ifndef __CONFIG_H
> > ++#define __CONFIG_H
> > ++
> > ++#include <asm/arch/mx6.h>
> > ++
> > ++ /* High Level Configuration Options */
> > ++#define CONFIG_ARMV7
> > ++#define CONFIG_MXC
> > ++#define CONFIG_MX6DL
> > ++#define CONFIG_WANDBOARD
> > ++
> > ++/* Comment this line when compiling for the Wandboard Solo */
> > ++#define CONFIG_WANDBOARD_DUAL
> > ++
> > ++/* Setup memory depending if we have 512M/1G. */
> > ++#ifdef CONFIG_WANDBOARD_DUAL
> > ++#define CONFIG_MX6DL_DDR3
> > ++#define CONFIG_DDR_64BIT
> > ++#else
> > ++#define CONFIG_MX6SOLO_DDR3
> > ++#define CONFIG_DDR_32BIT
> > ++#endif
> > ++
> > ++#define CONFIG_FLASH_HEADER
> > ++#define CONFIG_FLASH_HEADER_OFFSET 0x400
> > ++#define CONFIG_MX6_CLK32 32768
> > ++
> > ++#define CONFIG_SKIP_RELOCATE_UBOOT
> > ++
> > ++#define CONFIG_ARCH_CPU_INIT
> > ++#undef CONFIG_ARCH_MMU /* disable MMU first */
> > ++#define CONFIG_L2_OFF /* disable L2 cache first*/
> > ++
> > ++#define CONFIG_MX6_HCLK_FREQ 24000000
> > ++
> > ++#define CONFIG_DISPLAY_CPUINFO
> > ++#define CONFIG_DISPLAY_BOARDINFO
> > ++
> > ++#define CONFIG_SYS_64BIT_VSPRINTF
> > ++
> > ++#define BOARD_LATE_INIT
> > ++
> > ++#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> > ++#define CONFIG_REVISION_TAG
> > ++#define CONFIG_SETUP_MEMORY_TAGS
> > ++
> > ++/*
> > ++ * Size of malloc() pool
> > ++ */
> > ++#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
> > ++/* size in bytes reserved for initial data */
> > ++#define CONFIG_SYS_GBL_DATA_SIZE 128
> > ++
> > ++/*
> > ++ * Hardware drivers
> > ++ */
> > ++#define CONFIG_MXC_UART
> > ++#define CONFIG_MXC_GPIO
> > ++#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR
> > ++
> > ++/* allow to overwrite serial and ethaddr */
> > ++#define CONFIG_ENV_OVERWRITE
> > ++#define CONFIG_CONS_INDEX 1
> > ++#define CONFIG_BAUDRATE 115200
> > ++#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600,
> 115200}
> > ++
> > ++/***********************************************************
> > ++ * Command definition
> > ++ ***********************************************************/
> > ++
> > ++#define CONFIG_CMD_BDI /* bdinfo
> */
> > ++#define CONFIG_CMD_CONSOLE /* coninfo
> */
> > ++#define CONFIG_CMD_ECHO /* echo
> arguments */
> > ++#define CONFIG_CMD_IMI /* iminfo
> */
> > ++#define CONFIG_CMD_ITEST /* Integer (and string)
> test */
> > ++#define CONFIG_CMD_LOADB /* loadb
> */
> > ++#define CONFIG_CMD_LOADS /* loads
> */
> > ++#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp
> crc base loop mtest */
> > ++#define CONFIG_CMD_MISC /* Misc
> functions like sleep etc*/
> > ++#define CONFIG_CMD_RUN /* run command
> in env variable */
> > ++#define CONFIG_CMD_SAVEENV /* saveenv
> */
> > ++#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
> > ++#define CONFIG_CMD_SOURCE /* "source" command
> support */
> > ++#define CONFIG_CMD_XIMG /* Load part of
> Multi Image */
> > ++
> > ++#define CONFIG_PARTITIONS 1
> > ++
> > ++#define CONFIG_SYS_NO_FLASH
> > ++#define CONFIG_CMD_BOOTD /* bootd */
> > ++
> > ++#define CONFIG_CMD_IMXOTP
> > ++#define CONFIG_CMD_NET
> > ++#define CONFIG_NET_MULTI
> 1
> > ++#define CONFIG_FEC0_IOBASE
> ENET_BASE_ADDR
> > ++#define CONFIG_FEC0_PINMUX -1
> > ++#define CONFIG_FEC0_MIIBASE -1
> > ++#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
> > ++#define CONFIG_MXC_FEC
> > ++#define CONFIG_FEC0_PHY_ADDR 0xFF
> > ++#define CONFIG_DISCOVER_PHY
> > ++#define CONFIG_ETH_PRIME
> > ++#define CONFIG_RMII
> > ++#define CONFIG_CMD_MII
> > ++#define CONFIG_CMD_DHCP
> > ++#define CONFIG_CMD_PING
> > ++#define CONFIG_IPADDR 192.168.1.103
> > ++#define CONFIG_SERVERIP 192.168.1.101
> > ++#define CONFIG_NETMASK 255.255.255.0
> > ++
> > ++/* Enable below configure when supporting nand */
> > ++#define CONFIG_CMD_MMC
> > ++#define CONFIG_CMD_ENV
> > ++#define CONFIG_CMD_REGUL
> > ++
> > ++#define CONFIG_CMD_CLOCK
> > ++#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
> > ++
> > ++#undef CONFIG_CMD_IMLS
> > ++
> > ++#define CONFIG_CMD_IMX_DOWNLOAD_MODE
> > ++
> > ++#define CONFIG_BOOTDELAY 1
> > ++
> > ++#define CONFIG_LOADADDR 0x10800000 /* loadaddr env
> var */
> > ++#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
> > ++
> > ++#define CONFIG_EXTRA_ENV_SETTINGS \
> > ++ "netdev=eth0\0" \
> > ++ "uboot=u-boot.bin\0" \
> > ++ "kernel=uImage\0" \
> > ++ "bootargs=console=ttymxc0,115200\0" \
> > ++
> "videoargs=video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24\0" \
> > ++ "bootargs_base=setenv bootargs
> console=ttymxc0,115200\0" \
> > ++ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs
> " \
> > ++ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
> " \
> > ++ "video=${videoargs}\0" \
> > ++ "bootcmd_net=dhcp; run bootargs_base
> bootargs_nfs;bootm\0" \
> > ++ "bootargs_mmc=setenv bootargs ${bootargs} " \
> > ++ "root=/dev/mmcblk0p2 rootwait rw " \
> > ++ "video=${videoargs}\0" \
> > ++ "bootcmd_mmc=run bootargs_base bootargs_mmc;mmc dev 2;"
> \
> > ++ "fatload mmc 2 ${loadaddr} ${kernel};bootm\0" \
> > ++ "bootcmd=run bootcmd_mmc\0" \
> > ++ "upgradeu=for disk in 0 1 ; do mmc dev ${disk} ;" \
> > ++ "for fs in fat ext2 ; do " \
> > ++ "${fs}load mmc ${disk}:1
> 10008000 " \
> > ++ "/6q_upgrade && " \
> > ++ "source 10008000 ; " \
> > ++ "done ; " \
> > ++ "done\0" \
> > ++ "bootfile=_BOOT_FILE_PATH_IN_TFTP_\0" \
> > ++ "nfsroot=_ROOTFS_PATH_IN_NFS_\0"
> > ++
> > ++#define CONFIG_ARP_TIMEOUT 200UL
> > ++
> > ++/*
> > ++ * Miscellaneous configurable options
> > ++ */
> > ++#define CONFIG_SYS_LONGHELP /* undef to save memory */
> > ++#define CONFIG_SYS_PROMPT "WANDBOARD U-Boot > "
> > ++#define CONFIG_AUTO_COMPLETE
> > ++#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer
> Size */
> > ++/* Print Buffer Size */
> > ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +
> sizeof(CONFIG_SYS_PROMPT) + 16)
> > ++#define CONFIG_SYS_MAXARGS 16 /* max number of command args
> */
> > ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer
> Size */
> > ++
> > ++#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest
> works on */
> > ++#define CONFIG_SYS_MEMTEST_END 0x10010000
> > ++
> > ++#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl
> board info, in Hz */
> > ++
> > ++#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> > ++
> > ++#define CONFIG_SYS_HZ 1000
> > ++
> > ++#define CONFIG_CMDLINE_EDITING
> > ++
> > ++/*
> > ++ * OCOTP Configs
> > ++ */
> > ++#ifdef CONFIG_CMD_IMXOTP
> > ++ #define CONFIG_IMX_OTP
> > ++ #define IMX_OTP_BASE OCOTP_BASE_ADDR
> > ++ #define IMX_OTP_ADDR_MAX 0x7F
> > ++ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
> > ++#endif
> > ++
> > ++/* Regulator Configs */
> > ++#ifdef CONFIG_CMD_REGUL
> > ++ #define CONFIG_ANATOP_REGULATOR
> > ++ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
> > ++ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
> > ++#endif
> > ++
> > ++/*
> > ++ * MMC Configs
> > ++ */
> > ++#ifdef CONFIG_CMD_MMC
> > ++ #define CONFIG_MMC
> > ++ #define CONFIG_GENERIC_MMC
> > ++ #define CONFIG_IMX_MMC
> > ++ #define CONFIG_SYS_FSL_USDHC_NUM 3
> > ++ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > ++ #define CONFIG_SYS_MMC_ENV_DEV
> 2
> > ++ #define CONFIG_DOS_PARTITION
> 1
> > ++ #define CONFIG_CMD_FAT
> 1
> > ++ #define CONFIG_CMD_EXT2
> 1
> > ++
> > ++ /* detect whether SD1 or 3 is boot device */
> > ++ #define CONFIG_DYNAMIC_MMC_DEVNO
> > ++
> > ++ /* No 8 bit MMC */
> > ++ #define CONFIG_MMC_8BIT_PORTS 0x0
> > ++#endif
> > ++
> > ++/*-------------------------------------------------------------------
> ----
> > ++ * Stack sizes
> > ++ *
> > ++ * The stack sizes are set up in start.S using the settings below
> > ++ */
> > ++#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
> > ++
> > ++/*-------------------------------------------------------------------
> ----
> > ++ * Physical Memory Map
> > ++ */
> > ++#define CONFIG_NR_DRAM_BANKS 1
> > ++#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
> > ++#ifdef CONFIG_DDR_64BIT
> > ++ #define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
> > ++#else
> > ++ #define PHYS_SDRAM_1_SIZE (512u * 1024 * 1024)
> > ++#endif
> > ++#define iomem_valid_addr(addr, size) \
> > ++ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 +
> PHYS_SDRAM_1_SIZE))
> > ++
> > ++/*-------------------------------------------------------------------
> ----
> > ++ * FLASH and environment organization
> > ++ */
> > ++
> > ++/* No NAND */
> > ++#define CONFIG_SYS_NO_FLASH
> > ++
> > ++/* Monitor at beginning of flash */
> > ++#define CONFIG_FSL_ENV_IN_MMC
> > ++
> > ++#define CONFIG_ENV_SECT_SIZE (8 * 1024)
> > ++#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> > ++#define CONFIG_ENV_IS_IN_MMC 1
> > ++#define CONFIG_ENV_OFFSET (768 * 1024)
> > ++
> > ++#endif /* __CONFIG_H */
> > +--
> > +1.7.9.5
> > +
> > diff --git a/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend b/recipes-
> bsp/u-boot/u-boot-imx_2009.08.bbappend
> > new file mode 100644
> > index 0000000..0a50ccf
> > --- /dev/null
> > +++ b/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
> > @@ -0,0 +1,8 @@
> > +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}"
> > +
> > +PRINC := "${@int(PRINC) + 1}"
> > +
> > +# Wandboard-specific patches
> > +SRC_URI_append_mx6= " \
> > + file://Initial-support-for-Wandboard-Dual.patch \
> > +"
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > meta-freescale mailing list
> > meta-freescale@yoctoproject.org
> > https://lists.yoctoproject.org/listinfo/meta-freescale
>
>
>
> --
> Otavio Salvador O.S. Systems
> E-mail: otavio@ossystems.com.br http://www.ossystems.com.br
> Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [meta-fsl-arm-extra][PATCH 2/3] Add U-boot support for Wandboard Dual
2013-02-26 20:11 ` John Weber
@ 2013-02-26 20:17 ` Otavio Salvador
0 siblings, 0 replies; 8+ messages in thread
From: Otavio Salvador @ 2013-02-26 20:17 UTC (permalink / raw)
To: John Weber; +Cc: meta-freescale
On Tue, Feb 26, 2013 at 5:11 PM, John Weber <rjohnweber@gmail.com> wrote:
> Hi Otavio -
>
> The U-boot recipe, I've had problems using SRC_URI_apppend_<machine name> to
> target patches to a particular machine. What I've done below is target them
> to i.mx6 and then bitbake ties this to u-boot. I can put the wandboard-dual
> specific patch into a subdirectory, as show below:
>
> FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}"
>
> PRINC := "${@int(PRINC) + 1}"
>
> # Wandboard-specific patches
> SRC_URI_append_mx6= " \
> file://wandboard-dual/Initial-support-for-Wandboard-Dual.patch \
> "
>
> But, if I do SRC_URI_append_wandboard-dual = "..." , this does not work.
Please check the overrides:
bitbake u-boot-imx -e | grep OVERRIDES
It should how the overrides it is taking.
--
Otavio Salvador O.S. Systems
E-mail: otavio@ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2013-02-26 20:17 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-02-23 20:29 [meta-fsl-arm-extra][PATCH 1/3] Add kernel support for Wandboard Dual John Weber
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 2/3] Add U-boot " John Weber
2013-02-26 19:24 ` Otavio Salvador
2013-02-26 20:11 ` John Weber
2013-02-26 20:17 ` Otavio Salvador
2013-02-23 20:29 ` [meta-fsl-arm-extra][PATCH 3/3] Add conf " John Weber
2013-02-26 19:25 ` Otavio Salvador
2013-02-26 19:24 ` [meta-fsl-arm-extra][PATCH 1/3] Add kernel " Otavio Salvador
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