From: Ulf Hansson <ulf.hansson@linaro.org>
To: Andrew Jeffery <andrew@aj.id.au>
Cc: "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Adrian Hunter <adrian.hunter@intel.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
DTML <devicetree@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
linux-aspeed <linux-aspeed@lists.ozlabs.org>,
ryan_chen@aspeedtech.com
Subject: Re: [PATCH v5 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning
Date: Mon, 14 Dec 2020 16:56:59 +0100 [thread overview]
Message-ID: <CAPDyKFpCiA_fT0tQ58z_3mt183RJ30QZWE_qjbmXGO3imHqMzw@mail.gmail.com> (raw)
In-Reply-To: <20201208012615.2717412-1-andrew@aj.id.au>
On Tue, 8 Dec 2020 at 02:26, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> Hello,
>
> This series implements support for the MMC core clk-phase-* devicetree bindings
> in the Aspeed SD/eMMC driver. The relevant register was exposed on the AST2600
> and is present for both the SD/MMC controller and the dedicated eMMC
> controller.
>
> v5 fixes some build issues identified by the kernel test robot.
>
> v4 can be found here:
>
> https://lore.kernel.org/linux-mmc/20201207142556.2045481-1-andrew@aj.id.au/
>
> The series has had light testing on an AST2600-based platform which requires
> 180deg of input and output clock phase correction at HS200, as well as some
> synthetic testing under qemu and KUnit.
>
> Please review!
FYI, other than the comment I had on patch1, I think the series looks
good to me.
[...]
Kind regards
Uffe
WARNING: multiple messages have this Message-ID (diff)
From: Ulf Hansson <ulf.hansson@linaro.org>
To: Andrew Jeffery <andrew@aj.id.au>
Cc: DTML <devicetree@vger.kernel.org>,
ryan_chen@aspeedtech.com,
linux-aspeed <linux-aspeed@lists.ozlabs.org>,
"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning
Date: Mon, 14 Dec 2020 16:56:59 +0100 [thread overview]
Message-ID: <CAPDyKFpCiA_fT0tQ58z_3mt183RJ30QZWE_qjbmXGO3imHqMzw@mail.gmail.com> (raw)
In-Reply-To: <20201208012615.2717412-1-andrew@aj.id.au>
On Tue, 8 Dec 2020 at 02:26, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> Hello,
>
> This series implements support for the MMC core clk-phase-* devicetree bindings
> in the Aspeed SD/eMMC driver. The relevant register was exposed on the AST2600
> and is present for both the SD/MMC controller and the dedicated eMMC
> controller.
>
> v5 fixes some build issues identified by the kernel test robot.
>
> v4 can be found here:
>
> https://lore.kernel.org/linux-mmc/20201207142556.2045481-1-andrew@aj.id.au/
>
> The series has had light testing on an AST2600-based platform which requires
> 180deg of input and output clock phase correction at HS200, as well as some
> synthetic testing under qemu and KUnit.
>
> Please review!
FYI, other than the comment I had on patch1, I think the series looks
good to me.
[...]
Kind regards
Uffe
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-12-14 15:58 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-08 1:26 [PATCH v5 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning Andrew Jeffery
2020-12-08 1:26 ` Andrew Jeffery
2020-12-08 1:26 ` [PATCH v5 1/6] mmc: core: Add helper for parsing clock phase properties Andrew Jeffery
2020-12-08 1:26 ` Andrew Jeffery
2020-12-14 15:48 ` Ulf Hansson
2020-12-14 15:48 ` Ulf Hansson
2020-12-14 23:31 ` Andrew Jeffery
2020-12-14 23:31 ` Andrew Jeffery
2020-12-08 1:26 ` [PATCH v5 2/6] mmc: sdhci-of-aspeed: Expose clock phase controls Andrew Jeffery
2020-12-08 1:26 ` Andrew Jeffery
2020-12-08 1:26 ` [PATCH v5 3/6] mmc: sdhci-of-aspeed: Add AST2600 bus clock support Andrew Jeffery
2020-12-08 1:26 ` Andrew Jeffery
2020-12-08 1:26 ` [PATCH v5 4/6] mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations Andrew Jeffery
2020-12-08 1:26 ` Andrew Jeffery
2020-12-08 1:26 ` [PATCH v5 5/6] MAINTAINERS: Add entry for the ASPEED SD/MMC driver Andrew Jeffery
2020-12-08 1:26 ` Andrew Jeffery
2020-12-08 1:26 ` [PATCH v5 6/6] ARM: dts: rainier: Add eMMC clock phase compensation Andrew Jeffery
2020-12-08 1:26 ` Andrew Jeffery
2020-12-08 4:47 ` Joel Stanley
2020-12-08 4:47 ` Joel Stanley
2020-12-14 15:56 ` Ulf Hansson [this message]
2020-12-14 15:56 ` [PATCH v5 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning Ulf Hansson
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