* [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning
@ 2019-06-17 20:10 Raul E Rangel
2019-06-17 20:10 ` [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width Raul E Rangel
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Raul E Rangel @ 2019-06-17 20:10 UTC (permalink / raw)
To: linux-mmc
Cc: ernest.zhang, djkurtz, Raul E Rangel, Adrian Hunter,
linux-kernel, Ulf Hansson
The O2Micro controller only supports tuning at 4-bits. So the host driver
needs to change the bus width while tuning and then set it back when done.
There was a bug in the original implementation in that mmc->ios.bus_width
also wasn't updated. Thus setting the incorrect blocksize in
sdhci_send_tuning which results in a tuning failure.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Fixes: 0086fc217d5d7 ("mmc: sdhci: Add support for O2 hardware tuning")
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-pci-o2micro.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
index b29bf4e7dcb48..dd21315922c87 100644
--- a/drivers/mmc/host/sdhci-pci-o2micro.c
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -115,6 +115,7 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
*/
if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
current_bus_width = mmc->ios.bus_width;
+ mmc->ios.bus_width = MMC_BUS_WIDTH_4;
sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
}
@@ -126,8 +127,10 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
sdhci_end_tuning(host);
- if (current_bus_width == MMC_BUS_WIDTH_8)
+ if (current_bus_width == MMC_BUS_WIDTH_8) {
+ mmc->ios.bus_width = MMC_BUS_WIDTH_8;
sdhci_set_bus_width(host, current_bus_width);
+ }
host->flags &= ~SDHCI_HS400_TUNING;
return 0;
--
2.22.0.410.gd8fdbe21b5-goog
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width
2019-06-17 20:10 [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning Raul E Rangel
@ 2019-06-17 20:10 ` Raul E Rangel
2019-06-18 6:56 ` Adrian Hunter
2019-06-18 11:40 ` Ulf Hansson
2019-06-17 20:10 ` [PATCH v2 3/3] mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS Raul E Rangel
2019-06-18 11:40 ` [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning Ulf Hansson
2 siblings, 2 replies; 7+ messages in thread
From: Raul E Rangel @ 2019-06-17 20:10 UTC (permalink / raw)
To: linux-mmc
Cc: ernest.zhang, djkurtz, Raul E Rangel, linux-kernel,
Adrian Hunter, Ulf Hansson
The O2 controller supports 8-bit EMMC access.
JESD84-B51 section A.6.3.a defines the bus testing procedure that
`mmc_select_bus_width()` implements. This is used to determine the actual
bus width of the eMMC.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
---
I tested this on an AMD chromebook.
$ cat /sys/kernel/debug/mmc1/ios
clock: 200000000 Hz
actual clock: 200000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 9 (mmc HS200)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
Before this patch only 4 bit was negotiated.
drivers/mmc/host/sdhci-pci-o2micro.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
index dd21315922c87..9dc4548271b4b 100644
--- a/drivers/mmc/host/sdhci-pci-o2micro.c
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -395,11 +395,21 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
{
struct sdhci_pci_chip *chip;
struct sdhci_host *host;
- u32 reg;
+ u32 reg, caps;
int ret;
chip = slot->chip;
host = slot->host;
+
+ caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+
+ /*
+ * mmc_select_bus_width() will test the bus to determine the actual bus
+ * width.
+ */
+ if (caps & SDHCI_CAN_DO_8BIT)
+ host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
switch (chip->pdev->device) {
case PCI_DEVICE_ID_O2_SDS0:
case PCI_DEVICE_ID_O2_SEABIRD0:
--
2.22.0.410.gd8fdbe21b5-goog
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width
2019-06-17 20:10 ` [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width Raul E Rangel
@ 2019-06-18 6:56 ` Adrian Hunter
2019-06-18 11:40 ` Ulf Hansson
1 sibling, 0 replies; 7+ messages in thread
From: Adrian Hunter @ 2019-06-18 6:56 UTC (permalink / raw)
To: Raul E Rangel, linux-mmc; +Cc: ernest.zhang, djkurtz, linux-kernel, Ulf Hansson
On 17/06/19 11:10 PM, Raul E Rangel wrote:
> The O2 controller supports 8-bit EMMC access.
>
> JESD84-B51 section A.6.3.a defines the bus testing procedure that
> `mmc_select_bus_width()` implements. This is used to determine the actual
> bus width of the eMMC.
>
> Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> I tested this on an AMD chromebook.
>
> $ cat /sys/kernel/debug/mmc1/ios
> clock: 200000000 Hz
> actual clock: 200000000 Hz
> vdd: 21 (3.3 ~ 3.4 V)
> bus mode: 2 (push-pull)
> chip select: 0 (don't care)
> power mode: 2 (on)
> bus width: 3 (8 bits)
> timing spec: 9 (mmc HS200)
> signal voltage: 1 (1.80 V)
> driver type: 0 (driver type B)
>
> Before this patch only 4 bit was negotiated.
>
> drivers/mmc/host/sdhci-pci-o2micro.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index dd21315922c87..9dc4548271b4b 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -395,11 +395,21 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
> {
> struct sdhci_pci_chip *chip;
> struct sdhci_host *host;
> - u32 reg;
> + u32 reg, caps;
> int ret;
>
> chip = slot->chip;
> host = slot->host;
> +
> + caps = sdhci_readl(host, SDHCI_CAPABILITIES);
> +
> + /*
> + * mmc_select_bus_width() will test the bus to determine the actual bus
> + * width.
> + */
> + if (caps & SDHCI_CAN_DO_8BIT)
> + host->mmc->caps |= MMC_CAP_8_BIT_DATA;
> +
> switch (chip->pdev->device) {
> case PCI_DEVICE_ID_O2_SDS0:
> case PCI_DEVICE_ID_O2_SEABIRD0:
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width
2019-06-17 20:10 ` [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width Raul E Rangel
2019-06-18 6:56 ` Adrian Hunter
@ 2019-06-18 11:40 ` Ulf Hansson
1 sibling, 0 replies; 7+ messages in thread
From: Ulf Hansson @ 2019-06-18 11:40 UTC (permalink / raw)
To: Raul E Rangel
Cc: linux-mmc, ernest.zhang, Daniel Kurtz, Linux Kernel Mailing List,
Adrian Hunter
On Mon, 17 Jun 2019 at 22:10, Raul E Rangel <rrangel@chromium.org> wrote:
>
> The O2 controller supports 8-bit EMMC access.
>
> JESD84-B51 section A.6.3.a defines the bus testing procedure that
> `mmc_select_bus_width()` implements. This is used to determine the actual
> bus width of the eMMC.
>
> Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> I tested this on an AMD chromebook.
>
> $ cat /sys/kernel/debug/mmc1/ios
> clock: 200000000 Hz
> actual clock: 200000000 Hz
> vdd: 21 (3.3 ~ 3.4 V)
> bus mode: 2 (push-pull)
> chip select: 0 (don't care)
> power mode: 2 (on)
> bus width: 3 (8 bits)
> timing spec: 9 (mmc HS200)
> signal voltage: 1 (1.80 V)
> driver type: 0 (driver type B)
>
> Before this patch only 4 bit was negotiated.
>
> drivers/mmc/host/sdhci-pci-o2micro.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index dd21315922c87..9dc4548271b4b 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -395,11 +395,21 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
> {
> struct sdhci_pci_chip *chip;
> struct sdhci_host *host;
> - u32 reg;
> + u32 reg, caps;
> int ret;
>
> chip = slot->chip;
> host = slot->host;
> +
> + caps = sdhci_readl(host, SDHCI_CAPABILITIES);
> +
> + /*
> + * mmc_select_bus_width() will test the bus to determine the actual bus
> + * width.
> + */
> + if (caps & SDHCI_CAN_DO_8BIT)
> + host->mmc->caps |= MMC_CAP_8_BIT_DATA;
> +
> switch (chip->pdev->device) {
> case PCI_DEVICE_ID_O2_SDS0:
> case PCI_DEVICE_ID_O2_SEABIRD0:
> --
> 2.22.0.410.gd8fdbe21b5-goog
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS
2019-06-17 20:10 [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning Raul E Rangel
2019-06-17 20:10 ` [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width Raul E Rangel
@ 2019-06-17 20:10 ` Raul E Rangel
2019-06-18 11:40 ` Ulf Hansson
2019-06-18 11:40 ` [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning Ulf Hansson
2 siblings, 1 reply; 7+ messages in thread
From: Raul E Rangel @ 2019-06-17 20:10 UTC (permalink / raw)
To: linux-mmc
Cc: ernest.zhang, djkurtz, Raul E Rangel, Adrian Hunter,
linux-kernel, Ulf Hansson
Remove whitespace in front of SDHCI_CTRL_8BITBUS. The value is not part
of SDHCI_CTRL_DMA_MASK.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 199712e7adbb3..89fd96596a1f7 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -89,7 +89,7 @@
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
#define SDHCI_CTRL_ADMA3 0x18
-#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_8BITBUS 0x20
#define SDHCI_CTRL_CDTEST_INS 0x40
#define SDHCI_CTRL_CDTEST_EN 0x80
--
2.22.0.410.gd8fdbe21b5-goog
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 3/3] mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS
2019-06-17 20:10 ` [PATCH v2 3/3] mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS Raul E Rangel
@ 2019-06-18 11:40 ` Ulf Hansson
0 siblings, 0 replies; 7+ messages in thread
From: Ulf Hansson @ 2019-06-18 11:40 UTC (permalink / raw)
To: Raul E Rangel
Cc: linux-mmc, ernest.zhang, Daniel Kurtz, Adrian Hunter,
Linux Kernel Mailing List
On Mon, 17 Jun 2019 at 22:10, Raul E Rangel <rrangel@chromium.org> wrote:
>
> Remove whitespace in front of SDHCI_CTRL_8BITBUS. The value is not part
> of SDHCI_CTRL_DMA_MASK.
>
> Signed-off-by: Raul E Rangel <rrangel@chromium.org>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> drivers/mmc/host/sdhci.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 199712e7adbb3..89fd96596a1f7 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -89,7 +89,7 @@
> #define SDHCI_CTRL_ADMA32 0x10
> #define SDHCI_CTRL_ADMA64 0x18
> #define SDHCI_CTRL_ADMA3 0x18
> -#define SDHCI_CTRL_8BITBUS 0x20
> +#define SDHCI_CTRL_8BITBUS 0x20
> #define SDHCI_CTRL_CDTEST_INS 0x40
> #define SDHCI_CTRL_CDTEST_EN 0x80
>
> --
> 2.22.0.410.gd8fdbe21b5-goog
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning
2019-06-17 20:10 [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning Raul E Rangel
2019-06-17 20:10 ` [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width Raul E Rangel
2019-06-17 20:10 ` [PATCH v2 3/3] mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS Raul E Rangel
@ 2019-06-18 11:40 ` Ulf Hansson
2 siblings, 0 replies; 7+ messages in thread
From: Ulf Hansson @ 2019-06-18 11:40 UTC (permalink / raw)
To: Raul E Rangel
Cc: linux-mmc, ernest.zhang, Daniel Kurtz, Adrian Hunter,
Linux Kernel Mailing List
On Mon, 17 Jun 2019 at 22:10, Raul E Rangel <rrangel@chromium.org> wrote:
>
> The O2Micro controller only supports tuning at 4-bits. So the host driver
> needs to change the bus width while tuning and then set it back when done.
>
> There was a bug in the original implementation in that mmc->ios.bus_width
> also wasn't updated. Thus setting the incorrect blocksize in
> sdhci_send_tuning which results in a tuning failure.
>
> Signed-off-by: Raul E Rangel <rrangel@chromium.org>
> Fixes: 0086fc217d5d7 ("mmc: sdhci: Add support for O2 hardware tuning")
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Applied for fixes and by adding a stable tag, thanks!
Kind regards
Uffe
> ---
>
> drivers/mmc/host/sdhci-pci-o2micro.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index b29bf4e7dcb48..dd21315922c87 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -115,6 +115,7 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
> */
> if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
> current_bus_width = mmc->ios.bus_width;
> + mmc->ios.bus_width = MMC_BUS_WIDTH_4;
> sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
> }
>
> @@ -126,8 +127,10 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
>
> sdhci_end_tuning(host);
>
> - if (current_bus_width == MMC_BUS_WIDTH_8)
> + if (current_bus_width == MMC_BUS_WIDTH_8) {
> + mmc->ios.bus_width = MMC_BUS_WIDTH_8;
> sdhci_set_bus_width(host, current_bus_width);
> + }
>
> host->flags &= ~SDHCI_HS400_TUNING;
> return 0;
> --
> 2.22.0.410.gd8fdbe21b5-goog
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-06-18 11:41 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-17 20:10 [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning Raul E Rangel
2019-06-17 20:10 ` [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width Raul E Rangel
2019-06-18 6:56 ` Adrian Hunter
2019-06-18 11:40 ` Ulf Hansson
2019-06-17 20:10 ` [PATCH v2 3/3] mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS Raul E Rangel
2019-06-18 11:40 ` Ulf Hansson
2019-06-18 11:40 ` [PATCH v2 1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning Ulf Hansson
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