[PATCH linux dev-4.7 0/4] SuperIO and Host Interface Controllers

[PATCH linux dev-4.7 0/4] SuperIO and Host Interface Controllers

[Andrew Jeffery]

Hello,

This series adds some sysfs drivers exposing parts of the LPC controller. The
patches are pretty bare-bones in that they provide zero sanity checking and
leave decisions entirely to userspace. They're also slightly tedious, so I
expect (hope) their current form will be short-lived.

Cheers,

Andrew

Andrew Jeffery (4):
  misc: Expose Aspeed SuperIO scratch registers (SCRxSIO)
  misc: Add partial Aspeed LPC Host Interface Control (HIC) driver
  arm: aspeed: dt: Add SuperIO scratch register nodes
  arm: aspeed: dt: Add LPC Host Interface Controller nodes

 arch/arm/boot/dts/aspeed-g4.dtsi |  10 ++
 arch/arm/boot/dts/aspeed-g5.dtsi |  10 ++
 drivers/misc/Kconfig             |  14 +++
 drivers/misc/Makefile            |   2 +
 drivers/misc/aspeed-hic.c        | 198 +++++++++++++++++++++++++++++++++++++++
 drivers/misc/aspeed-scrsio.c     | 141 ++++++++++++++++++++++++++++
 6 files changed, 375 insertions(+)
 create mode 100644 drivers/misc/aspeed-hic.c
 create mode 100644 drivers/misc/aspeed-scrsio.c

-- 
2.9.3

[PATCH linux dev-4.7 1/4] misc: Expose Aspeed SuperIO scratch registers (SCRxSIO)

[Andrew Jeffery]

Exposes a sysfs interface to manipulate the SuperIO scratch registers
present in the LPC controller.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/misc/Kconfig         |   7 +++
 drivers/misc/Makefile        |   1 +
 drivers/misc/aspeed-scrsio.c | 141 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 drivers/misc/aspeed-scrsio.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4617ddc3c538..27327f44a709 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -51,6 +51,13 @@ config AD525X_DPOT_SPI
 	  To compile this driver as a module, choose M here: the
 	  module will be called ad525x_dpot-spi.
 
+config ASPEED_SCRSIO
+	bool "Support for Aspeed SuperIO scratch registers"
+	depends on ARCH_ASPEED || COMPILE_TEST
+	help
+	  Select this if you wish to expose to userspace the SuperIO scratch
+	  registers in the LPC control space on an Aspeed BMC SoC.
+
 config ATMEL_TCLIB
 	bool "Atmel AT32/AT91 Timer/Counter Library"
 	depends on (AVR32 || ARCH_AT91)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 724861b7f291..0bcd6ff61a12 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_IBM_ASM)		+= ibmasm/
 obj-$(CONFIG_AD525X_DPOT)	+= ad525x_dpot.o
 obj-$(CONFIG_AD525X_DPOT_I2C)	+= ad525x_dpot-i2c.o
 obj-$(CONFIG_AD525X_DPOT_SPI)	+= ad525x_dpot-spi.o
+obj-$(CONFIG_ASPEED_SCRSIO)	+= aspeed-scrsio.o
 obj-$(CONFIG_INTEL_MID_PTI)	+= pti.o
 obj-$(CONFIG_ATMEL_SSC)		+= atmel-ssc.o
 obj-$(CONFIG_ATMEL_TCLIB)	+= atmel_tclib.o
diff --git a/drivers/misc/aspeed-scrsio.c b/drivers/misc/aspeed-scrsio.c
new file mode 100644
index 000000000000..8d097b35612e
--- /dev/null
+++ b/drivers/misc/aspeed-scrsio.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2016 IBM Corporation
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#define LPC_SCR0SIO	0x0
+#define LPC_SCR1SIO	0x4
+#define LPC_SCR2SIO	0x8
+#define LPC_SCR3SIO	0xc
+
+struct aspeed_scrsio {
+	void __iomem *base;
+};
+
+static ssize_t scrsio_store(struct device *dev, struct device_attribute *attr,
+			    const char *buf, size_t len, int reg)
+{
+	struct aspeed_scrsio *scrsio = dev_get_drvdata(dev);
+	int r;
+	u32 value;
+
+	r = kstrtou32(buf, 0, &value);
+	if (r)
+		return r;
+
+	iowrite32(value, scrsio->base + reg);
+
+	return len;
+}
+
+ssize_t scrsio_show(struct device *dev, struct device_attribute *attr,
+		    char *buf, int reg)
+{
+	struct aspeed_scrsio *scrsio = dev_get_drvdata(dev);
+	u32 value;
+
+	value = ioread32(scrsio->base + reg);
+
+	return scnprintf(buf, PAGE_SIZE, "0x%08x\n", value);
+}
+
+static ssize_t scr0sio_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t len)
+{
+	return scrsio_store(dev, attr, buf, len, LPC_SCR0SIO);
+}
+
+static ssize_t scr0sio_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	return scrsio_show(dev, attr, buf, LPC_SCR0SIO);
+}
+DEVICE_ATTR_RW(scr0sio);
+
+static ssize_t scr1sio_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t len)
+{
+	return scrsio_store(dev, attr, buf, len, LPC_SCR1SIO);
+}
+
+static ssize_t scr1sio_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	return scrsio_show(dev, attr, buf, LPC_SCR1SIO);
+}
+DEVICE_ATTR_RW(scr1sio);
+
+static ssize_t scr2sio_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	return scrsio_show(dev, attr, buf, LPC_SCR2SIO);
+}
+DEVICE_ATTR_RO(scr2sio);
+
+static ssize_t scr3sio_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	return scrsio_show(dev, attr, buf, LPC_SCR3SIO);
+}
+DEVICE_ATTR_RO(scr3sio);
+
+static struct attribute *sio_attrs[] = {
+	&dev_attr_scr0sio.attr,
+	&dev_attr_scr1sio.attr,
+	&dev_attr_scr2sio.attr,
+	&dev_attr_scr3sio.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(sio);
+
+static const struct attribute_group sio_attr_group = {
+	.attrs = sio_attrs,
+};
+
+static int __init aspeed_scrsio_probe(struct platform_device *pdev)
+{
+	struct aspeed_scrsio *scrsio;
+	struct resource *res;
+
+	scrsio = devm_kzalloc(&pdev->dev, sizeof(*scrsio), GFP_KERNEL);
+	if (!scrsio)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	scrsio->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(scrsio->base))
+		return PTR_ERR(scrsio->base);
+
+	dev_set_drvdata(&pdev->dev, scrsio);
+
+	return sysfs_create_groups(&pdev->dev.kobj, sio_groups);
+};
+
+static const struct of_device_id aspeed_scrsio_of_match[] = {
+	{ .compatible = "aspeed,ast2400-scrsio"},
+	{ .compatible = "aspeed,ast2500-scrsio"},
+};
+
+static struct platform_driver aspeed_scrsio_driver = {
+	.driver = {
+		.name = "aspeed_scrsio",
+		.of_match_table = aspeed_scrsio_of_match,
+	},
+};
+module_platform_driver_probe(aspeed_scrsio_driver, aspeed_scrsio_probe);
+
+MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Aspeed SuperIO scratch registers");
-- 
2.9.3

[PATCH linux dev-4.7 2/4] misc: Add partial Aspeed LPC Host Interface Control (HIC) driver

[Andrew Jeffery]

Exposes some of the LPC controller's host interface control registers in
sysfs, specifically HICR5-HICR8, HICR9-HICRA.  At the moment the
resource range also covers the SNPWADR and SNPWDR (LPC Snoop registers),
but they are not exposed in sysfs.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/misc/Kconfig      |   7 ++
 drivers/misc/Makefile     |   1 +
 drivers/misc/aspeed-hic.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 206 insertions(+)
 create mode 100644 drivers/misc/aspeed-hic.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 27327f44a709..1c5b9b2b26aa 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -58,6 +58,13 @@ config ASPEED_SCRSIO
 	  Select this if you wish to expose to userspace the SuperIO scratch
 	  registers in the LPC control space on an Aspeed BMC SoC.
 
+config ASPEED_HIC
+	bool "Support for Aspeed LPC Host Interface Control Registers"
+	depends on ARCH_ASPEED || COMPILE_TEST
+	help
+	  Select this if you wish to expose to userspace the LPC Host Interface
+	  Control Registers on an Aspeed BMC SoC.
+
 config ATMEL_TCLIB
 	bool "Atmel AT32/AT91 Timer/Counter Library"
 	depends on (AVR32 || ARCH_AT91)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 0bcd6ff61a12..b49051932471 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_IBM_ASM)		+= ibmasm/
 obj-$(CONFIG_AD525X_DPOT)	+= ad525x_dpot.o
 obj-$(CONFIG_AD525X_DPOT_I2C)	+= ad525x_dpot-i2c.o
 obj-$(CONFIG_AD525X_DPOT_SPI)	+= ad525x_dpot-spi.o
+obj-$(CONFIG_ASPEED_HIC)	+= aspeed-hic.o
 obj-$(CONFIG_ASPEED_SCRSIO)	+= aspeed-scrsio.o
 obj-$(CONFIG_INTEL_MID_PTI)	+= pti.o
 obj-$(CONFIG_ATMEL_SSC)		+= atmel-ssc.o
diff --git a/drivers/misc/aspeed-hic.c b/drivers/misc/aspeed-hic.c
new file mode 100644
index 000000000000..d26b9daab126
--- /dev/null
+++ b/drivers/misc/aspeed-hic.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright 2016 IBM Corporation
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#define LPC_HICR5		0x0
+#define LPC_HICR6		0x4
+#define LPC_HICR7		0x8
+#define LPC_HICR8		0xc
+#define LPC_HICR9		0x18
+#define LPC_HICRA		0x1c
+
+struct aspeed_hic {
+	void __iomem *hicr5;
+};
+
+static ssize_t hic_store(void __iomem *base, int reg, const char *buf,
+		size_t len)
+{
+	int r;
+	u32 value;
+
+	r = kstrtou32(buf, 0, &value);
+	if (r)
+		return r;
+
+	iowrite32(value, base + reg);
+
+	return len;
+}
+
+ssize_t hic_show(void __iomem *base, int reg, char *buf)
+{
+	u32 value = ioread32(base + reg);
+
+	return scnprintf(buf, PAGE_SIZE, "0x%08x\n", value);
+}
+
+static ssize_t hicr5_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t len)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_store(hic->hicr5, LPC_HICR5, buf, len);
+}
+
+static ssize_t hicr5_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_show(hic->hicr5, LPC_HICR5, buf);
+}
+DEVICE_ATTR_RW(hicr5);
+
+static ssize_t hicr6_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t len)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_store(hic->hicr5, LPC_HICR6, buf, len);
+}
+
+static ssize_t hicr6_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_show(hic->hicr5, LPC_HICR6, buf);
+}
+DEVICE_ATTR_RW(hicr6);
+
+static ssize_t hicr7_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t len)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_store(hic->hicr5, LPC_HICR7, buf, len);
+}
+
+static ssize_t hicr7_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_show(hic->hicr5, LPC_HICR7, buf);
+}
+DEVICE_ATTR_RW(hicr7);
+
+static ssize_t hicr8_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t len)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_store(hic->hicr5, LPC_HICR8, buf, len);
+}
+
+static ssize_t hicr8_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_show(hic->hicr5, LPC_HICR8, buf);
+}
+DEVICE_ATTR_RW(hicr8);
+
+static ssize_t hicr9_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t len)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_store(hic->hicr5, LPC_HICR9, buf, len);
+}
+
+static ssize_t hicr9_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_show(hic->hicr5, LPC_HICR9, buf);
+}
+DEVICE_ATTR_RW(hicr9);
+
+static ssize_t hicra_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t len)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_store(hic->hicr5, LPC_HICRA, buf, len);
+}
+
+static ssize_t hicra_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	struct aspeed_hic *hic = dev_get_drvdata(dev);
+
+	return hic_show(hic->hicr5, LPC_HICRA, buf);
+}
+DEVICE_ATTR_RW(hicra);
+
+static struct attribute *hic_attrs[] = {
+	&dev_attr_hicr5.attr,
+	&dev_attr_hicr6.attr,
+	&dev_attr_hicr7.attr,
+	&dev_attr_hicr8.attr,
+	&dev_attr_hicr9.attr,
+	&dev_attr_hicra.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(hic);
+
+static int __init aspeed_hic_probe(struct platform_device *pdev)
+{
+	struct aspeed_hic *hic;
+	struct resource *res;
+
+	hic = devm_kzalloc(&pdev->dev, sizeof(*hic), GFP_KERNEL);
+	if (!hic)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hic->hicr5 = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(hic->hicr5))
+		return PTR_ERR(hic->hicr5);
+
+	dev_set_drvdata(&pdev->dev, hic);
+
+	return sysfs_create_groups(&pdev->dev.kobj, hic_groups);
+}
+
+static const struct of_device_id aspeed_hic_of_match[] = {
+	{ .compatible = "aspeed,ast2400-hic"},
+	{ .compatible = "aspeed,ast2500-hic"},
+};
+
+static struct platform_driver aspeed_hic_driver = {
+	.driver = {
+		.name = "aspeed_hic",
+		.of_match_table = aspeed_hic_of_match,
+	},
+};
+module_platform_driver_probe(aspeed_hic_driver, aspeed_hic_probe);
+
+MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Aspeed LPC Host Interface Controller");
-- 
2.9.3

[PATCH linux dev-4.7 3/4] arm: aspeed: dt: Add SuperIO scratch register nodes

[Andrew Jeffery]

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++++
 arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 68eadec4ab34..1ee9e87aa5b2 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -857,6 +857,11 @@
 				clocks = <&clk_apb>;
 			};
 
+			scrsio: scrsio@1e789170 {
+				compatible = "aspeed,ast2400-scrsio";
+				reg = <0x1e789170 0x10>;
+			};
+
 			ibt: ibt@1e789140 {
 				compatible = "aspeed,bt-host";
 				reg = <0x1e789140 0x18>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d72aea7ab8f2..505f4878d9af 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -991,6 +991,11 @@
 				clocks = <&clk_apb>;
 			};
 
+			scrsio: scrsio@1e789170 {
+				compatible = "aspeed,ast2500-scrsio";
+				reg = <0x1e789170 0x10>;
+			};
+
 			ibt: ibt@1e789140 {
 				compatible = "aspeed,bt-host";
 				reg = <0x1e789140 0x18>;
-- 
2.9.3

[PATCH linux dev-4.7 4/4] arm: aspeed: dt: Add LPC Host Interface Controller nodes

[Andrew Jeffery]

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++++
 arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 1ee9e87aa5b2..85669dc64433 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -857,6 +857,11 @@
 				clocks = <&clk_apb>;
 			};
 
+			hic: hic@1e789080 {
+				compatible = "aspeed,ast2400-hic";
+				reg = <0x1e789080 0x20>;
+			};
+
 			scrsio: scrsio@1e789170 {
 				compatible = "aspeed,ast2400-scrsio";
 				reg = <0x1e789170 0x10>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 505f4878d9af..2aed7492788d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -991,6 +991,11 @@
 				clocks = <&clk_apb>;
 			};
 
+			hic: hic@1e789080 {
+				compatible = "aspeed,ast2500-hic";
+				reg = <0x1e789080 0x10>;
+			};
+
 			scrsio: scrsio@1e789170 {
 				compatible = "aspeed,ast2500-scrsio";
 				reg = <0x1e789170 0x10>;
-- 
2.9.3

Re: [PATCH linux dev-4.7 0/4] SuperIO and Host Interface Controllers

[Xo Wang]

Hi folks,

On Wed, Nov 9, 2016 at 5:35 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> Hello,
>
> This series adds some sysfs drivers exposing parts of the LPC controller. The
> patches are pretty bare-bones in that they provide zero sanity checking and
> leave decisions entirely to userspace. They're also slightly tedious, so I
> expect (hope) their current form will be short-lived.
>
> Cheers,
>
> Andrew
>
> Andrew Jeffery (4):
>   misc: Expose Aspeed SuperIO scratch registers (SCRxSIO)
>   misc: Add partial Aspeed LPC Host Interface Control (HIC) driver
>   arm: aspeed: dt: Add SuperIO scratch register nodes
>   arm: aspeed: dt: Add LPC Host Interface Controller nodes
>
>  arch/arm/boot/dts/aspeed-g4.dtsi |  10 ++
>  arch/arm/boot/dts/aspeed-g5.dtsi |  10 ++
>  drivers/misc/Kconfig             |  14 +++
>  drivers/misc/Makefile            |   2 +
>  drivers/misc/aspeed-hic.c        | 198 +++++++++++++++++++++++++++++++++++++++
>  drivers/misc/aspeed-scrsio.c     | 141 ++++++++++++++++++++++++++++
>  6 files changed, 375 insertions(+)
>  create mode 100644 drivers/misc/aspeed-hic.c
>  create mode 100644 drivers/misc/aspeed-scrsio.c
>
> --
> 2.9.3
>
> _______________________________________________
> openbmc mailing list
> openbmc@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/openbmc

I noticed that this driver wasn't merged. Was there a change of plan
to how LPC controller functionality should be exported?

This is still useful for us to set up memboot and to listen for port
80 post codes.

cheers
xo

Re: [PATCH linux dev-4.7 0/4] SuperIO and Host Interface Controllers

[Andrew Jeffery]

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Hi Xo,

On Mon, 2017-01-09 at 15:11 -0800, Xo Wang wrote:
> Hi folks,
> 
> > On Wed, Nov 9, 2016 at 5:35 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> > Hello,
> > 
> > This series adds some sysfs drivers exposing parts of the LPC controller. The
> > patches are pretty bare-bones in that they provide zero sanity checking and
> > leave decisions entirely to userspace. They're also slightly tedious, so I
> > expect (hope) their current form will be short-lived.
> > 
> > Cheers,
> > 
> > Andrew
> > 
> > Andrew Jeffery (4):
> >   misc: Expose Aspeed SuperIO scratch registers (SCRxSIO)
> >   misc: Add partial Aspeed LPC Host Interface Control (HIC) driver
> >   arm: aspeed: dt: Add SuperIO scratch register nodes
> >   arm: aspeed: dt: Add LPC Host Interface Controller nodes
> > 
> >  arch/arm/boot/dts/aspeed-g4.dtsi |  10 ++
> >  arch/arm/boot/dts/aspeed-g5.dtsi |  10 ++
> >  drivers/misc/Kconfig             |  14 +++
> >  drivers/misc/Makefile            |   2 +
> >  drivers/misc/aspeed-hic.c        | 198 +++++++++++++++++++++++++++++++++++++++
> >  drivers/misc/aspeed-scrsio.c     | 141 ++++++++++++++++++++++++++++
> >  6 files changed, 375 insertions(+)
> >  create mode 100644 drivers/misc/aspeed-hic.c
> >  create mode 100644 drivers/misc/aspeed-scrsio.c
> > 
> > --
> > 2.9.3
> > 
> > _______________________________________________
> > openbmc mailing list
> > openbmc@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/openbmc
> 
> I noticed that this driver wasn't merged. Was there a change of plan
> to how LPC controller functionality should be exported?
> 
> This is still useful for us to set up memboot and to listen for port
> 80 post codes.

Cyril has reworked the HICR parts of the memboot function here:

https://lists.ozlabs.org/pipermail/openbmc/2016-December/006089.html

It would be good to get your feedback the approach. Cyril is going to
send out another revision shortly and will Cc you.

As for the post codes these patches didn't expose the PCCRs in sysfs -
have you modified them?

Regardless, given Cyril now has a better approach for the LPC Host
Interface Controller we should probably rethink the approach for
SuperIO scratch registers and PCCRs. These patches were always just
hacks and Joel had to pushed me to send them out.

Andrew

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Re: [PATCH linux dev-4.7 0/4] SuperIO and Host Interface Controllers

[Xo Wang]

Hi Andrew,

On Mon, Jan 9, 2017 at 4:03 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> Hi Xo,
>
> On Mon, 2017-01-09 at 15:11 -0800, Xo Wang wrote:
>> Hi folks,
>>
>> > On Wed, Nov 9, 2016 at 5:35 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
>> > Hello,
>> >
>> > This series adds some sysfs drivers exposing parts of the LPC controller. The
>> > patches are pretty bare-bones in that they provide zero sanity checking and
>> > leave decisions entirely to userspace. They're also slightly tedious, so I
>> > expect (hope) their current form will be short-lived.
>> >
>> > Cheers,
>> >
>> > Andrew
>> >
>> > Andrew Jeffery (4):
>> >   misc: Expose Aspeed SuperIO scratch registers (SCRxSIO)
>> >   misc: Add partial Aspeed LPC Host Interface Control (HIC) driver
>> >   arm: aspeed: dt: Add SuperIO scratch register nodes
>> >   arm: aspeed: dt: Add LPC Host Interface Controller nodes
>> >
>> >  arch/arm/boot/dts/aspeed-g4.dtsi |  10 ++
>> >  arch/arm/boot/dts/aspeed-g5.dtsi |  10 ++
>> >  drivers/misc/Kconfig             |  14 +++
>> >  drivers/misc/Makefile            |   2 +
>> >  drivers/misc/aspeed-hic.c        | 198 +++++++++++++++++++++++++++++++++++++++
>> >  drivers/misc/aspeed-scrsio.c     | 141 ++++++++++++++++++++++++++++
>> >  6 files changed, 375 insertions(+)
>> >  create mode 100644 drivers/misc/aspeed-hic.c
>> >  create mode 100644 drivers/misc/aspeed-scrsio.c
>> >
>> > --
>> > 2.9.3
>> >
>> > _______________________________________________
>> > openbmc mailing list
>> > openbmc@lists.ozlabs.org
>> > https://lists.ozlabs.org/listinfo/openbmc
>>
>> I noticed that this driver wasn't merged. Was there a change of plan
>> to how LPC controller functionality should be exported?
>>
>> This is still useful for us to set up memboot and to listen for port
>> 80 post codes.
>
> Cyril has reworked the HICR parts of the memboot function here:
>
> https://lists.ozlabs.org/pipermail/openbmc/2016-December/006089.html
>
> It would be good to get your feedback the approach. Cyril is going to
> send out another revision shortly and will Cc you.
>
> As for the post codes these patches didn't expose the PCCRs in sysfs -
> have you modified them?

We don't have code that touch PCCRs. I was waiting to see how these
drivers would go and discuss with Jagha how she would like to
implement that part of her POST code work.

>
> Regardless, given Cyril now has a better approach for the LPC Host
> Interface Controller we should probably rethink the approach for
> SuperIO scratch registers and PCCRs. These patches were always just
> hacks and Joel had to pushed me to send them out.
>
> Andrew

cheers
xo