From: Sam Protsenko <semen.protsenko@linaro.org> To: David Virag <virag.david003@gmail.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, Rob Herring <robh+dt@kernel.org>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, Chanwoo Choi <cw00.choi@samsung.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 5/7] clk: samsung: clk-pll: Add support for pll1417x Date: Tue, 7 Dec 2021 21:00:44 +0200 [thread overview] Message-ID: <CAPLW+4kSDHUsvHo0njykTTRGqaAehRt6MXdJF73OzR47avOm9Q@mail.gmail.com> (raw) In-Reply-To: <20211206153124.427102-6-virag.david003@gmail.com> On Mon, 6 Dec 2021 at 17:32, David Virag <virag.david003@gmail.com> wrote: > > pll1417x is used in Exynos7885 SoC for top-level integer PLLs. > It is similar enough to pll0822x that practically the same code can > handle both. The difference that's to be noted is that when defining a > pl1417x PLL, the "con" parameter of the PLL macro should be set to the > CON1 register instead of CON3, like this: > > PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", > PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, > NULL), > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > Signed-off-by: David Virag <virag.david003@gmail.com> > --- > Changes in v2: > - Nothing > > Changes in v3: > - Nothing > > Changes in v4: > - Added R-b tag by Krzysztof Kozlowski > > drivers/clk/samsung/clk-pll.c | 1 + > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index 83d1b03647db..70cdc87f714e 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, > else > init.ops = &samsung_pll35xx_clk_ops; > break; > + case pll_1417x: I wonder why this switch have a bunch of fall through cases, but none marked with "fallthrough;" line, and both checkpatch and "make" turn blind eye on that? Anyway, I guess it's ok as is, just an observation. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > case pll_0822x: > pll->enable_offs = PLL0822X_ENABLE_SHIFT; > pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; > diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h > index a739f2b7ae80..c83a20195f6d 100644 > --- a/drivers/clk/samsung/clk-pll.h > +++ b/drivers/clk/samsung/clk-pll.h > @@ -32,6 +32,7 @@ enum samsung_pll_type { > pll_2550xx, > pll_2650x, > pll_2650xx, > + pll_1417x, > pll_1450x, > pll_1451x, > pll_1452x, > -- > 2.34.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Sam Protsenko <semen.protsenko@linaro.org> To: David Virag <virag.david003@gmail.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, Rob Herring <robh+dt@kernel.org>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, Chanwoo Choi <cw00.choi@samsung.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 5/7] clk: samsung: clk-pll: Add support for pll1417x Date: Tue, 7 Dec 2021 21:00:44 +0200 [thread overview] Message-ID: <CAPLW+4kSDHUsvHo0njykTTRGqaAehRt6MXdJF73OzR47avOm9Q@mail.gmail.com> (raw) In-Reply-To: <20211206153124.427102-6-virag.david003@gmail.com> On Mon, 6 Dec 2021 at 17:32, David Virag <virag.david003@gmail.com> wrote: > > pll1417x is used in Exynos7885 SoC for top-level integer PLLs. > It is similar enough to pll0822x that practically the same code can > handle both. The difference that's to be noted is that when defining a > pl1417x PLL, the "con" parameter of the PLL macro should be set to the > CON1 register instead of CON3, like this: > > PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", > PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, > NULL), > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > Signed-off-by: David Virag <virag.david003@gmail.com> > --- > Changes in v2: > - Nothing > > Changes in v3: > - Nothing > > Changes in v4: > - Added R-b tag by Krzysztof Kozlowski > > drivers/clk/samsung/clk-pll.c | 1 + > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index 83d1b03647db..70cdc87f714e 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, > else > init.ops = &samsung_pll35xx_clk_ops; > break; > + case pll_1417x: I wonder why this switch have a bunch of fall through cases, but none marked with "fallthrough;" line, and both checkpatch and "make" turn blind eye on that? Anyway, I guess it's ok as is, just an observation. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > case pll_0822x: > pll->enable_offs = PLL0822X_ENABLE_SHIFT; > pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; > diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h > index a739f2b7ae80..c83a20195f6d 100644 > --- a/drivers/clk/samsung/clk-pll.h > +++ b/drivers/clk/samsung/clk-pll.h > @@ -32,6 +32,7 @@ enum samsung_pll_type { > pll_2550xx, > pll_2650x, > pll_2650xx, > + pll_1417x, > pll_1450x, > pll_1451x, > pll_1452x, > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-12-07 19:01 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-06 15:31 [PATCH v4 0/7] Initial Samsung Galaxy A8 (2018) support David Virag 2021-12-06 15:31 ` David Virag 2021-12-06 15:31 ` [PATCH v4 1/7] dt-bindings: clock: Add bindings definitions for Exynos7885 CMU David Virag 2021-12-06 15:31 ` David Virag 2021-12-07 18:15 ` Sam Protsenko 2021-12-07 18:15 ` Sam Protsenko 2021-12-10 21:26 ` Rob Herring 2021-12-10 21:26 ` Rob Herring 2021-12-12 18:39 ` Krzysztof Kozlowski 2021-12-12 18:39 ` Krzysztof Kozlowski 2021-12-20 9:40 ` Krzysztof Kozlowski 2021-12-20 9:40 ` Krzysztof Kozlowski 2021-12-19 22:52 ` Sylwester Nawrocki 2021-12-19 22:52 ` Sylwester Nawrocki 2021-12-06 15:31 ` [PATCH v4 2/7] dt-bindings: clock: Document Exynos7885 CMU bindings David Virag 2021-12-06 15:31 ` David Virag 2021-12-07 18:23 ` Sam Protsenko 2021-12-07 18:23 ` Sam Protsenko 2021-12-10 21:28 ` Rob Herring 2021-12-10 21:28 ` Rob Herring 2021-12-06 15:31 ` [PATCH v4 3/7] dt-bindings: arm: samsung: document jackpotlte board binding David Virag 2021-12-06 15:31 ` David Virag 2021-12-07 18:26 ` Sam Protsenko 2021-12-07 18:26 ` Sam Protsenko 2021-12-10 21:30 ` Rob Herring 2021-12-10 21:30 ` Rob Herring 2021-12-15 16:21 ` (subset) " Krzysztof Kozlowski 2021-12-15 16:21 ` Krzysztof Kozlowski 2021-12-19 14:53 ` David Virag 2021-12-19 14:53 ` David Virag 2021-12-20 9:38 ` Krzysztof Kozlowski 2021-12-20 9:38 ` Krzysztof Kozlowski 2021-12-06 15:31 ` [PATCH v4 4/7] clk: samsung: Make exynos850_register_cmu shared David Virag 2021-12-06 15:31 ` David Virag 2021-12-07 9:32 ` Krzysztof Kozlowski 2021-12-07 9:32 ` Krzysztof Kozlowski 2021-12-07 18:53 ` Sam Protsenko 2021-12-07 18:53 ` Sam Protsenko 2021-12-06 15:31 ` [PATCH v4 5/7] clk: samsung: clk-pll: Add support for pll1417x David Virag 2021-12-06 15:31 ` David Virag 2021-12-07 19:00 ` Sam Protsenko [this message] 2021-12-07 19:00 ` Sam Protsenko 2021-12-08 8:50 ` Krzysztof Kozlowski 2021-12-08 8:50 ` Krzysztof Kozlowski 2021-12-06 15:31 ` [PATCH v4 6/7] clk: samsung: Add initial Exynos7885 clock driver David Virag 2021-12-06 15:31 ` David Virag 2021-12-07 9:33 ` Krzysztof Kozlowski 2021-12-07 9:33 ` Krzysztof Kozlowski 2021-12-07 19:14 ` Sam Protsenko 2021-12-07 19:14 ` Sam Protsenko 2021-12-06 15:31 ` [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC David Virag 2021-12-06 15:31 ` David Virag 2021-12-07 9:39 ` Krzysztof Kozlowski 2021-12-07 9:39 ` Krzysztof Kozlowski 2021-12-07 19:42 ` Marc Zyngier 2021-12-07 19:42 ` Marc Zyngier 2021-12-19 14:36 ` David Virag 2021-12-19 14:36 ` David Virag 2021-12-20 8:44 ` Marc Zyngier 2021-12-20 8:44 ` Marc Zyngier 2021-12-07 20:19 ` Sam Protsenko 2021-12-07 20:19 ` Sam Protsenko 2021-12-07 22:29 ` David Virag 2021-12-07 22:29 ` David Virag 2021-12-08 0:55 ` Chanho Park 2021-12-08 0:55 ` Chanho Park 2021-12-08 9:05 ` Krzysztof Kozlowski 2021-12-08 9:05 ` Krzysztof Kozlowski 2021-12-08 15:37 ` Sam Protsenko 2021-12-08 15:37 ` Sam Protsenko 2021-12-08 16:28 ` Krzysztof Kozlowski 2021-12-08 16:28 ` Krzysztof Kozlowski 2021-12-08 16:51 ` Sam Protsenko 2021-12-08 16:51 ` Sam Protsenko 2022-01-31 15:35 ` Krzysztof Kozlowski 2022-01-31 15:35 ` Krzysztof Kozlowski 2022-02-01 0:47 ` David Virag 2022-02-01 0:47 ` David Virag
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