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From: Dan Williams <dan.j.williams@intel.com>
To: Yigal Korman <yigal@plexistor.com>
Cc: Mike Snitzer <msnitzer@redhat.com>,
	linux-nvdimm <linux-nvdimm@lists.01.org>, X86 ML <x86@kernel.org>,
	device-mapper development <dm-devel@redhat.com>,
	Ingo Molnar <mingo@redhat.com>,
	Mikulas Patocka <mpatocka@redhat.com>,
	pmem <pmem@googlegroups.com>
Subject: Re: [PATCH] x86: optimize memcpy_flushcache
Date: Wed, 27 Jun 2018 06:03:09 -0700	[thread overview]
Message-ID: <CAPcyv4hzfy0pvniMz4-PcaAXo6kFC=n4hyPzd=0v-JxCsUhMhQ@mail.gmail.com> (raw)
In-Reply-To: <CACTTzNbu5FNXiyDeSBgTZCE7x=aNKQWvMLnhy5rkE51JJV9Rzg@mail.gmail.com>

On Wed, Jun 27, 2018 at 4:23 AM, Yigal Korman <yigal@plexistor.com> wrote:
> Hi,
> I'm a bit late on this but I have a question about the original patch -
> I thought that in order for movnt (movntil, movntiq) to push the data
> into the persistency domain (ADR),
> one must work with length that is multiple of cacheline size,
> otherwise the write-combine buffers remain partially
> filled and you need to commit them with a fence (sfence) - which ruins
> the whole performance gain you got here.
> Am I wrong, are the write-combine buffers are part of the ADR domain
> or something?

The intent is to allow a batch of memcpy_flushcache() calls followed
by a single sfence. Specifying a multiple of a cacheline size does not
necessarily help as sfence is still needed to make sure that the movnt
result has reached the ADR-safe domain.
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WARNING: multiple messages have this Message-ID (diff)
From: Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
To: Yigal Korman <yigal-/8YdC2HfS5554TAoqtyWWQ@public.gmane.org>
Cc: Mike Snitzer <msnitzer-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	linux-nvdimm
	<linux-nvdimm-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org>,
	X86 ML <x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	device-mapper development
	<dm-devel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	Ingo Molnar <mingo-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	Mikulas Patocka
	<mpatocka-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	pmem <pmem-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>
Subject: Re: [PATCH] x86: optimize memcpy_flushcache
Date: Wed, 27 Jun 2018 06:03:09 -0700	[thread overview]
Message-ID: <CAPcyv4hzfy0pvniMz4-PcaAXo6kFC=n4hyPzd=0v-JxCsUhMhQ@mail.gmail.com> (raw)
In-Reply-To: <CACTTzNbu5FNXiyDeSBgTZCE7x=aNKQWvMLnhy5rkE51JJV9Rzg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

On Wed, Jun 27, 2018 at 4:23 AM, Yigal Korman <yigal-/8YdC2HfS5554TAoqtyWWQ@public.gmane.org> wrote:
> Hi,
> I'm a bit late on this but I have a question about the original patch -
> I thought that in order for movnt (movntil, movntiq) to push the data
> into the persistency domain (ADR),
> one must work with length that is multiple of cacheline size,
> otherwise the write-combine buffers remain partially
> filled and you need to commit them with a fence (sfence) - which ruins
> the whole performance gain you got here.
> Am I wrong, are the write-combine buffers are part of the ADR domain
> or something?

The intent is to allow a batch of memcpy_flushcache() calls followed
by a single sfence. Specifying a multiple of a cacheline size does not
necessarily help as sfence is still needed to make sure that the movnt
result has reached the ADR-safe domain.

  reply	other threads:[~2018-06-27 13:03 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-18 12:50 [PATCH] x86: optimize memcpy_flushcache Mikulas Patocka
2018-06-18 12:50 ` Mikulas Patocka
2018-06-18 13:17 ` Mike Snitzer
2018-06-18 13:17   ` Mike Snitzer
2018-06-18 16:38 ` [PATCH] " Dan Williams
2018-06-18 16:38   ` Dan Williams
2018-06-27 11:23   ` Yigal Korman
2018-06-27 11:23     ` Yigal Korman
2018-06-27 13:03     ` Dan Williams [this message]
2018-06-27 13:03       ` Dan Williams
2018-06-27 14:02       ` Yigal Korman
2018-06-27 14:02         ` Yigal Korman

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