* [PATCH 0/7] exynos: add basic support for exynos5260 SoC @ 2013-12-06 15:56 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-samsung-soc, devicetree, linux-arm-kernel Cc: mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open, Rahul Sharma add basic support for exynos5260 SoC. This series is based on linux-next, Kukjin's for-next and Mike's clk-for-linus-3.13 branches. This patch is dependent on the following series from Tomasz Figa <t.figa@samsung.com>: http://www.spinics.net/lists/arm-kernel/msg280223.html Arun Kumar K (1): ARM: dts: add dts files for exynos5260 SoC Pankaj Dubey (2): ARM: EXYNOS: initial board support for exynos5260 SoC clk/samsung: add support for pll2550xx Rahul Sharma (3): clk/samsung: add support for multuple clock providers clk/samsung: add support for pll2650xx clk/exynos5260: add clock file for exynos5260 Young-Gun Jang (1): pinctrl: exynos: add exynos5260 SoC specific data .../devicetree/bindings/clock/exynos5260-clock.txt | 228 ++ .../bindings/pinctrl/samsung-pinctrl.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 586 +++++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 85 + arch/arm/boot/dts/exynos5260.dtsi | 315 +++ arch/arm/mach-exynos/Kconfig | 9 + arch/arm/mach-exynos/common.c | 19 +- arch/arm/mach-exynos/cpuidle.c | 2 +- arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos4.c | 47 +- drivers/clk/samsung/clk-exynos5250.c | 26 +- drivers/clk/samsung/clk-exynos5260.c | 2661 ++++++++++++++++++++ drivers/clk/samsung/clk-exynos5260.h | 496 ++++ drivers/clk/samsung/clk-exynos5420.c | 24 +- drivers/clk/samsung/clk-exynos5440.c | 18 +- drivers/clk/samsung/clk-pll.c | 222 +- drivers/clk/samsung/clk-pll.h | 3 +- drivers/clk/samsung/clk-s3c64xx.c | 44 +- drivers/clk/samsung/clk.c | 110 +- drivers/clk/samsung/clk.h | 46 +- drivers/pinctrl/pinctrl-exynos.c | 82 + drivers/pinctrl/pinctrl-samsung.c | 2 + drivers/pinctrl/pinctrl-samsung.h | 1 + include/dt-bindings/clk/exynos5260-clk.h | 169 ++ 30 files changed, 5076 insertions(+), 137 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h create mode 100644 include/dt-bindings/clk/exynos5260-clk.h -- 1.7.9.5 ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 0/7] exynos: add basic support for exynos5260 SoC @ 2013-12-06 15:56 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-arm-kernel add basic support for exynos5260 SoC. This series is based on linux-next, Kukjin's for-next and Mike's clk-for-linus-3.13 branches. This patch is dependent on the following series from Tomasz Figa <t.figa@samsung.com>: http://www.spinics.net/lists/arm-kernel/msg280223.html Arun Kumar K (1): ARM: dts: add dts files for exynos5260 SoC Pankaj Dubey (2): ARM: EXYNOS: initial board support for exynos5260 SoC clk/samsung: add support for pll2550xx Rahul Sharma (3): clk/samsung: add support for multuple clock providers clk/samsung: add support for pll2650xx clk/exynos5260: add clock file for exynos5260 Young-Gun Jang (1): pinctrl: exynos: add exynos5260 SoC specific data .../devicetree/bindings/clock/exynos5260-clock.txt | 228 ++ .../bindings/pinctrl/samsung-pinctrl.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 586 +++++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 85 + arch/arm/boot/dts/exynos5260.dtsi | 315 +++ arch/arm/mach-exynos/Kconfig | 9 + arch/arm/mach-exynos/common.c | 19 +- arch/arm/mach-exynos/cpuidle.c | 2 +- arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos4.c | 47 +- drivers/clk/samsung/clk-exynos5250.c | 26 +- drivers/clk/samsung/clk-exynos5260.c | 2661 ++++++++++++++++++++ drivers/clk/samsung/clk-exynos5260.h | 496 ++++ drivers/clk/samsung/clk-exynos5420.c | 24 +- drivers/clk/samsung/clk-exynos5440.c | 18 +- drivers/clk/samsung/clk-pll.c | 222 +- drivers/clk/samsung/clk-pll.h | 3 +- drivers/clk/samsung/clk-s3c64xx.c | 44 +- drivers/clk/samsung/clk.c | 110 +- drivers/clk/samsung/clk.h | 46 +- drivers/pinctrl/pinctrl-exynos.c | 82 + drivers/pinctrl/pinctrl-samsung.c | 2 + drivers/pinctrl/pinctrl-samsung.h | 1 + include/dt-bindings/clk/exynos5260-clk.h | 169 ++ 30 files changed, 5076 insertions(+), 137 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h create mode 100644 include/dt-bindings/clk/exynos5260-clk.h -- 1.7.9.5 ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-06 15:56 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-samsung-soc, devicetree, linux-arm-kernel Cc: mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open From: Pankaj Dubey <pankaj.dubey@samsung.com> This patch add basic arch side support for exynos5260 SoC. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> --- arch/arm/mach-exynos/Kconfig | 9 +++++++++ arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++- arch/arm/mach-exynos/cpuidle.c | 2 +- arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++ arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++ arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + 8 files changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f9d67a0..dcae2ec 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -93,6 +93,15 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5260 + bool "SAMSUNG EXYNOS5260" + default y + depends on ARCH_EXYNOS5 + select AUTO_ZRELADDR + select SAMSUNG_DMADEV + help + Enable EXYNOS5260 SoC support + config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 61d2906..5eb77d1 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; static const char name_exynos4412[] = "EXYNOS4412"; static const char name_exynos5250[] = "EXYNOS5250"; +static const char name_exynos5260[] = "EXYNOS5260"; static const char name_exynos5420[] = "EXYNOS5420"; static const char name_exynos5440[] = "EXYNOS5440"; @@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = { .init = exynos_init, .name = name_exynos5250, }, { + .idcode = EXYNOS5260_SOC_ID, + .idmask = EXYNOS5_SOC_MASK, + .map_io = exynos5_map_io, + .init = exynos_init, + .name = name_exynos5260, + }, { .idcode = EXYNOS5420_SOC_ID, .idmask = EXYNOS5_SOC_MASK, .map_io = exynos5_map_io, @@ -263,6 +270,15 @@ static struct map_desc exynos5_iodesc[] __initdata = { }, }; +static struct map_desc exynos5260_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + void exynos4_restart(enum reboot_mode mode, const char *cmd) { __raw_writel(0x1, S5P_SWRESET); @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void) static void __init exynos5_map_io(void) { iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); - + if (soc_is_exynos5260()) + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc)); if (soc_is_exynos5250()) iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); } diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index ddbfe87..405c11a 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, cpu_suspend(0, idle_finisher); #ifdef CONFIG_SMP - if (!soc_is_exynos5250()) + if (!soc_is_exynos5250() || soc_is_exynos5260()) scu_enable(S5P_VA_SCU); #endif cpu_pm_exit(); diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 7b046b5..bd6fa02 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -29,6 +29,7 @@ #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000 #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000 #define EXYNOS_PA_CHIPID 0x10000000 diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 2cdb63e..09ae29a 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -234,6 +234,10 @@ #define EXYNOS5_SYS_WDTRESET (1 << 20) +#define EXYNOS5260_A7_WDTRST (1 << 24) +#define EXYNOS5260_A15_WDTRST (1 << 23) +#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST) + #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 1fe075a..d23cdc3 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void) static char const *exynos5_dt_compat[] __initdata = { "samsung,exynos5250", + "samsung,exynos5260", "samsung,exynos5420", "samsung,exynos5440", NULL diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 335beb3..60687aa 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id; #define EXYNOS4_CPU_MASK 0xFFFE0000 #define EXYNOS5250_SOC_ID 0x43520000 +#define EXYNOS5260_SOC_ID 0xE5260000 #define EXYNOS5420_SOC_ID 0xE5420000 #define EXYNOS5440_SOC_ID 0xE5440000 #define EXYNOS5_SOC_MASK 0xFFFFF000 @@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) @@ -148,6 +150,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5260) +# define soc_is_exynos5260() is_samsung_exynos5260() +#else +# define soc_is_exynos5260() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h index c186786..804597c 100644 --- a/arch/arm/plat-samsung/include/plat/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h @@ -23,6 +23,7 @@ #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) + #define S5P_VA_DMC0 S3C_ADDR(0x02440000) #define S5P_VA_DMC1 S3C_ADDR(0x02480000) #define S5P_VA_SROMC S3C_ADDR(0x024C0000) -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC @ 2013-12-06 15:56 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-arm-kernel From: Pankaj Dubey <pankaj.dubey@samsung.com> This patch add basic arch side support for exynos5260 SoC. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> --- arch/arm/mach-exynos/Kconfig | 9 +++++++++ arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++- arch/arm/mach-exynos/cpuidle.c | 2 +- arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++ arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++ arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + 8 files changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f9d67a0..dcae2ec 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -93,6 +93,15 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5260 + bool "SAMSUNG EXYNOS5260" + default y + depends on ARCH_EXYNOS5 + select AUTO_ZRELADDR + select SAMSUNG_DMADEV + help + Enable EXYNOS5260 SoC support + config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 61d2906..5eb77d1 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; static const char name_exynos4412[] = "EXYNOS4412"; static const char name_exynos5250[] = "EXYNOS5250"; +static const char name_exynos5260[] = "EXYNOS5260"; static const char name_exynos5420[] = "EXYNOS5420"; static const char name_exynos5440[] = "EXYNOS5440"; @@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = { .init = exynos_init, .name = name_exynos5250, }, { + .idcode = EXYNOS5260_SOC_ID, + .idmask = EXYNOS5_SOC_MASK, + .map_io = exynos5_map_io, + .init = exynos_init, + .name = name_exynos5260, + }, { .idcode = EXYNOS5420_SOC_ID, .idmask = EXYNOS5_SOC_MASK, .map_io = exynos5_map_io, @@ -263,6 +270,15 @@ static struct map_desc exynos5_iodesc[] __initdata = { }, }; +static struct map_desc exynos5260_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + void exynos4_restart(enum reboot_mode mode, const char *cmd) { __raw_writel(0x1, S5P_SWRESET); @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void) static void __init exynos5_map_io(void) { iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); - + if (soc_is_exynos5260()) + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc)); if (soc_is_exynos5250()) iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); } diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index ddbfe87..405c11a 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, cpu_suspend(0, idle_finisher); #ifdef CONFIG_SMP - if (!soc_is_exynos5250()) + if (!soc_is_exynos5250() || soc_is_exynos5260()) scu_enable(S5P_VA_SCU); #endif cpu_pm_exit(); diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 7b046b5..bd6fa02 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -29,6 +29,7 @@ #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000 #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000 #define EXYNOS_PA_CHIPID 0x10000000 diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 2cdb63e..09ae29a 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -234,6 +234,10 @@ #define EXYNOS5_SYS_WDTRESET (1 << 20) +#define EXYNOS5260_A7_WDTRST (1 << 24) +#define EXYNOS5260_A15_WDTRST (1 << 23) +#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST) + #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 1fe075a..d23cdc3 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void) static char const *exynos5_dt_compat[] __initdata = { "samsung,exynos5250", + "samsung,exynos5260", "samsung,exynos5420", "samsung,exynos5440", NULL diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 335beb3..60687aa 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id; #define EXYNOS4_CPU_MASK 0xFFFE0000 #define EXYNOS5250_SOC_ID 0x43520000 +#define EXYNOS5260_SOC_ID 0xE5260000 #define EXYNOS5420_SOC_ID 0xE5420000 #define EXYNOS5440_SOC_ID 0xE5440000 #define EXYNOS5_SOC_MASK 0xFFFFF000 @@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) @@ -148,6 +150,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5260) +# define soc_is_exynos5260() is_samsung_exynos5260() +#else +# define soc_is_exynos5260() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h index c186786..804597c 100644 --- a/arch/arm/plat-samsung/include/plat/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h @@ -23,6 +23,7 @@ #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) + #define S5P_VA_DMC0 S3C_ADDR(0x02440000) #define S5P_VA_DMC1 S3C_ADDR(0x02480000) #define S5P_VA_SROMC S3C_ADDR(0x024C0000) -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* Re: [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-09 6:23 ` Sachin Kamat -1 siblings, 0 replies; 57+ messages in thread From: Sachin Kamat @ 2013-12-09 6:23 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar, Rahul Sharma Hi Rahul, On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > This patch add basic arch side support for exynos5260 SoC. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Since you are posting the patch, your signed off is also required. [snip] > void exynos4_restart(enum reboot_mode mode, const char *cmd) > { > __raw_writel(0x1, S5P_SWRESET); > @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void) > static void __init exynos5_map_io(void) > { > iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); > - > + if (soc_is_exynos5260()) > + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc)); Add this after 5250 to maintain numerical order. > if (soc_is_exynos5250()) > iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); > } [snip] > > #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) > #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) > + Unnecessary blank line addition. -- With warm regards, Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC @ 2013-12-09 6:23 ` Sachin Kamat 0 siblings, 0 replies; 57+ messages in thread From: Sachin Kamat @ 2013-12-09 6:23 UTC (permalink / raw) To: linux-arm-kernel Hi Rahul, On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > This patch add basic arch side support for exynos5260 SoC. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Since you are posting the patch, your signed off is also required. [snip] > void exynos4_restart(enum reboot_mode mode, const char *cmd) > { > __raw_writel(0x1, S5P_SWRESET); > @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void) > static void __init exynos5_map_io(void) > { > iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); > - > + if (soc_is_exynos5260()) > + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc)); Add this after 5250 to maintain numerical order. > if (soc_is_exynos5250()) > iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); > } [snip] > > #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) > #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) > + Unnecessary blank line addition. -- With warm regards, Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC 2013-12-09 6:23 ` Sachin Kamat @ 2013-12-09 6:33 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-09 6:33 UTC (permalink / raw) To: Sachin Kamat Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Thanks Sachin, On 9 December 2013 11:53, Sachin Kamat <sachin.kamat@linaro.org> wrote: > Hi Rahul, > > On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: >> From: Pankaj Dubey <pankaj.dubey@samsung.com> >> >> This patch add basic arch side support for exynos5260 SoC. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > > Since you are posting the patch, your signed off is also required. > > [snip] > >> void exynos4_restart(enum reboot_mode mode, const char *cmd) >> { >> __raw_writel(0x1, S5P_SWRESET); >> @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void) >> static void __init exynos5_map_io(void) >> { >> iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); >> - >> + if (soc_is_exynos5260()) >> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc)); > > Add this after 5250 to maintain numerical order. > >> if (soc_is_exynos5250()) >> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); >> } > > [snip] >> >> #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) >> #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) >> + > Unnecessary blank line addition. > I will correct all these in next version. Regards, Rahul Sharma > > -- > With warm regards, > Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC @ 2013-12-09 6:33 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-09 6:33 UTC (permalink / raw) To: linux-arm-kernel Thanks Sachin, On 9 December 2013 11:53, Sachin Kamat <sachin.kamat@linaro.org> wrote: > Hi Rahul, > > On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: >> From: Pankaj Dubey <pankaj.dubey@samsung.com> >> >> This patch add basic arch side support for exynos5260 SoC. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > > Since you are posting the patch, your signed off is also required. > > [snip] > >> void exynos4_restart(enum reboot_mode mode, const char *cmd) >> { >> __raw_writel(0x1, S5P_SWRESET); >> @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void) >> static void __init exynos5_map_io(void) >> { >> iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); >> - >> + if (soc_is_exynos5260()) >> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc)); > > Add this after 5250 to maintain numerical order. > >> if (soc_is_exynos5250()) >> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); >> } > > [snip] >> >> #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) >> #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) >> + > Unnecessary blank line addition. > I will correct all these in next version. Regards, Rahul Sharma > > -- > With warm regards, > Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
[parent not found: <CAK9yfHzX1+Rp3DCZiJSjE7VO6+TaDW7iqUZVpgRNkjVJofWauA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC 2013-12-09 6:23 ` Sachin Kamat @ 2013-12-23 4:39 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-23 4:39 UTC (permalink / raw) To: Sachin Kamat Cc: Rahul Sharma, linux-samsung-soc, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Thanks Sachin, On 9 December 2013 11:53, Sachin Kamat <sachin.kamat-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote: > Hi Rahul, > > On 6 December 2013 21:26, Rahul Sharma <rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote: >> From: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> >> >> This patch add basic arch side support for exynos5260 SoC. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> >> Signed-off-by: Arun Kumar K <arun.kk-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> > > Since you are posting the patch, your signed off is also required. Right. I will add my Sign off. > > [snip] > >> void exynos4_restart(enum reboot_mode mode, const char *cmd) >> { >> __raw_writel(0x1, S5P_SWRESET); >> @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void) >> static void __init exynos5_map_io(void) >> { >> iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); >> - >> + if (soc_is_exynos5260()) >> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc)); > > Add this after 5250 to maintain numerical order. ok. > >> if (soc_is_exynos5250()) >> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); >> } > > [snip] >> >> #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) >> #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) >> + > Unnecessary blank line addition. I will remove this. Regards, Rahul Sharma. > > > -- > With warm regards, > Sachin -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC @ 2013-12-23 4:39 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-23 4:39 UTC (permalink / raw) To: linux-arm-kernel Thanks Sachin, On 9 December 2013 11:53, Sachin Kamat <sachin.kamat@linaro.org> wrote: > Hi Rahul, > > On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: >> From: Pankaj Dubey <pankaj.dubey@samsung.com> >> >> This patch add basic arch side support for exynos5260 SoC. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > > Since you are posting the patch, your signed off is also required. Right. I will add my Sign off. > > [snip] > >> void exynos4_restart(enum reboot_mode mode, const char *cmd) >> { >> __raw_writel(0x1, S5P_SWRESET); >> @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void) >> static void __init exynos5_map_io(void) >> { >> iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); >> - >> + if (soc_is_exynos5260()) >> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc)); > > Add this after 5250 to maintain numerical order. ok. > >> if (soc_is_exynos5250()) >> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); >> } > > [snip] >> >> #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) >> #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) >> + > Unnecessary blank line addition. I will remove this. Regards, Rahul Sharma. > > > -- > With warm regards, > Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-10 15:57 ` Tomasz Figa -1 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-10 15:57 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open Hi Pankaj, Rahul, Arun, In addition to issues already pointed by Sachin, please also see my comments inline. On Friday 06 of December 2013 21:26:25 Rahul Sharma wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > This patch add basic arch side support for exynos5260 SoC. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > --- > arch/arm/mach-exynos/Kconfig | 9 +++++++++ > arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++- > arch/arm/mach-exynos/cpuidle.c | 2 +- > arch/arm/mach-exynos/include/mach/map.h | 1 + > arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++ > arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + > arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++ > arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + > 8 files changed, 43 insertions(+), 2 deletions(-) [snip] > diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c > index ddbfe87..405c11a 100644 > --- a/arch/arm/mach-exynos/cpuidle.c > +++ b/arch/arm/mach-exynos/cpuidle.c > @@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, > cpu_suspend(0, idle_finisher); > > #ifdef CONFIG_SMP > - if (!soc_is_exynos5250()) > + if (!soc_is_exynos5250() || soc_is_exynos5260()) The added OR condition doesn't affect the if condition in any way, because when running on Exynos5260, soc_is_exynos5250() will return false and make the whole condition evaluate to true. Shouldn't it be if (!soc_is_exynos5250() && !soc_is_exynos5260()) if Exynos5260 doesn't need scu_enable(), or left as is if it needs? > scu_enable(S5P_VA_SCU); > #endif > cpu_pm_exit(); > diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h > index 7b046b5..bd6fa02 100644 > --- a/arch/arm/mach-exynos/include/mach/map.h > +++ b/arch/arm/mach-exynos/include/mach/map.h > @@ -29,6 +29,7 @@ > #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000 > #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 > #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 > +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000 > > #define EXYNOS_PA_CHIPID 0x10000000 > > diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h > index 2cdb63e..09ae29a 100644 > --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h > +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h > @@ -234,6 +234,10 @@ > > #define EXYNOS5_SYS_WDTRESET (1 << 20) > > +#define EXYNOS5260_A7_WDTRST (1 << 24) > +#define EXYNOS5260_A15_WDTRST (1 << 23) > +#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST) > + Are these definitions needed? I don't see any user in this patch. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC @ 2013-12-10 15:57 ` Tomasz Figa 0 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-10 15:57 UTC (permalink / raw) To: linux-arm-kernel Hi Pankaj, Rahul, Arun, In addition to issues already pointed by Sachin, please also see my comments inline. On Friday 06 of December 2013 21:26:25 Rahul Sharma wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > This patch add basic arch side support for exynos5260 SoC. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > --- > arch/arm/mach-exynos/Kconfig | 9 +++++++++ > arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++- > arch/arm/mach-exynos/cpuidle.c | 2 +- > arch/arm/mach-exynos/include/mach/map.h | 1 + > arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++ > arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + > arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++ > arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + > 8 files changed, 43 insertions(+), 2 deletions(-) [snip] > diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c > index ddbfe87..405c11a 100644 > --- a/arch/arm/mach-exynos/cpuidle.c > +++ b/arch/arm/mach-exynos/cpuidle.c > @@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, > cpu_suspend(0, idle_finisher); > > #ifdef CONFIG_SMP > - if (!soc_is_exynos5250()) > + if (!soc_is_exynos5250() || soc_is_exynos5260()) The added OR condition doesn't affect the if condition in any way, because when running on Exynos5260, soc_is_exynos5250() will return false and make the whole condition evaluate to true. Shouldn't it be if (!soc_is_exynos5250() && !soc_is_exynos5260()) if Exynos5260 doesn't need scu_enable(), or left as is if it needs? > scu_enable(S5P_VA_SCU); > #endif > cpu_pm_exit(); > diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h > index 7b046b5..bd6fa02 100644 > --- a/arch/arm/mach-exynos/include/mach/map.h > +++ b/arch/arm/mach-exynos/include/mach/map.h > @@ -29,6 +29,7 @@ > #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000 > #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 > #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 > +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000 > > #define EXYNOS_PA_CHIPID 0x10000000 > > diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h > index 2cdb63e..09ae29a 100644 > --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h > +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h > @@ -234,6 +234,10 @@ > > #define EXYNOS5_SYS_WDTRESET (1 << 20) > > +#define EXYNOS5260_A7_WDTRST (1 << 24) > +#define EXYNOS5260_A15_WDTRST (1 << 23) > +#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST) > + Are these definitions needed? I don't see any user in this patch. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC 2013-12-10 15:57 ` Tomasz Figa @ 2014-01-03 9:24 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-03 9:24 UTC (permalink / raw) To: Tomasz Figa Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Hi Tomasz, Sorry for responding late. On 10 December 2013 21:27, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Pankaj, Rahul, Arun, > > In addition to issues already pointed by Sachin, please also see my > comments inline. > > On Friday 06 of December 2013 21:26:25 Rahul Sharma wrote: >> From: Pankaj Dubey <pankaj.dubey@samsung.com> >> >> This patch add basic arch side support for exynos5260 SoC. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> >> --- >> arch/arm/mach-exynos/Kconfig | 9 +++++++++ >> arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++- >> arch/arm/mach-exynos/cpuidle.c | 2 +- >> arch/arm/mach-exynos/include/mach/map.h | 1 + >> arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++ >> arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + >> arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++ >> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + >> 8 files changed, 43 insertions(+), 2 deletions(-) > [snip] >> diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c >> index ddbfe87..405c11a 100644 >> --- a/arch/arm/mach-exynos/cpuidle.c >> +++ b/arch/arm/mach-exynos/cpuidle.c >> @@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, >> cpu_suspend(0, idle_finisher); >> >> #ifdef CONFIG_SMP >> - if (!soc_is_exynos5250()) >> + if (!soc_is_exynos5250() || soc_is_exynos5260()) > > The added OR condition doesn't affect the if condition in any way, because > when running on Exynos5260, soc_is_exynos5250() will return false and make > the whole condition evaluate to true. > > Shouldn't it be > > if (!soc_is_exynos5250() && !soc_is_exynos5260()) > > if Exynos5260 doesn't need scu_enable(), or left as is if it needs? > Actually we don't need to call scu_enable() for 5260. Hence leaving it as it is. >> scu_enable(S5P_VA_SCU); >> #endif >> cpu_pm_exit(); >> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h >> index 7b046b5..bd6fa02 100644 >> --- a/arch/arm/mach-exynos/include/mach/map.h >> +++ b/arch/arm/mach-exynos/include/mach/map.h >> @@ -29,6 +29,7 @@ >> #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000 >> #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 >> #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 >> +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000 >> >> #define EXYNOS_PA_CHIPID 0x10000000 >> >> diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h >> index 2cdb63e..09ae29a 100644 >> --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h >> +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h >> @@ -234,6 +234,10 @@ >> >> #define EXYNOS5_SYS_WDTRESET (1 << 20) >> >> +#define EXYNOS5260_A7_WDTRST (1 << 24) >> +#define EXYNOS5260_A15_WDTRST (1 << 23) >> +#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST) >> + > > Are these definitions needed? I don't see any user in this patch. > Removed these definitions. Regards, Rahul Sharma. > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC @ 2014-01-03 9:24 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-03 9:24 UTC (permalink / raw) To: linux-arm-kernel Hi Tomasz, Sorry for responding late. On 10 December 2013 21:27, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Pankaj, Rahul, Arun, > > In addition to issues already pointed by Sachin, please also see my > comments inline. > > On Friday 06 of December 2013 21:26:25 Rahul Sharma wrote: >> From: Pankaj Dubey <pankaj.dubey@samsung.com> >> >> This patch add basic arch side support for exynos5260 SoC. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> >> --- >> arch/arm/mach-exynos/Kconfig | 9 +++++++++ >> arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++- >> arch/arm/mach-exynos/cpuidle.c | 2 +- >> arch/arm/mach-exynos/include/mach/map.h | 1 + >> arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++ >> arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + >> arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++ >> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + >> 8 files changed, 43 insertions(+), 2 deletions(-) > [snip] >> diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c >> index ddbfe87..405c11a 100644 >> --- a/arch/arm/mach-exynos/cpuidle.c >> +++ b/arch/arm/mach-exynos/cpuidle.c >> @@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, >> cpu_suspend(0, idle_finisher); >> >> #ifdef CONFIG_SMP >> - if (!soc_is_exynos5250()) >> + if (!soc_is_exynos5250() || soc_is_exynos5260()) > > The added OR condition doesn't affect the if condition in any way, because > when running on Exynos5260, soc_is_exynos5250() will return false and make > the whole condition evaluate to true. > > Shouldn't it be > > if (!soc_is_exynos5250() && !soc_is_exynos5260()) > > if Exynos5260 doesn't need scu_enable(), or left as is if it needs? > Actually we don't need to call scu_enable() for 5260. Hence leaving it as it is. >> scu_enable(S5P_VA_SCU); >> #endif >> cpu_pm_exit(); >> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h >> index 7b046b5..bd6fa02 100644 >> --- a/arch/arm/mach-exynos/include/mach/map.h >> +++ b/arch/arm/mach-exynos/include/mach/map.h >> @@ -29,6 +29,7 @@ >> #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000 >> #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 >> #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 >> +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000 >> >> #define EXYNOS_PA_CHIPID 0x10000000 >> >> diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h >> index 2cdb63e..09ae29a 100644 >> --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h >> +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h >> @@ -234,6 +234,10 @@ >> >> #define EXYNOS5_SYS_WDTRESET (1 << 20) >> >> +#define EXYNOS5260_A7_WDTRST (1 << 24) >> +#define EXYNOS5260_A15_WDTRST (1 << 23) >> +#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST) >> + > > Are these definitions needed? I don't see any user in this patch. > Removed these definitions. Regards, Rahul Sharma. > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-06 15:56 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-samsung-soc, devicetree, linux-arm-kernel Cc: mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open, Rahul Sharma From: Young-Gun Jang <yg1004.jang@samsung.com> Add Samsung Exynos5260 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5260. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> --- .../bindings/pinctrl/samsung-pinctrl.txt | 1 + drivers/pinctrl/pinctrl-exynos.c | 82 ++++++++++++++++++++ drivers/pinctrl/pinctrl-samsung.c | 2 + drivers/pinctrl/pinctrl-samsung.h | 1 + 4 files changed, 86 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 257677d..2b32783 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -16,6 +16,7 @@ Required Properties: - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. + - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 155b1b3..9a93df6 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { }, }; +/* pin banks of exynos5260 pin-controller 0 */ +static struct samsung_pin_bank exynos5260_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5260 pin-controller 1 */ +static struct samsung_pin_bank exynos5260_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), +}; + +/* pin banks of exynos5260 pin-controller 2 */ +static struct samsung_pin_bank exynos5260_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5260_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5260-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5260_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5260_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl2", + }, +}; + /* pin banks of exynos5420 pin-controller 0 */ static struct samsung_pin_bank exynos5420_pin_banks0[] = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 47ec2e8..0324d4c 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos4x12_pin_ctrl }, { .compatible = "samsung,exynos5250-pinctrl", .data = (void *)exynos5250_pin_ctrl }, + { .compatible = "samsung,exynos5260-pinctrl", + .data = (void *)exynos5260_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl", diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index 30622d9..bab9c21 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -254,6 +254,7 @@ struct samsung_pmx_func { extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data @ 2013-12-06 15:56 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-arm-kernel From: Young-Gun Jang <yg1004.jang@samsung.com> Add Samsung Exynos5260 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5260. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> --- .../bindings/pinctrl/samsung-pinctrl.txt | 1 + drivers/pinctrl/pinctrl-exynos.c | 82 ++++++++++++++++++++ drivers/pinctrl/pinctrl-samsung.c | 2 + drivers/pinctrl/pinctrl-samsung.h | 1 + 4 files changed, 86 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 257677d..2b32783 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -16,6 +16,7 @@ Required Properties: - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. + - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 155b1b3..9a93df6 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { }, }; +/* pin banks of exynos5260 pin-controller 0 */ +static struct samsung_pin_bank exynos5260_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5260 pin-controller 1 */ +static struct samsung_pin_bank exynos5260_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), +}; + +/* pin banks of exynos5260 pin-controller 2 */ +static struct samsung_pin_bank exynos5260_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5260_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5260-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5260_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5260_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl2", + }, +}; + /* pin banks of exynos5420 pin-controller 0 */ static struct samsung_pin_bank exynos5420_pin_banks0[] = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 47ec2e8..0324d4c 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos4x12_pin_ctrl }, { .compatible = "samsung,exynos5250-pinctrl", .data = (void *)exynos5250_pin_ctrl }, + { .compatible = "samsung,exynos5260-pinctrl", + .data = (void *)exynos5260_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl", diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index 30622d9..bab9c21 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -254,6 +254,7 @@ struct samsung_pmx_func { extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* Re: [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-09 4:51 ` Sachin Kamat -1 siblings, 0 replies; 57+ messages in thread From: Sachin Kamat @ 2013-12-09 4:51 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, yg1004.jang, Arun Kumar, Rahul Sharma Hi Rahul, Young-Gun, On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: > From: Young-Gun Jang <yg1004.jang@samsung.com> > > Add Samsung Exynos5260 SoC specific data to enable pinctrl > support for all platforms based on EXYNOS5260. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Author's (Young-Gun Jang) signed-off by is missing here. [snip] > + > +/* pin banks of exynos5260 pin-controller 2 */ > +static struct samsung_pin_bank exynos5260_pin_banks2[] = { > + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), > + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), > +}; > + > +/* > + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes s/5420/5260 ? -- With warm regards, Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data @ 2013-12-09 4:51 ` Sachin Kamat 0 siblings, 0 replies; 57+ messages in thread From: Sachin Kamat @ 2013-12-09 4:51 UTC (permalink / raw) To: linux-arm-kernel Hi Rahul, Young-Gun, On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: > From: Young-Gun Jang <yg1004.jang@samsung.com> > > Add Samsung Exynos5260 SoC specific data to enable pinctrl > support for all platforms based on EXYNOS5260. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Author's (Young-Gun Jang) signed-off by is missing here. [snip] > + > +/* pin banks of exynos5260 pin-controller 2 */ > +static struct samsung_pin_bank exynos5260_pin_banks2[] = { > + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), > + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), > +}; > + > +/* > + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes s/5420/5260 ? -- With warm regards, Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data 2013-12-09 4:51 ` Sachin Kamat @ 2013-12-09 6:36 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-09 6:36 UTC (permalink / raw) To: Sachin Kamat Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar On 9 December 2013 10:21, Sachin Kamat <sachin.kamat@linaro.org> wrote: > Hi Rahul, Young-Gun, > > On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: >> From: Young-Gun Jang <yg1004.jang@samsung.com> >> >> Add Samsung Exynos5260 SoC specific data to enable pinctrl >> support for all platforms based on EXYNOS5260. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > > Author's (Young-Gun Jang) signed-off by is missing here. I will add his signed-off. > > [snip] > >> + >> +/* pin banks of exynos5260 pin-controller 2 */ >> +static struct samsung_pin_bank exynos5260_pin_banks2[] = { >> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), >> +}; >> + >> +/* >> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes > > s/5420/5260 ? > It should be 5260. I will change this in next version. Thanks, Rahul Sharma. > -- > With warm regards, > Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data @ 2013-12-09 6:36 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-09 6:36 UTC (permalink / raw) To: linux-arm-kernel On 9 December 2013 10:21, Sachin Kamat <sachin.kamat@linaro.org> wrote: > Hi Rahul, Young-Gun, > > On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: >> From: Young-Gun Jang <yg1004.jang@samsung.com> >> >> Add Samsung Exynos5260 SoC specific data to enable pinctrl >> support for all platforms based on EXYNOS5260. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > > Author's (Young-Gun Jang) signed-off by is missing here. I will add his signed-off. > > [snip] > >> + >> +/* pin banks of exynos5260 pin-controller 2 */ >> +static struct samsung_pin_bank exynos5260_pin_banks2[] = { >> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), >> +}; >> + >> +/* >> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes > > s/5420/5260 ? > It should be 5260. I will change this in next version. Thanks, Rahul Sharma. > -- > With warm regards, > Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data 2013-12-09 4:51 ` Sachin Kamat @ 2014-01-03 9:25 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-03 9:25 UTC (permalink / raw) To: Sachin Kamat Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Hi Sachin, On 9 December 2013 10:21, Sachin Kamat <sachin.kamat@linaro.org> wrote: > Hi Rahul, Young-Gun, > > On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: >> From: Young-Gun Jang <yg1004.jang@samsung.com> >> >> Add Samsung Exynos5260 SoC specific data to enable pinctrl >> support for all platforms based on EXYNOS5260. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > > Author's (Young-Gun Jang) signed-off by is missing here. > done. > [snip] > >> + >> +/* pin banks of exynos5260 pin-controller 2 */ >> +static struct samsung_pin_bank exynos5260_pin_banks2[] = { >> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), >> +}; >> + >> +/* >> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes > > s/5420/5260 ? done. Regards, Rahul Sharma. > > -- > With warm regards, > Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data @ 2014-01-03 9:25 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-03 9:25 UTC (permalink / raw) To: linux-arm-kernel Hi Sachin, On 9 December 2013 10:21, Sachin Kamat <sachin.kamat@linaro.org> wrote: > Hi Rahul, Young-Gun, > > On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: >> From: Young-Gun Jang <yg1004.jang@samsung.com> >> >> Add Samsung Exynos5260 SoC specific data to enable pinctrl >> support for all platforms based on EXYNOS5260. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > > Author's (Young-Gun Jang) signed-off by is missing here. > done. > [snip] > >> + >> +/* pin banks of exynos5260 pin-controller 2 */ >> +static struct samsung_pin_bank exynos5260_pin_banks2[] = { >> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), >> +}; >> + >> +/* >> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes > > s/5420/5260 ? done. Regards, Rahul Sharma. > > -- > With warm regards, > Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-10 16:04 ` Tomasz Figa -1 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-10 16:04 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open Hi Young-Gun, Pankaj, Rahul, Arun, Please see my comments inline. On Friday 06 of December 2013 21:26:26 Rahul Sharma wrote: > From: Young-Gun Jang <yg1004.jang@samsung.com> > > Add Samsung Exynos5260 SoC specific data to enable pinctrl > support for all platforms based on EXYNOS5260. [snip] > diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c > index 155b1b3..9a93df6 100644 > --- a/drivers/pinctrl/pinctrl-exynos.c > +++ b/drivers/pinctrl/pinctrl-exynos.c > @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { > }, > }; > > +/* pin banks of exynos5260 pin-controller 0 */ > +static struct samsung_pin_bank exynos5260_pin_banks0[] = { > + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), > + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), > + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), > + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), > + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), > + EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14), > + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), > + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c), > + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), > + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), > + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), > + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), > + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), > + EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34), > + EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38), > + EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c), > + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), > + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), > + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), > + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), > + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), nit: Please use lowercase hexadecimal characters. Despite of already existing code, lowercase is the preferred way. > +}; > + > +/* pin banks of exynos5260 pin-controller 1 */ > +static struct samsung_pin_bank exynos5260_pin_banks1[] = { > + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), > + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), > + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), > + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), > + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), > +}; > + > +/* pin banks of exynos5260 pin-controller 2 */ > +static struct samsung_pin_bank exynos5260_pin_banks2[] = { > + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), > + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), > +}; > + > +/* > + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes > + * four gpio/pin-mux/pinconfig controllers. Hmm, I can see only three of them below. Is there one left undefined? Otherwise, the patch looks fine. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data @ 2013-12-10 16:04 ` Tomasz Figa 0 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-10 16:04 UTC (permalink / raw) To: linux-arm-kernel Hi Young-Gun, Pankaj, Rahul, Arun, Please see my comments inline. On Friday 06 of December 2013 21:26:26 Rahul Sharma wrote: > From: Young-Gun Jang <yg1004.jang@samsung.com> > > Add Samsung Exynos5260 SoC specific data to enable pinctrl > support for all platforms based on EXYNOS5260. [snip] > diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c > index 155b1b3..9a93df6 100644 > --- a/drivers/pinctrl/pinctrl-exynos.c > +++ b/drivers/pinctrl/pinctrl-exynos.c > @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { > }, > }; > > +/* pin banks of exynos5260 pin-controller 0 */ > +static struct samsung_pin_bank exynos5260_pin_banks0[] = { > + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), > + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), > + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), > + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), > + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), > + EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14), > + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), > + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c), > + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), > + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), > + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), > + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), > + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), > + EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34), > + EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38), > + EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c), > + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), > + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), > + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), > + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), > + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), nit: Please use lowercase hexadecimal characters. Despite of already existing code, lowercase is the preferred way. > +}; > + > +/* pin banks of exynos5260 pin-controller 1 */ > +static struct samsung_pin_bank exynos5260_pin_banks1[] = { > + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), > + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), > + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), > + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), > + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), > +}; > + > +/* pin banks of exynos5260 pin-controller 2 */ > +static struct samsung_pin_bank exynos5260_pin_banks2[] = { > + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), > + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), > +}; > + > +/* > + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes > + * four gpio/pin-mux/pinconfig controllers. Hmm, I can see only three of them below. Is there one left undefined? Otherwise, the patch looks fine. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data 2013-12-10 16:04 ` Tomasz Figa @ 2014-01-03 9:26 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-03 9:26 UTC (permalink / raw) To: Tomasz Figa Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Tomasz, On 10 December 2013 21:34, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Young-Gun, Pankaj, Rahul, Arun, > > Please see my comments inline. > > On Friday 06 of December 2013 21:26:26 Rahul Sharma wrote: >> From: Young-Gun Jang <yg1004.jang@samsung.com> >> >> Add Samsung Exynos5260 SoC specific data to enable pinctrl >> support for all platforms based on EXYNOS5260. > [snip] >> diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c >> index 155b1b3..9a93df6 100644 >> --- a/drivers/pinctrl/pinctrl-exynos.c >> +++ b/drivers/pinctrl/pinctrl-exynos.c >> @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { >> }, >> }; >> >> +/* pin banks of exynos5260 pin-controller 0 */ >> +static struct samsung_pin_bank exynos5260_pin_banks0[] = { >> + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), >> + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), >> + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), >> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), >> + EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14), >> + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), >> + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c), >> + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), >> + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), >> + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), >> + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), >> + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), >> + EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34), >> + EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38), >> + EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c), >> + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), >> + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), >> + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), >> + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), >> + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), > > nit: Please use lowercase hexadecimal characters. Despite of already > existing code, lowercase is the preferred way. > Changed. >> +}; >> + >> +/* pin banks of exynos5260 pin-controller 1 */ >> +static struct samsung_pin_bank exynos5260_pin_banks1[] = { >> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), >> + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), >> + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), >> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), >> +}; >> + >> +/* pin banks of exynos5260 pin-controller 2 */ >> +static struct samsung_pin_bank exynos5260_pin_banks2[] = { >> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), >> +}; >> + >> +/* >> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes >> + * four gpio/pin-mux/pinconfig controllers. > > Hmm, I can see only three of them below. Is there one left undefined? There are only three. I updated the comment. regards, Rahul Sharma > > Otherwise, the patch looks fine. > > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data @ 2014-01-03 9:26 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-03 9:26 UTC (permalink / raw) To: linux-arm-kernel Tomasz, On 10 December 2013 21:34, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Young-Gun, Pankaj, Rahul, Arun, > > Please see my comments inline. > > On Friday 06 of December 2013 21:26:26 Rahul Sharma wrote: >> From: Young-Gun Jang <yg1004.jang@samsung.com> >> >> Add Samsung Exynos5260 SoC specific data to enable pinctrl >> support for all platforms based on EXYNOS5260. > [snip] >> diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c >> index 155b1b3..9a93df6 100644 >> --- a/drivers/pinctrl/pinctrl-exynos.c >> +++ b/drivers/pinctrl/pinctrl-exynos.c >> @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { >> }, >> }; >> >> +/* pin banks of exynos5260 pin-controller 0 */ >> +static struct samsung_pin_bank exynos5260_pin_banks0[] = { >> + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), >> + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), >> + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), >> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), >> + EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14), >> + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), >> + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c), >> + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), >> + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), >> + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), >> + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), >> + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), >> + EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34), >> + EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38), >> + EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c), >> + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), >> + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), >> + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), >> + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), >> + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), > > nit: Please use lowercase hexadecimal characters. Despite of already > existing code, lowercase is the preferred way. > Changed. >> +}; >> + >> +/* pin banks of exynos5260 pin-controller 1 */ >> +static struct samsung_pin_bank exynos5260_pin_banks1[] = { >> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), >> + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), >> + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), >> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), >> +}; >> + >> +/* pin banks of exynos5260 pin-controller 2 */ >> +static struct samsung_pin_bank exynos5260_pin_banks2[] = { >> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), >> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), >> +}; >> + >> +/* >> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes >> + * four gpio/pin-mux/pinconfig controllers. > > Hmm, I can see only three of them below. Is there one left undefined? There are only three. I updated the comment. regards, Rahul Sharma > > Otherwise, the patch looks fine. > > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
[parent not found: <1386345391-23482-1-git-send-email-rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>]
* [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-06 15:56 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: mturquette-QSEj5FYQhm4dnm+yROfE0A, kgene.kim-Sze3O3UU22JBDgjK7y7TUQ, thomas.ab-Sze3O3UU22JBDgjK7y7TUQ, tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w, joshi-Sze3O3UU22JBDgjK7y7TUQ, pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ, yg1004.jang-Sze3O3UU22JBDgjK7y7TUQ, arun.kk-Sze3O3UU22JBDgjK7y7TUQ, r.sh.open-Re5JQEeQqe8AvxtiuMwx3w, Rahul Sharma From: Arun Kumar K <arun.kk-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> The patch adds the dts files for exynos5260 and for xyref evt0 board. Signed-off-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Signed-off-by: Rahul Sharma <rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Signed-off-by: Arun Kumar K <arun.kk-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 586 +++++++++++++++++++++++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 85 ++++ arch/arm/boot/dts/exynos5260.dtsi | 315 ++++++++++++ 4 files changed, 987 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 741bf73..8d26135 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5260-xyref5260-evt0.dtb \ exynos5420-smdk5420.dtb \ exynos5440-sd5v1.dtb \ exynos5440-ssdk5440.dtb diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi new file mode 100644 index 0000000..67aaee7 --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -0,0 +1,586 @@ +/* + * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11600000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-5", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + usb3_vbus0_en: usb3-vbus0-en { + samsung,pins = "gpa2-4"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif1_bus: spdif1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_hs_bus: i2c0-hs-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_hs_bus: i2c1-hs-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c2_hs_bus: i2c2-hs-bus { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_hs_bus: i2c3-hs-bus { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb4-2", "gpb4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpb4-4", "gpb4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpb4-6", "gpb4-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c8_bus: i2c8-bus { + samsung,pins = "gpb5-0", "gpb5-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c9_bus: i2c9-bus { + samsung,pins = "gpb5-2", "gpb5-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c10_bus: i2c10-bus { + samsung,pins = "gpb5-4", "gpb5-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c11_bus: i2c11-bus { + samsung,pins = "gpb5-6", "gpb5-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_gpio_a: cam-gpio-a { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_gpio_b: cam-gpio-b { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c1_bus: cam-i2c1-bus { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_i2c0_bus: cam-i2c0-bus { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi0_bus: cam-spi0-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_spi1_bus: cam-spi1-bus { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@12290000 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpc1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + }; + + pinctrl@128B0000 { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts new file mode 100644 index 0000000..aa1fcda --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts @@ -0,0 +1,85 @@ +/* + * SAMSUNG XYREF5260 EVT0 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5260.dtsi" + +/ { + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260"; + compatible = "samsung,xyref5260", "samsung,exynos5260"; + + chosen { + bootargs = "console=ttySAC2,115200"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5260-oscclk"; + clock-frequency = <24000000>; + }; + }; + + serial@12C00000 { + status = "okay"; + }; + + serial@12C10000 { + status = "okay"; + }; + + serial@12C20000 { + status = "okay"; + }; + + serial@12860000 { + status = "okay"; + }; + + dwmmc0@12140000 { + status = "okay"; + num-slots = <1>; + broken-cd; + bypass-smu; + supports-highspeed; + supports-hs200-mode; /* 200 Mhz */ + fifo-depth = <0x40>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + dwmmc2@12160000 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x40>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi new file mode 100644 index 0000000..fcb8d4f --- /dev/null +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -0,0 +1,315 @@ +/* + * SAMSUNG EXYNOS5260 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "skeleton.dtsi" +#include "exynos5260-pinctrl.dtsi" + +#include <dt-bindings/clk/exynos5260-clk.h> + +/ { + compatible = "samsung,exynos5260"; + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + }; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + cci-control-port = <&cci_control1>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + cci-control-port = <&cci_control1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cci-control-port = <&cci_control0>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cci-control-port = <&cci_control0>; + }; + cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cci-control-port = <&cci_control0>; + }; + cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + cci-control-port = <&cci_control0>; + }; + }; + + cmus { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cmu_top: clock-controller@0x10010000 { + compatible = "exynos5260-cmu-top", + "samsung,exynos5260-clock"; + reg = <0x10010000 0x10000>; + #clock-cells = <1>; + }; + + cmu_peri: clock-controller@0x10200000 { + compatible = "exynos5260-cmu-peri", "samsung,exynos5260-clock"; + reg = <0x10200000 0x10000>; + #clock-cells = <1>; + }; + + cmu_egl: clock-controller@0x10600000 { + compatible = "exynos5260-cmu-egl", "samsung,exynos5260-clock"; + reg = <0x10600000 0x10000>; + #clock-cells = <1>; + }; + + cmu_kfc: clock-controller@0x10700000 { + compatible = "exynos5260-cmu-kfc", "samsung,exynos5260-clock"; + reg = <0x10700000 0x10000>; + #clock-cells = <1>; + }; + + cmu_g2d: clock-controller@0x10A00000 { + compatible = "exynos5260-cmu-g2d", "samsung,exynos5260-clock"; + reg = <0x10A00000 0x10000>; + #clock-cells = <1>; + }; + + cmu_mif: clock-controller@0x10CE0000 { + compatible = "exynos5260-cmu-mif", "samsung,exynos5260-clock"; + reg = <0x10CE0000 0x10000>; + #clock-cells = <1>; + }; + + cmu_mfc: clock-controller@0x11090000 { + compatible = "exynos5260-cmu-mfc", "samsung,exynos5260-clock"; + reg = <0x11090000 0x10000>; + #clock-cells = <1>; + }; + + cmu_g3d: clock-controller@0x11830000 { + compatible = "exynos5260-cmu-g3d", "samsung,exynos5260-clock"; + reg = <0x11830000 0x10000>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller@0x122E0000 { + compatible = "exynos5260-cmu-fsys", "samsung,exynos5260-clock"; + reg = <0x122E0000 0x10000>; + #clock-cells = <1>; + }; + + cmu_aud: clock-controller@0x128C0000 { + compatible = "exynos5260-cmu-aud", "samsung,exynos5260-clock"; + reg = <0x128C0000 0x10000>; + #clock-cells = <1>; + }; + + cmu_isp: clock-controller@0x133C0000 { + compatible = "exynos5260-cmu-isp", "samsung,exynos5260-clock"; + reg = <0x133C0000 0x10000>; + #clock-cells = <1>; + }; + + cmu_gscl: clock-controller@0x13F00000 { + compatible = "exynos5260-cmu-gscl", "samsung,exynos5260-clock"; + reg = <0x13F00000 0x10000>; + #clock-cells = <1>; + }; + + cmu_disp: clock-controller@0x14550000 { + compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock"; + reg = <0x14550000 0x10000>; + #clock-cells = <1>; + }; + }; + + gic:interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + mct@100B0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x100B0000 0xb00>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>; + clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &gic 0 104 0>, + <0x1 0 &gic 0 105 0>, + <0x2 0 &gic 0 106 0>, + <0x3 0 &gic 0 107 0>, + <0x4 0 &gic 0 122 0>, + <0x5 0 &gic 0 123 0>, + <0x6 0 &gic 0 124 0>, + <0x7 0 &gic 0 125 0>, + <0x8 0 &gic 0 126 0>, + <0x9 0 &gic 0 127 0>, + <0xa 0 &gic 0 128 0>, + <0xb 0 &gic 0 129 0>; + }; + }; + + cci@10F00000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10F00000 0x1000>; + ranges = <0x0 0x10F00000 0x6000>; + + cci_control0: slave-if@4000 { /* Please check again */ + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; /* Please check again */ + }; + + cci_control1: slave-if@5000 { /* Please check again */ + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; /* Please check again */ + }; + }; + + pinctrl_0: pinctrl@11600000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x11600000 0x1000>; + interrupts = <0 79 0>; /* GPIO_RT */ + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_1: pinctrl@12290000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x12290000 0x1000>; /* GPIO_FSYS */ + interrupts = <0 157 0>; + }; + + pinctrl_2: pinctrl@128B0000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x128B0000 0x1000>; + interrupts = <0 243 0>; /* GPIO_AUD */ + }; + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 146 0>; + clocks = <&cmu_peri PERI_PCLK_UART0>, <&cmu_peri PERI_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 147 0>; + clocks = <&cmu_peri PERI_PCLK_UART1>, <&cmu_peri PERI_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 148 0>; + clocks = <&cmu_peri PERI_PCLK_UART2>, <&cmu_peri PERI_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial@12860000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12860000 0x100>; + interrupts = <0 145 0>; + clocks = <&cmu_aud AUD_PCLK_AUD_UART>, <&cmu_aud AUD_SCLK_AUD_UART>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + dwmmc_0: dwmmc0@12140000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12140000 0x2000>; + interrupts = <0 156 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys FSYS_HCLK_MMC0>, <&cmu_top TOP_SCLK_MMC0>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + dwmmc_1: dwmmc1@12150000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12150000 0x2000>; + interrupts = <0 158 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys FSYS_HCLK_MMC1>, <&cmu_top TOP_SCLK_MMC1>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + dwmmc_2: dwmmc2@12160000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12160000 0x2000>; + interrupts = <0 159 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys FSYS_HCLK_MMC2>, <&cmu_top TOP_SCLK_MMC2>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; +}; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC @ 2013-12-06 15:56 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-arm-kernel From: Arun Kumar K <arun.kk@samsung.com> The patch adds the dts files for exynos5260 and for xyref evt0 board. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 586 +++++++++++++++++++++++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 85 ++++ arch/arm/boot/dts/exynos5260.dtsi | 315 ++++++++++++ 4 files changed, 987 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 741bf73..8d26135 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5260-xyref5260-evt0.dtb \ exynos5420-smdk5420.dtb \ exynos5440-sd5v1.dtb \ exynos5440-ssdk5440.dtb diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi new file mode 100644 index 0000000..67aaee7 --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -0,0 +1,586 @@ +/* + * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl at 11600000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-5", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + usb3_vbus0_en: usb3-vbus0-en { + samsung,pins = "gpa2-4"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif1_bus: spdif1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_hs_bus: i2c0-hs-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_hs_bus: i2c1-hs-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c2_hs_bus: i2c2-hs-bus { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_hs_bus: i2c3-hs-bus { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb4-2", "gpb4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpb4-4", "gpb4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpb4-6", "gpb4-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c8_bus: i2c8-bus { + samsung,pins = "gpb5-0", "gpb5-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c9_bus: i2c9-bus { + samsung,pins = "gpb5-2", "gpb5-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c10_bus: i2c10-bus { + samsung,pins = "gpb5-4", "gpb5-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c11_bus: i2c11-bus { + samsung,pins = "gpb5-6", "gpb5-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_gpio_a: cam-gpio-a { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_gpio_b: cam-gpio-b { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c1_bus: cam-i2c1-bus { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_i2c0_bus: cam-i2c0-bus { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi0_bus: cam-spi0-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_spi1_bus: cam-spi1-bus { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl at 12290000 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpc1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + }; + + pinctrl at 128B0000 { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts new file mode 100644 index 0000000..aa1fcda --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts @@ -0,0 +1,85 @@ +/* + * SAMSUNG XYREF5260 EVT0 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5260.dtsi" + +/ { + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260"; + compatible = "samsung,xyref5260", "samsung,exynos5260"; + + chosen { + bootargs = "console=ttySAC2,115200"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5260-oscclk"; + clock-frequency = <24000000>; + }; + }; + + serial at 12C00000 { + status = "okay"; + }; + + serial at 12C10000 { + status = "okay"; + }; + + serial at 12C20000 { + status = "okay"; + }; + + serial at 12860000 { + status = "okay"; + }; + + dwmmc0 at 12140000 { + status = "okay"; + num-slots = <1>; + broken-cd; + bypass-smu; + supports-highspeed; + supports-hs200-mode; /* 200 Mhz */ + fifo-depth = <0x40>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot at 0 { + reg = <0>; + bus-width = <8>; + }; + }; + + dwmmc2 at 12160000 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x40>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot at 0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi new file mode 100644 index 0000000..fcb8d4f --- /dev/null +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -0,0 +1,315 @@ +/* + * SAMSUNG EXYNOS5260 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "skeleton.dtsi" +#include "exynos5260-pinctrl.dtsi" + +#include <dt-bindings/clk/exynos5260-clk.h> + +/ { + compatible = "samsung,exynos5260"; + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + }; + + chipid at 10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + cci-control-port = <&cci_control1>; + }; + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + cci-control-port = <&cci_control1>; + }; + cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cci-control-port = <&cci_control0>; + }; + cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cci-control-port = <&cci_control0>; + }; + cpu at 4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cci-control-port = <&cci_control0>; + }; + cpu at 5 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + cci-control-port = <&cci_control0>; + }; + }; + + cmus { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cmu_top: clock-controller at 0x10010000 { + compatible = "exynos5260-cmu-top", + "samsung,exynos5260-clock"; + reg = <0x10010000 0x10000>; + #clock-cells = <1>; + }; + + cmu_peri: clock-controller at 0x10200000 { + compatible = "exynos5260-cmu-peri", "samsung,exynos5260-clock"; + reg = <0x10200000 0x10000>; + #clock-cells = <1>; + }; + + cmu_egl: clock-controller at 0x10600000 { + compatible = "exynos5260-cmu-egl", "samsung,exynos5260-clock"; + reg = <0x10600000 0x10000>; + #clock-cells = <1>; + }; + + cmu_kfc: clock-controller at 0x10700000 { + compatible = "exynos5260-cmu-kfc", "samsung,exynos5260-clock"; + reg = <0x10700000 0x10000>; + #clock-cells = <1>; + }; + + cmu_g2d: clock-controller at 0x10A00000 { + compatible = "exynos5260-cmu-g2d", "samsung,exynos5260-clock"; + reg = <0x10A00000 0x10000>; + #clock-cells = <1>; + }; + + cmu_mif: clock-controller at 0x10CE0000 { + compatible = "exynos5260-cmu-mif", "samsung,exynos5260-clock"; + reg = <0x10CE0000 0x10000>; + #clock-cells = <1>; + }; + + cmu_mfc: clock-controller at 0x11090000 { + compatible = "exynos5260-cmu-mfc", "samsung,exynos5260-clock"; + reg = <0x11090000 0x10000>; + #clock-cells = <1>; + }; + + cmu_g3d: clock-controller at 0x11830000 { + compatible = "exynos5260-cmu-g3d", "samsung,exynos5260-clock"; + reg = <0x11830000 0x10000>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller at 0x122E0000 { + compatible = "exynos5260-cmu-fsys", "samsung,exynos5260-clock"; + reg = <0x122E0000 0x10000>; + #clock-cells = <1>; + }; + + cmu_aud: clock-controller at 0x128C0000 { + compatible = "exynos5260-cmu-aud", "samsung,exynos5260-clock"; + reg = <0x128C0000 0x10000>; + #clock-cells = <1>; + }; + + cmu_isp: clock-controller at 0x133C0000 { + compatible = "exynos5260-cmu-isp", "samsung,exynos5260-clock"; + reg = <0x133C0000 0x10000>; + #clock-cells = <1>; + }; + + cmu_gscl: clock-controller at 0x13F00000 { + compatible = "exynos5260-cmu-gscl", "samsung,exynos5260-clock"; + reg = <0x13F00000 0x10000>; + #clock-cells = <1>; + }; + + cmu_disp: clock-controller at 0x14550000 { + compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock"; + reg = <0x14550000 0x10000>; + #clock-cells = <1>; + }; + }; + + gic:interrupt-controller at 10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + mct at 100B0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x100B0000 0xb00>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>; + clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &gic 0 104 0>, + <0x1 0 &gic 0 105 0>, + <0x2 0 &gic 0 106 0>, + <0x3 0 &gic 0 107 0>, + <0x4 0 &gic 0 122 0>, + <0x5 0 &gic 0 123 0>, + <0x6 0 &gic 0 124 0>, + <0x7 0 &gic 0 125 0>, + <0x8 0 &gic 0 126 0>, + <0x9 0 &gic 0 127 0>, + <0xa 0 &gic 0 128 0>, + <0xb 0 &gic 0 129 0>; + }; + }; + + cci at 10F00000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10F00000 0x1000>; + ranges = <0x0 0x10F00000 0x6000>; + + cci_control0: slave-if at 4000 { /* Please check again */ + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; /* Please check again */ + }; + + cci_control1: slave-if at 5000 { /* Please check again */ + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; /* Please check again */ + }; + }; + + pinctrl_0: pinctrl at 11600000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x11600000 0x1000>; + interrupts = <0 79 0>; /* GPIO_RT */ + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_1: pinctrl at 12290000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x12290000 0x1000>; /* GPIO_FSYS */ + interrupts = <0 157 0>; + }; + + pinctrl_2: pinctrl at 128B0000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x128B0000 0x1000>; + interrupts = <0 243 0>; /* GPIO_AUD */ + }; + + serial at 12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 146 0>; + clocks = <&cmu_peri PERI_PCLK_UART0>, <&cmu_peri PERI_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial at 12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 147 0>; + clocks = <&cmu_peri PERI_PCLK_UART1>, <&cmu_peri PERI_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial at 12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 148 0>; + clocks = <&cmu_peri PERI_PCLK_UART2>, <&cmu_peri PERI_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial at 12860000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12860000 0x100>; + interrupts = <0 145 0>; + clocks = <&cmu_aud AUD_PCLK_AUD_UART>, <&cmu_aud AUD_SCLK_AUD_UART>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + dwmmc_0: dwmmc0 at 12140000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12140000 0x2000>; + interrupts = <0 156 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys FSYS_HCLK_MMC0>, <&cmu_top TOP_SCLK_MMC0>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + dwmmc_1: dwmmc1 at 12150000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12150000 0x2000>; + interrupts = <0 158 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys FSYS_HCLK_MMC1>, <&cmu_top TOP_SCLK_MMC1>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + dwmmc_2: dwmmc2 at 12160000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12160000 0x2000>; + interrupts = <0 159 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys FSYS_HCLK_MMC2>, <&cmu_top TOP_SCLK_MMC2>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; +}; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* Re: [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-10 17:10 ` Tomasz Figa -1 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-10 17:10 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open Hi Pankaj, Rahul, Arun, Please split generic SoC dtsi files and board dts files into separate patches. Also please see my comments inline. On Friday 06 of December 2013 21:26:27 Rahul Sharma wrote: > From: Arun Kumar K <arun.kk@samsung.com> > > The patch adds the dts files for exynos5260 and for xyref > evt0 board. [snip] > + gpx0: gpx0 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; Just to make sure, all your GPX banks are muxed type, with wake-up interrupts muxed to a single GIC interrupt line, right? > + }; [snip] > + cam_gpio_a: cam-gpio-a { > + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", > + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", > + "gpe1-0", "gpe1-1"; > + samsung,pin-function = <2>; Incorrect indentation. > + samsung,pin-pud = <0>; > + samsung,pin-drv = <0>; > + }; [snip] > + hdmi_hpd_irq: hdmi-hpd-irq { > + samsung,pins = "gpx3-7"; > + samsung,pin-function = <0>; Function 0 is input, not a special function. It shouldn't be handled this way. If a board needs to set up pull-up/down and driver strength for GPIO pins then it should add its own board-specific pinconf nodes with just pin-pud and/or pin-drv properties and without pin-function. > + samsung,pin-pud = <1>; > + samsung,pin-drv = <0>; > + }; > + }; [snip] > + sd0_bus1: sd0-bus-width1 { > + samsung,pins = "gpc0-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <3>; > + }; > + > + sd0_bus4: sd0-bus-width4 { > + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <3>; > + }; > + > + sd0_bus8: sd0-bus-width8 { > + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <3>; > + }; This is inconsistent. To specify 1- and 4-bit SD busses you need to include reference to just one pinconf node (sd0_bus1 or sd0_bus4), but for 8-bit bus you need to specify both sd0_bus4 and sd0_bus8. Please make the nodes exclusive, so you always need to specify all possible configurations with given wiring (e.g. with 4 wires, you can run in 1-bit and 4-bit modes, not just 4-bit). Same for remaining instances of SD bus. [snip] > diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts > new file mode 100644 > index 0000000..aa1fcda > --- /dev/null > +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts > @@ -0,0 +1,85 @@ > +/* > + * SAMSUNG XYREF5260 EVT0 board device tree source > + * > + * Copyright (c) 2013 Samsung Electronics Co., Ltd. > + * http://www.samsung.com > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > +*/ > + > +/dts-v1/; > +#include "exynos5260.dtsi" > + > +/ { > + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260"; > + compatible = "samsung,xyref5260", "samsung,exynos5260"; > + Shouldn't you have a memory node here? > + chosen { > + bootargs = "console=ttySAC2,115200"; > + }; > + > + fixed-rate-clocks { > + oscclk { > + compatible = "samsung,exynos5260-oscclk"; > + clock-frequency = <24000000>; > + }; > + }; Please use generic fixed clock bindings. You can take [1] as an example how to use them. [1] arch/arm/boot/dts/s3c6410-smdk6410.dtsi > + > + serial@12C00000 { > + status = "okay"; > + }; > + > + serial@12C10000 { > + status = "okay"; > + }; > + > + serial@12C20000 { > + status = "okay"; > + }; > + > + serial@12860000 { Is it the correct UART address? It seems a bit off compared to addresses of other ports. > + status = "okay"; > + }; > + > + dwmmc0@12140000 { > + status = "okay"; > + num-slots = <1>; > + broken-cd; > + bypass-smu; This is not a valid property, according to binding documentation. > + supports-highspeed; > + supports-hs200-mode; /* 200 Mhz */ Neither is this one. > + fifo-depth = <0x40>; This is a property of the SoC, not the board. > + card-detect-delay = <200>; > + samsung,dw-mshc-ciu-div = <3>; > + samsung,dw-mshc-sdr-timing = <0 4>; > + samsung,dw-mshc-ddr-timing = <0 2>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; > + > + slot@0 { > + reg = <0>; > + bus-width = <8>; > + }; > + }; > + > + dwmmc2@12160000 { > + status = "okay"; > + num-slots = <1>; > + supports-highspeed; > + fifo-depth = <0x40>; See above. > + card-detect-delay = <200>; > + samsung,dw-mshc-ciu-div = <3>; > + samsung,dw-mshc-sdr-timing = <2 3>; > + samsung,dw-mshc-ddr-timing = <1 2>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; > + > + slot@0 { > + reg = <0>; > + bus-width = <4>; > + disable-wp; > + }; > + }; > +}; > diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi > new file mode 100644 > index 0000000..fcb8d4f > --- /dev/null > +++ b/arch/arm/boot/dts/exynos5260.dtsi > @@ -0,0 +1,315 @@ > +/* > + * SAMSUNG EXYNOS5260 SoC device tree source > + * > + * Copyright (c) 2013 Samsung Electronics Co., Ltd. > + * http://www.samsung.com > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > +*/ > + > +#include "skeleton.dtsi" > +#include "exynos5260-pinctrl.dtsi" > + > +#include <dt-bindings/clk/exynos5260-clk.h> This won't compile, because this file hasn't been added yet by previous patches. Isn't it possible to reuse some of the definitions from exynos5.dtsi? How much different is this SoC from other SoCs from the series? > + > +/ { > + compatible = "samsung,exynos5260"; > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_0; > + pinctrl1 = &pinctrl_1; > + pinctrl2 = &pinctrl_2; > + }; > + > + chipid@10000000 { > + compatible = "samsung,exynos4210-chipid"; > + reg = <0x10000000 0x100>; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a15"; > + reg = <0>; > + cci-control-port = <&cci_control1>; > + }; > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a15"; > + reg = <1>; > + cci-control-port = <&cci_control1>; > + }; > + cpu@2 { @unit-address suffix must match the first entry of reg property. > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x100>; > + cci-control-port = <&cci_control0>; > + }; > + cpu@3 { Ditto. > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x101>; > + cci-control-port = <&cci_control0>; > + }; > + cpu@4 { Ditto. > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x102>; > + cci-control-port = <&cci_control0>; > + }; > + cpu@5 { Ditto. > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x103>; > + cci-control-port = <&cci_control0>; > + }; > + }; > + > + cmus { You need compatible = "simple-bus" here if you need the nodes below to be instantiated. However I'm not sure if there is a point in placing them inside a simple-bus. This needs more thought, so please give me a bit more time to think over this and patches 4 and 7. > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + cmu_top: clock-controller@0x10010000 { coding style: There should be no 0x prefix in @unit-address suffix. + all the CMU instances below. [snip] > + > + gic:interrupt-controller@10481000 { coding style: There should be a space after the colon ending the label. > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + #size-cells = <0>; > + interrupt-controller; > + reg = <0x10481000 0x1000>, > + <0x10482000 0x1000>, > + <0x10484000 0x2000>, > + <0x10486000 0x2000>; > + interrupts = <1 9 0xf04>; > + }; > + > + mct@100B0000 { > + compatible = "samsung,exynos4210-mct"; > + reg = <0x100B0000 0xb00>; nit: Inconsistent hexadecimal character case, on Exynos in dts* files upper case should be used. Also the reg size looks a bit suspicious, as it's not even page aligned. Is it the whole area used by the MCT block, not just the used registers? > + interrupt-controller; MCT is not an interrupt controller. > + #interrups-cells = <2>; Ditto. This is a property specific to interrupt controllers. > + interrupt-parent = <&mct_map>; > + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, > + <4 0>, <5 0>, <6 0>, <7 0>, > + <8 0>, <9 0>, <10 0>, <11 0>; > + clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>; > + clock-names = "fin_pll", "mct"; > + > + mct_map: mct-map { > + #interrupt-cells = <2>; Why two cells are needed? Using just one woudl simplify interrupt specifiers above and interrupt-map specifiers below. > + #address-cells = <0>; > + #size-cells = <0>; > + interrupt-map = <0x0 0 &gic 0 104 0>, > + <0x1 0 &gic 0 105 0>, > + <0x2 0 &gic 0 106 0>, > + <0x3 0 &gic 0 107 0>, > + <0x4 0 &gic 0 122 0>, > + <0x5 0 &gic 0 123 0>, > + <0x6 0 &gic 0 124 0>, > + <0x7 0 &gic 0 125 0>, > + <0x8 0 &gic 0 126 0>, > + <0x9 0 &gic 0 127 0>, > + <0xa 0 &gic 0 128 0>, > + <0xb 0 &gic 0 129 0>; > + }; > + }; > + > + cci@10F00000 { > + compatible = "arm,cci-400"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x10F00000 0x1000>; > + ranges = <0x0 0x10F00000 0x6000>; > + > + cci_control0: slave-if@4000 { /* Please check again */ Huh? Please check again and send correct data. > + compatible = "arm,cci-400-ctrl-if"; > + interface-type = "ace"; > + reg = <0x4000 0x1000>; /* Please check again */ > + }; > + > + cci_control1: slave-if@5000 { /* Please check again */ > + compatible = "arm,cci-400-ctrl-if"; > + interface-type = "ace"; > + reg = <0x5000 0x1000>; /* Please check again */ > + }; > + }; > + > + pinctrl_0: pinctrl@11600000 { > + compatible = "samsung,exynos5260-pinctrl"; > + reg = <0x11600000 0x1000>; > + interrupts = <0 79 0>; /* GPIO_RT */ Instead of using such comment, maybe it would be better to rename labels of pinctrl nodes to be more meaningful, such as pinctrl_rt, pinctrl_fsys and pinctrl_aud? > + > + wakeup-interrupt-controller { > + compatible = "samsung,exynos4210-wakeup-eint"; > + interrupt-parent = <&gic>; > + interrupts = <0 32 0>; > + }; > + }; [snip] > + > + dwmmc_0: dwmmc0@12140000 { Please use generic "mmc@" names for MMC nodes and move fifo-depth property here to SoC-level dtsi. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC @ 2013-12-10 17:10 ` Tomasz Figa 0 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-10 17:10 UTC (permalink / raw) To: linux-arm-kernel Hi Pankaj, Rahul, Arun, Please split generic SoC dtsi files and board dts files into separate patches. Also please see my comments inline. On Friday 06 of December 2013 21:26:27 Rahul Sharma wrote: > From: Arun Kumar K <arun.kk@samsung.com> > > The patch adds the dts files for exynos5260 and for xyref > evt0 board. [snip] > + gpx0: gpx0 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; Just to make sure, all your GPX banks are muxed type, with wake-up interrupts muxed to a single GIC interrupt line, right? > + }; [snip] > + cam_gpio_a: cam-gpio-a { > + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", > + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", > + "gpe1-0", "gpe1-1"; > + samsung,pin-function = <2>; Incorrect indentation. > + samsung,pin-pud = <0>; > + samsung,pin-drv = <0>; > + }; [snip] > + hdmi_hpd_irq: hdmi-hpd-irq { > + samsung,pins = "gpx3-7"; > + samsung,pin-function = <0>; Function 0 is input, not a special function. It shouldn't be handled this way. If a board needs to set up pull-up/down and driver strength for GPIO pins then it should add its own board-specific pinconf nodes with just pin-pud and/or pin-drv properties and without pin-function. > + samsung,pin-pud = <1>; > + samsung,pin-drv = <0>; > + }; > + }; [snip] > + sd0_bus1: sd0-bus-width1 { > + samsung,pins = "gpc0-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <3>; > + }; > + > + sd0_bus4: sd0-bus-width4 { > + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <3>; > + }; > + > + sd0_bus8: sd0-bus-width8 { > + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; > + samsung,pin-function = <2>; > + samsung,pin-pud = <3>; > + samsung,pin-drv = <3>; > + }; This is inconsistent. To specify 1- and 4-bit SD busses you need to include reference to just one pinconf node (sd0_bus1 or sd0_bus4), but for 8-bit bus you need to specify both sd0_bus4 and sd0_bus8. Please make the nodes exclusive, so you always need to specify all possible configurations with given wiring (e.g. with 4 wires, you can run in 1-bit and 4-bit modes, not just 4-bit). Same for remaining instances of SD bus. [snip] > diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts > new file mode 100644 > index 0000000..aa1fcda > --- /dev/null > +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts > @@ -0,0 +1,85 @@ > +/* > + * SAMSUNG XYREF5260 EVT0 board device tree source > + * > + * Copyright (c) 2013 Samsung Electronics Co., Ltd. > + * http://www.samsung.com > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > +*/ > + > +/dts-v1/; > +#include "exynos5260.dtsi" > + > +/ { > + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260"; > + compatible = "samsung,xyref5260", "samsung,exynos5260"; > + Shouldn't you have a memory node here? > + chosen { > + bootargs = "console=ttySAC2,115200"; > + }; > + > + fixed-rate-clocks { > + oscclk { > + compatible = "samsung,exynos5260-oscclk"; > + clock-frequency = <24000000>; > + }; > + }; Please use generic fixed clock bindings. You can take [1] as an example how to use them. [1] arch/arm/boot/dts/s3c6410-smdk6410.dtsi > + > + serial at 12C00000 { > + status = "okay"; > + }; > + > + serial at 12C10000 { > + status = "okay"; > + }; > + > + serial at 12C20000 { > + status = "okay"; > + }; > + > + serial at 12860000 { Is it the correct UART address? It seems a bit off compared to addresses of other ports. > + status = "okay"; > + }; > + > + dwmmc0 at 12140000 { > + status = "okay"; > + num-slots = <1>; > + broken-cd; > + bypass-smu; This is not a valid property, according to binding documentation. > + supports-highspeed; > + supports-hs200-mode; /* 200 Mhz */ Neither is this one. > + fifo-depth = <0x40>; This is a property of the SoC, not the board. > + card-detect-delay = <200>; > + samsung,dw-mshc-ciu-div = <3>; > + samsung,dw-mshc-sdr-timing = <0 4>; > + samsung,dw-mshc-ddr-timing = <0 2>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; > + > + slot at 0 { > + reg = <0>; > + bus-width = <8>; > + }; > + }; > + > + dwmmc2 at 12160000 { > + status = "okay"; > + num-slots = <1>; > + supports-highspeed; > + fifo-depth = <0x40>; See above. > + card-detect-delay = <200>; > + samsung,dw-mshc-ciu-div = <3>; > + samsung,dw-mshc-sdr-timing = <2 3>; > + samsung,dw-mshc-ddr-timing = <1 2>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; > + > + slot at 0 { > + reg = <0>; > + bus-width = <4>; > + disable-wp; > + }; > + }; > +}; > diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi > new file mode 100644 > index 0000000..fcb8d4f > --- /dev/null > +++ b/arch/arm/boot/dts/exynos5260.dtsi > @@ -0,0 +1,315 @@ > +/* > + * SAMSUNG EXYNOS5260 SoC device tree source > + * > + * Copyright (c) 2013 Samsung Electronics Co., Ltd. > + * http://www.samsung.com > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > +*/ > + > +#include "skeleton.dtsi" > +#include "exynos5260-pinctrl.dtsi" > + > +#include <dt-bindings/clk/exynos5260-clk.h> This won't compile, because this file hasn't been added yet by previous patches. Isn't it possible to reuse some of the definitions from exynos5.dtsi? How much different is this SoC from other SoCs from the series? > + > +/ { > + compatible = "samsung,exynos5260"; > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_0; > + pinctrl1 = &pinctrl_1; > + pinctrl2 = &pinctrl_2; > + }; > + > + chipid at 10000000 { > + compatible = "samsung,exynos4210-chipid"; > + reg = <0x10000000 0x100>; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a15"; > + reg = <0>; > + cci-control-port = <&cci_control1>; > + }; > + cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a15"; > + reg = <1>; > + cci-control-port = <&cci_control1>; > + }; > + cpu at 2 { @unit-address suffix must match the first entry of reg property. > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x100>; > + cci-control-port = <&cci_control0>; > + }; > + cpu at 3 { Ditto. > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x101>; > + cci-control-port = <&cci_control0>; > + }; > + cpu at 4 { Ditto. > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x102>; > + cci-control-port = <&cci_control0>; > + }; > + cpu at 5 { Ditto. > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x103>; > + cci-control-port = <&cci_control0>; > + }; > + }; > + > + cmus { You need compatible = "simple-bus" here if you need the nodes below to be instantiated. However I'm not sure if there is a point in placing them inside a simple-bus. This needs more thought, so please give me a bit more time to think over this and patches 4 and 7. > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + cmu_top: clock-controller at 0x10010000 { coding style: There should be no 0x prefix in @unit-address suffix. + all the CMU instances below. [snip] > + > + gic:interrupt-controller at 10481000 { coding style: There should be a space after the colon ending the label. > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + #size-cells = <0>; > + interrupt-controller; > + reg = <0x10481000 0x1000>, > + <0x10482000 0x1000>, > + <0x10484000 0x2000>, > + <0x10486000 0x2000>; > + interrupts = <1 9 0xf04>; > + }; > + > + mct at 100B0000 { > + compatible = "samsung,exynos4210-mct"; > + reg = <0x100B0000 0xb00>; nit: Inconsistent hexadecimal character case, on Exynos in dts* files upper case should be used. Also the reg size looks a bit suspicious, as it's not even page aligned. Is it the whole area used by the MCT block, not just the used registers? > + interrupt-controller; MCT is not an interrupt controller. > + #interrups-cells = <2>; Ditto. This is a property specific to interrupt controllers. > + interrupt-parent = <&mct_map>; > + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, > + <4 0>, <5 0>, <6 0>, <7 0>, > + <8 0>, <9 0>, <10 0>, <11 0>; > + clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>; > + clock-names = "fin_pll", "mct"; > + > + mct_map: mct-map { > + #interrupt-cells = <2>; Why two cells are needed? Using just one woudl simplify interrupt specifiers above and interrupt-map specifiers below. > + #address-cells = <0>; > + #size-cells = <0>; > + interrupt-map = <0x0 0 &gic 0 104 0>, > + <0x1 0 &gic 0 105 0>, > + <0x2 0 &gic 0 106 0>, > + <0x3 0 &gic 0 107 0>, > + <0x4 0 &gic 0 122 0>, > + <0x5 0 &gic 0 123 0>, > + <0x6 0 &gic 0 124 0>, > + <0x7 0 &gic 0 125 0>, > + <0x8 0 &gic 0 126 0>, > + <0x9 0 &gic 0 127 0>, > + <0xa 0 &gic 0 128 0>, > + <0xb 0 &gic 0 129 0>; > + }; > + }; > + > + cci at 10F00000 { > + compatible = "arm,cci-400"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x10F00000 0x1000>; > + ranges = <0x0 0x10F00000 0x6000>; > + > + cci_control0: slave-if at 4000 { /* Please check again */ Huh? Please check again and send correct data. > + compatible = "arm,cci-400-ctrl-if"; > + interface-type = "ace"; > + reg = <0x4000 0x1000>; /* Please check again */ > + }; > + > + cci_control1: slave-if at 5000 { /* Please check again */ > + compatible = "arm,cci-400-ctrl-if"; > + interface-type = "ace"; > + reg = <0x5000 0x1000>; /* Please check again */ > + }; > + }; > + > + pinctrl_0: pinctrl at 11600000 { > + compatible = "samsung,exynos5260-pinctrl"; > + reg = <0x11600000 0x1000>; > + interrupts = <0 79 0>; /* GPIO_RT */ Instead of using such comment, maybe it would be better to rename labels of pinctrl nodes to be more meaningful, such as pinctrl_rt, pinctrl_fsys and pinctrl_aud? > + > + wakeup-interrupt-controller { > + compatible = "samsung,exynos4210-wakeup-eint"; > + interrupt-parent = <&gic>; > + interrupts = <0 32 0>; > + }; > + }; [snip] > + > + dwmmc_0: dwmmc0 at 12140000 { Please use generic "mmc@" names for MMC nodes and move fifo-depth property here to SoC-level dtsi. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC 2013-12-10 17:10 ` Tomasz Figa @ 2014-01-06 9:40 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-06 9:40 UTC (permalink / raw) To: Tomasz Figa Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Hi Tomasz, On 10 December 2013 22:40, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Pankaj, Rahul, Arun, > > Please split generic SoC dtsi files and board dts files into separate > patches. Also please see my comments inline. I will split them to SoC and Board DT patches. > > On Friday 06 of December 2013 21:26:27 Rahul Sharma wrote: >> From: Arun Kumar K <arun.kk@samsung.com> >> >> The patch adds the dts files for exynos5260 and for xyref >> evt0 board. > [snip] >> + gpx0: gpx0 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; > > Just to make sure, all your GPX banks are muxed type, with wake-up > interrupts muxed to a single GIC interrupt line, right? There is no combiner in 5260. Each GPX bank is connected one GIC interrupt line. > >> + }; > [snip] >> + cam_gpio_a: cam-gpio-a { >> + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", >> + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", >> + "gpe1-0", "gpe1-1"; >> + samsung,pin-function = <2>; > > Incorrect indentation. > Done. >> + samsung,pin-pud = <0>; >> + samsung,pin-drv = <0>; >> + }; > [snip] >> + hdmi_hpd_irq: hdmi-hpd-irq { >> + samsung,pins = "gpx3-7"; >> + samsung,pin-function = <0>; > > Function 0 is input, not a special function. It shouldn't be handled > this way. If a board needs to set up pull-up/down and driver strength > for GPIO pins then it should add its own board-specific pinconf nodes > with just pin-pud and/or pin-drv properties and without pin-function. I moved this node to Board file. I hope that is correct. > >> + samsung,pin-pud = <1>; >> + samsung,pin-drv = <0>; >> + }; >> + }; > [snip] >> + sd0_bus1: sd0-bus-width1 { >> + samsung,pins = "gpc0-3"; >> + samsung,pin-function = <2>; >> + samsung,pin-pud = <3>; >> + samsung,pin-drv = <3>; >> + }; >> + >> + sd0_bus4: sd0-bus-width4 { >> + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; >> + samsung,pin-function = <2>; >> + samsung,pin-pud = <3>; >> + samsung,pin-drv = <3>; >> + }; >> + >> + sd0_bus8: sd0-bus-width8 { >> + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; >> + samsung,pin-function = <2>; >> + samsung,pin-pud = <3>; >> + samsung,pin-drv = <3>; >> + }; > > This is inconsistent. To specify 1- and 4-bit SD busses you need to > include reference to just one pinconf node (sd0_bus1 or sd0_bus4), but > for 8-bit bus you need to specify both sd0_bus4 and sd0_bus8. > > Please make the nodes exclusive, so you always need to specify all > possible configurations with given wiring (e.g. with 4 wires, you can > run in 1-bit and 4-bit modes, not just 4-bit). > Ok. I will remove "gpc0-3" from sdX_bus4. > Same for remaining instances of SD bus. > > [snip] > >> diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts >> new file mode 100644 >> index 0000000..aa1fcda >> --- /dev/null >> +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts >> @@ -0,0 +1,85 @@ >> +/* >> + * SAMSUNG XYREF5260 EVT0 board device tree source >> + * >> + * Copyright (c) 2013 Samsung Electronics Co., Ltd. >> + * http://www.samsung.com >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> +*/ >> + >> +/dts-v1/; >> +#include "exynos5260.dtsi" >> + >> +/ { >> + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260"; >> + compatible = "samsung,xyref5260", "samsung,exynos5260"; >> + > > Shouldn't you have a memory node here? I added memory node here. > >> + chosen { >> + bootargs = "console=ttySAC2,115200"; >> + }; >> + >> + fixed-rate-clocks { >> + oscclk { >> + compatible = "samsung,exynos5260-oscclk"; >> + clock-frequency = <24000000>; >> + }; >> + }; > > Please use generic fixed clock bindings. You can take [1] as an example > how to use them. > > [1] arch/arm/boot/dts/s3c6410-smdk6410.dtsi Ok. I will changes this. > >> + >> + serial@12C00000 { >> + status = "okay"; >> + }; >> + >> + serial@12C10000 { >> + status = "okay"; >> + }; >> + >> + serial@12C20000 { >> + status = "okay"; >> + }; >> + >> + serial@12860000 { > > Is it the correct UART address? It seems a bit off compared to addresses > of other ports. > This is correct. >> + status = "okay"; >> + }; >> + >> + dwmmc0@12140000 { >> + status = "okay"; >> + num-slots = <1>; >> + broken-cd; >> + bypass-smu; > > This is not a valid property, according to binding documentation. > >> + supports-highspeed; >> + supports-hs200-mode; /* 200 Mhz */ > > Neither is this one. > >> + fifo-depth = <0x40>; > > This is a property of the SoC, not the board. > >> + card-detect-delay = <200>; >> + samsung,dw-mshc-ciu-div = <3>; >> + samsung,dw-mshc-sdr-timing = <0 4>; >> + samsung,dw-mshc-ddr-timing = <0 2>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; >> + >> + slot@0 { >> + reg = <0>; >> + bus-width = <8>; >> + }; >> + }; >> + >> + dwmmc2@12160000 { >> + status = "okay"; >> + num-slots = <1>; >> + supports-highspeed; >> + fifo-depth = <0x40>; > > See above. I will remove them. These are optional properties which are not being referred in the mainline driver. > >> + card-detect-delay = <200>; >> + samsung,dw-mshc-ciu-div = <3>; >> + samsung,dw-mshc-sdr-timing = <2 3>; >> + samsung,dw-mshc-ddr-timing = <1 2>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >> + >> + slot@0 { >> + reg = <0>; >> + bus-width = <4>; >> + disable-wp; >> + }; >> + }; >> +}; >> diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi >> new file mode 100644 >> index 0000000..fcb8d4f >> --- /dev/null >> +++ b/arch/arm/boot/dts/exynos5260.dtsi >> @@ -0,0 +1,315 @@ >> +/* >> + * SAMSUNG EXYNOS5260 SoC device tree source >> + * >> + * Copyright (c) 2013 Samsung Electronics Co., Ltd. >> + * http://www.samsung.com >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> +*/ >> + >> +#include "skeleton.dtsi" >> +#include "exynos5260-pinctrl.dtsi" >> + >> +#include <dt-bindings/clk/exynos5260-clk.h> > > This won't compile, because this file hasn't been added yet by previous > patches. > I will reorder the patches to ensure build doesn't break. > Isn't it possible to reuse some of the definitions from exynos5.dtsi? How > much different is this SoC from other SoCs from the series? It is quite different than other Exynos5 SoCs specially the physical address of the IPs. > >> + >> +/ { >> + compatible = "samsung,exynos5260"; >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + pinctrl0 = &pinctrl_0; >> + pinctrl1 = &pinctrl_1; >> + pinctrl2 = &pinctrl_2; >> + }; >> + >> + chipid@10000000 { >> + compatible = "samsung,exynos4210-chipid"; >> + reg = <0x10000000 0x100>; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a15"; >> + reg = <0>; >> + cci-control-port = <&cci_control1>; >> + }; >> + cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a15"; >> + reg = <1>; >> + cci-control-port = <&cci_control1>; >> + }; >> + cpu@2 { > > @unit-address suffix must match the first entry of reg property. Ok. I will change this. > >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0x100>; >> + cci-control-port = <&cci_control0>; >> + }; >> + cpu@3 { > > Ditto. > >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0x101>; >> + cci-control-port = <&cci_control0>; >> + }; >> + cpu@4 { > > Ditto. > >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0x102>; >> + cci-control-port = <&cci_control0>; >> + }; >> + cpu@5 { > > Ditto. > >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0x103>; >> + cci-control-port = <&cci_control0>; >> + }; >> + }; >> + >> + cmus { > > You need compatible = "simple-bus" here if you need the nodes below > to be instantiated. > > However I'm not sure if there is a point in placing them inside > a simple-bus. This needs more thought, so please give me a bit > more time to think over this and patches 4 and 7. Please let me know if you have a better solution. > >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + cmu_top: clock-controller@0x10010000 { > > coding style: There should be no 0x prefix in @unit-address suffix. ok. Done. > + all the CMU instances below. > > [snip] >> + >> + gic:interrupt-controller@10481000 { > > coding style: There should be a space after the colon ending the label. > Done. >> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; >> + #size-cells = <0>; >> + interrupt-controller; >> + reg = <0x10481000 0x1000>, >> + <0x10482000 0x1000>, >> + <0x10484000 0x2000>, >> + <0x10486000 0x2000>; >> + interrupts = <1 9 0xf04>; >> + }; >> + >> + mct@100B0000 { >> + compatible = "samsung,exynos4210-mct"; >> + reg = <0x100B0000 0xb00>; > > nit: Inconsistent hexadecimal character case, on Exynos in dts* files > upper case should be used. > > Also the reg size looks a bit suspicious, as it's not even page aligned. > Is it the whole area used by the MCT block, not just the used registers? > Done. >> + interrupt-controller; > > MCT is not an interrupt controller. > >> + #interrups-cells = <2>; > > Ditto. This is a property specific to interrupt controllers. > >> + interrupt-parent = <&mct_map>; >> + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, >> + <4 0>, <5 0>, <6 0>, <7 0>, >> + <8 0>, <9 0>, <10 0>, <11 0>; >> + clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>; >> + clock-names = "fin_pll", "mct"; >> + >> + mct_map: mct-map { >> + #interrupt-cells = <2>; > > Why two cells are needed? Using just one woudl simplify interrupt > specifiers above and interrupt-map specifiers below. > Done. >> + #address-cells = <0>; >> + #size-cells = <0>; >> + interrupt-map = <0x0 0 &gic 0 104 0>, >> + <0x1 0 &gic 0 105 0>, >> + <0x2 0 &gic 0 106 0>, >> + <0x3 0 &gic 0 107 0>, >> + <0x4 0 &gic 0 122 0>, >> + <0x5 0 &gic 0 123 0>, >> + <0x6 0 &gic 0 124 0>, >> + <0x7 0 &gic 0 125 0>, >> + <0x8 0 &gic 0 126 0>, >> + <0x9 0 &gic 0 127 0>, >> + <0xa 0 &gic 0 128 0>, >> + <0xb 0 &gic 0 129 0>; >> + }; >> + }; >> + >> + cci@10F00000 { >> + compatible = "arm,cci-400"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + reg = <0x10F00000 0x1000>; >> + ranges = <0x0 0x10F00000 0x6000>; >> + >> + cci_control0: slave-if@4000 { /* Please check again */ > > Huh? Please check again and send correct data. > >> + compatible = "arm,cci-400-ctrl-if"; >> + interface-type = "ace"; >> + reg = <0x4000 0x1000>; /* Please check again */ >> + }; >> + >> + cci_control1: slave-if@5000 { /* Please check again */ >> + compatible = "arm,cci-400-ctrl-if"; >> + interface-type = "ace"; >> + reg = <0x5000 0x1000>; /* Please check again */ >> + }; >> + }; >> + >> + pinctrl_0: pinctrl@11600000 { >> + compatible = "samsung,exynos5260-pinctrl"; >> + reg = <0x11600000 0x1000>; >> + interrupts = <0 79 0>; /* GPIO_RT */ > > Instead of using such comment, maybe it would be better to rename > labels of pinctrl nodes to be more meaningful, such as pinctrl_rt, > pinctrl_fsys and pinctrl_aud? I removed the comments. > >> + >> + wakeup-interrupt-controller { >> + compatible = "samsung,exynos4210-wakeup-eint"; >> + interrupt-parent = <&gic>; >> + interrupts = <0 32 0>; >> + }; >> + }; > [snip] >> + >> + dwmmc_0: dwmmc0@12140000 { > > Please use generic "mmc@" names for MMC nodes and move fifo-depth property > here to SoC-level dtsi. Done. Regards, Rahul Sharma. > > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC @ 2014-01-06 9:40 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-06 9:40 UTC (permalink / raw) To: linux-arm-kernel Hi Tomasz, On 10 December 2013 22:40, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Pankaj, Rahul, Arun, > > Please split generic SoC dtsi files and board dts files into separate > patches. Also please see my comments inline. I will split them to SoC and Board DT patches. > > On Friday 06 of December 2013 21:26:27 Rahul Sharma wrote: >> From: Arun Kumar K <arun.kk@samsung.com> >> >> The patch adds the dts files for exynos5260 and for xyref >> evt0 board. > [snip] >> + gpx0: gpx0 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; > > Just to make sure, all your GPX banks are muxed type, with wake-up > interrupts muxed to a single GIC interrupt line, right? There is no combiner in 5260. Each GPX bank is connected one GIC interrupt line. > >> + }; > [snip] >> + cam_gpio_a: cam-gpio-a { >> + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", >> + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", >> + "gpe1-0", "gpe1-1"; >> + samsung,pin-function = <2>; > > Incorrect indentation. > Done. >> + samsung,pin-pud = <0>; >> + samsung,pin-drv = <0>; >> + }; > [snip] >> + hdmi_hpd_irq: hdmi-hpd-irq { >> + samsung,pins = "gpx3-7"; >> + samsung,pin-function = <0>; > > Function 0 is input, not a special function. It shouldn't be handled > this way. If a board needs to set up pull-up/down and driver strength > for GPIO pins then it should add its own board-specific pinconf nodes > with just pin-pud and/or pin-drv properties and without pin-function. I moved this node to Board file. I hope that is correct. > >> + samsung,pin-pud = <1>; >> + samsung,pin-drv = <0>; >> + }; >> + }; > [snip] >> + sd0_bus1: sd0-bus-width1 { >> + samsung,pins = "gpc0-3"; >> + samsung,pin-function = <2>; >> + samsung,pin-pud = <3>; >> + samsung,pin-drv = <3>; >> + }; >> + >> + sd0_bus4: sd0-bus-width4 { >> + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; >> + samsung,pin-function = <2>; >> + samsung,pin-pud = <3>; >> + samsung,pin-drv = <3>; >> + }; >> + >> + sd0_bus8: sd0-bus-width8 { >> + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; >> + samsung,pin-function = <2>; >> + samsung,pin-pud = <3>; >> + samsung,pin-drv = <3>; >> + }; > > This is inconsistent. To specify 1- and 4-bit SD busses you need to > include reference to just one pinconf node (sd0_bus1 or sd0_bus4), but > for 8-bit bus you need to specify both sd0_bus4 and sd0_bus8. > > Please make the nodes exclusive, so you always need to specify all > possible configurations with given wiring (e.g. with 4 wires, you can > run in 1-bit and 4-bit modes, not just 4-bit). > Ok. I will remove "gpc0-3" from sdX_bus4. > Same for remaining instances of SD bus. > > [snip] > >> diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts >> new file mode 100644 >> index 0000000..aa1fcda >> --- /dev/null >> +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts >> @@ -0,0 +1,85 @@ >> +/* >> + * SAMSUNG XYREF5260 EVT0 board device tree source >> + * >> + * Copyright (c) 2013 Samsung Electronics Co., Ltd. >> + * http://www.samsung.com >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> +*/ >> + >> +/dts-v1/; >> +#include "exynos5260.dtsi" >> + >> +/ { >> + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260"; >> + compatible = "samsung,xyref5260", "samsung,exynos5260"; >> + > > Shouldn't you have a memory node here? I added memory node here. > >> + chosen { >> + bootargs = "console=ttySAC2,115200"; >> + }; >> + >> + fixed-rate-clocks { >> + oscclk { >> + compatible = "samsung,exynos5260-oscclk"; >> + clock-frequency = <24000000>; >> + }; >> + }; > > Please use generic fixed clock bindings. You can take [1] as an example > how to use them. > > [1] arch/arm/boot/dts/s3c6410-smdk6410.dtsi Ok. I will changes this. > >> + >> + serial at 12C00000 { >> + status = "okay"; >> + }; >> + >> + serial at 12C10000 { >> + status = "okay"; >> + }; >> + >> + serial at 12C20000 { >> + status = "okay"; >> + }; >> + >> + serial at 12860000 { > > Is it the correct UART address? It seems a bit off compared to addresses > of other ports. > This is correct. >> + status = "okay"; >> + }; >> + >> + dwmmc0 at 12140000 { >> + status = "okay"; >> + num-slots = <1>; >> + broken-cd; >> + bypass-smu; > > This is not a valid property, according to binding documentation. > >> + supports-highspeed; >> + supports-hs200-mode; /* 200 Mhz */ > > Neither is this one. > >> + fifo-depth = <0x40>; > > This is a property of the SoC, not the board. > >> + card-detect-delay = <200>; >> + samsung,dw-mshc-ciu-div = <3>; >> + samsung,dw-mshc-sdr-timing = <0 4>; >> + samsung,dw-mshc-ddr-timing = <0 2>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; >> + >> + slot at 0 { >> + reg = <0>; >> + bus-width = <8>; >> + }; >> + }; >> + >> + dwmmc2 at 12160000 { >> + status = "okay"; >> + num-slots = <1>; >> + supports-highspeed; >> + fifo-depth = <0x40>; > > See above. I will remove them. These are optional properties which are not being referred in the mainline driver. > >> + card-detect-delay = <200>; >> + samsung,dw-mshc-ciu-div = <3>; >> + samsung,dw-mshc-sdr-timing = <2 3>; >> + samsung,dw-mshc-ddr-timing = <1 2>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >> + >> + slot at 0 { >> + reg = <0>; >> + bus-width = <4>; >> + disable-wp; >> + }; >> + }; >> +}; >> diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi >> new file mode 100644 >> index 0000000..fcb8d4f >> --- /dev/null >> +++ b/arch/arm/boot/dts/exynos5260.dtsi >> @@ -0,0 +1,315 @@ >> +/* >> + * SAMSUNG EXYNOS5260 SoC device tree source >> + * >> + * Copyright (c) 2013 Samsung Electronics Co., Ltd. >> + * http://www.samsung.com >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> +*/ >> + >> +#include "skeleton.dtsi" >> +#include "exynos5260-pinctrl.dtsi" >> + >> +#include <dt-bindings/clk/exynos5260-clk.h> > > This won't compile, because this file hasn't been added yet by previous > patches. > I will reorder the patches to ensure build doesn't break. > Isn't it possible to reuse some of the definitions from exynos5.dtsi? How > much different is this SoC from other SoCs from the series? It is quite different than other Exynos5 SoCs specially the physical address of the IPs. > >> + >> +/ { >> + compatible = "samsung,exynos5260"; >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + pinctrl0 = &pinctrl_0; >> + pinctrl1 = &pinctrl_1; >> + pinctrl2 = &pinctrl_2; >> + }; >> + >> + chipid at 10000000 { >> + compatible = "samsung,exynos4210-chipid"; >> + reg = <0x10000000 0x100>; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu at 0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a15"; >> + reg = <0>; >> + cci-control-port = <&cci_control1>; >> + }; >> + cpu at 1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a15"; >> + reg = <1>; >> + cci-control-port = <&cci_control1>; >> + }; >> + cpu at 2 { > > @unit-address suffix must match the first entry of reg property. Ok. I will change this. > >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0x100>; >> + cci-control-port = <&cci_control0>; >> + }; >> + cpu at 3 { > > Ditto. > >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0x101>; >> + cci-control-port = <&cci_control0>; >> + }; >> + cpu at 4 { > > Ditto. > >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0x102>; >> + cci-control-port = <&cci_control0>; >> + }; >> + cpu at 5 { > > Ditto. > >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0x103>; >> + cci-control-port = <&cci_control0>; >> + }; >> + }; >> + >> + cmus { > > You need compatible = "simple-bus" here if you need the nodes below > to be instantiated. > > However I'm not sure if there is a point in placing them inside > a simple-bus. This needs more thought, so please give me a bit > more time to think over this and patches 4 and 7. Please let me know if you have a better solution. > >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + cmu_top: clock-controller at 0x10010000 { > > coding style: There should be no 0x prefix in @unit-address suffix. ok. Done. > + all the CMU instances below. > > [snip] >> + >> + gic:interrupt-controller at 10481000 { > > coding style: There should be a space after the colon ending the label. > Done. >> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; >> + #size-cells = <0>; >> + interrupt-controller; >> + reg = <0x10481000 0x1000>, >> + <0x10482000 0x1000>, >> + <0x10484000 0x2000>, >> + <0x10486000 0x2000>; >> + interrupts = <1 9 0xf04>; >> + }; >> + >> + mct at 100B0000 { >> + compatible = "samsung,exynos4210-mct"; >> + reg = <0x100B0000 0xb00>; > > nit: Inconsistent hexadecimal character case, on Exynos in dts* files > upper case should be used. > > Also the reg size looks a bit suspicious, as it's not even page aligned. > Is it the whole area used by the MCT block, not just the used registers? > Done. >> + interrupt-controller; > > MCT is not an interrupt controller. > >> + #interrups-cells = <2>; > > Ditto. This is a property specific to interrupt controllers. > >> + interrupt-parent = <&mct_map>; >> + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, >> + <4 0>, <5 0>, <6 0>, <7 0>, >> + <8 0>, <9 0>, <10 0>, <11 0>; >> + clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>; >> + clock-names = "fin_pll", "mct"; >> + >> + mct_map: mct-map { >> + #interrupt-cells = <2>; > > Why two cells are needed? Using just one woudl simplify interrupt > specifiers above and interrupt-map specifiers below. > Done. >> + #address-cells = <0>; >> + #size-cells = <0>; >> + interrupt-map = <0x0 0 &gic 0 104 0>, >> + <0x1 0 &gic 0 105 0>, >> + <0x2 0 &gic 0 106 0>, >> + <0x3 0 &gic 0 107 0>, >> + <0x4 0 &gic 0 122 0>, >> + <0x5 0 &gic 0 123 0>, >> + <0x6 0 &gic 0 124 0>, >> + <0x7 0 &gic 0 125 0>, >> + <0x8 0 &gic 0 126 0>, >> + <0x9 0 &gic 0 127 0>, >> + <0xa 0 &gic 0 128 0>, >> + <0xb 0 &gic 0 129 0>; >> + }; >> + }; >> + >> + cci at 10F00000 { >> + compatible = "arm,cci-400"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + reg = <0x10F00000 0x1000>; >> + ranges = <0x0 0x10F00000 0x6000>; >> + >> + cci_control0: slave-if at 4000 { /* Please check again */ > > Huh? Please check again and send correct data. > >> + compatible = "arm,cci-400-ctrl-if"; >> + interface-type = "ace"; >> + reg = <0x4000 0x1000>; /* Please check again */ >> + }; >> + >> + cci_control1: slave-if at 5000 { /* Please check again */ >> + compatible = "arm,cci-400-ctrl-if"; >> + interface-type = "ace"; >> + reg = <0x5000 0x1000>; /* Please check again */ >> + }; >> + }; >> + >> + pinctrl_0: pinctrl at 11600000 { >> + compatible = "samsung,exynos5260-pinctrl"; >> + reg = <0x11600000 0x1000>; >> + interrupts = <0 79 0>; /* GPIO_RT */ > > Instead of using such comment, maybe it would be better to rename > labels of pinctrl nodes to be more meaningful, such as pinctrl_rt, > pinctrl_fsys and pinctrl_aud? I removed the comments. > >> + >> + wakeup-interrupt-controller { >> + compatible = "samsung,exynos4210-wakeup-eint"; >> + interrupt-parent = <&gic>; >> + interrupts = <0 32 0>; >> + }; >> + }; > [snip] >> + >> + dwmmc_0: dwmmc0 at 12140000 { > > Please use generic "mmc@" names for MMC nodes and move fifo-depth property > here to SoC-level dtsi. Done. Regards, Rahul Sharma. > > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 7/7] clk/exynos5260: add clock file for exynos5260 [not found] ` <1386345391-23482-1-git-send-email-rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-06 15:56 ` Rahul Sharma 1 sibling, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: mturquette-QSEj5FYQhm4dnm+yROfE0A, kgene.kim-Sze3O3UU22JBDgjK7y7TUQ, thomas.ab-Sze3O3UU22JBDgjK7y7TUQ, tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w, joshi-Sze3O3UU22JBDgjK7y7TUQ, pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ, yg1004.jang-Sze3O3UU22JBDgjK7y7TUQ, arun.kk-Sze3O3UU22JBDgjK7y7TUQ, r.sh.open-Re5JQEeQqe8AvxtiuMwx3w, Rahul Sharma Add support for exynos5260 clocks in clock driver. Signed-off-by: Rahul Sharma <rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Signed-off-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Signed-off-by: Young-Gun Jang <yg1004.jang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> --- .../devicetree/bindings/clock/exynos5260-clock.txt | 228 ++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5260.c | 2661 ++++++++++++++++++++ drivers/clk/samsung/clk-exynos5260.h | 496 ++++ include/dt-bindings/clk/exynos5260-clk.h | 169 ++ 5 files changed, 3555 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h create mode 100644 include/dt-bindings/clk/exynos5260-clk.h diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file mode 100644 index 0000000..b5c021c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt @@ -0,0 +1,228 @@ +* Samsung Exynos5260 Clock Controller + +The Exynos5260 clock controller encalsulate all CMUs which are +instantiaited independently from the device-tree. As a whole, +these CMUs generates and supplies clocks to various controllers +within the Exynos5260 SoC. + +Required Properties: + +- compatible: should be one of the following. + - First compatible should be one of the following + "exynos5260-cmu-all" + "exynos5260-cmu-top" + "exynos5260-cmu-peri" + "exynos5260-cmu-egl" + "exynos5260-cmu-kfc" + "exynos5260-cmu-g2d" + "exynos5260-cmu-mif" + "exynos5260-cmu-mfc" + "exynos5260-cmu-g3d" + "exynos5260-cmu-fsys" + "exynos5260-cmu-aud" + "exynos5260-cmu-isp" + "exynos5260-cmu-gscl" + "exynos5260-cmu-disp" + - Second compatible should be "samsung,exynos5260-clock". + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the each controller. Each +clock is assigned a MACRO constant. These constants are defined in +"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to specify +the clock which they consume. + +----------------------- + CMU_TOP clocks +----------------------- + + FIN_PLL + TOP_FOUT_DISP_PLL + TOP_FOUT_AUD_PLL + TOP_SCLK_MMC0 + TOP_SCLK_MMC1 + TOP_SCLK_MMC2 + TOP_SCLK_HDMIPHY + TOP_SCLK_FIMD1 + TOP_MOUT_FIMD1 + TOP_MOUT_DISP_PLL + +----------------------- + CMU_EGL clocks +----------------------- + + EGL_FOUT_EGL_PLL + EGL_FOUT_EGL_DPLL + +----------------------- + CMU_KFC clocks +----------------------- + + KFC_FOUT_KFC_PLL + +----------------------- + CMU_MIF clocks +----------------------- + + MIF_FOUT_MEM_PLL + MIF_FOUT_BUS_PLL + MIF_FOUT_MEDIA_PLL + +----------------------- + CMU_G3D clocks +----------------------- + + G3D_FOUT_G3D_PLL + G3D_ACLK_G3D + +----------------------- + CMU_AUD clocks +----------------------- + + AUD_SCLK_AUD_UART + AUD_SCLK_PCM + AUD_ACLK_SRAMC + AUD_ACLK_DMAC + AUD_PCLK_AUD_UART + AUD_PCLK_PCM + AUD_PCLK_I2S + AUD_PCLK_DMAC + +----------------------- + CMU_MFC clocks +----------------------- + + MFC_ACLK_MFC + MFC_PCLK_MFC + MFC_PCLK_SMMU_MFC0 + MFC_PCLK_SMMU_MFC1 + +----------------------- + CMU_GSCL clocks +----------------------- + + GSCL_ACLK_GSCL0 + GSCL_ACLK_GSCL1 + GSCL_PCLK_GSCL0 + GSCL_PCLK_GSCL1 + GSCL_PCLK_SMMU_GSCL0 + GSCL_PCLK_SMMU_GSCL1 + +----------------------- + CMU_FSYS clocks +----------------------- + + FSYS_HCLK_TSI + FSYS_PCLK_GPIO + FSYS_HCLK_USBHOST20 + FSYS_ACLK_USBDRD30 + FSYS_ACLK_PDMA0 + FSYS_ACLK_RTIC + FSYS_PCLK_SMMU_RTIC + FSYS_PHYCLK_USBDRD30 + FSYS_PHYCLK_USBHOST20 + FSYS_HCLK_MMC0 + FSYS_HCLK_MMC1 + FSYS_HCLK_MMC2 + FSYS_HCLK_SROMC + +----------------------- + CMU_PERI clocks +----------------------- + + PERI_PCLK_ADC + PERI_PCLK_TMU1 + PERI_PCLK_TMU0 + PERI_PCLK_SPI0 + PERI_PCLK_SPI1 + PERI_PCLK_SPI2 + PERI_PCLK_I2S1 + PERI_PCLK_PWM + PERI_PCLK_SPDIF + PERI_PCLK_ABB + PERI_PCLK_MCT + PERI_PCLK_HSIC0 + PERI_PCLK_HSIC1 + PERI_PCLK_HSIC2 + PERI_PCLK_HSIC3 + PERI_PCLK_UART0 + PERI_PCLK_UART1 + PERI_PCLK_UART2 + PERI_PCLK_PCM1 + PERI_PCLK_WDT_EGL + PERI_PCLK_WDT_KFC + PERI_PCLK_CHIPID + PERI_CLK_TMU0 + PERI_CLK_TMU1 + PERI_CLK_TMU2 + PERI_CLK_TMU3 + PERI_CLK_TMU4 + PERI_PCLK_I2C4 + PERI_PCLK_I2C5 + PERI_PCLK_I2C6 + PERI_PCLK_I2C7 + PERI_PCLK_I2C8 + PERI_PCLK_I2C9 + PERI_PCLK_I2C10 + PERI_PCLK_I2C11 + PERI_PCLK_TOP_RTC + PERI_SCLK_RTC + PERI_SCLK_UART0 + PERI_SCLK_UART1 + PERI_SCLK_UART2 + PERI_SCLK_SPDIF + PERI_SCLK_SPI0 + PERI_SCLK_SPI1 + PERI_SCLK_SPI2 + PERI_SCLK_I2S + PERI_SCLK_PCM1 + +----------------------- + CMU_DISP clocks +----------------------- + + DISP_SCLK_HDMI + DISP_SCLK_PIXEL + DISP_ACLK_MIXER + DISP_ACLK_HDMI + DISP_ACLK_FIMD1 + DISP_PCLK_SMMU_TV + DISP_PCLK_SMMU_FIMD1M1 + DISP_PCLK_SMMU_FIMD1M0 + DISP_PCLK_DSIM1 + DISP_PCLK_HDMIPHY + DISP_PCLK_HDMI + DISP_DP + DISP_MOUT_HDMI_PHY_PIXEL + +----------------------- + CMU_G2D clocks +----------------------- + + G2D_ACLK_MDMA + G2D_NR_CLK + +Example 1: An example of a clock controller node is listed below. + + cmu_disp: clock-controller@0x14550000 { + compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock"; + reg = <0x14550000 0x10000>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the + peri clock controller. Refer to the standard clock bindings for + information about 'clocks' and 'clock-names' property. + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 146 0>; + clocks = <&cmu_peri PERI_PCLK_UART0>, <&cmu_peri PERI_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..f791b31 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c new file mode 100644 index 0000000..c5814ad --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -0,0 +1,2661 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5260 SoC. +*/ + +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/syscore_ops.h> + +#include "clk-exynos5260.h" +#include "clk.h" +#include "clk-pll.h" + +#include <dt-bindings/clk/exynos5260-clk.h> + +static LIST_HEAD(clock_reg_cache_list); + +struct exynos5260_clock_reg_cache { + struct list_head node; + void __iomem *reg_base; + struct samsung_clk_reg_dump *rdump; + unsigned int rd_num; +}; + +#ifdef CONFIG_PM_SLEEP + +/* + * list of controller registers to be saved and restored during a + * suspend/resume cycle. +*/ + +static struct samsung_clk_reg_dump exynos5260_aud_clk_regs[] __initdata = { +/* + *Registers for CMU_AUD +*/ + { MUX_SEL_AUD, 0}, + { DIV_AUD0, 0}, + { DIV_AUD1, 0}, + { EN_ACLK_AUD, 0}, + { EN_PCLK_AUD, 0}, + { EN_SCLK_AUD, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_disp_clk_regs[] __initdata = { +/* + *Registers for CMU_DISP +*/ + { MUX_SEL_DISP0, 0}, + { MUX_SEL_DISP1, 0}, + { MUX_SEL_DISP2, 0}, + { MUX_SEL_DISP3, 0}, + { MUX_SEL_DISP4, 0}, + { DIV_DISP, 0}, + { EN_ACLK_DISP, 0}, + { EN_PCLK_DISP, 0}, + { EN_SCLK_DISP0, 0}, + { EN_SCLK_DISP1, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_egl_clk_regs[] __initdata = { +/* + *Registers for CMU_EGL +*/ + { EGL_PLL_LOCK, 0}, + { EGL_PLL_CON0, 0}, + { EGL_PLL_CON1, 0}, + { EGL_PLL_FREQ_DET, 0}, + + { MUX_SEL_EGL, 0}, + { MUX_ENABLE_EGL, 0}, + { DIV_EGL, 0}, + { DIV_EGL_PLL_FDET, 0}, + { EN_ACLK_EGL, 0}, + { EN_PCLK_EGL, 0}, + { EN_SCLK_EGL, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_fsys_clk_regs[] __initdata = { +/* + *Registers for CMU_FSYS +*/ + { MUX_SEL_FSYS0, 0}, + { MUX_SEL_FSYS1, 0}, + { EN_ACLK_FSYS, 0}, + { EN_ACLK_FSYS_SECURE_RTIC, 0}, + { EN_ACLK_FSYS_SECURE_SMMU_RTIC, 0}, + { EN_SCLK_FSYS, 0}, + { EN_IP_FSYS, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_g2d_clk_regs[] __initdata = { +/* + *Registers for CMU_G2D +*/ + { MUX_SEL_G2D, 0}, + { MUX_STAT_G2D, 0}, + { DIV_G2D, 0}, + { EN_ACLK_G2D, 0}, + { EN_ACLK_G2D_SECURE_SSS, 0}, + { EN_ACLK_G2D_SECURE_SLIM_SSS, 0}, + { EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS, 0}, + { EN_ACLK_G2D_SECURE_SMMU_SSS, 0}, + { EN_ACLK_G2D_SECURE_SMMU_MDMA, 0}, + { EN_ACLK_G2D_SECURE_SMMU_G2D, 0}, + { EN_PCLK_G2D, 0}, + { EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS, 0}, + { EN_PCLK_G2D_SECURE_SMMU_SSS, 0}, + { EN_PCLK_G2D_SECURE_SMMU_MDMA, 0}, + { EN_PCLK_G2D_SECURE_SMMU_G2D, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_g3d_clk_regs[] __initdata = { +/* + *Registers for CMU_G3D +*/ + { G3D_PLL_LOCK, 0}, + { G3D_PLL_CON0, 0}, + { G3D_PLL_CON1, 0}, + { G3D_PLL_FDET, 0}, + { MUX_SEL_G3D, 0}, + { DIV_G3D, 0}, + { DIV_G3D_PLL_FDET, 0}, + { EN_ACLK_G3D, 0}, + { EN_PCLK_G3D, 0}, + { EN_SCLK_G3D, 0}, + { EN_IP_G3D, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_gscl_clk_regs[] __initdata = { +/* + *Registers for CMU_GSCL +*/ + { MUX_SEL_GSCL, 0}, + { DIV_GSCL, 0}, + { EN_ACLK_GSCL, 0}, + { EN_ACLK_GSCL_FIMC, 0}, + { EN_ACLK_GSCL_SECURE_SMMU_GSCL0, 0}, + { EN_ACLK_GSCL_SECURE_SMMU_GSCL1, 0}, + { EN_ACLK_GSCL_SECURE_SMMU_MSCL0, 0}, + { EN_ACLK_GSCL_SECURE_SMMU_MSCL1, 0}, + { EN_PCLK_GSCL, 0}, + { EN_PCLK_GSCL_FIMC, 0}, + { EN_PCLK_GSCL_SECURE_SMMU_GSCL0, 0}, + { EN_PCLK_GSCL_SECURE_SMMU_GSCL1, 0}, + { EN_PCLK_GSCL_SECURE_SMMU_MSCL0, 0}, + { EN_PCLK_GSCL_SECURE_SMMU_MSCL1, 0}, + { EN_SCLK_GSCL, 0}, + { EN_SCLK_GSCL_FIMC, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_isp_clk_regs[] __initdata = { +/* + *Registers for CMU_ISP +*/ + { MUX_SEL_ISP0, 0}, + { MUX_SEL_ISP1, 0}, + { DIV_ISP, 0}, + { EN_ACLK_ISP0, 0}, + { EN_ACLK_ISP1, 0}, + { EN_PCLK_ISP0, 0}, + { EN_PCLK_ISP1, 0}, + { EN_SCLK_ISP, 0}, + { EN_IP_ISP0, 0}, + { EN_IP_ISP1, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_kfc_clk_regs[] __initdata = { +/* + *Registers for CMU_KFC +*/ + { KFC_PLL_LOCK, 0}, + { KFC_PLL_CON0, 0}, + { KFC_PLL_CON1, 0}, + { KFC_PLL_FDET, 0}, + { MUX_SEL_KFC0, 0}, + { MUX_SEL_KFC2, 0}, + { DIV_KFC, 0}, + { DIV_KFC_PLL_FDET, 0}, + { EN_ACLK_KFC, 0}, + { EN_PCLK_KFC, 0}, + { EN_SCLK_KFC, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_mfc_clk_regs[] __initdata = { +/* + *Registers for CMU_MFC +*/ + { MUX_SEL_MFC, 0}, + { DIV_MFC, 0}, + { EN_ACLK_MFC, 0}, + { EN_ACLK_SECURE_SMMU2_MFC, 0}, + { EN_PCLK_MFC, 0}, + { EN_PCLK_SECURE_SMMU2_MFC, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_mif_clk_regs[] __initdata = { +/* + *Registers for CMU_MIF +*/ + { MEM_PLL_LOCK, 0}, + { BUS_PLL_LOCK, 0}, + { MEDIA_PLL_LOCK, 0}, + { MEM_PLL_CON0, 0}, + { MEM_PLL_CON1, 0}, + { MEM_PLL_FDET, 0}, + { BUS_PLL_CON0, 0}, + { BUS_PLL_CON1, 0}, + { BUS_PLL_FDET, 0}, + { MEDIA_PLL_CON0, 0}, + { MEDIA_PLL_CON1, 0}, + { MEDIA_PLL_FDET, 0}, + { MUX_SEL_MIF, 0}, + { DIV_MIF, 0}, + { DIV_MIF_PLL_FDET, 0}, + { EN_ACLK_MIF, 0}, + { EN_ACLK_MIF_SECURE_DREX1_TZ, 0}, + { EN_ACLK_MIF_SECURE_DREX0_TZ, 0}, + { EN_ACLK_MIF_SECURE_INTMEM, 0}, + { EN_PCLK_MIF, 0}, + { EN_PCLK_MIF_SECURE_MONOCNT, 0}, + { EN_PCLK_MIF_SECURE_RTC_APBIF, 0}, + { EN_PCLK_MIF_SECURE_DREX1_TZ, 0}, + { EN_PCLK_MIF_SECURE_DREX0_TZ, 0}, + { EN_SCLK_MIF, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_peri_clk_regs[] __initdata = { +/* + *Registers for CMU_PERI +*/ + { MUX_SEL_PERI, 0}, + { MUX_SEL_PERI1, 0}, + { DIV_PERI, 0}, + { EN_PCLK_PERI0, 0}, + { EN_PCLK_PERI1, 0}, + { EN_PCLK_PERI2, 0}, + { EN_PCLK_PERI3, 0}, + { EN_PCLK_PERI_SECURE_CHIPID, 0}, + { EN_PCLK_PERI_SECURE_PROVKEY0, 0}, + { EN_PCLK_PERI_SECURE_PROVKEY1, 0}, + { EN_PCLK_PERI_SECURE_SECKEY, 0}, + { EN_PCLK_PERI_SECURE_ANTIRBKCNT, 0}, + { EN_PCLK_PERI_SECURE_TOP_RTC, 0}, + { EN_PCLK_PERI_SECURE_TZPC, 0}, + { EN_SCLK_PERI, 0}, + { EN_SCLK_PERI_SECURE_TOP_RTC, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_top_clk_regs[] __initdata = { +/* + *Registers for CMU_TOP +*/ + { DISP_PLL_LOCK, 0}, + { AUD_PLL_LOCK, 0}, + { DISP_PLL_CON0, 0}, + { DISP_PLL_CON1, 0}, + { DISP_PLL_FDET, 0}, + { AUD_PLL_CON0, 0}, + { AUD_PLL_CON1, 0}, + { AUD_PLL_CON2, 0}, + { AUD_PLL_FDET, 0}, + { MUX_SEL_TOP_PLL0, 0}, + { MUX_SEL_TOP_MFC, 0}, + { MUX_SEL_TOP_G2D, 0}, + { MUX_SEL_TOP_GSCL, 0}, + { MUX_SEL_TOP_ISP10, 0}, + { MUX_SEL_TOP_ISP11, 0}, + { MUX_SEL_TOP_DISP0, 0}, + { MUX_SEL_TOP_DISP1, 0}, + { MUX_SEL_TOP_BUS, 0}, + { MUX_SEL_TOP_PERI0, 0}, + { MUX_SEL_TOP_PERI1, 0}, + { MUX_SEL_TOP_FSYS, 0}, + { DIV_TOP_G2D_MFC, 0}, + { DIV_TOP_GSCL_ISP0, 0}, + { DIV_TOP_ISP10, 0}, + { DIV_TOP_ISP11, 0}, + { DIV_TOP_DISP, 0}, + { DIV_TOP_BUS, 0}, + { DIV_TOP_PERI0, 0}, + { DIV_TOP_PERI1, 0}, + { DIV_TOP_PERI2, 0}, + { DIV_TOP_FSYS0, 0}, + { DIV_TOP_FSYS1, 0}, + { DIV_TOP_HPM, 0}, + { DIV_TOP_PLL_FDET, 0}, + { EN_ACLK_TOP, 0}, + { EN_SCLK_TOP, 0}, +}; + +static int exynos5260_clk_suspend(void) +{ + struct exynos5260_clock_reg_cache *cache; + + list_for_each_entry(cache, &clock_reg_cache_list, node) + samsung_clk_save(cache->reg_base, cache->rdump, + cache->rd_num); + + return 0; +} + +static void exynos5260_clk_resume(void) +{ + struct exynos5260_clock_reg_cache *cache; + + list_for_each_entry(cache, &clock_reg_cache_list, node) + samsung_clk_restore(cache->reg_base, cache->rdump, + cache->rd_num); +} + +static struct syscore_ops exynos5260_clk_syscore_ops = { + .suspend = exynos5260_clk_suspend, + .resume = exynos5260_clk_resume, +}; + +static void exynos5260_clk_sleep_init(void __iomem *reg_base, + struct samsung_clk_reg_dump *rdump, + unsigned long nr_rdump) +{ + struct exynos5260_clock_reg_cache *reg_cache; + + reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache), + GFP_KERNEL); + if (!reg_cache) + panic("could not allocate register cache.\n"); + + reg_cache->reg_base = reg_base; + reg_cache->rdump = rdump; + reg_cache->rd_num = nr_rdump; + list_add_tail(®_cache->node, &clock_reg_cache_list); + + register_syscore_ops(&exynos5260_clk_syscore_ops); + + exynos5260_clk_suspend(); +} + +#else +static void exynos5260_clk_sleep_init(void) {} +#endif + +/* + * List of parent clocks for muses in CMU_AUD +*/ +PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_audcdclk0_user"}; +PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_audcdclk0_user"}; + +/* + * List of parent clocks for muses in CMU_DISP +*/ +PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch3_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch2_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch1_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch0_txd_clk"}; + +PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"}; +PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"}; +PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"}; +PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_tmds_clko"}; +PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_ref_clko"}; +PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_pixel_clko"}; +PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll", + "phyclk_hdmi_link_o_tmds_clkhi"}; +PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll", + "phyclk_mipi_dphy_4l_m_txbyte_clkhs"}; +PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll", + "phyclk_dptx_phy_o_ref_clk_24m"}; +PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll", + "phyclk_dptx_phy_clk_div2"}; +PNAME(mout_sclk_dsim1_tx_clk_esc_clk_user_p) = {"fin_pll", + "sclk_dsim1_txclkescclk"}; +PNAME(mout_sclk_dsim1_tx_clk_esc3_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc3"}; +PNAME(mout_sclk_dsim1_tx_clk_esc2_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc2"}; +PNAME(mout_sclk_dsim1_tx_clk_esc1_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc1"}; +PNAME(mout_sclk_dsim1_tx_clk_esc0_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc0"}; +PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user", + "mout_aclk_disp_222_user"}; +PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll", + "phyclk_mipi_dphy_4l_m_rxclkesc0"}; +PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", + "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; + +/* + * List of parent clocks for muses in CMU_EGL +*/ +PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; +PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; + +/* + * List of parent clocks for muses in CMU_FSYS +*/ +PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_phyclock"}; +PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_freeclk"}; +PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_clk48mohci"}; +PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll", + "phyclk_usbdrd30_udrd30_pipe_pclk"}; +PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", + "phyclk_usbdrd30_udrd30_phyclock"}; + +/* + * List of parent clocks for muses in CMU_G2D +*/ +PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; + +/* + * List of parent clocks for muses in CMU_G3D +*/ +PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; + +/* + * List of parent clocks for muses in CMU_GSCL +*/ +PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; +PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; +PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; + +/* + * List of parent clocks for muses in CMU_ISP +*/ +PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; +PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; + +/* + * List of parent clocks for muses in CMU_KFC +*/ +PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; +PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; + +/* + * List of parent clocks for muses in CMU_MFC +*/ +PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; + +/* + * List of parent clocks for muses in CMU_MIF +*/ +PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"}; +PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"}; +PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"}; +PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"}; +PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"}; +PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; +PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; + +/* + * List of parent clocks for muses in CMU_PERI +*/ +PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud", + "phyclk_hdmi_phy_ref_cko"}; +PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud", + "phyclk_hdmi_phy_ref_cko"}; +PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extlk", "fin_pll", + "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; + +/* + * List of parent clocks for muses in CMU_TOP +*/ +PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"}; +PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"}; +PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"}; +PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"}; +PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"}; + +PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"}; + +PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"}; + +PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user", + "mout_gscl_bustop_333"}; +PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user", + "mout_m2m_mediatop_400"}; +PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user", + "mout_gscl_bustop_fimc"}; + +PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user", + "mout_memtop_pll_user"}; +PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"}; +PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"}; + +PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"}; + +PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; +PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"}; +PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; +PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"}; +PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user", + "mout_bustop_pll_user"}; +PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"}; + +PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; +PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; + +PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"}; + +PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a", + "mout_mediatop_pll_user"}; +PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a", + "mout_mediatop_pll_user"}; +PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", + "mout_mediatop_pll_user"}; + +/* fixed rate clocks generated outside the soc */ +struct samsung_fixed_rate_clock exynos5260_fixed_rate_ext_clks[] __initdata = { + FRATE(FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "xrtcxti", NULL, CLK_IS_ROOT, 32768), + + FRATE(ID_NONE, "ioclk_audcdclk0_user", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_pcm_extclk", NULL, CLK_IS_ROOT, 2048000), + FRATE(ID_NONE, "ioclk_aud_i2s_bclk", NULL, CLK_IS_ROOT, 2048000), + FRATE(ID_NONE, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 49152000), + FRATE(ID_NONE, "ioclk_i2s_cdclk", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spdif_extlk", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_i2s_sclk", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi0_clkin", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi1_clkin", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi2_clkin", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_mmc0_sdrdqs_in", NULL, CLK_IS_ROOT, 200000000), + + FRATE(ID_NONE, "ioclk_spi0_isp_spi_clk_in", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi1_isp_spi_clk_in", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi0_isp_spi_clk_out", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi1_isp_spi_clk_out", NULL, + CLK_IS_ROOT, 50000000), +}; + +/* fixed rate clocks generated inside the soc */ +struct samsung_fixed_rate_clock exynos5260_fixed_rate_clks[] __initdata = { + FRATE(ID_NONE, "phyclk_dptx_phy_ch3_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch2_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch1_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch0_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_hdmi_phy_tmds_clko", NULL, + CLK_IS_ROOT, 250000000), + FRATE(TOP_SCLK_HDMIPHY, "phyclk_hdmi_phy_pixel_clko", NULL, + CLK_IS_ROOT, 1660000000), + FRATE(ID_NONE, "phyclk_hdmi_link_o_tmds_clkhi", NULL, + CLK_IS_ROOT, 125000000), + FRATE(ID_NONE, "phyclk_mipi_dphy_4l_m_txbyteclkhs", NULL, + CLK_IS_ROOT, 187500000), + FRATE(ID_NONE, "phyclk_dptx_phy_o_ref_clk_24m", NULL, + CLK_IS_ROOT, 24000000), + FRATE(ID_NONE, "phyclk_dptx_phy_clk_div2", NULL, + CLK_IS_ROOT, 135000000), + FRATE(ID_NONE, "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, + CLK_IS_ROOT, 20000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_phyclock", NULL, + CLK_IS_ROOT, 60000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_freeclk", NULL, + CLK_IS_ROOT, 60000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_clk48mohci", NULL, + CLK_IS_ROOT, 48000000), + FRATE(ID_NONE, "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, + CLK_IS_ROOT, 125000000), + FRATE(ID_NONE, "phyclk_usbdrd30_udrd30_phyclock", NULL, + CLK_IS_ROOT, 60000000), +}; + +struct samsung_fixed_factor_clock exynos5260_fixed_factor_clks[] __initdata = { +}; + +/* MULITPLEXER CLOCKS */ + +/* + * List of Mux clocks for CMU_AUD +*/ +struct samsung_mux_clock exynos5260_aud_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, + MUX_SEL_AUD, 8, 1), + MUX(ID_NONE, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, MUX_SEL_AUD, 4, + 1), + MUX(ID_NONE, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 0, + 1), +}; + +/* + * List of Mux clocks for CMU_DISP +*/ +struct samsung_mux_clock exynos5260_disp_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_hdmi_spdif", mout_sclk_hdmi_spdif_p, + MUX_SEL_DISP4, 4, 2), + + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc_clk_user", + mout_sclk_dsim1_tx_clk_esc_clk_user_p, + MUX_SEL_DISP2, 28, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc3_user", + mout_sclk_dsim1_tx_clk_esc3_user_p, MUX_SEL_DISP2, + 24, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc2_user", + mout_sclk_dsim1_tx_clk_esc2_user_p, MUX_SEL_DISP2, + 20, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc1_user", + mout_sclk_dsim1_tx_clk_esc1_user_p, MUX_SEL_DISP2, + 16, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc0_user", + mout_sclk_dsim1_tx_clk_esc0_user_p, MUX_SEL_DISP2, + 12, 1), + MUX(ID_NONE, "mout_sclk_hdmi_pixel", mout_sclk_hdmi_pixel_p, + MUX_SEL_DISP2, 4, 1), + MUX(ID_NONE, "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user", + mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p, + MUX_SEL_DISP2, 0, 1), + + MUX(ID_NONE, "mout_phyclk_hdmi_phy_tmds_clko_user", + mout_phyclk_hdmi_phy_tmds_clko_user_p, + MUX_SEL_DISP1, 28, 1), + MUX(ID_NONE, "mout_phyclk_hdmi_phy_ref_clko_user", + mout_phyclk_hdmi_phy_ref_clko_user_p, + MUX_SEL_DISP1, 24, 1), + MUX(DISP_MOUT_HDMI_PHY_PIXEL, "mout_phyclk_hdmi_phy_pixel_clko_user", + mout_phyclk_hdmi_phy_pixel_clko_user_p, + MUX_SEL_DISP1, 20, 1), + MUX(ID_NONE, "mout_phyclk_hdmi_link_o_tmds_clkhi_user", + mout_phyclk_hdmi_link_o_tmds_clkhi_user_p, + MUX_SEL_DISP1, 16, 1), + MUX(ID_NONE, "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs", + mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, + MUX_SEL_DISP1, 8, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_o_ref_clk_24m_user", + mout_phyclk_dptx_phy_o_ref_clk_24m_user_p, + MUX_SEL_DISP1, 4, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_clk_div2_user", + mout_phyclk_dptx_phy_clk_div2_user_p, + MUX_SEL_DISP1, 0, 1), + + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch3_txd_clk_user", + mout_phyclk_dptx_phy_ch3_txd_clk_user_p, + MUX_SEL_DISP0, 28, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch2_txd_clk_user", + mout_phyclk_dptx_phy_ch2_txd_clk_user_p, + MUX_SEL_DISP0, 24, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch1_txd_clk_user", + mout_phyclk_dptx_phy_ch1_txd_clk_user_p, + MUX_SEL_DISP0, 20, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch0_txd_clk_user", + mout_phyclk_dptx_phy_ch0_txd_clk_user_p, + MUX_SEL_DISP0, 16, 1), + MUX(ID_NONE, "mout_aclk_disp_222_user", mout_aclk_disp_222_user_p, + MUX_SEL_DISP0, 8, 1), + MUX(ID_NONE, "mout_sclk_disp_pixel_user", mout_sclk_disp_pixel_user_p, + MUX_SEL_DISP0, 4, 1), + MUX(ID_NONE, "mout_aclk_disp_333_user", mout_aclk_disp_333_user_p, + MUX_SEL_DISP0, 0, 1), +}; + +/* + * List of Mux clocks for CMU_EGL +*/ +struct samsung_mux_clock exynos5260_egl_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), + MUX(ID_NONE, "mout_egl_pll", mout_egl_pll_p, MUX_SEL_EGL, 4, 1), +}; + +/* + * List of Mux clocks for CMU_FSYS +*/ +struct samsung_mux_clock exynos5260_fsys_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_phyclk_usbhost20_phyclk_user", + mout_phyclk_usbhost20_phyclk_user_p, + MUX_SEL_FSYS1, 16, 1), + MUX(ID_NONE, "mout_phyclk_usbhost20_freeclk_user", + mout_phyclk_usbhost20_freeclk_user_p, + MUX_SEL_FSYS1, 12, 1), + MUX(ID_NONE, "mout_phyclk_usbhost20_clk48mohci_user", + mout_phyclk_usbhost20_clk48mohci_user_p, + MUX_SEL_FSYS1, 8, 1), + MUX(ID_NONE, "mout_phyclk_usbdrd30_pipe_pclk_user", + mout_phyclk_usbdrd30_pipe_pclk_user_p, + MUX_SEL_FSYS1, 4, 1), + MUX(ID_NONE, "mout_phyclk_usbdrd30_phyclock_user", + mout_phyclk_usbdrd30_phyclock_user_p, + MUX_SEL_FSYS1, 0, 1), +}; + +/* + * List of Mux clocks for CMU_G2D +*/ +struct samsung_mux_clock exynos5260_g2d_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_g2d_333_user", mout_aclk_g2d_333_user_p, + MUX_SEL_G2D, 0, 1), +}; + +/* + * List of Mux clocks for CMU_G3D +*/ +struct samsung_mux_clock exynos5260_g3d_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_g3d_pll", mout_g3d_pll_p, MUX_SEL_G3D, 0, 1), +}; + +/* + * List of Mux clocks for CMU_GSCL +*/ +struct samsung_mux_clock exynos5260_gscl_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_csis", mout_aclk_csis_p, MUX_SEL_GSCL, 24, 1), + MUX(ID_NONE, "mout_aclk_gscl_fimc_user", mout_aclk_gscl_fimc_user_p, + MUX_SEL_GSCL, 8, 1), + MUX(ID_NONE, "mout_aclk_m2m_400_user", mout_aclk_m2m_400_user_p, + MUX_SEL_GSCL, 4, 1), + MUX(ID_NONE, "mout_aclk_gscl_333_user", mout_aclk_gscl_333_user_p, + MUX_SEL_GSCL, 0, 1), +}; + +/* + * List of Mux clocks for CMU_ISP +*/ +struct samsung_mux_clock exynos5260_isp_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_isp_400_user", mout_isp_400_user_p, MUX_SEL_ISP0, + 4, 1), + MUX(ID_NONE, "mout_isp_266_user", mout_isp_266_user_p, MUX_SEL_ISP0, + 0, 1), +}; + +/* + * List of Mux clocks for CMU_KFC +*/ +struct samsung_mux_clock exynos5260_kfc_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_kfc_pll", mout_kfc_pll_p, MUX_SEL_KFC0, 0, 1), + MUX(ID_NONE, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), +}; + +/* + * List of Mux clocks for CMU_MFC +*/ +struct samsung_mux_clock exynos5260_mfc_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_mfc_333_user", mout_aclk_mfc_333_user_p, + MUX_SEL_MFC, 0, 1), +}; + +/* + * List of Mux clocks for CMU_MIF +*/ +struct samsung_mux_clock exynos5260_mif_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_clk2x_phy", mout_clk2x_phy_p, MUX_SEL_MIF, 24, 1), + MUX(ID_NONE, "mout_mif_drex2x", mout_mif_drex2x_p, MUX_SEL_MIF, 20, + 1), + MUX(ID_NONE, "mout_clkm_phy", mout_clkm_phy_p, MUX_SEL_MIF, 16, 1), + MUX(ID_NONE, "mout_mif_drex", mout_mif_drex_p, MUX_SEL_MIF, 12, 1), + MUX(ID_NONE, "mout_media_pll", mout_media_pll_p, MUX_SEL_MIF, 8, 1), + MUX(ID_NONE, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF, 4, 1), + MUX(ID_NONE, "mout_mem_pll", mout_mem_pll_p, MUX_SEL_MIF, 0, 1), +}; + +/* + * List of Mux clocks for CMU_PERI +*/ +struct samsung_mux_clock exynos5260_peri_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_spdif", mout_sclk_spdif_p, MUX_SEL_PERI1, 20, + 2), + MUX(ID_NONE, "mout_sclk_i2scod", mout_sclk_i2scod_p, MUX_SEL_PERI1, + 12, 2), + MUX(ID_NONE, "mout_sclk_pcm", mout_sclk_pcm_p, MUX_SEL_PERI1, 4, 2), +}; + +/* + * List of Mux clocks for CMU_TOP +*/ +struct samsung_mux_clock exynos5260_top_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_audtop_pll_user", mout_audtop_pll_user_p, + MUX_SEL_TOP_PLL0, 24, 1), + MUX(ID_NONE, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP_PLL0, 16, 1), + MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, + MUX_SEL_TOP_PLL0, 12, 1), + MUX(ID_NONE, "mout_bustop_pll_user", mout_bustop_pll_user_p, + MUX_SEL_TOP_PLL0, 8, 1), + MUX(ID_NONE, "mout_memtop_pll_user", mout_memtop_pll_user_p, + MUX_SEL_TOP_PLL0, 4, 1), + MUX(ID_NONE, "mout_mediatop_pll_user", mout_mediatop_pll_user_p, + MUX_SEL_TOP_PLL0, 0, 1), + + + MUX(ID_NONE, "mout_disp_disp_333", mout_disp_disp_333_p, + MUX_SEL_TOP_DISP0, 0, 1), + MUX(ID_NONE, "mout_aclk_disp_333", mout_aclk_disp_333_p, + MUX_SEL_TOP_DISP0, 8, 1), + MUX(ID_NONE, "mout_disp_disp_222", mout_disp_disp_222_p, + MUX_SEL_TOP_DISP0, 12, 1), + MUX(ID_NONE, "mout_aclk_disp_222", mout_aclk_disp_222_p, + MUX_SEL_TOP_DISP0, 20, 1), + MUX(ID_NONE, "mout_disp_media_pixel", mout_disp_media_pixel_p, + MUX_SEL_TOP_DISP1, 8, 1), + MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p, + MUX_SEL_TOP_DISP1, 0, 1), + + MUX(ID_NONE, "mout_sclk_peri_spi0_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 8, 1), + MUX(ID_NONE, "mout_sclk_peri_spi1_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 4, 1), + MUX(ID_NONE, "mout_sclk_peri_spi2_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 0, 1), + MUX(ID_NONE, "mout_sclk_peri_uart0_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 20, 1), + MUX(ID_NONE, "mout_sclk_peri_uart2_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 16, 1), + MUX(ID_NONE, "mout_sclk_peri_uart1_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 12, 1), + + MUX(ID_NONE, "mout_bus4_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 28, 1), + MUX(ID_NONE, "mout_bus4_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 24, 1), + MUX(ID_NONE, "mout_bus3_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 20, 1), + MUX(ID_NONE, "mout_bus3_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 16, 1), + MUX(ID_NONE, "mout_bus2_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 12, 1), + MUX(ID_NONE, "mout_bus2_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 8, 1), + MUX(ID_NONE, "mout_bus1_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 4, 1), + MUX(ID_NONE, "mout_bus1_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 0, 1), + + MUX(ID_NONE, "mout_sclk_fsys_usb", mout_sclk_fsys_usb_p, + MUX_SEL_TOP_FSYS, 0, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc0_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, MUX_SEL_TOP_FSYS, + 20, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc1_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, MUX_SEL_TOP_FSYS, + 12, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc2_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, MUX_SEL_TOP_FSYS, + 4, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc0_sdclkin_b", + mout_sclk_fsys_mmc0_sdclkin_b_p, MUX_SEL_TOP_FSYS, + 24, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc1_sdclkin_b", + mout_sclk_fsys_mmc1_sdclkin_b_p, MUX_SEL_TOP_FSYS, + 16, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc2_sdclkin_b", + mout_sclk_fsys_mmc2_sdclkin_b_p, MUX_SEL_TOP_FSYS, + 8, 1), + + MUX(ID_NONE, "mout_aclk_isp1_266", mout_aclk_isp1_266_p, + MUX_SEL_TOP_ISP10, 20, 1), + MUX(ID_NONE, "mout_isp1_media_266", mout_isp1_media_266_p, + MUX_SEL_TOP_ISP10, 16, 1), + MUX(ID_NONE, "mout_aclk_isp1_400", mout_aclk_isp1_400_p, + MUX_SEL_TOP_ISP10, 8 , 1), + MUX(ID_NONE, "mout_isp1_media_400", mout_isp1_media_400_p, + MUX_SEL_TOP_ISP10, 4, 1), + + MUX(ID_NONE, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p, + MUX_SEL_TOP_ISP11, 4, 1), + MUX(ID_NONE, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p, + MUX_SEL_TOP_ISP11, 8, 1), + MUX(ID_NONE, "mout_sclk_isp1_uart", mout_sclk_isp_uart_p, + MUX_SEL_TOP_ISP11, 12, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor2", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 24, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor1", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 20, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor0", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 16, 1), + + MUX(ID_NONE, "mout_aclk_mfc_333", mout_aclk_mfc_333_p, + MUX_SEL_TOP_MFC, 8, 1), + MUX(ID_NONE, "mout_mfc_bustop_333", mout_mfc_bustop_333_p, + MUX_SEL_TOP_MFC, 4, 1), + + MUX(ID_NONE, "mout_aclk_g2d_333", mout_aclk_g2d_333_p, + MUX_SEL_TOP_G2D, 8, 1), + MUX(ID_NONE, "mout_g2d_bustop_333", mout_g2d_bustop_333_p, + MUX_SEL_TOP_G2D, 4, 1), + + MUX(ID_NONE, "mout_aclk_gscl_fimc", mout_aclk_gscl_fimc_p, + MUX_SEL_TOP_GSCL, 20, 1), + MUX(ID_NONE, "mout_gscl_bustop_fimc", mout_gscl_bustop_fimc_p, + MUX_SEL_TOP_GSCL, 16, 1), + MUX(ID_NONE, "mout_aclk_gscl_333", mout_aclk_gscl_333_p, + MUX_SEL_TOP_GSCL, 12, 1), + MUX(ID_NONE, "mout_gscl_bustop_333", mout_gscl_bustop_333_p, + MUX_SEL_TOP_GSCL, 8, 1), + MUX(ID_NONE, "mout_aclk_gscl_400", mout_aclk_gscl_400_p, + MUX_SEL_TOP_GSCL, 4, 1), + MUX(ID_NONE, "mout_m2m_mediatop_400", mout_m2m_mediatop_400_p, + MUX_SEL_TOP_GSCL, 0, 1), + + /* + * TODO: Add for ISP clocks + */ +}; + +/* DIVIDER CLOCKS */ + +/* + * List of Divider clocks for CMU_AUD +*/ +struct samsung_div_clock exynos5260_aud_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_aud_131", "mout_aud_pll_user", DIV_AUD0, 0, + 4), + DIV(ID_NONE, "dout_sclk_aud_uart", "mout_aud_pll_user", DIV_AUD1, 12, + 4), + DIV(ID_NONE, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm", DIV_AUD1, 4, + 8), + DIV(ID_NONE, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s", DIV_AUD1, 0, + 4), +}; + +/* + * List of Divider clocks for CMU_DISP +*/ +struct samsung_div_clock exynos5260_disp_div_clks[] __initdata = { + DIV(ID_NONE, "dout_sclk_hdmi_phy_pixel_clki", "mout_sclk_hdmi_pixel", + DIV_DISP, 16, 4), + DIV(ID_NONE, "dout_sclk_fimd1_extclkpll", "mout_sclk_disp_pixel_user", + DIV_DISP, 12, 4), + DIV(ID_NONE, "dout_pclk_disp_111", "mout_aclk_disp_222_user", + DIV_DISP, 8, 4), +}; + +/* + * List of Divider clocks for CMU_EGL +*/ +struct samsung_div_clock exynos5260_egl_div_clks[] __initdata = { + DIV(ID_NONE, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3), + DIV(ID_NONE, "dout_egl_pclk_dbg", "dout_egl_atclk", DIV_EGL, 20, 3), + DIV(ID_NONE, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3), + DIV(ID_NONE, "dout_pclk_egl", "dout_egl_atclk", DIV_EGL, 12, 3), + DIV(ID_NONE, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), + DIV(ID_NONE, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), + DIV(ID_NONE, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), +}; + +/* + * List of Divider clocks for CMU_G2D +*/ +struct samsung_div_clock exynos5260_g2d_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", DIV_G2D, 0, + 3), +}; + +/* + * List of Divider clocks for CMU_G3D +*/ + +struct samsung_div_clock exynos5260_g3d_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), + DIV(ID_NONE, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), +}; + +/* + * List of Divider clocks for CMU_GSCL +*/ +struct samsung_div_clock exynos5260_gscl_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_csis_200", "mout_aclk_m2m_400_user", DIV_GSCL, + 4, 3), + DIV(ID_NONE, "dout_pclk_m2m_100", "mout_aclk_m2m_400_user", DIV_GSCL, + 0, 3), +}; + +/* + * List of Divider clocks for CMU_ISP +*/ + +struct samsung_div_clock exynos5260_isp_div_clks[] __initdata = { + DIV(ID_NONE, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), + DIV(ID_NONE, "dout_ca5_pclkdbg", "mout_kfc", DIV_ISP, 16, 4), + DIV(ID_NONE, "dout_ca5_atclkin", "mout_kfc", DIV_ISP, 12, 3), + DIV(ID_NONE, "dout_pclk_isp_133", "mout_kfc", DIV_ISP, 4, 4), + DIV(ID_NONE, "dout_pclk_isp_66", "mout_kfc", DIV_ISP, 0, 3), +}; + +/* + * List of Divider clocks for CMU_KFC +*/ +struct samsung_div_clock exynos5260_kfc_div_clks[] __initdata = { + DIV(ID_NONE, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3), + DIV(ID_NONE, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3), + DIV(ID_NONE, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3), + DIV(ID_NONE, "dout_kfc_pclk_dbg", "dout_kfc2", DIV_KFC, 12, 3), + DIV(ID_NONE, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), + DIV(ID_NONE, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), + DIV(ID_NONE, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), +}; + +/* + * List of Divider clocks for CMU_MFC +*/ +struct samsung_div_clock exynos5260_mfc_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", DIV_MFC, 0, + 3), +}; + +/* + * List of Divider clocks for CMU_MIF +*/ +struct samsung_div_clock exynos5260_mif_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_bus_100", "dout_bus_pll", DIV_MIF, 28, 4), + DIV(ID_NONE, "dout_aclk_bus_200", "dout_bus_pll", DIV_MIF, 24, 3), + DIV(ID_NONE, "dout_aclk_mif_466", "dout_clk2x_phy", DIV_MIF, 20, 3), + DIV(ID_NONE, "dout_clk2x_phy", "mout_clk2x_phy", DIV_MIF, 16, 4), + DIV(ID_NONE, "dout_clkm_phy", "mout_clkm_phy", DIV_MIF, 12, 3), + DIV(ID_NONE, "dout_bus_pll", "mout_bus_pll", DIV_MIF, 8, 3), + DIV(ID_NONE, "dout_mem_pll", "mout_mem_pll", DIV_MIF, 4, 3), + DIV(ID_NONE, "dout_media_pll", "mout_media_pll", DIV_MIF, 0, 3), +}; + +/* + * List of Divider clocks for CMU_peri +*/ +struct samsung_div_clock exynos5260_peri_div_clks[] __initdata = { + DIV(ID_NONE, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 0, 6), + DIV(ID_NONE, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), +}; + +/* + * List of Divider clocks for CMU_TOP +*/ +struct samsung_div_clock exynos5260_top_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_mfc_333", "mout_aclk_mfc_333", + DIV_TOP_G2D_MFC, 4, 3), + + DIV(ID_NONE, "dout_aclk_g2d_333", "mout_aclk_g2d_333", + DIV_TOP_GSCL_ISP0, 0, 3), + + DIV(ID_NONE, "dout_sclk_isp1_sensor2_a", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 24, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor1_a", "mout_aclk_gscl_400", + DIV_TOP_GSCL_ISP0, 20, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor0_a", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 16, 4), + DIV(ID_NONE, "dout_aclk_gscl_fimc", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 8, 3), + DIV(ID_NONE, "dout_aclk_gscl_400", "mout_aclk_gscl_400", + DIV_TOP_GSCL_ISP0, 4, 3), + DIV(ID_NONE, "dout_aclk_gscl_333", "mout_aclk_gscl_333", + DIV_TOP_GSCL_ISP0, 0, 3), + + DIV(ID_NONE, "dout_sclk_isp1_spi0_b", "dout_sclk_isp1_spi0_a", + DIV_TOP_ISP10, 16, 8), + DIV(ID_NONE, "dout_sclk_isp1_spi0_a", "mout_sclk_isp1_spi0", + DIV_TOP_ISP10, 12, 4), + DIV(ID_NONE, "dout_aclk_isp1_400", "mout_aclk_isp1_400", + DIV_TOP_ISP10, 4, 3), + DIV(ID_NONE, "dout_aclk_isp1_266", "mout_aclk_isp1_266", + DIV_TOP_ISP10, 0, 3), + DIV(ID_NONE, "dout_sclk_isp1_uart", "mout_sclk_isp1_uart", + DIV_TOP_ISP11, 12, 4), + DIV(ID_NONE, "dout_sclk_isp1_spi1_b", "dout_sclk_isp1_spi1_a", + DIV_TOP_ISP11, 4, 8), + DIV(ID_NONE, "dout_sclk_isp1_spi1_a", "mout_sclk_isp1_spi1", + DIV_TOP_ISP11, 0, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor2_b", "dout_sclk_isp1_sensor2_a", + DIV_TOP_ISP11, 24, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor1_b", "dout_sclk_isp1_sensor1_a", + DIV_TOP_ISP11, 20, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor0_b", "dout_sclk_isp1_sensor0_a", + DIV_TOP_ISP11, 16, 4), + + DIV(ID_NONE, "dout_sclk_hpm_targetclk", "mout_bustop_pll_user", + DIV_TOP_HPM, 0, 3), + + DIV(ID_NONE, "dout_sclk_disp_pixel", "mout_sclk_disp_pixel", + DIV_TOP_DISP, 8, 3), + DIV(ID_NONE, "dout_aclk_disp_222", "mout_aclk_disp_222", DIV_TOP_DISP, + 4, 3), + DIV(ID_NONE, "dout_aclk_disp_333", "mout_aclk_disp_333", DIV_TOP_DISP, + 0, 3), + + DIV(ID_NONE, "dout_aclk_bus4_100", "mout_bus4_bustop_100", + DIV_TOP_BUS, 28, 4), + DIV(ID_NONE, "dout_aclk_bus4_400", "mout_bus4_bustop_400", + DIV_TOP_BUS, 24, 3), + DIV(ID_NONE, "dout_aclk_bus3_100", "mout_bus3_bustop_100", + DIV_TOP_BUS, 20, 4), + DIV(ID_NONE, "dout_aclk_bus3_400", "mout_bus3_bustop_400", + DIV_TOP_BUS, 16, 3), + DIV(ID_NONE, "dout_aclk_bus2_100", "mout_bus2_bustop_100", + DIV_TOP_BUS, 12, 4), + DIV(ID_NONE, "dout_aclk_bus2_400", "mout_bus2_bustop_400", + DIV_TOP_BUS, 8, 3), + DIV(ID_NONE, "dout_aclk_bus1_100", "mout_bus1_bustop_100", + DIV_TOP_BUS, 4, 4), + DIV(ID_NONE, "dout_aclk_bus1_400", "mout_bus1_bustop_400", + DIV_TOP_BUS, 0, 3), + + DIV(ID_NONE, "dout_sclk_peri_spi1_b", "dout_sclk_peri_spi1_a", + DIV_TOP_PERI0, 20, 8), + DIV(ID_NONE, "dout_sclk_peri_spi1_a", "mout_sclk_peri_spi1_clk", + DIV_TOP_PERI0, 16, 4), + DIV(ID_NONE, "dout_sclk_peri_spi0_b", "dout_sclk_peri_spi0_a", + DIV_TOP_PERI0, 8, 8), + DIV(ID_NONE, "dout_sclk_peri_spi0_a", "mout_sclk_peri_spi0_clk", + DIV_TOP_PERI0, 4, 4), + DIV(ID_NONE, "dout_sclk_peri_uart0", "mout_sclk_peri_uart0_uclk", + DIV_TOP_PERI1, 24, 4), + DIV(ID_NONE, "dout_sclk_peri_uart2", "mout_sclk_peri_uart2_uclk", + DIV_TOP_PERI1, 20, 4), + DIV(ID_NONE, "dout_sclk_peri_uart1", "mout_sclk_peri_uart1_uclk", + DIV_TOP_PERI1, 16, 4), + DIV(ID_NONE, "dout_sclk_peri_spi2_b", "dout_sclk_peri_spi2_a", + DIV_TOP_PERI1, 4, 8), + DIV(ID_NONE, "dout_sclk_peri_spi2_a", "mout_sclk_peri_spi2_clk", + DIV_TOP_PERI1, 0, 4), + DIV(ID_NONE, "dout_aclk_peri_aud", "mout_audtop_pll_user", + DIV_TOP_PERI2, 24, 3), + DIV(ID_NONE, "dout_aclk_peri_66", "mout_bustop_pll_user", + DIV_TOP_PERI2, 20, 4), + + DIV(ID_NONE, "dout_sclk_fsys_mmc0_sdclkin_b", + "dout_sclk_fsys_mmc0_sdclkin_a", DIV_TOP_FSYS0, + 16, 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc0_sdclkin_a", + "mout_sclk_fsys_mmc0_sdclkin_b", DIV_TOP_FSYS0, + 12, 4), + DIV(ID_NONE, "dout_sclk_fsys_usbdrd30_suspend_clk", + "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4), + DIV(ID_NONE, "dout_aclk_fsys_200", "mout_bustop_pll_user", + DIV_TOP_FSYS0, 0, 3), + + DIV(ID_NONE, "dout_sclk_fsys_mmc2_sdclkin_b", + "dout_sclk_fsys_mmc2_sdclkin_a", DIV_TOP_FSYS1, + 16, 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc2_sdclkin_a", + "mout_sclk_fsys_mmc2_sdclkin_b", DIV_TOP_FSYS1, + 12, 4), + DIV(ID_NONE, "dout_sclk_fsys_mmc1_sdclkin_b", + "dout_sclk_fsys_mmc1_sdclkin_a", DIV_TOP_FSYS1, 4, + 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc1_sdclkin_a", + "mout_sclk_fsys_mmc1_sdclkin_b", DIV_TOP_FSYS1, 0, + 4), +}; + +/* GATE CLOCKS */ + +/* + * List of Gate clocks for CMU_AUD +*/ +struct samsung_gate_clock exynos5260_aud_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_axids_lpassp", "dout_aclk_aud_131", EN_ACLK_AUD, + 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axi2apb_lpassp", "dout_aclk_aud_131", EN_ACLK_AUD, + 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_lpassx", "dout_aclk_aud_131", EN_ACLK_AUD, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_audnd_133", "dout_aclk_aud_131", EN_ACLK_AUD, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_audnp_133", "dout_aclk_aud_131", EN_ACLK_AUD, 2, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_ACLK_SRAMC, "aclk_sramc", "dout_aclk_aud_131", EN_ACLK_AUD, + 1, CLK_IGNORE_UNUSED, 0), + GATE(AUD_ACLK_DMAC, "aclk_dmac", "dout_aclk_aud_131", EN_ACLK_AUD, 0, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_gpio_aud", "dout_aclk_aud_131", EN_PCLK_AUD, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_aud", "dout_aclk_aud_131", EN_PCLK_AUD, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_aud", "dout_aclk_aud_131", EN_PCLK_AUD, 5, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_PCLK_AUD_UART, "pclk_aud_uart", "dout_aclk_aud_131", + EN_PCLK_AUD, 4, CLK_IGNORE_UNUSED, 0), + GATE(AUD_PCLK_PCM, "pclk_pcm", "dout_aclk_aud_131", EN_PCLK_AUD, 3, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_PCLK_I2S, "pclk_i2s", "dout_aclk_aud_131", EN_PCLK_AUD, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sfr_ctrl", "dout_aclk_aud_131", EN_PCLK_AUD, 1, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_PCLK_DMAC, "pclk_dmac", "dout_aclk_aud_131", EN_PCLK_AUD, 0, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart", + EN_SCLK_AUD, 2, CLK_IGNORE_UNUSED, 0), + GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", EN_SCLK_AUD, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_aud_i2s", "dout_sclk_aud_i2s", EN_SCLK_AUD, 0, + CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_DISP +*/ +struct samsung_gate_clock exynos5260_disp_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_noc_d_disp_disp1nd_333", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 30, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_disp_disp0nd_333", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 29, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axius64to128_gsclkx_fimd1x", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 28, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axius64to128_tv", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 27, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_fimd0x", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 26, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncaxi_tv_aclkm", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 25, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncaxi_tv_aclks", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 24, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_fimd0x", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 23, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_tvx", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 22, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_tvx", "mout_aclk_disp_222_user", EN_ACLK_DISP, + 21, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_fimd1x", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 20, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_fimd1m1", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_fimd1m0", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_tvm1", "mout_aclk_disp_222_user", EN_ACLK_DISP, + 16, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_tvm0", "mout_aclk_disp_222_user", EN_ACLK_DISP, + 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_fimd1m1", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_fimd1m0", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_tvx", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_fimd1x", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncfifo_mixer1_aclks", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncfifo_mixer1_aclkm", + "mout_aclk_disp_222_user", EN_ACLK_DISP, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncfifo_mixer0_aclks", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncfifo_mixer0_aclkm", + "mout_aclk_disp_222_user", EN_ACLK_DISP, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncdisp_m1", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncdisp_m0", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 4, CLK_IGNORE_UNUSED, 0), + GATE(DISP_ACLK_MIXER, "aclk_mixer", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 3, CLK_IGNORE_UNUSED, 0), + GATE(DISP_ACLK_HDMI, "aclk_hdmi_link", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 2, CLK_IGNORE_UNUSED, 0), + GATE(DISP_ACLK_FIMD1, "aclk_fimd1_128", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncaxim_gsclx_fimd1x", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "phyclk_dptx_link_i_div2", + "mout_phyclk_dptx_phy_clk_div2_user", + EN_SCLK_DISP0, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_ch3_tx", + "mout_phyclk_dptx_phy_ch3_txd_clk_user", + EN_SCLK_DISP0, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_ch2_tx", + "mout_phyclk_dptx_phy_ch2_txd_clk_user", + EN_SCLK_DISP0, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_ch1_tx", + "mout_phyclk_dptx_phy_ch1_txd_clk_user", + EN_SCLK_DISP0, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_ch0_tx", + "mout_phyclk_dptx_phy_ch0_txd_clk_user", + EN_SCLK_DISP0, 1, + CLK_IGNORE_UNUSED, 0), + GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki", + "dout_sclk_hdmi_phy_pixel_clki", EN_SCLK_DISP0, + 29, CLK_IGNORE_UNUSED, + 0), + + GATE(ID_NONE, "pclk_ppmu_fimd0x", "dout_pclk_disp_111", EN_PCLK_DISP, + 30, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_noc_p_disp_dispnp_111", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 28, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncaxi_tv", "dout_pclk_disp_111", EN_PCLK_DISP, + 27, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_disp", "dout_pclk_disp_111", EN_PCLK_DISP, + 26, CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_SMMU_TV, "pclk_smmu3_tvx", "dout_pclk_disp_111", + EN_PCLK_DISP, 25, CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_SMMU_FIMD1M1, "pclk_smmu3_fimd1m1", + "dout_pclk_disp_111", EN_PCLK_DISP, 23, + CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_SMMU_FIMD1M0, "pclk_smmu3_fimd1m0", + "dout_pclk_disp_111", EN_PCLK_DISP, 22, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_tvm1", "dout_pclk_disp_111", EN_PCLK_DISP, 21, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_tvm0", "dout_pclk_disp_111", EN_PCLK_DISP, 20, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_fimd1m1", "dout_pclk_disp_111", EN_PCLK_DISP, + 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_fimd1m0", "dout_pclk_disp_111", EN_PCLK_DISP, + 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_tvx", "dout_pclk_disp_111", EN_PCLK_DISP, 16, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_fimd1x", "dout_pclk_disp_111", EN_PCLK_DISP, + 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_disp", "dout_pclk_disp_111", EN_PCLK_DISP, 14, + CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_HDMIPHY, "pclk_hdmi_phy_i", "dout_pclk_disp_111", + EN_PCLK_DISP, 13, CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_HDMI, "pclk_hdmi_link", "dout_pclk_disp_111", + EN_PCLK_DISP, 12, CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_DSIM1, "pclk_dsim1", "dout_pclk_disp_111", + EN_PCLK_DISP, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_dptx_link_i_pclk1", "dout_pclk_disp_111", + EN_PCLK_DISP, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_dptx_link_i_pclk0", "dout_pclk_disp_111", + EN_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncaxim_gsclx_fimd1x", "dout_pclk_disp_111", + EN_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ahb2apb_disp1p", "dout_pclk_disp_111", + EN_PCLK_DISP, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ahb2apb_disp0p", "dout_pclk_disp_111", + EN_PCLK_DISP, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahbsyncdn_disp0p", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahbsyncdn_disp1p", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_noc_p_dispnp_111", "mout_aclk_disp_333_user", + EN_PCLK_DISP, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_fimd1_128", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb_sfrdisph", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "sclk_fimd1_128_extclkpll", "dout_sclk_fimd1_extclkpll", + EN_SCLK_DISP0, 31, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_hdmi_link_i_spdif", "mout_sclk_hdmi_spdif", + EN_SCLK_DISP0, 27, CLK_IGNORE_UNUSED, 0), + GATE(DISP_SCLK_HDMI, "sclk_hdmi_link_i_pixel", + "mout_phyclk_hdmi_phy_pixel_clko_user", + EN_SCLK_DISP0, 26, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_hdmi_phy_tmds_clki", + "mout_phyclk_hdmi_link_o_tmds_clkhi_user", + EN_SCLK_DISP0, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_hdmi_phy_ref_cko", + "mout_phyclk_hdmi_phy_ref_clko_user", + EN_SCLK_DISP0, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_hdmi_link_i_tmds", + "mout_phyclk_hdmi_link_o_tmds_clkhi_user", + EN_SCLK_DISP0, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dsim1_rxclkesc0", + "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user", + EN_SCLK_DISP0, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dsim1_bitclkdiv8", + "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs", + EN_SCLK_DISP0, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_24m", + "mout_phyclk_dptx_phy_o_ref_clk_24m_user", + EN_SCLK_DISP0, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mixer_i_vclk_hdmi", + "mout_phyclk_hdmi_phy_pixel_clko_user", + EN_SCLK_DISP1, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkescclk", + "mout_sclk_dsim1_tx_clk_esc_clk_user", + EN_SCLK_DISP1, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkesc3", + "mout_sclk_dsim1_tx_clk_esc3_user", EN_SCLK_DISP1, + 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkesc2", + "mout_sclk_dsim1_tx_clk_esc2_user", EN_SCLK_DISP1, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkesc1", + "mout_sclk_dsim1_tx_clk_esc1_user", EN_SCLK_DISP1, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkesc0", + "mout_sclk_dsim1_tx_clk_esc0_user", EN_SCLK_DISP1, + 0, CLK_IGNORE_UNUSED, 0), + + GATE(DISP_DP, "dptx_phy", "fin_pll", EN_IP_DISP, 5, CLK_IGNORE_UNUSED, + 0), +}; + +/* + * List of Gate clocks for CMU_EGL +*/ +struct samsung_gate_clock exynos5260_egl_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_cssys_traceclkin", "dout_egl_atclk", EN_ACLK_EGL, + 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_cssys_ctm", "dout_egl_atclk", EN_ACLK_EGL, 10, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_cssys", "dout_egl_atclk", EN_ACLK_EGL, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_cssys_atclk", "dout_egl_atclk", EN_ACLK_EGL, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asatbmat_kfc_3_cssys", "dout_egl_atclk", + EN_ACLK_EGL, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asatbmat_kfc_2_cssys", "dout_egl_atclk", + EN_ACLK_EGL, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asatbmat_kfc_1_cssys", "dout_egl_atclk", + EN_ACLK_EGL, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asatbmat_kfc_0_cssys", "dout_egl_atclk", + EN_ACLK_EGL, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbs_cssys_cci", "dout_egl_atclk", + EN_ACLK_EGL, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ace_async_egl_cci_i", "dout_aclk_egl", + EN_ACLK_EGL, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_eglp", "dout_pclk_egl", EN_ACLK_EGL, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_eagle_200", "dout_pclk_egl", EN_ACLK_EGL, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_egl_hpm_sfrif", "dout_pclk_egl", EN_PCLK_EGL, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_cssys_pclkdbg", "dout_egl_pclk_dbg", EN_PCLK_EGL, + 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_cortexa15_pclkdbg", "dout_egl_pclk_dbg", + EN_PCLK_EGL, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_aud_cssys", "dout_egl_pclk_dbg", + EN_PCLK_EGL, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_isp_cssys", "dout_egl_pclk_dbg", + EN_PCLK_EGL, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_kfc_cssys", "dout_egl_pclk_dbg", + EN_PCLK_EGL, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_egl", "dout_pclk_egl", EN_PCLK_EGL, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_egl", "dout_pclk_egl", EN_PCLK_EGL, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_secjtag", "dout_egl_pclk_dbg", EN_PCLK_EGL, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "sclk_iem_hpm_target", "dout_sclk_hpm_targetclk", + EN_SCLK_EGL, 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_FSYS +*/ +struct samsung_gate_clock exynos5260_fsys_gate_clks[] __initdata = { + GATE(FSYS_HCLK_TSI, "hclk_tsi", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 25, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_PCLK_GPIO, "pclk_gpio", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 24, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_usblink", "dout_aclk_fsys_200", EN_ACLK_FSYS, 23, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_fsys", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 22, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_fsys_top", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 21, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu", "dout_aclk_fsys_200", EN_ACLK_FSYS, 20, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_USBHOST20, "hclk_usbhost20", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 19, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_SROMC, "hclk_sromc", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 18, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_MMC2, "hclk_mmc2", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 17, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_MMC1, "hclk_mmc1", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 16, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_MMC0, "hclk_mmc0", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_fsysp", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb_usbhs", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb_fsysh", "dout_aclk_fsys_200", EN_ACLK_FSYS, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_fd64x", "dout_aclk_fsys_200", EN_ACLK_FSYS, 8, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_ACLK_USBDRD30, "aclk_usbdrd30", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu", "dout_aclk_fsys_200", EN_ACLK_FSYS, 6, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_ACLK_PDMA0, "aclk_pdma0", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_fsys_200", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_fsys_200", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axius32to64_usbhs_fd64x", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axius32to64_pdma0_fd64x", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ahb2axi_usbhs_fd64x", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 0, CLK_IGNORE_UNUSED, 0), + + GATE(FSYS_ACLK_RTIC, "aclk_rtic_i", "dout_aclk_fsys_200", + EN_ACLK_FSYS_SECURE_RTIC, 12, CLK_IGNORE_UNUSED, + 0), + + GATE(FSYS_PCLK_SMMU_RTIC, "pclk_smmu_rtic", "dout_aclk_fsys_200", + EN_ACLK_FSYS_SECURE_SMMU_RTIC, 14, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu_rtic", "dout_aclk_fsys_200", + EN_ACLK_FSYS_SECURE_SMMU_RTIC, 13, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "phyclk_usbdrd30_udrd30_pipe", + "mout_phyclk_usbdrd30_pipe_pclk_user", + EN_SCLK_FSYS, 8, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g", + "mout_phyclk_usbdrd30_phyclock_user", + EN_SCLK_FSYS, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_usbhost20_clk48mohci", + "mout_phyclk_usbhost20_clk48mohci_user", + EN_SCLK_FSYS, 6, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", + "mout_phyclk_usbdrd30_phyclock_user", + EN_SCLK_FSYS, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_usbhost20_freeclock_gatet", + "mout_phyclk_usbhost20_freeclk_user", + EN_SCLK_FSYS, 0, + CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_G2D +*/ +struct samsung_gate_clock exynos5260_g2d_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_xiu_async_g2d2x_g2d1x_aclks", + "mout_aclk_g2d_333_user", EN_ACLK_G2D, 26, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_async_g2d2x_g2d1x_aclkm", + "mout_aclk_g2d_333_user", EN_ACLK_G2D, 25, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mdma", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 24, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_g2d2x", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 23, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_g2d1x", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 22, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_jpeg", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 20, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_jpeg", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 14, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 10, CLK_IGNORE_UNUSED, 0), + GATE(G2D_ACLK_MDMA, "aclk_mdma", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_jpeg", "mout_aclk_g2d_333_user", EN_ACLK_G2D, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_slim_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_mdma", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_jpeg", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_g2d", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axi_us_64to128_g2d2x_g2d1x", + "mout_aclk_g2d_333_user", EN_ACLK_G2D, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_alb_g2d1x_g2dnd", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "aclk_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SSS, 21, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_slim_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SLIM_SSS, 15, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu_slim_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS, 17, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SMMU_SSS, 18, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu_mdma", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SMMU_MDMA, 16, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_g2d", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SMMU_G2D, 19, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "hclk_ahb_tz", "dout_pclk_g2d_83", EN_PCLK_G2D, 18, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_xiu_async_g2d2x_g2d1x", "dout_pclk_g2d_83", + EN_PCLK_G2D, 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mdma", "dout_pclk_g2d_83", EN_PCLK_G2D, 16, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 15, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 14, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_jpeg", "dout_pclk_g2d_83", EN_PCLK_G2D, 13, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_jpeg", "dout_pclk_g2d_83", EN_PCLK_G2D, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_alb_g2d1x_g2dnd", "dout_pclk_g2d_83", EN_PCLK_G2D, + 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbslave_g2dh_jpeg", "dout_pclk_g2d_83", + EN_PCLK_G2D, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbmaster_g2dh_jpeg", + "mout_aclk_g2d_333_user", EN_PCLK_G2D, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_sfrg2d", "dout_pclk_g2d_83", EN_PCLK_G2D, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_smmu_slim_sss", "dout_pclk_g2d_83", + EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS, 10, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu_sss", "dout_pclk_g2d_83", + EN_PCLK_G2D_SECURE_SMMU_SSS, 11, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu_mdma", "dout_pclk_g2d_83", + EN_PCLK_G2D_SECURE_SMMU_MDMA, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_g2d", "dout_pclk_g2d_83", + EN_PCLK_G2D_SECURE_SMMU_G2D, 12, + CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_G3D +*/ +struct samsung_gate_clock exynos5260_g3d_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_noc_p_g3d", "dout_pclk_g3d", EN_ACLK_G3D, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_g3d", "dout_aclk_g3d", EN_ACLK_G3D, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncapb_socp_g3d", "dout_aclk_g3d", EN_ACLK_G3D, + 3, CLK_IGNORE_UNUSED, 0), + GATE(G3D_ACLK_G3D, "aclk_g3d", "dout_aclk_g3d", EN_ACLK_G3D, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_acr_lite_g3d", "dout_aclk_g3d", EN_ACLK_G3D, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_g3d", "dout_aclk_g3d", EN_ACLK_G3D, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_g3d_hpm_sfrif", "dout_pclk_g3d", EN_PCLK_G3D, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_reg_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_ace_lite_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_socp_g3d", "dout_pclk_g3d", EN_PCLK_G3D, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 0, + CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_GSCL +*/ +struct samsung_gate_clock exynos5260_gscl_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_noc_d_gscl_333", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 27, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_mscl_400", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 26, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_gscl_100", "dout_pclk_m2m_100", + EN_ACLK_GSCL, 25, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_msclx", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 24, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_gsclx", "mout_aclk_gscl_333", EN_ACLK_GSCL, + 23, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mscl1", "mout_aclk_m2m_400_user", EN_ACLK_GSCL, + 19, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mscl0", "mout_aclk_m2m_400_user", EN_ACLK_GSCL, + 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_mscl", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_m2mscaler1", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_m2mscaler0", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 14, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_asyncs_gsclx", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_gscl1", "mout_aclk_gscl_333", EN_ACLK_GSCL, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_gscl0", "mout_aclk_gscl_333", EN_ACLK_GSCL, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_gscl", "mout_aclk_gscl_333", EN_ACLK_GSCL, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncs_gscl1", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncs_gscl0", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncm_gscl0", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 3, CLK_IGNORE_UNUSED, 0), + GATE(GSCL_ACLK_GSCL1, "aclk_gscaler1", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 1, CLK_IGNORE_UNUSED, 0), + GATE(GSCL_ACLK_GSCL0, "aclk_gscaler0", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "aclk_noc_d_fimc_333", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_fimc_lite_d_i", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_fimc_lite_b_i", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_fimc_lite_a_i", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_lite_d", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_lite_b", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_lite_a", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_lite_d", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_lite_b", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_lite_a", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_fimc", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_fimcx", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_gscl0", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_SECURE_SMMU_GSCL0, 10, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_gscl1", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_SECURE_SMMU_GSCL1, 11, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_mscl0", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_SECURE_SMMU_MSCL0, 00, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_mscl1", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_SECURE_SMMU_MSCL1, 21, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_sysreg_gscl", "dout_pclk_m2m_100", EN_PCLK_GSCL, + 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mscl1", "dout_pclk_m2m_100", EN_PCLK_GSCL, 13, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mscl0", "dout_pclk_m2m_100", EN_PCLK_GSCL, 12, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_gscl1", "dout_pclk_m2m_100", EN_PCLK_GSCL, 11, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_gscl0", "dout_pclk_m2m_100", EN_PCLK_GSCL, 10, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_mscl", "dout_pclk_m2m_100", EN_PCLK_GSCL, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_gscl", "dout_pclk_m2m_100", EN_PCLK_GSCL, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_gscl", "dout_pclk_m2m_100", EN_PCLK_GSCL, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_m2mscaler1", "dout_pclk_m2m_100", EN_PCLK_GSCL, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_m2mscaler0", "dout_pclk_m2m_100", EN_PCLK_GSCL, 5, + CLK_IGNORE_UNUSED, 0), + GATE(GSCL_PCLK_GSCL1, "pclk_gscaler1", "dout_pclk_m2m_100", + EN_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), + GATE(GSCL_PCLK_GSCL0, "pclk_gscaler0", "dout_pclk_m2m_100", + EN_PCLK_GSCL, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_msclp", "dout_pclk_m2m_100", EN_PCLK_GSCL, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_gsclp", "dout_pclk_m2m_100", EN_PCLK_GSCL, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_fimc", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_lite_d", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 16, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_lite_b", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_lite_a", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 14, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_lite_d", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_lite_b", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_lite_a", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_fimc_lite_d", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_fimc_lite_b", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_fimc_lite_a", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_csis1", "dout_pclk_m2m_100", EN_PCLK_GSCL_FIMC, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_csis0", "dout_pclk_m2m_100", EN_PCLK_GSCL_FIMC, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_hpm9t_wrap_gscl", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_fimcp", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb_gsclh", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbm_isph", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbm_fimcnp", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbs_fimcnp", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 0, CLK_IGNORE_UNUSED, 0), + GATE(GSCL_PCLK_SMMU_GSCL0, "pclk_smmu3_gscl0", "dout_pclk_m2m_100", + EN_PCLK_GSCL_SECURE_SMMU_GSCL0, 14, + CLK_IGNORE_UNUSED, 0), + GATE(GSCL_PCLK_SMMU_GSCL1, "pclk_smmu3_gscl1", "dout_pclk_m2m_100", + EN_PCLK_GSCL_SECURE_SMMU_GSCL1, 15, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_mscl0", "dout_pclk_m2m_100", + EN_PCLK_GSCL_SECURE_SMMU_MSCL0, 16, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_mscl1", "dout_pclk_m2m_100", + EN_PCLK_GSCL_SECURE_SMMU_MSCL1, 17, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "sclk_gscl_hpm_targetclk", "dout_sclk_hpm_targetclk", + EN_SCLK_GSCL, 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_csis1_wrap", "dout_aclk_csis_200", + EN_SCLK_GSCL_FIMC, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_csis0_wrap", "dout_aclk_csis_200", + EN_SCLK_GSCL_FIMC, 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_ISP +*/ +struct samsung_gate_clock exynos5260_isp_gate_clks[] __initdata = { +}; + +/* + * List of Gate clocks for CMU_KFC +*/ +struct samsung_gate_clock exynos5260_kfc_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_asyncatbs_kfc_3", "dout_kfc_atclk", EN_ACLK_KFC, + 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncatbs_kfc_2", "dout_kfc_atclk", EN_ACLK_KFC, + 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncatbs_kfc_1", "dout_kfc_atclk", EN_ACLK_KFC, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncatbs_kfc_0", "dout_kfc_atclk", EN_ACLK_KFC, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncaces_kfc_cci", "dout_aclk_kfc", EN_ACLK_KFC, + 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_kfc_hpm_sfrif", "dout_pclk_kfc", EN_PCLK_KFC, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_atbdownsizer63to32_kfc3", "dout_aclk_kfc", + EN_PCLK_KFC, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_atbdownsizer63to32_kfc2", "dout_aclk_kfc", + EN_PCLK_KFC, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_atbdownsizer63to32_kfc1", "dout_aclk_kfc", + EN_PCLK_KFC, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_atbdownsizer63to32_kfc0", "dout_aclk_kfc", + EN_PCLK_KFC, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_kfcp", "dout_pclk_kfc", EN_PCLK_KFC, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_nocp_kfc_225", "dout_pclk_kfc", EN_PCLK_KFC, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_dapapbmux_dbg", "dout_kfc_pclk_dbg", EN_PCLK_KFC, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_kfc", "dout_pclk_kfc", EN_PCLK_KFC, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_kfc", "dout_pclk_kfc", EN_PCLK_KFC, 0, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_kfc_hpm_targetclk", "dout_sclk_hpm_targetclk", + EN_SCLK_KFC, 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_MFC +*/ +struct samsung_gate_clock exynos5260_mfc_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_xiu_mfcx_2x1_top", "mout_aclk_mfc_333_user", + EN_ACLK_MFC, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mfcm1", "mout_aclk_mfc_333_user", EN_ACLK_MFC, + 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mfcm0", "mout_aclk_mfc_333_user", EN_ACLK_MFC, + 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_mfc", "mout_aclk_mfc_333_user", EN_ACLK_MFC, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_mfc_333", "mout_aclk_mfc_333_user", + EN_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), + GATE(MFC_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_333_user", EN_ACLK_MFC, + 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "aclk_smmu2_mfcm1", "mout_aclk_mfc_333_user", + EN_ACLK_SECURE_SMMU2_MFC, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "aclk_smmu2_mfcm0", "mout_aclk_mfc_333_user", + EN_ACLK_SECURE_SMMU2_MFC, 5, CLK_IGNORE_UNUSED, + 0), + + GATE(ID_NONE, "pclk_sysreg_mfc", "dout_pclk_mfc_83", EN_PCLK_MFC, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mfcm1", "dout_pclk_mfc_83", EN_PCLK_MFC, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mfcm0", "dout_pclk_mfc_83", EN_PCLK_MFC, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_mfc", "dout_pclk_mfc_83", EN_PCLK_MFC, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_mfc", "dout_pclk_mfc_83", EN_PCLK_MFC, 3, + CLK_IGNORE_UNUSED, 0), + GATE(MFC_PCLK_MFC, "pclk_mfc", "dout_pclk_mfc_83", EN_PCLK_MFC, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ahb2apb_mfcp", "dout_pclk_mfc_83", EN_PCLK_MFC, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_mfc_83", "dout_pclk_mfc_83", EN_PCLK_MFC, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(MFC_PCLK_SMMU_MFC1, "pclk_smmu2_mfcm1", "dout_pclk_mfc_83", + EN_PCLK_SECURE_SMMU2_MFC, 8, CLK_IGNORE_UNUSED, 0), + GATE(MFC_PCLK_SMMU_MFC0, "pclk_smmu2_mfcm0", "dout_pclk_mfc_83", + EN_PCLK_SECURE_SMMU2_MFC, 8, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_MIF +*/ +struct samsung_gate_clock exynos5260_mif_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_lpddr3phy_wrap_u1", "dout_clk2x_phy", EN_ACLK_MIF, + 22, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_lpddr3phy_wrap_u0", "dout_clk2x_phy", EN_ACLK_MIF, + 21, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ace_async_mi_top_kfc", "dout_aclk_mif_466", + EN_ACLK_MIF, 20, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ace_async_mi_top_egl", "dout_aclk_mif_466", + EN_ACLK_MIF, 19, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncahb_master_hclkm", "dout_aclk_mif_466", + EN_ACLK_MIF, 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ahb2axi_mmd32", "dout_aclk_mif_466", EN_ACLK_MIF, + 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axi_us_32to128_top_buf", "dout_aclk_mif_466", + EN_ACLK_MIF, 16, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_kfc", "dout_aclk_mif_466", EN_ACLK_MIF, 15, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_egl", "dout_aclk_mif_466", EN_ACLK_MIF, 14, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_drexi1_1", "dout_aclk_mif_466", EN_ACLK_MIF, + 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_drexi1_0", "dout_aclk_mif_466", EN_ACLK_MIF, + 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_drexi0_1", "dout_aclk_mif_466", EN_ACLK_MIF, + 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_drexi0_0", "dout_aclk_mif_466", EN_ACLK_MIF, + 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_kfc", "dout_aclk_mif_466", EN_ACLK_MIF, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_egl", "dout_aclk_mif_466", EN_ACLK_MIF, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_mif", "dout_aclk_mif_466", EN_ACLK_MIF, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_cci400", "dout_aclk_mif_466", EN_ACLK_MIF, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_mif_nocpnp_100", "dout_aclk_bus_100", + EN_ACLK_MIF, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_mif_nocdnp_200", "dout_aclk_bus_200", + EN_ACLK_MIF, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_mif_nocpnd_200", "dout_aclk_bus_200", + EN_ACLK_MIF, 1, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "aclk_drexi_v2_u1", "dout_aclk_bus_200", + EN_ACLK_MIF_SECURE_DREX1_TZ, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "aclk_drexi_v2_u0", "dout_aclk_bus_200", + EN_ACLK_MIF_SECURE_DREX0_TZ, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "aclk_intmem", "dout_aclk_bus_200", + EN_ACLK_MIF_SECURE_INTMEM, 0, CLK_IGNORE_UNUSED, + 0), + + GATE(ID_NONE, "pclk_sysreg_mif", "dout_aclk_bus_100", EN_PCLK_MIF, 21, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_mif", "dout_aclk_bus_100", EN_PCLK_MIF, 20, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_kfc", "dout_aclk_bus_100", EN_PCLK_MIF, 19, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_egl", "dout_aclk_bus_100", EN_PCLK_MIF, 18, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_drex1_1", "dout_aclk_bus_100", EN_PCLK_MIF, + 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_drex1_0", "dout_aclk_bus_100", EN_PCLK_MIF, + 16, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_drex0_1", "dout_aclk_bus_100", EN_PCLK_MIF, + 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_drex0_0", "dout_aclk_bus_100", EN_PCLK_MIF, + 14, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_kfc", "dout_aclk_bus_100", EN_PCLK_MIF, 13, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_egl", "dout_aclk_bus_100", EN_PCLK_MIF, 12, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_lpddr3phy_wrap_u1", "dout_aclk_bus_100", + EN_PCLK_MIF, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_lpddr3phy_wrap_u0", "dout_aclk_bus_100", + EN_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sfr_apbif", "dout_aclk_bus_100", EN_PCLK_MIF, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_gic_cpu", "dout_aclk_bus_100", EN_PCLK_MIF, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_axi2apb_csp", "dout_aclk_bus_100", EN_PCLK_MIF, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_axi2apb_cdrexp", "dout_aclk_bus_100", EN_PCLK_MIF, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_xiu_cnvsx", "dout_aclk_bus_100", EN_PCLK_MIF, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_cssys", "dout_aclk_bus_100", EN_PCLK_MIF, + 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_monocnt_apbif", "dout_aclk_bus_100", + EN_PCLK_MIF_SECURE_MONOCNT, 5, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_rtc_apbif", "dout_aclk_bus_100", + EN_PCLK_MIF_SECURE_RTC_APBIF, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_drexi_v2_u1", "dout_aclk_bus_100", + EN_PCLK_MIF_SECURE_DREX1_TZ, 0, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_drexi_v2_u0", "dout_aclk_bus_100", + EN_PCLK_MIF_SECURE_DREX0_TZ, 0, CLK_IGNORE_UNUSED, + 0), + + GATE(ID_NONE, "sclk_lpddr3phy_wrap_u1", "dout_clkm_phy", EN_SCLK_MIF, + 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_lpddr3phy_wrap_u0", "dout_clkm_phy", EN_SCLK_MIF, + 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_PERI +*/ +struct samsung_gate_clock exynos5260_peri_gate_clks[] __initdata = { + GATE(ID_NONE, "pclk_pmu_peri", "dout_aclk_peri_66", EN_PCLK_PERI0, 23, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2S1, "pclk_i2s1", "dout_aclk_peri_66", EN_PCLK_PERI0, + 22, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C7, "pclk_i2c7", "dout_aclk_peri_66", EN_PCLK_PERI0, + 20, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C6, "pclk_i2c6", "dout_aclk_peri_66", EN_PCLK_PERI0, + 19, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C5, "pclk_i2c5", "dout_aclk_peri_66", EN_PCLK_PERI0, + 18, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C4, "pclk_i2c4", "dout_aclk_peri_66", EN_PCLK_PERI0, + 17, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C9, "pclk_i2c9", "dout_aclk_peri_66", EN_PCLK_PERI0, + 16, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C8, "pclk_i2c8", "dout_aclk_peri_66", EN_PCLK_PERI0, + 15, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C11, "pclk_i2c11", "dout_aclk_peri_66", + EN_PCLK_PERI0, 14, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C10, "pclk_i2c10", "dout_aclk_peri_66", + EN_PCLK_PERI0, 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_hdmicec", "dout_aclk_peri_66", EN_PCLK_PERI0, 12, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_cmutop", "dout_aclk_peri_66", EN_PCLK_PERI0, 11, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_efuse_writer_sc", "dout_aclk_peri_66", + EN_PCLK_PERI0, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_efuse_writer_nsc", "dout_aclk_peri_66", + EN_PCLK_PERI0, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "nclk_perinp", "dout_aclk_peri_66", EN_PCLK_PERI0, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_peris1p", "dout_aclk_peri_66", EN_PCLK_PERI0, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_peris0p", "dout_aclk_peri_66", EN_PCLK_PERI0, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_perih", "dout_aclk_peri_66", EN_PCLK_PERI0, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_peric1p", "dout_aclk_peri_66", EN_PCLK_PERI0, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_peric0p", "dout_aclk_peri_66", EN_PCLK_PERI0, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_asv_tbl", "dout_aclk_peri_66", EN_PCLK_PERI1, 20, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_ADC, "pclk_adc", "dout_aclk_peri_66", EN_PCLK_PERI1, + 15, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_TMU1, "pclk_tmu1", "dout_aclk_peri_66", EN_PCLK_PERI1, + 14, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_TMU0, "pclk_tmu0", "dout_aclk_peri_66", EN_PCLK_PERI1, + 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_peri", "dout_aclk_peri_66", EN_PCLK_PERI1, + 12, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_SPI2, "pclk_spi2", "dout_aclk_peri_66", EN_PCLK_PERI1, + 11, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_SPI1, "pclk_spi1", "dout_aclk_peri_66", EN_PCLK_PERI1, + 10, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_SPI0, "pclk_spi0", "dout_aclk_peri_66", EN_PCLK_PERI1, + 9, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_SPDIF, "pclk_spdif", "dout_aclk_peri_66", + EN_PCLK_PERI1, 8, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_PWM, "pclk_pwm", "dout_aclk_peri_66", EN_PCLK_PERI1, 5, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_ABB, "pclk_abb", "dout_aclk_peri_66", EN_PCLK_PERI1, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pcm1", "dout_aclk_peri_66", EN_PCLK_PERI1, 1, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_MCT, "pclk_mct", "dout_aclk_peri_66", EN_PCLK_PERI1, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(PERI_PCLK_HSIC3, "pclk_hsic3", "dout_aclk_peri_66", + EN_PCLK_PERI2, 17, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_HSIC2, "pclk_hsic2", "dout_aclk_peri_66", + EN_PCLK_PERI2, 15, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_HSIC1, "pclk_hsic1", "dout_aclk_peri_66", + EN_PCLK_PERI2, 13, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_HSIC0, "pclk_hsic0", "dout_aclk_peri_66", + EN_PCLK_PERI2, 11, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_UART0, "pclk_uart0", "dout_aclk_peri_66", + EN_PCLK_PERI2, 9, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_UART2, "pclk_uart2", "dout_aclk_peri_66", + EN_PCLK_PERI2, 8, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_UART1, "pclk_uart1", "dout_aclk_peri_66", + EN_PCLK_PERI2, 7, CLK_IGNORE_UNUSED, 0), + + GATE(PERI_PCLK_WDT_KFC, "pclk_wdt_kfc", "dout_aclk_peri_66", + EN_PCLK_PERI3, 20, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_WDT_EGL, "pclk_wdt_egl", "dout_aclk_peri_66", + EN_PCLK_PERI3, 19, CLK_IGNORE_UNUSED, 0), + + GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2", + EN_SCLK_PERI, 12, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1", + EN_SCLK_PERI, 11, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0", + EN_SCLK_PERI, 10, CLK_IGNORE_UNUSED, 0), + + GATE(PERI_PCLK_CHIPID, "pclk_chipid", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_CHIPID, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_provkey0", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_PROVKEY0, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_provkey1", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_PROVKEY1, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_seckey", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_SECKEY, 7, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_antirbkcnt", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_ANTIRBKCNT, 7, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_TOP_RTC, "pclk_top_rtc", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TOP_RTC, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc3", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 19, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc2", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 18, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc1", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 17, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc0", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 16, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc10", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc9", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc8", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc7", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc6", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc5", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc4", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, + 0), + + GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b", + EN_SCLK_PERI, 9, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b", + EN_SCLK_PERI, 8, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b", + EN_SCLK_PERI, 7, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b", + EN_SCLK_PERI, 2, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(PERI_SCLK_RTC, "sclk_rtc_clkout", "xrtcxti", + EN_SCLK_PERI_SECURE_TOP_RTC, 7, CLK_IGNORE_UNUSED, + 0), +}; + +/* + * List of Gate clocks for CMU_TOP +*/ +struct samsung_gate_clock exynos5260_top_gate_clks[] __initdata = { + GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel", + EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED, 0), + GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin", + "dout_sclk_fsys_mmc2_sdclkin_b", EN_SCLK_TOP, 9, + CLK_SET_RATE_PARENT, + 0), + GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin", + "dout_sclk_fsys_mmc1_sdclkin_b", EN_SCLK_TOP, 8, + CLK_SET_RATE_PARENT, + 0), + GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", + "dout_sclk_fsys_mmc0_sdclkin_b", EN_SCLK_TOP, 7, + CLK_SET_RATE_PARENT, + 0), +}; + +/* +* Applicable for all 2550 Type PLLS for Exynos5260, listed below +* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, +* BUS_PLL, MEDIA_PLL, G3D_PLL. +*/ +static const struct samsung_pll_rate_table exynos5260_pll2550_24mhz_tbl[] = { + PLL_35XX_RATE(1700000000, 425, 6, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 400, 4, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(933000000, 311, 4, 1), + PLL_35XX_RATE(900000000, 300, 4, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(733000000, 733, 12, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(667000000, 667, 12, 1), + PLL_35XX_RATE(633000000, 211, 4, 1), + PLL_35XX_RATE(620000000, 310, 3, 2), + PLL_35XX_RATE(600000000, 400, 4, 2), + PLL_35XX_RATE(543000000, 362, 4, 2), + PLL_35XX_RATE(533000000, 533, 6, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(450000000, 300, 4, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(350000000, 175, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(266000000, 266, 3, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + PLL_35XX_RATE(160000000, 160, 3, 3), +}; + +/* +* Applicable for 2650 Type PLL for AUD_PLL. +*/ +static const struct samsung_pll_rate_table exynos5260_pll2650_24mhz_tbl[] = { + PLL_36XX_RATE(1600000000, 200, 3, 0, 0), + PLL_36XX_RATE(1200000000, 100, 2, 0, 0), + PLL_36XX_RATE(1000000000, 250, 3, 1, 0), + PLL_36XX_RATE(800000000, 200, 3, 1, 0), + PLL_36XX_RATE(600000000, 100, 2, 1, 0), + PLL_36XX_RATE(532000000, 266, 3, 2, 0), + PLL_36XX_RATE(480000000, 160, 2, 2, 0), + PLL_36XX_RATE(432000000, 144, 2, 2, 0), + PLL_36XX_RATE(400000000, 200, 3, 2, 0), + PLL_36XX_RATE(394216000, 459, 7, 2, 49282), + PLL_36XX_RATE(333000000, 111, 2, 2, 0), + PLL_36XX_RATE(300000000, 100, 2, 2, 0), + PLL_36XX_RATE(266000000, 266, 3, 3, 0), + PLL_36XX_RATE(200000000, 200, 3, 3, 0), + PLL_36XX_RATE(166000000, 166, 3, 3, 0), + PLL_36XX_RATE(133000000, 266, 3, 4, 0), + PLL_36XX_RATE(100000000, 200, 3, 4, 0), + PLL_36XX_RATE(66000000, 176, 2, 5, 0), +}; + +static struct of_device_id ext_clk_match[] __initdata = { + { .compatible = "samsung,exynos5260-oscclk", .data = (void *)0, }, + { }, +}; + +static struct of_device_id cmu_subtype_match_table[] = { + { + .compatible = "exynos5260-cmu-all", + .data = (void *)CMU_TYPE_ALL, + }, { + .compatible = "exynos5260-cmu-top", + .data = (void *)CMU_TYPE_TOP, + }, { + .compatible = "exynos5260-cmu-peri", + .data = (void *)CMU_TYPE_PERI, + }, { + .compatible = "exynos5260-cmu-egl", + .data = (void *)CMU_TYPE_EGL, + }, { + .compatible = "exynos5260-cmu-kfc", + .data = (void *)CMU_TYPE_KFC, + }, { + .compatible = "exynos5260-cmu-g2d", + .data = (void *)CMU_TYPE_G2D, + }, { + .compatible = "exynos5260-cmu-mif", + .data = (void *)CMU_TYPE_MIF, + }, { + .compatible = "exynos5260-cmu-mfc", + .data = (void *)CMU_TYPE_MFC, + }, { + .compatible = "exynos5260-cmu-g3d", + .data = (void *)CMU_TYPE_G3D, + }, { + .compatible = "exynos5260-cmu-fsys", + .data = (void *)CMU_TYPE_FSYS, + }, { + .compatible = "exynos5260-cmu-aud", + .data = (void *)CMU_TYPE_AUD, + }, { + .compatible = "exynos5260-cmu-isp", + .data = (void *)CMU_TYPE_ISP, + }, { + .compatible = "exynos5260-cmu-gscl", + .data = (void *)CMU_TYPE_GSCL, + }, { + .compatible = "exynos5260-cmu-disp", + .data = (void *)CMU_TYPE_DISP, + }, { + /* end node */ + } +}; + +static struct samsung_pll_clock exynos5260_top_pll_clks[] __initdata = { + PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", + DISP_PLL_LOCK, DISP_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", + AUD_PLL_LOCK, AUD_PLL_CON0, + exynos5260_pll2650_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_egl_pll_clks[] __initdata = { + PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll", + EGL_PLL_LOCK, EGL_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_kfc_pll_clks[] __initdata = { + PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll", + KFC_PLL_LOCK, KFC_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_mif_pll_clks[] __initdata = { + PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll", + MEM_PLL_LOCK, MEM_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll", + BUS_PLL_LOCK, BUS_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll", + MEDIA_PLL_LOCK, MEDIA_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_g3d_pll_clks[] __initdata = { + PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll", + G3D_PLL_LOCK, G3D_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +void __init exynos5260_clk_init(struct device_node *np) +{ + void __iomem *reg_base; + const struct of_device_id *match; + struct samsung_clk_reg_dump *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine soc\n", __func__); + + match = of_match_node(cmu_subtype_match_table, np); + + if (!match) + panic("%s: cmu type (%s) is not supported.\n", __func__, + np->name); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + if ((int)match->data == CMU_TYPE_AUD) { + rdump = exynos5260_aud_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_aud_clk_regs); + + ctx = samsung_clk_init(np, reg_base, AUD_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_aud_mux_clks, + ARRAY_SIZE(exynos5260_aud_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_aud_div_clks, + ARRAY_SIZE(exynos5260_aud_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_aud_gate_clks, + ARRAY_SIZE(exynos5260_aud_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_DISP) { + rdump = exynos5260_disp_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_disp_clk_regs); + + ctx = samsung_clk_init(np, reg_base, DISP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_disp_mux_clks, + ARRAY_SIZE(exynos5260_disp_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_disp_div_clks, + ARRAY_SIZE(exynos5260_disp_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_disp_gate_clks, + ARRAY_SIZE(exynos5260_disp_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_EGL) { + rdump = exynos5260_egl_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_egl_clk_regs); + + ctx = samsung_clk_init(np, reg_base, EGL_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_egl_pll_clks, + ARRAY_SIZE(exynos5260_egl_pll_clks), + reg_base); + + samsung_clk_register_mux(ctx, exynos5260_egl_mux_clks, + ARRAY_SIZE(exynos5260_egl_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_egl_div_clks, + ARRAY_SIZE(exynos5260_egl_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_egl_gate_clks, + ARRAY_SIZE(exynos5260_egl_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_FSYS) { + rdump = exynos5260_fsys_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_fsys_clk_regs); + + ctx = samsung_clk_init(np, reg_base, FSYS_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_fsys_mux_clks, + ARRAY_SIZE(exynos5260_fsys_mux_clks)); + samsung_clk_register_gate(ctx, exynos5260_fsys_gate_clks, + ARRAY_SIZE(exynos5260_fsys_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_G2D) { + rdump = exynos5260_g2d_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_g2d_clk_regs); + + ctx = samsung_clk_init(np, reg_base, G2D_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_g2d_mux_clks, + ARRAY_SIZE(exynos5260_g2d_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_g2d_div_clks, + ARRAY_SIZE(exynos5260_g2d_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_g2d_gate_clks, + ARRAY_SIZE(exynos5260_g2d_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_G3D) { + rdump = exynos5260_g3d_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_g3d_clk_regs); + + ctx = samsung_clk_init(np, reg_base, G3D_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + samsung_clk_register_pll(ctx, exynos5260_g3d_pll_clks, + ARRAY_SIZE(exynos5260_g3d_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_g3d_mux_clks, + ARRAY_SIZE(exynos5260_g3d_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_g3d_div_clks, + ARRAY_SIZE(exynos5260_g3d_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_g3d_gate_clks, + ARRAY_SIZE(exynos5260_g3d_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_GSCL) { + rdump = exynos5260_gscl_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_gscl_clk_regs); + + ctx = samsung_clk_init(np, reg_base, GSCL_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_gscl_mux_clks, + ARRAY_SIZE(exynos5260_gscl_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_gscl_div_clks, + ARRAY_SIZE(exynos5260_gscl_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_gscl_gate_clks, + ARRAY_SIZE(exynos5260_gscl_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_ISP) { + rdump = exynos5260_isp_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_isp_clk_regs); + + ctx = samsung_clk_init(np, reg_base, ISP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_isp_mux_clks, + ARRAY_SIZE(exynos5260_isp_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_isp_div_clks, + ARRAY_SIZE(exynos5260_isp_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_isp_gate_clks, + ARRAY_SIZE(exynos5260_isp_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_KFC) { + rdump = exynos5260_kfc_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_kfc_clk_regs); + + ctx = samsung_clk_init(np, reg_base, KFC_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_kfc_pll_clks, + ARRAY_SIZE(exynos5260_kfc_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_kfc_mux_clks, + ARRAY_SIZE(exynos5260_kfc_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_kfc_div_clks, + ARRAY_SIZE(exynos5260_kfc_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_kfc_gate_clks, + ARRAY_SIZE(exynos5260_kfc_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_MFC) { + rdump = exynos5260_mfc_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_mfc_clk_regs); + + ctx = samsung_clk_init(np, reg_base, MFC_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_mfc_mux_clks, + ARRAY_SIZE(exynos5260_mfc_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_mfc_div_clks, + ARRAY_SIZE(exynos5260_mfc_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_mfc_gate_clks, + ARRAY_SIZE(exynos5260_mfc_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_MIF) { + rdump = exynos5260_mif_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_mif_clk_regs); + + ctx = samsung_clk_init(np, reg_base, MIF_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_mif_pll_clks, + ARRAY_SIZE(exynos5260_mif_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_mif_mux_clks, + ARRAY_SIZE(exynos5260_mif_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_mif_div_clks, + ARRAY_SIZE(exynos5260_mif_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_mif_gate_clks, + ARRAY_SIZE(exynos5260_mif_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_PERI) { + rdump = exynos5260_peri_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_peri_clk_regs); + + ctx = samsung_clk_init(np, reg_base, PERI_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_peri_mux_clks, + ARRAY_SIZE(exynos5260_peri_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_peri_div_clks, + ARRAY_SIZE(exynos5260_peri_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_peri_gate_clks, + ARRAY_SIZE(exynos5260_peri_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_TOP) { + rdump = exynos5260_top_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_top_clk_regs); + + ctx = samsung_clk_init(np, reg_base, TOP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, + exynos5260_fixed_rate_ext_clks, + ARRAY_SIZE( + exynos5260_fixed_rate_ext_clks), + ext_clk_match); + + samsung_clk_register_fixed_rate(ctx, + exynos5260_fixed_rate_clks, + ARRAY_SIZE(exynos5260_fixed_rate_clks)); + + samsung_clk_register_pll(ctx, exynos5260_top_pll_clks, + ARRAY_SIZE(exynos5260_top_pll_clks), + + reg_base); + + samsung_clk_register_mux(ctx, exynos5260_top_mux_clks, + ARRAY_SIZE(exynos5260_top_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_top_div_clks, + ARRAY_SIZE(exynos5260_top_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_top_gate_clks, + ARRAY_SIZE(exynos5260_top_gate_clks)); + } else { + panic("%s: invalid cmu sub-type.\n", __func__); + }; + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +CLK_OF_DECLARE(exynos5260_clk, "samsung,exynos5260-clock", exynos5260_clk_init); + + + + + + + diff --git a/drivers/clk/samsung/clk-exynos5260.h b/drivers/clk/samsung/clk-exynos5260.h new file mode 100644 index 0000000..def73e6 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5260.h @@ -0,0 +1,496 @@ +#ifndef __CLK_EXYNOS5260_H +#define __CLK_EXYNOS5260_H + +#define CMU_TYPE_AUD 1 +#define CMU_TYPE_DISP 2 +#define CMU_TYPE_EGL 3 +#define CMU_TYPE_FSYS 4 +#define CMU_TYPE_G2D 5 +#define CMU_TYPE_G3D 6 +#define CMU_TYPE_GSCL 7 +#define CMU_TYPE_ISP 8 +#define CMU_TYPE_KFC 9 +#define CMU_TYPE_MFC 10 +#define CMU_TYPE_MIF 11 +#define CMU_TYPE_PERI 12 +#define CMU_TYPE_TOP 13 + +#define CMU_TYPE_ALL 14 + +/* +*Base address for different CMUs +*TODO: All Bases should be removed at earliest. +*/ +#define CMU_AUD_BASE 0x128C0000 +#define CMU_DISP_BASE 0x14550000 +#define CMU_EGL_BASE 0x10600000 +#define CMU_FSYS_BASE 0x122E0000 +#define CMU_G2D_BASE 0x10A00000 +#define CMU_G3D_BASE 0x11830000 +#define CMU_GSCL_BASE 0x13F00000 +#define CMU_ISP_BASE 0x133C0000 +#define CMU_KFC_BASE 0x10700000 +#define CMU_MFC_BASE 0x11090000 +#define CMU_MIF_BASE 0x10CE0000 +#define CMU_PERI_BASE 0x10200000 +#define CMU_TOP_BASE 0x10010000 + +#define AUD_REG(x) (x) +#define DISP_REG(x) (x) +#define EGL_REG(x) (x) +#define FSYS_REG(x) (x) +#define G2D_REG(x) (x) +#define G3D_REG(x) (x) +#define GSCL_REG(x) (x) +#define ISP_REG(x) (x) +#define KFC_REG(x) (x) +#define MFC_REG(x) (x) +#define MIF_REG(x) (x) +#define PERI_REG(x) (x) +#define TOP_REG(x) (x) + +/* +*Registers for CMU_AUD +*/ +#define MUX_SEL_AUD AUD_REG(0x0200) +#define MUX_ENABLE_AUD AUD_REG(0x0300) +#define MUX_STAT_AUD AUD_REG(0x0400) +#define MUX_IGNORE_AUD AUD_REG(0x0500) +#define DIV_AUD0 AUD_REG(0x0600) +#define DIV_AUD1 AUD_REG(0x0604) +#define DIV_STAT_AUD0 AUD_REG(0x0700) +#define DIV_STAT_AUD1 AUD_REG(0x0704) +#define EN_ACLK_AUD AUD_REG(0x0800) +#define EN_PCLK_AUD AUD_REG(0x0900) +#define EN_SCLK_AUD AUD_REG(0x0a00) +#define EN_IP_AUD AUD_REG(0x0b00) + +/* +*Registers for CMU_DISP +*/ +#define MUX_SEL_DISP0 DISP_REG(0x0200) +#define MUX_SEL_DISP1 DISP_REG(0x0204) +#define MUX_SEL_DISP2 DISP_REG(0x0208) +#define MUX_SEL_DISP3 DISP_REG(0x020C) +#define MUX_SEL_DISP4 DISP_REG(0x0210) +#define MUX_ENABLE_DISP0 DISP_REG(0x0300) +#define MUX_ENABLE_DISP1 DISP_REG(0x0304) +#define MUX_ENABLE_DISP2 DISP_REG(0x0308) +#define MUX_ENABLE_DISP3 DISP_REG(0x030c) +#define MUX_ENABLE_DISP4 DISP_REG(0x0310) +#define MUX_STAT_DISP0 DISP_REG(0x0400) +#define MUX_STAT_DISP1 DISP_REG(0x0404) +#define MUX_STAT_DISP2 DISP_REG(0x0408) +#define MUX_STAT_DISP3 DISP_REG(0x040c) +#define MUX_STAT_DISP4 DISP_REG(0x0410) +#define MUX_IGNORE_DISP0 DISP_REG(0x0500) +#define MUX_IGNORE_DISP1 DISP_REG(0x0504) +#define MUX_IGNORE_DISP2 DISP_REG(0x0508) +#define MUX_IGNORE_DISP3 DISP_REG(0x050c) +#define MUX_IGNORE_DISP4 DISP_REG(0x0510) +#define DIV_DISP DISP_REG(0x0600) +#define DIV_STAT_DISP DISP_REG(0x0700) +#define EN_ACLK_DISP DISP_REG(0x0800) +#define EN_PCLK_DISP DISP_REG(0x0900) +#define EN_SCLK_DISP0 DISP_REG(0x0a00) +#define EN_SCLK_DISP1 DISP_REG(0x0a04) +#define EN_IP_DISP DISP_REG(0x0b00) +#define EN_IP_DISP_BUS DISP_REG(0x0b04) + + +/* +*Registers for CMU_EGL +*/ +#define EGL_PLL_LOCK EGL_REG(0x0000) +#define EGL_DPLL_LOCK EGL_REG(0x0004) +#define EGL_PLL_CON0 EGL_REG(0x0100) +#define EGL_PLL_CON1 EGL_REG(0x0104) +#define EGL_PLL_FREQ_DET EGL_REG(0x010c) +#define EGL_DPLL_CON0 EGL_REG(0x0110) +#define EGL_DPLL_CON1 EGL_REG(0x0114) +#define EGL_DPLL_FREQ_DET EGL_REG(0x011c) +#define MUX_SEL_EGL EGL_REG(0x0200) +#define MUX_ENABLE_EGL EGL_REG(0x0300) +#define MUX_STAT_EGL EGL_REG(0x0400) +#define DIV_EGL EGL_REG(0x0600) +#define DIV_EGL_PLL_FDET EGL_REG(0x0604) +#define DIV_STAT_EGL EGL_REG(0x0700) +#define DIV_STAT_EGL_PLL_FDET EGL_REG(0x0704) +#define EN_ACLK_EGL EGL_REG(0x0800) +#define EN_PCLK_EGL EGL_REG(0x0900) +#define EN_SCLK_EGL EGL_REG(0x0a00) +#define EN_IP_EGL EGL_REG(0x0b00) +#define CLKOUT_CMU_EGL EGL_REG(0x0c00) +#define CLKOUT_CMU_EGL_DIV_STAT EGL_REG(0x0c04) +#define ARMCLK_STOPCTRL EGL_REG(0x1000) +#define EAGLE_EMA_CTRL EGL_REG(0x1008) +#define EAGLE_EMA_STATUS EGL_REG(0x100c) +#define PWR_CTRL EGL_REG(0x1020) +#define PWR_CTRL2 EGL_REG(0x1024) +#define CLKSTOP_CTRL EGL_REG(0x1028) +#define INTR_SPREAD_EN EGL_REG(0x1080) +#define INTR_SPREAD_USE_STANDBYWFI EGL_REG(0x1084) +#define INTR_SPREAD_BLOCKING_DURATION EGL_REG(0x1088) +#define CMU_EGL_SPARE0 EGL_REG(0x2000) +#define CMU_EGL_SPARE1 EGL_REG(0x2004) +#define CMU_EGL_SPARE2 EGL_REG(0x2008) +#define CMU_EGL_SPARE3 EGL_REG(0x200c) +#define CMU_EGL_SPARE4 EGL_REG(0x2010) + +/* +*Registers for CMU_FSYS +*/ + +#define MUX_SEL_FSYS0 FSYS_REG(0x0200) +#define MUX_SEL_FSYS1 FSYS_REG(0x0204) +#define MUX_ENABLE_FSYS0 FSYS_REG(0x0300) +#define MUX_ENABLE_FSYS1 FSYS_REG(0x0304) +#define MUX_STAT_FSYS0 FSYS_REG(0x0400) +#define MUX_STAT_FSYS1 FSYS_REG(0x0404) +#define MUX_IGNORE_FSYS0 FSYS_REG(0x0500) +#define MUX_IGNORE_FSYS1 FSYS_REG(0x0504) +#define EN_ACLK_FSYS FSYS_REG(0x0800) +#define EN_ACLK_FSYS_SECURE_RTIC FSYS_REG(0x0804) +#define EN_ACLK_FSYS_SECURE_SMMU_RTIC FSYS_REG(0x0808) +#define EN_PCLK_FSYS FSYS_REG(0x0900) +#define EN_SCLK_FSYS FSYS_REG(0x0a00) +#define EN_IP_FSYS FSYS_REG(0x0b00) +#define EN_IP_FSYS_SECURE_RTIC FSYS_REG(0x0b04) +#define EN_IP_FSYS_SECURE_SMMU_RTIC FSYS_REG(0x0b08) + +/* +*Registers for CMU_G2D +*/ + +#define MUX_SEL_G2D G2D_REG(0x0200) +#define MUX_ENABLE_G2D G2D_REG(0x0300) +#define MUX_STAT_G2D G2D_REG(0x0400) +#define DIV_G2D G2D_REG(0x0600) +#define DIV_STAT_G2D G2D_REG(0x0700) +#define EN_ACLK_G2D G2D_REG(0x0800) +#define EN_ACLK_G2D_SECURE_SSS G2D_REG(0x0804) +#define EN_ACLK_G2D_SECURE_SLIM_SSS G2D_REG(0x0808) +#define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x080c) +#define EN_ACLK_G2D_SECURE_SMMU_SSS G2D_REG(0x0810) +#define EN_ACLK_G2D_SECURE_SMMU_MDMA G2D_REG(0x0814) +#define EN_ACLK_G2D_SECURE_SMMU_G2D G2D_REG(0x0818) +#define EN_PCLK_G2D G2D_REG(0x0900) +#define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x0904) +#define EN_PCLK_G2D_SECURE_SMMU_SSS G2D_REG(0x0908) +#define EN_PCLK_G2D_SECURE_SMMU_MDMA G2D_REG(0x090c) +#define EN_PCLK_G2D_SECURE_SMMU_G2D G2D_REG(0x0910) +#define EN_IP_G2D G2D_REG(0x0b00) +#define EN_IP_G2D_SECURE_SSS G2D_REG(0x0b04) +#define EN_IP_G2D_SECURE_SLIM_SSS G2D_REG(0x0b08) +#define EN_IP_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x0b0c) +#define EN_IP_G2D_SECURE_SMMU_SSS G2D_REG(0x0b10) +#define EN_IP_G2D_SECURE_SMMU_MDMA G2D_REG(0x0b14) +#define EN_IP_G2D_SECURE_SMMU_G2D G2D_REG(0x0b18) + +/* +*Registers for CMU_G3D +*/ + +#define G3D_PLL_LOCK G3D_REG(0x0000) +#define G3D_PLL_CON0 G3D_REG(0x0100) +#define G3D_PLL_CON1 G3D_REG(0x0104) +#define G3D_PLL_FDET G3D_REG(0x010c) +#define MUX_SEL_G3D G3D_REG(0x0200) +#define MUX_EN_G3D G3D_REG(0x0300) +#define MUX_STAT_G3D G3D_REG(0x0400) +#define MUX_IGNORE_G3D G3D_REG(0x0500) +#define DIV_G3D G3D_REG(0x0600) +#define DIV_G3D_PLL_FDET G3D_REG(0x0604) +#define DIV_STAT_G3D G3D_REG(0x0700) +#define DIV_STAT_G3D_PLL_FDET G3D_REG(0x0704) +#define EN_ACLK_G3D G3D_REG(0x0800) +#define EN_PCLK_G3D G3D_REG(0x0900) +#define EN_SCLK_G3D G3D_REG(0x0a00) +#define EN_IP_G3D G3D_REG(0x0b00) +#define CLKOUT_CMU_G3D G3D_REG(0x0c00) +#define CLKOUT_CMU_G3D_DIV_STAT G3D_REG(0x0c04) +#define G3DCLK_STOPCTRL G3D_REG(0x1000) +#define G3D_EMA_CTRL G3D_REG(0x1008) +#define G3D_EMA_STATUS G3D_REG(0x100c) + +/* +*Registers for CMU_GSCL +*/ + +#define MUX_SEL_GSCL GSCL_REG(0x0200) +#define MUX_EN_GSCL GSCL_REG(0x0300) +#define MUX_STAT_GSCL GSCL_REG(0x0400) +#define MUX_IGNORE_GSCL GSCL_REG(0x0500) +#define DIV_GSCL GSCL_REG(0x0600) +#define DIV_STAT_GSCL GSCL_REG(0x0700) +#define EN_ACLK_GSCL GSCL_REG(0x0800) +#define EN_ACLK_GSCL_FIMC GSCL_REG(0x0804) +#define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0808) +#define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x080c) +#define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0810) +#define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0814) +#define EN_PCLK_GSCL GSCL_REG(0x0900) +#define EN_PCLK_GSCL_FIMC GSCL_REG(0x0904) +#define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0908) +#define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x090c) +#define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0910) +#define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0914) +#define EN_SCLK_GSCL GSCL_REG(0x0a00) +#define EN_SCLK_GSCL_FIMC GSCL_REG(0x0a04) +#define EN_IP_GSCL GSCL_REG(0x0b00) +#define EN_IP_GSCL_FIMC GSCL_REG(0x0b04) +#define EN_IP_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0b08) +#define EN_IP_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x0b0c) +#define EN_IP_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0b10) +#define EN_IP_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0b14) + +/* +*Registers for CMU_ISP +*/ +#define MUX_SEL_ISP0 ISP_REG(0x0200) +#define MUX_SEL_ISP1 ISP_REG(0x0204) +#define MUX_ENABLE_ISP0 ISP_REG(0x0300) +#define MUX_ENABLE_ISP1 ISP_REG(0x0304) +#define MUX_STAT_ISP0 ISP_REG(0x0400) +#define MUX_STAT_ISP1 ISP_REG(0x0404) +#define MUX_IGNORE_ISP0 ISP_REG(0x0500) +#define MUX_IGNORE_ISP1 ISP_REG(0x0504) +#define DIV_ISP ISP_REG(0x0600) +#define DIV_STAT_ISP ISP_REG(0x0700) +#define EN_ACLK_ISP0 ISP_REG(0x0800) +#define EN_ACLK_ISP1 ISP_REG(0x0804) +#define EN_PCLK_ISP0 ISP_REG(0x0900) +#define EN_PCLK_ISP1 ISP_REG(0x0904) +#define EN_SCLK_ISP ISP_REG(0x0a00) +#define EN_IP_ISP0 ISP_REG(0x0b00) +#define EN_IP_ISP1 ISP_REG(0x0b04) + +/* +*Registers for CMU_KFC +*/ +#define KFC_PLL_LOCK KFC_REG(0x0000) +#define KFC_PLL_CON0 KFC_REG(0x0100) +#define KFC_PLL_CON1 KFC_REG(0x0104) +#define KFC_PLL_FDET KFC_REG(0x010c) +#define MUX_SEL_KFC0 KFC_REG(0x0200) +#define MUX_SEL_KFC2 KFC_REG(0x0208) +#define MUX_ENABLE_KFC0 KFC_REG(0x0300) +#define MUX_ENABLE_KFC2 KFC_REG(0x0308) +#define MUX_STAT_KFC0 KFC_REG(0x0400) +#define MUX_STAT_KFC2 KFC_REG(0x0408) +#define DIV_KFC KFC_REG(0x0600) +#define DIV_KFC_PLL_FDET KFC_REG(0x0604) +#define DIV_STAT_KFC KFC_REG(0x0700) +#define DIV_STAT_KFC_PLL_FDET KFC_REG(0x0704) +#define EN_ACLK_KFC KFC_REG(0x0800) +#define EN_PCLK_KFC KFC_REG(0x0900) +#define EN_SCLK_KFC KFC_REG(0x0a00) +#define EN_IP_KFC KFC_REG(0x0b00) +#define CLKOUT_CMU_KFC KFC_REG(0x0c00) +#define CLKOUT_CMU_KFC_DIV_STAT KFC_REG(0x0c04) +#define ARMCLK_STOPCTRL_KFC KFC_REG(0x1000) +#define ARM_EMA_CTRL KFC_REG(0x1008) +#define ARM_EMA_STATUS KFC_REG(0x100c) +#define PWR_CTRL_KFC KFC_REG(0x1020) +#define PWR_CTRL2_KFC KFC_REG(0x1024) +#define CLKSTOP_CTRL_KFC KFC_REG(0x1028) +#define INTR_SPREAD_ENABLE_KFC KFC_REG(0x1080) +#define INTR_SPREAD_USE_STANDBYWFI_KFC KFC_REG(0x1084) +#define INTR_SPREAD_BLOCKING_DURATION_KFC KFC_REG(0x1088) +#define CMU_KFC_SPARE0 KFC_REG(0x2000) +#define CMU_KFC_SPARE1 KFC_REG(0x2004) +#define CMU_KFC_SPARE2 KFC_REG(0x2008) +#define CMU_KFC_SPARE3 KFC_REG(0x200c) +#define CMU_KFC_SPARE4 KFC_REG(0x2010) + +/* +*Registers for CMU_MFC +*/ +#define MUX_SEL_MFC MFC_REG(0x0200) +#define MUX_ENABLE_MFC MFC_REG(0x0300) +#define MUX_STAT_MFC MFC_REG(0x0400) +#define DIV_MFC MFC_REG(0x0600) +#define DIV_STAT_MFC MFC_REG(0x0700) +#define EN_ACLK_MFC MFC_REG(0x0800) +#define EN_ACLK_SECURE_SMMU2_MFC MFC_REG(0x0804) +#define EN_PCLK_MFC MFC_REG(0x0900) +#define EN_PCLK_SECURE_SMMU2_MFC MFC_REG(0x0904) +#define EN_IP_MFC MFC_REG(0x0b00) +#define EN_IP_SECURE_SMMU2_MFC MFC_REG(0x0b04) + +/* +*Registers for CMU_MIF +*/ +#define MEM_PLL_LOCK MIF_REG(0x0000) +#define BUS_PLL_LOCK MIF_REG(0x0004) +#define MEDIA_PLL_LOCK MIF_REG(0x0008) +#define MEM_PLL_CON0 MIF_REG(0x0100) +#define MEM_PLL_CON1 MIF_REG(0x0104) +#define MEM_PLL_FDET MIF_REG(0x010c) +#define BUS_PLL_CON0 MIF_REG(0x0110) +#define BUS_PLL_CON1 MIF_REG(0x0114) +#define BUS_PLL_FDET MIF_REG(0x011c) +#define MEDIA_PLL_CON0 MIF_REG(0x0120) +#define MEDIA_PLL_CON1 MIF_REG(0x0124) +#define MEDIA_PLL_FDET MIF_REG(0x012c) +#define MUX_SEL_MIF MIF_REG(0x0200) +#define MUX_ENABLE_MIF MIF_REG(0x0300) +#define MUX_STAT_MIF MIF_REG(0x0400) +#define MUX_IGNORE_MIF MIF_REG(0x0500) +#define DIV_MIF MIF_REG(0x0600) +#define DIV_MIF_PLL_FDET MIF_REG(0x0604) +#define DIV_STAT_MIF MIF_REG(0x0700) +#define DIV_STAT_MIF_PLL_FDET MIF_REG(0x0704) +#define EN_ACLK_MIF MIF_REG(0x0800) +#define EN_ACLK_MIF_SECURE_DREX1_TZ MIF_REG(0x0804) +#define EN_ACLK_MIF_SECURE_DREX0_TZ MIF_REG(0x0808) +#define EN_ACLK_MIF_SECURE_INTMEM MIF_REG(0x080c) +#define EN_PCLK_MIF MIF_REG(0x0900) +#define EN_PCLK_MIF_SECURE_MONOCNT MIF_REG(0x0904) +#define EN_PCLK_MIF_SECURE_RTC_APBIF MIF_REG(0x0908) +#define EN_PCLK_MIF_SECURE_DREX1_TZ MIF_REG(0x090c) +#define EN_PCLK_MIF_SECURE_DREX0_TZ MIF_REG(0x0910) +#define EN_SCLK_MIF MIF_REG(0x0a00) +#define EN_IP_MIF MIF_REG(0x0b00) +#define EN_IP_MIF_SECURE_MONOCNT MIF_REG(0x0b04) +#define EN_IP_MIF_SECURE_RTC_APBIF MIF_REG(0x0b08) +#define EN_IP_MIF_SECURE_DREX1_TZ MIF_REG(0x0b0c)EN_ACLK_MIF_SECURE_INTMEM +#define EN_IP_MIF_SECURE_DREX0_TZ MIF_REG(0x0b10) +#define EN_IP_MIF_SECURE_INTEMEM MIF_REG(0x0b14) +#define CLKOUT_CMU_MIF_DIV_STAT MIF_REG(0x0c04) +#define DREX_FREQ_CTRL MIF_REG(0x1000) +#define PAUSE MIF_REG(0x1004) +#define DDRPHY_LOCK_CTRL MIF_REG(0x1008) +#define CLKOUT_CMU_MIF MIF_REG(0xcb00) + +/* +*Registers for CMU_PERI +*/ +#define MUX_SEL_PERI PERI_REG(0x0200) +#define MUX_SEL_PERI1 PERI_REG(0x0204) +#define MUX_ENABLE_PERI PERI_REG(0x0300) +#define MUX_ENABLE_PERI1 PERI_REG(0x0304) +#define MUX_STAT_PERI PERI_REG(0x0400) +#define MUX_STAT_PERI1 PERI_REG(0x0404) +#define MUX_IGNORE_PERI PERI_REG(0x0500) +#define MUX_IGNORE_PERI1 PERI_REG(0x0504) +#define DIV_PERI PERI_REG(0x0600) +#define DIV_STAT_PERI PERI_REG(0x0700) +#define EN_PCLK_PERI0 PERI_REG(0x0800) +#define EN_PCLK_PERI1 PERI_REG(0x0804) +#define EN_PCLK_PERI2 PERI_REG(0x0808) +#define EN_PCLK_PERI3 PERI_REG(0x080c) +#define EN_PCLK_PERI_SECURE_CHIPID PERI_REG(0x0810) +#define EN_PCLK_PERI_SECURE_PROVKEY0 PERI_REG(0x0814) +#define EN_PCLK_PERI_SECURE_PROVKEY1 PERI_REG(0x0818) +#define EN_PCLK_PERI_SECURE_SECKEY PERI_REG(0x081c) +#define EN_PCLK_PERI_SECURE_ANTIRBKCNT PERI_REG(0x0820) +#define EN_PCLK_PERI_SECURE_TOP_RTC PERI_REG(0x0824) +#define EN_PCLK_PERI_SECURE_TZPC PERI_REG(0x0828) +#define EN_SCLK_PERI PERI_REG(0x0a00) +#define EN_SCLK_PERI_SECURE_TOP_RTC PERI_REG(0x0a04) +#define EN_IP_PERI0 PERI_REG(0x0b00) +#define EN_IP_PERI1 PERI_REG(0x0b04) +#define EN_IP_PERI2 PERI_REG(0x0b08) +#define EN_IP_PERI_SECURE_CHIPID PERI_REG(0x0b0c) +#define EN_IP_PERI_SECURE_PROVKEY0 PERI_REG(0x0b10) +#define EN_IP_PERI_SECURE_PROVKEY1 PERI_REG(0x0b14) +#define EN_IP_PERI_SECURE_SECKEY PERI_REG(0x0b18) +#define EN_IP_PERI_SECURE_ANTIRBKCNT PERI_REG(0x0b1c) +#define EN_IP_PERI_SECURE_TOP_RTC PERI_REG(0x0b20) +#define EN_IP_PERI_SECURE_TZPC PERI_REG(0x0b24) + +/* +*Registers for CMU_TOP +*/ +#define DISP_PLL_LOCK TOP_REG(0x0000) +#define AUD_PLL_LOCK TOP_REG(0x0004) +#define DISP_PLL_CON0 TOP_REG(0x0100) +#define DISP_PLL_CON1 TOP_REG(0x0104) +#define DISP_PLL_FDET TOP_REG(0x0108) +#define AUD_PLL_CON0 TOP_REG(0x0110) +#define AUD_PLL_CON1 TOP_REG(0x0114) +#define AUD_PLL_CON2 TOP_REG(0x0118) +#define AUD_PLL_FDET TOP_REG(0x011c) +#define MUX_SEL_TOP_PLL0 TOP_REG(0x0200) +#define MUX_SEL_TOP_MFC TOP_REG(0x0204) +#define MUX_SEL_TOP_G2D TOP_REG(0x0208) +#define MUX_SEL_TOP_GSCL TOP_REG(0x020c) +#define MUX_SEL_TOP_ISP10 TOP_REG(0x0214) +#define MUX_SEL_TOP_ISP11 TOP_REG(0x0218) +#define MUX_SEL_TOP_DISP0 TOP_REG(0x021c) +#define MUX_SEL_TOP_DISP1 TOP_REG(0x0220) +#define MUX_SEL_TOP_BUS TOP_REG(0x0224) +#define MUX_SEL_TOP_PERI0 TOP_REG(0x0228) +#define MUX_SEL_TOP_PERI1 TOP_REG(0x022c) +#define MUX_SEL_TOP_FSYS TOP_REG(0x0230) +#define MUX_ENABLE_TOP_PLL0 TOP_REG(0x0300) +#define MUX_ENABLE_TOP_MFC TOP_REG(0x0304) +#define MUX_ENABLE_TOP_G2D TOP_REG(0x0308) +#define MUX_ENABLE_TOP_GSCL TOP_REG(0x030c) +#define MUX_ENABLE_TOP_ISP10 TOP_REG(0x0314) +#define MUX_ENABLE_TOP_ISP11 TOP_REG(0x0318) +#define MUX_ENABLE_TOP_DISP0 TOP_REG(0x031c) +#define MUX_ENABLE_TOP_DISP1 TOP_REG(0x0320) +#define MUX_ENABLE_TOP_BUS TOP_REG(0x0324) +#define MUX_ENABLE_TOP_PERI0 TOP_REG(0x0328) +#define MUX_ENABLE_TOP_PERI1 TOP_REG(0x032c) +#define MUX_ENABLE_TOP_FSYS TOP_REG(0x0330) +#define MUX_STAT_TOP_PLL0 TOP_REG(0x0400) +#define MUX_STAT_TOP_MFC TOP_REG(0x0404) +#define MUX_STAT_TOP_G2D TOP_REG(0x0408) +#define MUX_STAT_TOP_GSCL TOP_REG(0x040c) +#define MUX_STAT_TOP_ISP10 TOP_REG(0x0414) +#define MUX_STAT_TOP_ISP11 TOP_REG(0x0418) +#define MUX_STAT_TOP_DISP0 TOP_REG(0x041c) +#define MUX_STAT_TOP_DISP1 TOP_REG(0x0420) +#define MUX_STAT_TOP_BUS TOP_REG(0x0424) +#define MUX_STAT_TOP_PERI0 TOP_REG(0x0428) +#define MUX_STAT_TOP_PERI1 TOP_REG(0x042c) +#define MUX_STAT_TOP_FSYS TOP_REG(0x0430) +#define MUX_IGNORE_TOP_PLL0 TOP_REG(0x0500) +#define MUX_IGNORE_TOP_MFC TOP_REG(0x0504) +#define MUX_IGNORE_TOP_G2D TOP_REG(0x0508) +#define MUX_IGNORE_TOP_GSCL TOP_REG(0x050c) +#define MUX_IGNORE_TOP_ISP10 TOP_REG(0x0514) +#define MUX_IGNORE_TOP_ISP11 TOP_REG(0x0518) +#define MUX_IGNORE_TOP_DISP0 TOP_REG(0x051c) +#define MUX_IGNORE_TOP_DISP1 TOP_REG(0x0520) +#define MUX_IGNORE_TOP_BUS TOP_REG(0x0524) +#define MUX_IGNORE_TOP_PERI0 TOP_REG(0x0528) +#define MUX_IGNORE_TOP_PERI1 TOP_REG(0x052c) +#define MUX_IGNORE_TOP_FSYS TOP_REG(0x0530) +#define DIV_TOP_G2D_MFC TOP_REG(0x0600) +#define DIV_TOP_GSCL_ISP0 TOP_REG(0x0604) +#define DIV_TOP_ISP10 TOP_REG(0x0608) +#define DIV_TOP_ISP11 TOP_REG(0x060c) +#define DIV_TOP_DISP TOP_REG(0x0610) +#define DIV_TOP_BUS TOP_REG(0x0614) +#define DIV_TOP_PERI0 TOP_REG(0x0618) +#define DIV_TOP_PERI1 TOP_REG(0x061c) +#define DIV_TOP_PERI2 TOP_REG(0x0620) +#define DIV_TOP_FSYS0 TOP_REG(0x0624) +#define DIV_TOP_FSYS1 TOP_REG(0x0628) +#define DIV_TOP_HPM TOP_REG(0x062c) +#define DIV_TOP_PLL_FDET TOP_REG(0x0630) +#define DIV_STAT_TOP_G2D_MFC TOP_REG(0x0700) +#define DIV_STAT_TOP_GSCL_ISP0 TOP_REG(0x0704) +#define DIV_STAT_TOP_ISP10 TOP_REG(0x0708) +#define DIV_STAT_TOP_ISP11 TOP_REG(0x070c) +#define DIV_STAT_TOP_DISP TOP_REG(0x0710) +#define DIV_STAT_TOP_BUS TOP_REG(0x0714) +#define DIV_STAT_TOP_PERI0 TOP_REG(0x0718) +#define DIV_STAT_TOP_PERI1 TOP_REG(0x071c) +#define DIV_STAT_TOP_PERI2 TOP_REG(0x0720) +#define DIV_STAT_TOP_FSYS0 TOP_REG(0x0724) +#define DIV_STAT_TOP_FSYS1 TOP_REG(0x0728) +#define DIV_STAT_TOP_HPM TOP_REG(0x072c) +#define DIV_STAT_TOP_PLL_FDET TOP_REG(0x0730) +#define EN_ACLK_TOP TOP_REG(0x0800) +#define EN_SCLK_TOP TOP_REG(0x0a00) +#define EN_IP_TOP TOP_REG(0x0b00) +#define CLKOUT_CMU_TOP TOP_REG(0x0c00) +#define CLKOUT_CMU_TOP_DIV_STAT TOP_REG(0x0c04) + +#endif /*__CLK_EXYNOS5260_H */ + diff --git a/include/dt-bindings/clk/exynos5260-clk.h b/include/dt-bindings/clk/exynos5260-clk.h new file mode 100644 index 0000000..73763e4 --- /dev/null +++ b/include/dt-bindings/clk/exynos5260-clk.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Provides Constants for Exynos5260 clocks. +*/ + +#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H +#define _DT_BINDINGS_CLK_EXYNOS5260_H + +#define ID_NONE 0 + +/* + * Clock names: XXXXXX_YYYYY_ZZZZZ + * |------| |----| |----| + * cmu type IP +*/ + +/* list of cocks for CMU_TOP */ +#define FIN_PLL 1 +#define TOP_FOUT_DISP_PLL 2 +#define TOP_FOUT_AUD_PLL 3 +#define TOP_SCLK_MMC0 4 +#define TOP_SCLK_MMC1 5 +#define TOP_SCLK_MMC2 6 +#define TOP_SCLK_HDMIPHY 7 +#define TOP_SCLK_FIMD1 8 +#define TOP_MOUT_FIMD1 9 +#define TOP_MOUT_DISP_PLL 10 +#define TOP_NR_CLK 11 + +/* list of cocks for CMU_EGL */ +#define EGL_FOUT_EGL_PLL 1 +#define EGL_FOUT_EGL_DPLL 2 +#define EGL_NR_CLK 3 + +/* list of cocks for CMU_KFC */ +#define KFC_FOUT_KFC_PLL 1 +#define KFC_NR_CLK 2 + +/* list of cocks for CMU_MIF */ +#define MIF_FOUT_MEM_PLL 1 +#define MIF_FOUT_BUS_PLL 2 +#define MIF_FOUT_MEDIA_PLL 3 +#define MIF_NR_CLK 4 + +/* list of cocks for CMU_G3D */ +#define G3D_FOUT_G3D_PLL 1 +#define G3D_ACLK_G3D 2 +#define G3D_NR_CLK 3 + +/* list of cocks for CMU_AUD */ +#define AUD_SCLK_AUD_UART 1 +#define AUD_SCLK_PCM 2 +#define AUD_ACLK_SRAMC 3 +#define AUD_ACLK_DMAC 4 +#define AUD_PCLK_AUD_UART 5 +#define AUD_PCLK_PCM 6 +#define AUD_PCLK_I2S 7 +#define AUD_PCLK_DMAC 8 +#define AUD_NR_CLK 9 + +/* list of cocks for CMU_MFC */ +#define MFC_ACLK_MFC 1 +#define MFC_PCLK_MFC 2 +#define MFC_PCLK_SMMU_MFC0 3 +#define MFC_PCLK_SMMU_MFC1 4 +#define MFC_NR_CLK 5 + +/* list of cocks for CMU_GSCL */ +#define GSCL_ACLK_GSCL0 1 +#define GSCL_ACLK_GSCL1 2 +#define GSCL_PCLK_GSCL0 3 +#define GSCL_PCLK_GSCL1 4 +#define GSCL_PCLK_SMMU_GSCL0 5 +#define GSCL_PCLK_SMMU_GSCL1 6 +#define GSCL_NR_CLK 7 + +/* list of cocks for CMU_FSYS */ +#define FSYS_HCLK_TSI 1 +#define FSYS_PCLK_GPIO 2 +#define FSYS_HCLK_USBHOST20 3 +#define FSYS_ACLK_USBDRD30 4 +#define FSYS_ACLK_PDMA0 5 +#define FSYS_ACLK_RTIC 6 +#define FSYS_PCLK_SMMU_RTIC 7 +#define FSYS_PHYCLK_USBDRD30 8 +#define FSYS_PHYCLK_USBHOST20 9 +#define FSYS_HCLK_MMC0 10 +#define FSYS_HCLK_MMC1 11 +#define FSYS_HCLK_MMC2 12 +#define FSYS_HCLK_SROMC 13 +#define FSYS_NR_CLK 14 + +/* list of cocks for CMU_PERI */ +#define PERI_PCLK_ADC 1 +#define PERI_PCLK_TMU1 2 +#define PERI_PCLK_TMU0 3 +#define PERI_PCLK_SPI0 4 +#define PERI_PCLK_SPI1 5 +#define PERI_PCLK_SPI2 6 +#define PERI_PCLK_I2S1 7 +#define PERI_PCLK_PWM 8 +#define PERI_PCLK_SPDIF 9 +#define PERI_PCLK_ABB 10 +#define PERI_PCLK_MCT 11 +#define PERI_PCLK_HSIC0 12 +#define PERI_PCLK_HSIC1 13 +#define PERI_PCLK_HSIC2 14 +#define PERI_PCLK_HSIC3 15 +#define PERI_PCLK_UART0 16 +#define PERI_PCLK_UART1 17 +#define PERI_PCLK_UART2 18 +#define PERI_PCLK_PCM1 19 +#define PERI_PCLK_WDT_EGL 20 +#define PERI_PCLK_WDT_KFC 21 +#define PERI_PCLK_CHIPID 22 +#define PERI_CLK_TMU0 23 +#define PERI_CLK_TMU1 24 +#define PERI_CLK_TMU2 25 +#define PERI_CLK_TMU3 26 +#define PERI_CLK_TMU4 27 +#define PERI_PCLK_I2C4 28 +#define PERI_PCLK_I2C5 29 +#define PERI_PCLK_I2C6 30 +#define PERI_PCLK_I2C7 31 +#define PERI_PCLK_I2C8 32 +#define PERI_PCLK_I2C9 33 +#define PERI_PCLK_I2C10 34 +#define PERI_PCLK_I2C11 35 +#define PERI_PCLK_TOP_RTC 36 +#define PERI_SCLK_RTC 37 +#define PERI_SCLK_UART0 38 +#define PERI_SCLK_UART1 39 +#define PERI_SCLK_UART2 40 +#define PERI_SCLK_SPDIF 41 +#define PERI_SCLK_SPI0 42 +#define PERI_SCLK_SPI1 43 +#define PERI_SCLK_SPI2 44 +#define PERI_SCLK_I2S 45 +#define PERI_SCLK_PCM1 46 +#define PERI_NR_CLK 47 + +/* list of cocks for CMU_DISP */ +#define DISP_SCLK_HDMI 1 +#define DISP_SCLK_PIXEL 2 +#define DISP_ACLK_MIXER 3 +#define DISP_ACLK_HDMI 4 +#define DISP_ACLK_FIMD1 5 +#define DISP_PCLK_SMMU_TV 6 +#define DISP_PCLK_SMMU_FIMD1M1 7 +#define DISP_PCLK_SMMU_FIMD1M0 8 +#define DISP_PCLK_DSIM1 9 +#define DISP_PCLK_HDMIPHY 10 +#define DISP_PCLK_HDMI 11 +#define DISP_DP 12 +#define DISP_MOUT_HDMI_PHY_PIXEL 13 +#define DISP_NR_CLK 14 + +/* list of cocks for CMU_G2D */ +#define G2D_ACLK_MDMA 1 +#define G2D_NR_CLK 2 + +#define ISP_NR_CLK 0 + +#endif -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH 4/7] clk/samsung: add support for multuple clock providers 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-06 15:56 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-samsung-soc, devicetree, linux-arm-kernel Cc: mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open, Rahul Sharma Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation SoC platforms are not able to use these helpers for registering mulitple clock providers and are forced to bypass this layer. This layer is modified acordingly to enable the support. Clockfile for exynos4, exynos5250, exynos5420, exynos5440 and S3c64xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> --- drivers/clk/samsung/clk-exynos4.c | 47 ++++++++------- drivers/clk/samsung/clk-exynos5250.c | 26 ++++---- drivers/clk/samsung/clk-exynos5420.c | 24 +++++--- drivers/clk/samsung/clk-exynos5440.c | 18 +++--- drivers/clk/samsung/clk-pll.c | 14 +++-- drivers/clk/samsung/clk-s3c64xx.c | 44 ++++++++------ drivers/clk/samsung/clk.c | 110 +++++++++++++++++++--------------- drivers/clk/samsung/clk.h | 46 ++++++++++---- 8 files changed, 195 insertions(+), 134 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ca2a940..e634ba9 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1093,7 +1093,7 @@ static unsigned long exynos4_get_xom(void) return xom; } -static void __init exynos4_clk_register_finpll(void) +static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) { struct samsung_fixed_rate_clock fclk; struct clk *clk; @@ -1116,7 +1116,7 @@ static void __init exynos4_clk_register_finpll(void) fclk.parent_name = NULL; fclk.flags = CLK_IS_ROOT; fclk.fixed_rate = finpll_f; - samsung_clk_register_fixed_rate(&fclk, 1); + samsung_clk_register_fixed_rate(ctx, &fclk, 1); } @@ -1226,22 +1226,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { static void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc soc) { + struct samsung_clk_provider *ctx; exynos4_soc = soc; reg_base = of_iomap(np, 0); if (!reg_base) panic("%s: failed to map registers\n", __func__); - samsung_clk_init(np, reg_base, nr_clks); + ctx = samsung_clk_init(np, reg_base, nr_clks); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); - samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, + samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks, ARRAY_SIZE(exynos4_fixed_rate_ext_clks), ext_clk_match); - exynos4_clk_register_finpll(); + exynos4_clk_register_finpll(ctx); if (exynos4_soc == EXYNOS4210) { - samsung_clk_register_mux(exynos4210_mux_early, + samsung_clk_register_mux(ctx, exynos4210_mux_early, ARRAY_SIZE(exynos4210_mux_early)); if (_get_rate("fin_pll") == 24000000) { @@ -1255,7 +1258,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4210_plls[vpll].rate_table = exynos4210_vpll_rates; - samsung_clk_register_pll(exynos4210_plls, + samsung_clk_register_pll(ctx, exynos4210_plls, ARRAY_SIZE(exynos4210_plls), reg_base); } else { if (_get_rate("fin_pll") == 24000000) { @@ -1267,42 +1270,42 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4x12_vpll_rates; } - samsung_clk_register_pll(exynos4x12_plls, + samsung_clk_register_pll(ctx, exynos4x12_plls, ARRAY_SIZE(exynos4x12_plls), reg_base); } - samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, + samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks, ARRAY_SIZE(exynos4_fixed_rate_clks)); - samsung_clk_register_mux(exynos4_mux_clks, + samsung_clk_register_mux(ctx, exynos4_mux_clks, ARRAY_SIZE(exynos4_mux_clks)); - samsung_clk_register_div(exynos4_div_clks, + samsung_clk_register_div(ctx, exynos4_div_clks, ARRAY_SIZE(exynos4_div_clks)); - samsung_clk_register_gate(exynos4_gate_clks, + samsung_clk_register_gate(ctx, exynos4_gate_clks, ARRAY_SIZE(exynos4_gate_clks)); if (exynos4_soc == EXYNOS4210) { - samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, + samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks, ARRAY_SIZE(exynos4210_fixed_rate_clks)); - samsung_clk_register_mux(exynos4210_mux_clks, + samsung_clk_register_mux(ctx, exynos4210_mux_clks, ARRAY_SIZE(exynos4210_mux_clks)); - samsung_clk_register_div(exynos4210_div_clks, + samsung_clk_register_div(ctx, exynos4210_div_clks, ARRAY_SIZE(exynos4210_div_clks)); - samsung_clk_register_gate(exynos4210_gate_clks, + samsung_clk_register_gate(ctx, exynos4210_gate_clks, ARRAY_SIZE(exynos4210_gate_clks)); - samsung_clk_register_alias(exynos4210_aliases, + samsung_clk_register_alias(ctx, exynos4210_aliases, ARRAY_SIZE(exynos4210_aliases)); } else { - samsung_clk_register_mux(exynos4x12_mux_clks, + samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); - samsung_clk_register_div(exynos4x12_div_clks, + samsung_clk_register_div(ctx, exynos4x12_div_clks, ARRAY_SIZE(exynos4x12_div_clks)); - samsung_clk_register_gate(exynos4x12_gate_clks, + samsung_clk_register_gate(ctx, exynos4x12_gate_clks, ARRAY_SIZE(exynos4x12_gate_clks)); - samsung_clk_register_alias(exynos4x12_aliases, + samsung_clk_register_alias(ctx, exynos4x12_aliases, ARRAY_SIZE(exynos4x12_aliases)); } - samsung_clk_register_alias(exynos4_aliases, + samsung_clk_register_alias(ctx, exynos4_aliases, ARRAY_SIZE(exynos4_aliases)); exynos4_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 82f14e1..af4f7fd 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -583,6 +583,8 @@ static struct of_device_id ext_clk_match[] __initdata = { /* register exynox5250 clocks */ static void __init exynos5250_clk_init(struct device_node *np) { + struct samsung_clk_provider *ctx; + if (np) { reg_base = of_iomap(np, 0); if (!reg_base) @@ -591,11 +593,14 @@ static void __init exynos5250_clk_init(struct device_node *np) panic("%s: unable to determine soc\n", __func__); } - samsung_clk_init(np, reg_base, nr_clks); - samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, + ctx = samsung_clk_init(np, reg_base, nr_clks); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), ext_clk_match); - samsung_clk_register_mux(exynos5250_pll_pmux_clks, + samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks, ARRAY_SIZE(exynos5250_pll_pmux_clks)); if (_get_rate("fin_pll") == 24 * MHZ) @@ -604,17 +609,18 @@ static void __init exynos5250_clk_init(struct device_node *np) if (_get_rate("mout_vpllsrc") == 24 * MHZ) exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; - samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls), - reg_base); - samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, + samsung_clk_register_pll(ctx, exynos5250_plls, + ARRAY_SIZE(exynos5250_plls), + reg_base); + samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks, ARRAY_SIZE(exynos5250_fixed_rate_clks)); - samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks, + samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks, ARRAY_SIZE(exynos5250_fixed_factor_clks)); - samsung_clk_register_mux(exynos5250_mux_clks, + samsung_clk_register_mux(ctx, exynos5250_mux_clks, ARRAY_SIZE(exynos5250_mux_clks)); - samsung_clk_register_div(exynos5250_div_clks, + samsung_clk_register_div(ctx, exynos5250_div_clks, ARRAY_SIZE(exynos5250_div_clks)); - samsung_clk_register_gate(exynos5250_gate_clks, + samsung_clk_register_gate(ctx, exynos5250_gate_clks, ARRAY_SIZE(exynos5250_gate_clks)); exynos5250_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 9de5bfd..e5493cf 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -808,6 +808,8 @@ static struct of_device_id ext_clk_match[] __initdata = { /* register exynos5420 clocks */ static void __init exynos5420_clk_init(struct device_node *np) { + struct samsung_clk_provider *ctx; + if (np) { reg_base = of_iomap(np, 0); if (!reg_base) @@ -816,21 +818,25 @@ static void __init exynos5420_clk_init(struct device_node *np) panic("%s: unable to determine soc\n", __func__); } - samsung_clk_init(np, reg_base, nr_clks); - samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, + ctx = samsung_clk_init(np, reg_base, nr_clks); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks, ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), ext_clk_match); - samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), - reg_base); - samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, + samsung_clk_register_pll(ctx, exynos5420_plls, + ARRAY_SIZE(exynos5420_plls), + reg_base); + samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks, ARRAY_SIZE(exynos5420_fixed_rate_clks)); - samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, + samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks, ARRAY_SIZE(exynos5420_fixed_factor_clks)); - samsung_clk_register_mux(exynos5420_mux_clks, + samsung_clk_register_mux(ctx, exynos5420_mux_clks, ARRAY_SIZE(exynos5420_mux_clks)); - samsung_clk_register_div(exynos5420_div_clks, + samsung_clk_register_div(ctx, exynos5420_div_clks, ARRAY_SIZE(exynos5420_div_clks)); - samsung_clk_register_gate(exynos5420_gate_clks, + samsung_clk_register_gate(ctx, exynos5420_gate_clks, ARRAY_SIZE(exynos5420_gate_clks)); exynos5420_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index e3e460a..c2f5d3c 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -106,6 +106,7 @@ static struct of_device_id ext_clk_match[] __initdata = { static void __init exynos5440_clk_init(struct device_node *np) { void __iomem *reg_base; + struct samsung_clk_provider *ctx; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -114,22 +115,25 @@ static void __init exynos5440_clk_init(struct device_node *np) return; } - samsung_clk_init(np, reg_base, nr_clks); - samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks, + ctx = samsung_clk_init(np, reg_base, nr_clks); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks, ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); - samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks, + samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks, ARRAY_SIZE(exynos5440_fixed_rate_clks)); - samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks, + samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks, ARRAY_SIZE(exynos5440_fixed_factor_clks)); - samsung_clk_register_mux(exynos5440_mux_clks, + samsung_clk_register_mux(ctx, exynos5440_mux_clks, ARRAY_SIZE(exynos5440_mux_clks)); - samsung_clk_register_div(exynos5440_div_clks, + samsung_clk_register_div(ctx, exynos5440_div_clks, ARRAY_SIZE(exynos5440_div_clks)); - samsung_clk_register_gate(exynos5440_gate_clks, + samsung_clk_register_gate(ctx, exynos5440_gate_clks, ARRAY_SIZE(exynos5440_gate_clks)); pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 529e11d..e8e8953 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -710,8 +710,9 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } -static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, - void __iomem *base) +static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, + struct samsung_pll_clock *pll_clk, + void __iomem *base) { struct samsung_clk_pll *pll; struct clk *clk; @@ -804,7 +805,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, return; } - samsung_clk_add_lookup(clk, pll_clk->id); + samsung_clk_add_lookup(ctx, clk, pll_clk->id); if (!pll_clk->alias) return; @@ -815,11 +816,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, __func__, pll_clk->name, ret); } -void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, - unsigned int nr_pll, void __iomem *base) +void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, + struct samsung_pll_clock *pll_list, + unsigned int nr_pll, void __iomem *base) { int cnt; for (cnt = 0; cnt < nr_pll; cnt++) - _samsung_clk_register_pll(&pll_list[cnt], base); + _samsung_clk_register_pll(ctx, &pll_list[cnt], base); } diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c index a43cbde..b7d06ae 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c @@ -442,12 +442,14 @@ static struct samsung_clock_alias s3c6410_clock_aliases[] = { ALIAS(MEM0_SROM, NULL, "srom"), }; -static void __init s3c64xx_clk_register_fixed_ext(unsigned long fin_pll_f, - unsigned long xusbxti_f) +static void __init s3c64xx_clk_register_fixed_ext( + struct samsung_clk_provider *ctx, + unsigned long fin_pll_f, + unsigned long xusbxti_f) { s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f; s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f; - samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_ext_clks, + samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks, ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks)); } @@ -456,6 +458,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, unsigned long xusbxti_f, bool s3c6400, void __iomem *base) { + struct samsung_clk_provider *ctx; + reg_base = base; is_s3c6400 = s3c6400; @@ -465,48 +469,50 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, panic("%s: failed to map registers\n", __func__); } - samsung_clk_init(np, reg_base, NR_CLKS); + ctx = samsung_clk_init(np, reg_base, NR_CLKS); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); /* Register external clocks. */ if (!np) - s3c64xx_clk_register_fixed_ext(xtal_f, xusbxti_f); + s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f); /* Register PLLs. */ - samsung_clk_register_pll(s3c64xx_pll_clks, + samsung_clk_register_pll(ctx, s3c64xx_pll_clks, ARRAY_SIZE(s3c64xx_pll_clks), reg_base); /* Register common internal clocks. */ - samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_clks, + samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks, ARRAY_SIZE(s3c64xx_fixed_rate_clks)); - samsung_clk_register_mux(s3c64xx_mux_clks, + samsung_clk_register_mux(ctx, s3c64xx_mux_clks, ARRAY_SIZE(s3c64xx_mux_clks)); - samsung_clk_register_div(s3c64xx_div_clks, + samsung_clk_register_div(ctx, s3c64xx_div_clks, ARRAY_SIZE(s3c64xx_div_clks)); - samsung_clk_register_gate(s3c64xx_gate_clks, + samsung_clk_register_gate(ctx, s3c64xx_gate_clks, ARRAY_SIZE(s3c64xx_gate_clks)); /* Register SoC-specific clocks. */ if (is_s3c6400) { - samsung_clk_register_mux(s3c6400_mux_clks, + samsung_clk_register_mux(ctx, s3c6400_mux_clks, ARRAY_SIZE(s3c6400_mux_clks)); - samsung_clk_register_div(s3c6400_div_clks, + samsung_clk_register_div(ctx, s3c6400_div_clks, ARRAY_SIZE(s3c6400_div_clks)); - samsung_clk_register_gate(s3c6400_gate_clks, + samsung_clk_register_gate(ctx, s3c6400_gate_clks, ARRAY_SIZE(s3c6400_gate_clks)); - samsung_clk_register_alias(s3c6400_clock_aliases, + samsung_clk_register_alias(ctx, s3c6400_clock_aliases, ARRAY_SIZE(s3c6400_clock_aliases)); } else { - samsung_clk_register_mux(s3c6410_mux_clks, + samsung_clk_register_mux(ctx, s3c6410_mux_clks, ARRAY_SIZE(s3c6410_mux_clks)); - samsung_clk_register_div(s3c6410_div_clks, + samsung_clk_register_div(ctx, s3c6410_div_clks, ARRAY_SIZE(s3c6410_div_clks)); - samsung_clk_register_gate(s3c6410_gate_clks, + samsung_clk_register_gate(ctx, s3c6410_gate_clks, ARRAY_SIZE(s3c6410_gate_clks)); - samsung_clk_register_alias(s3c6410_clock_aliases, + samsung_clk_register_alias(ctx, s3c6410_clock_aliases, ARRAY_SIZE(s3c6410_clock_aliases)); } - samsung_clk_register_alias(s3c64xx_clock_aliases, + samsung_clk_register_alias(ctx, s3c64xx_clock_aliases, ARRAY_SIZE(s3c64xx_clock_aliases)); s3c64xx_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 91bec3e..20de446 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -15,11 +15,6 @@ #include "clk.h" static DEFINE_SPINLOCK(lock); -static struct clk **clk_table; -static void __iomem *reg_base; -#ifdef CONFIG_OF -static struct clk_onecell_data clk_data; -#endif void samsung_clk_save(void __iomem *base, struct samsung_clk_reg_dump *rd, @@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( } /* setup the essentials required to support clock lookup using ccf */ -void __init samsung_clk_init(struct device_node *np, void __iomem *base, - unsigned long nr_clks) +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, + void __iomem *base, unsigned long nr_clks) { - reg_base = base; + struct samsung_clk_provider *ctx; + struct clk **clk_table; + int ret; + + if (!np) + return NULL; + + ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); + if (!ctx) + panic("could not allocate clock provider context.\n"); clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); if (!clk_table) panic("could not allocate clock lookup table\n"); - if (!np) - return; + ctx->reg_base = base; + ctx->clk_data.clks = clk_table; + ctx->clk_data.clk_num = nr_clks; -#ifdef CONFIG_OF - clk_data.clks = clk_table; - clk_data.clk_num = nr_clks; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -#endif + ret = of_clk_add_provider(np, of_clk_src_onecell_get, + &ctx->clk_data); + if (ret) + panic("could not register clock provide\n"); + + return ctx; } /* add a clock instance to the clock lookup table used for dt based lookup */ -void samsung_clk_add_lookup(struct clk *clk, unsigned int id) +void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, + unsigned int id) { - if (clk_table && id) - clk_table[id] = clk; + if (ctx->clk_data.clks && id) + ctx->clk_data.clks[id] = clk; } /* register a list of aliases */ -void __init samsung_clk_register_alias(struct samsung_clock_alias *list, - unsigned int nr_clk) +void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, + struct samsung_clock_alias *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; - if (!clk_table) { + if (!ctx->clk_data.clks) { pr_err("%s: clock table missing\n", __func__); return; } @@ -100,7 +108,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list, continue; } - clk = clk_table[list->id]; + clk = ctx->clk_data.clks[list->id]; if (!clk) { pr_err("%s: failed to find clock %d\n", __func__, list->id); @@ -115,7 +123,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list, } /* register a list of fixed clocks */ -void __init samsung_clk_register_fixed_rate( +void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *list, unsigned int nr_clk) { struct clk *clk; @@ -130,7 +138,7 @@ void __init samsung_clk_register_fixed_rate( continue; } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); /* * Unconditionally add a clock lookup for the fixed rate clocks. @@ -144,7 +152,7 @@ void __init samsung_clk_register_fixed_rate( } /* register a list of fixed factor clocks */ -void __init samsung_clk_register_fixed_factor( +void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, struct samsung_fixed_factor_clock *list, unsigned int nr_clk) { struct clk *clk; @@ -159,20 +167,22 @@ void __init samsung_clk_register_fixed_factor( continue; } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); } } /* register a list of mux clocks */ -void __init samsung_clk_register_mux(struct samsung_mux_clock *list, - unsigned int nr_clk) +void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, + struct samsung_mux_clock *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { clk = clk_register_mux(NULL, list->name, list->parent_names, - list->num_parents, list->flags, reg_base + list->offset, + list->num_parents, list->flags, + ctx->reg_base + list->offset, list->shift, list->width, list->mux_flags, &lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, @@ -180,7 +190,7 @@ void __init samsung_clk_register_mux(struct samsung_mux_clock *list, continue; } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); /* register a clock lookup only if a clock alias is specified */ if (list->alias) { @@ -194,8 +204,9 @@ void __init samsung_clk_register_mux(struct samsung_mux_clock *list, } /* register a list of div clocks */ -void __init samsung_clk_register_div(struct samsung_div_clock *list, - unsigned int nr_clk) +void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, + struct samsung_div_clock *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; @@ -203,22 +214,22 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list, for (idx = 0; idx < nr_clk; idx++, list++) { if (list->table) clk = clk_register_divider_table(NULL, list->name, - list->parent_name, list->flags, - reg_base + list->offset, list->shift, - list->width, list->div_flags, - list->table, &lock); + list->parent_name, list->flags, + ctx->reg_base + list->offset, + list->shift, list->width, list->div_flags, + list->table, &lock); else clk = clk_register_divider(NULL, list->name, - list->parent_name, list->flags, - reg_base + list->offset, list->shift, - list->width, list->div_flags, &lock); + list->parent_name, list->flags, + ctx->reg_base + list->offset, list->shift, + list->width, list->div_flags, &lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); continue; } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); /* register a clock lookup only if a clock alias is specified */ if (list->alias) { @@ -232,15 +243,16 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list, } /* register a list of gate clocks */ -void __init samsung_clk_register_gate(struct samsung_gate_clock *list, - unsigned int nr_clk) +void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, + struct samsung_gate_clock *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { clk = clk_register_gate(NULL, list->name, list->parent_name, - list->flags, reg_base + list->offset, + list->flags, ctx->reg_base + list->offset, list->bit_idx, list->gate_flags, &lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, @@ -257,7 +269,7 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list, __func__, list->alias); } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); } } @@ -266,21 +278,21 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list, * tree and register it */ #ifdef CONFIG_OF -void __init samsung_clk_of_register_fixed_ext( +void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *fixed_rate_clk, unsigned int nr_fixed_rate_clk, struct of_device_id *clk_matches) { const struct of_device_id *match; - struct device_node *np; + struct device_node *clk_np; u32 freq; - for_each_matching_node_and_match(np, clk_matches, &match) { - if (of_property_read_u32(np, "clock-frequency", &freq)) + for_each_matching_node_and_match(clk_np, clk_matches, &match) { + if (of_property_read_u32(clk_np, "clock-frequency", &freq)) continue; fixed_rate_clk[(u32)match->data].fixed_rate = freq; } - samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk); + samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk); } #endif diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index c7141ba..433bab3 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -21,6 +21,17 @@ #include <linux/of_address.h> #include "clk-pll.h" +/* Context node which holds information about the clock provider. */ +/** + * struct samsung_clk_provider: information about clock plovider + * @reg_base: virtual address for the register base. + * @clk_data: holds clock related data like clk* and number of clocks. + */ +struct samsung_clk_provider { + void __iomem *reg_base; + struct clk_onecell_data clk_data; +}; + /** * struct samsung_clock_alias: information about mux clock * @id: platform specific id of the clock. @@ -312,29 +323,40 @@ struct samsung_pll_clock { __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ _lock, _con, _rtable, _alias) -extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, - unsigned long nr_clks); +extern struct samsung_clk_provider *__init samsung_clk_init( + struct device_node *np, void __iomem *base, + unsigned long nr_clks); extern void __init samsung_clk_of_register_fixed_ext( + struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *fixed_rate_clk, unsigned int nr_fixed_rate_clk, struct of_device_id *clk_matches); -extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id); +extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, + struct clk *clk, unsigned int id); -extern void samsung_clk_register_alias(struct samsung_clock_alias *list, - unsigned int nr_clk); +extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, + struct samsung_clock_alias *list, + unsigned int nr_clk); extern void __init samsung_clk_register_fixed_rate( - struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); + struct samsung_clk_provider *ctx, + struct samsung_fixed_rate_clock *clk_list, + unsigned int nr_clk); extern void __init samsung_clk_register_fixed_factor( - struct samsung_fixed_factor_clock *list, unsigned int nr_clk); -extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list, + struct samsung_clk_provider *ctx, + struct samsung_fixed_factor_clock *list, + unsigned int nr_clk); +extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, + struct samsung_mux_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list, +extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, + struct samsung_div_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_gate( +extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, struct samsung_gate_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, - unsigned int nr_clk, void __iomem *base); +extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, + struct samsung_pll_clock *pll_list, + unsigned int nr_clk, void __iomem *base); extern unsigned long _get_rate(const char *clk_name); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH 4/7] clk/samsung: add support for multuple clock providers @ 2013-12-06 15:56 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-arm-kernel Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation SoC platforms are not able to use these helpers for registering mulitple clock providers and are forced to bypass this layer. This layer is modified acordingly to enable the support. Clockfile for exynos4, exynos5250, exynos5420, exynos5440 and S3c64xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> --- drivers/clk/samsung/clk-exynos4.c | 47 ++++++++------- drivers/clk/samsung/clk-exynos5250.c | 26 ++++---- drivers/clk/samsung/clk-exynos5420.c | 24 +++++--- drivers/clk/samsung/clk-exynos5440.c | 18 +++--- drivers/clk/samsung/clk-pll.c | 14 +++-- drivers/clk/samsung/clk-s3c64xx.c | 44 ++++++++------ drivers/clk/samsung/clk.c | 110 +++++++++++++++++++--------------- drivers/clk/samsung/clk.h | 46 ++++++++++---- 8 files changed, 195 insertions(+), 134 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ca2a940..e634ba9 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1093,7 +1093,7 @@ static unsigned long exynos4_get_xom(void) return xom; } -static void __init exynos4_clk_register_finpll(void) +static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) { struct samsung_fixed_rate_clock fclk; struct clk *clk; @@ -1116,7 +1116,7 @@ static void __init exynos4_clk_register_finpll(void) fclk.parent_name = NULL; fclk.flags = CLK_IS_ROOT; fclk.fixed_rate = finpll_f; - samsung_clk_register_fixed_rate(&fclk, 1); + samsung_clk_register_fixed_rate(ctx, &fclk, 1); } @@ -1226,22 +1226,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { static void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc soc) { + struct samsung_clk_provider *ctx; exynos4_soc = soc; reg_base = of_iomap(np, 0); if (!reg_base) panic("%s: failed to map registers\n", __func__); - samsung_clk_init(np, reg_base, nr_clks); + ctx = samsung_clk_init(np, reg_base, nr_clks); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); - samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, + samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks, ARRAY_SIZE(exynos4_fixed_rate_ext_clks), ext_clk_match); - exynos4_clk_register_finpll(); + exynos4_clk_register_finpll(ctx); if (exynos4_soc == EXYNOS4210) { - samsung_clk_register_mux(exynos4210_mux_early, + samsung_clk_register_mux(ctx, exynos4210_mux_early, ARRAY_SIZE(exynos4210_mux_early)); if (_get_rate("fin_pll") == 24000000) { @@ -1255,7 +1258,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4210_plls[vpll].rate_table = exynos4210_vpll_rates; - samsung_clk_register_pll(exynos4210_plls, + samsung_clk_register_pll(ctx, exynos4210_plls, ARRAY_SIZE(exynos4210_plls), reg_base); } else { if (_get_rate("fin_pll") == 24000000) { @@ -1267,42 +1270,42 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4x12_vpll_rates; } - samsung_clk_register_pll(exynos4x12_plls, + samsung_clk_register_pll(ctx, exynos4x12_plls, ARRAY_SIZE(exynos4x12_plls), reg_base); } - samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, + samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks, ARRAY_SIZE(exynos4_fixed_rate_clks)); - samsung_clk_register_mux(exynos4_mux_clks, + samsung_clk_register_mux(ctx, exynos4_mux_clks, ARRAY_SIZE(exynos4_mux_clks)); - samsung_clk_register_div(exynos4_div_clks, + samsung_clk_register_div(ctx, exynos4_div_clks, ARRAY_SIZE(exynos4_div_clks)); - samsung_clk_register_gate(exynos4_gate_clks, + samsung_clk_register_gate(ctx, exynos4_gate_clks, ARRAY_SIZE(exynos4_gate_clks)); if (exynos4_soc == EXYNOS4210) { - samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, + samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks, ARRAY_SIZE(exynos4210_fixed_rate_clks)); - samsung_clk_register_mux(exynos4210_mux_clks, + samsung_clk_register_mux(ctx, exynos4210_mux_clks, ARRAY_SIZE(exynos4210_mux_clks)); - samsung_clk_register_div(exynos4210_div_clks, + samsung_clk_register_div(ctx, exynos4210_div_clks, ARRAY_SIZE(exynos4210_div_clks)); - samsung_clk_register_gate(exynos4210_gate_clks, + samsung_clk_register_gate(ctx, exynos4210_gate_clks, ARRAY_SIZE(exynos4210_gate_clks)); - samsung_clk_register_alias(exynos4210_aliases, + samsung_clk_register_alias(ctx, exynos4210_aliases, ARRAY_SIZE(exynos4210_aliases)); } else { - samsung_clk_register_mux(exynos4x12_mux_clks, + samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); - samsung_clk_register_div(exynos4x12_div_clks, + samsung_clk_register_div(ctx, exynos4x12_div_clks, ARRAY_SIZE(exynos4x12_div_clks)); - samsung_clk_register_gate(exynos4x12_gate_clks, + samsung_clk_register_gate(ctx, exynos4x12_gate_clks, ARRAY_SIZE(exynos4x12_gate_clks)); - samsung_clk_register_alias(exynos4x12_aliases, + samsung_clk_register_alias(ctx, exynos4x12_aliases, ARRAY_SIZE(exynos4x12_aliases)); } - samsung_clk_register_alias(exynos4_aliases, + samsung_clk_register_alias(ctx, exynos4_aliases, ARRAY_SIZE(exynos4_aliases)); exynos4_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 82f14e1..af4f7fd 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -583,6 +583,8 @@ static struct of_device_id ext_clk_match[] __initdata = { /* register exynox5250 clocks */ static void __init exynos5250_clk_init(struct device_node *np) { + struct samsung_clk_provider *ctx; + if (np) { reg_base = of_iomap(np, 0); if (!reg_base) @@ -591,11 +593,14 @@ static void __init exynos5250_clk_init(struct device_node *np) panic("%s: unable to determine soc\n", __func__); } - samsung_clk_init(np, reg_base, nr_clks); - samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, + ctx = samsung_clk_init(np, reg_base, nr_clks); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), ext_clk_match); - samsung_clk_register_mux(exynos5250_pll_pmux_clks, + samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks, ARRAY_SIZE(exynos5250_pll_pmux_clks)); if (_get_rate("fin_pll") == 24 * MHZ) @@ -604,17 +609,18 @@ static void __init exynos5250_clk_init(struct device_node *np) if (_get_rate("mout_vpllsrc") == 24 * MHZ) exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; - samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls), - reg_base); - samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, + samsung_clk_register_pll(ctx, exynos5250_plls, + ARRAY_SIZE(exynos5250_plls), + reg_base); + samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks, ARRAY_SIZE(exynos5250_fixed_rate_clks)); - samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks, + samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks, ARRAY_SIZE(exynos5250_fixed_factor_clks)); - samsung_clk_register_mux(exynos5250_mux_clks, + samsung_clk_register_mux(ctx, exynos5250_mux_clks, ARRAY_SIZE(exynos5250_mux_clks)); - samsung_clk_register_div(exynos5250_div_clks, + samsung_clk_register_div(ctx, exynos5250_div_clks, ARRAY_SIZE(exynos5250_div_clks)); - samsung_clk_register_gate(exynos5250_gate_clks, + samsung_clk_register_gate(ctx, exynos5250_gate_clks, ARRAY_SIZE(exynos5250_gate_clks)); exynos5250_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 9de5bfd..e5493cf 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -808,6 +808,8 @@ static struct of_device_id ext_clk_match[] __initdata = { /* register exynos5420 clocks */ static void __init exynos5420_clk_init(struct device_node *np) { + struct samsung_clk_provider *ctx; + if (np) { reg_base = of_iomap(np, 0); if (!reg_base) @@ -816,21 +818,25 @@ static void __init exynos5420_clk_init(struct device_node *np) panic("%s: unable to determine soc\n", __func__); } - samsung_clk_init(np, reg_base, nr_clks); - samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, + ctx = samsung_clk_init(np, reg_base, nr_clks); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks, ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), ext_clk_match); - samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), - reg_base); - samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, + samsung_clk_register_pll(ctx, exynos5420_plls, + ARRAY_SIZE(exynos5420_plls), + reg_base); + samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks, ARRAY_SIZE(exynos5420_fixed_rate_clks)); - samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, + samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks, ARRAY_SIZE(exynos5420_fixed_factor_clks)); - samsung_clk_register_mux(exynos5420_mux_clks, + samsung_clk_register_mux(ctx, exynos5420_mux_clks, ARRAY_SIZE(exynos5420_mux_clks)); - samsung_clk_register_div(exynos5420_div_clks, + samsung_clk_register_div(ctx, exynos5420_div_clks, ARRAY_SIZE(exynos5420_div_clks)); - samsung_clk_register_gate(exynos5420_gate_clks, + samsung_clk_register_gate(ctx, exynos5420_gate_clks, ARRAY_SIZE(exynos5420_gate_clks)); exynos5420_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index e3e460a..c2f5d3c 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -106,6 +106,7 @@ static struct of_device_id ext_clk_match[] __initdata = { static void __init exynos5440_clk_init(struct device_node *np) { void __iomem *reg_base; + struct samsung_clk_provider *ctx; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -114,22 +115,25 @@ static void __init exynos5440_clk_init(struct device_node *np) return; } - samsung_clk_init(np, reg_base, nr_clks); - samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks, + ctx = samsung_clk_init(np, reg_base, nr_clks); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks, ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); - samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks, + samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks, ARRAY_SIZE(exynos5440_fixed_rate_clks)); - samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks, + samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks, ARRAY_SIZE(exynos5440_fixed_factor_clks)); - samsung_clk_register_mux(exynos5440_mux_clks, + samsung_clk_register_mux(ctx, exynos5440_mux_clks, ARRAY_SIZE(exynos5440_mux_clks)); - samsung_clk_register_div(exynos5440_div_clks, + samsung_clk_register_div(ctx, exynos5440_div_clks, ARRAY_SIZE(exynos5440_div_clks)); - samsung_clk_register_gate(exynos5440_gate_clks, + samsung_clk_register_gate(ctx, exynos5440_gate_clks, ARRAY_SIZE(exynos5440_gate_clks)); pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 529e11d..e8e8953 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -710,8 +710,9 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } -static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, - void __iomem *base) +static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, + struct samsung_pll_clock *pll_clk, + void __iomem *base) { struct samsung_clk_pll *pll; struct clk *clk; @@ -804,7 +805,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, return; } - samsung_clk_add_lookup(clk, pll_clk->id); + samsung_clk_add_lookup(ctx, clk, pll_clk->id); if (!pll_clk->alias) return; @@ -815,11 +816,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, __func__, pll_clk->name, ret); } -void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, - unsigned int nr_pll, void __iomem *base) +void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, + struct samsung_pll_clock *pll_list, + unsigned int nr_pll, void __iomem *base) { int cnt; for (cnt = 0; cnt < nr_pll; cnt++) - _samsung_clk_register_pll(&pll_list[cnt], base); + _samsung_clk_register_pll(ctx, &pll_list[cnt], base); } diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c index a43cbde..b7d06ae 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c @@ -442,12 +442,14 @@ static struct samsung_clock_alias s3c6410_clock_aliases[] = { ALIAS(MEM0_SROM, NULL, "srom"), }; -static void __init s3c64xx_clk_register_fixed_ext(unsigned long fin_pll_f, - unsigned long xusbxti_f) +static void __init s3c64xx_clk_register_fixed_ext( + struct samsung_clk_provider *ctx, + unsigned long fin_pll_f, + unsigned long xusbxti_f) { s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f; s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f; - samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_ext_clks, + samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks, ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks)); } @@ -456,6 +458,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, unsigned long xusbxti_f, bool s3c6400, void __iomem *base) { + struct samsung_clk_provider *ctx; + reg_base = base; is_s3c6400 = s3c6400; @@ -465,48 +469,50 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, panic("%s: failed to map registers\n", __func__); } - samsung_clk_init(np, reg_base, NR_CLKS); + ctx = samsung_clk_init(np, reg_base, NR_CLKS); + if (!ctx) + panic("%s: unable to allocate context.\n", __func__); /* Register external clocks. */ if (!np) - s3c64xx_clk_register_fixed_ext(xtal_f, xusbxti_f); + s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f); /* Register PLLs. */ - samsung_clk_register_pll(s3c64xx_pll_clks, + samsung_clk_register_pll(ctx, s3c64xx_pll_clks, ARRAY_SIZE(s3c64xx_pll_clks), reg_base); /* Register common internal clocks. */ - samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_clks, + samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks, ARRAY_SIZE(s3c64xx_fixed_rate_clks)); - samsung_clk_register_mux(s3c64xx_mux_clks, + samsung_clk_register_mux(ctx, s3c64xx_mux_clks, ARRAY_SIZE(s3c64xx_mux_clks)); - samsung_clk_register_div(s3c64xx_div_clks, + samsung_clk_register_div(ctx, s3c64xx_div_clks, ARRAY_SIZE(s3c64xx_div_clks)); - samsung_clk_register_gate(s3c64xx_gate_clks, + samsung_clk_register_gate(ctx, s3c64xx_gate_clks, ARRAY_SIZE(s3c64xx_gate_clks)); /* Register SoC-specific clocks. */ if (is_s3c6400) { - samsung_clk_register_mux(s3c6400_mux_clks, + samsung_clk_register_mux(ctx, s3c6400_mux_clks, ARRAY_SIZE(s3c6400_mux_clks)); - samsung_clk_register_div(s3c6400_div_clks, + samsung_clk_register_div(ctx, s3c6400_div_clks, ARRAY_SIZE(s3c6400_div_clks)); - samsung_clk_register_gate(s3c6400_gate_clks, + samsung_clk_register_gate(ctx, s3c6400_gate_clks, ARRAY_SIZE(s3c6400_gate_clks)); - samsung_clk_register_alias(s3c6400_clock_aliases, + samsung_clk_register_alias(ctx, s3c6400_clock_aliases, ARRAY_SIZE(s3c6400_clock_aliases)); } else { - samsung_clk_register_mux(s3c6410_mux_clks, + samsung_clk_register_mux(ctx, s3c6410_mux_clks, ARRAY_SIZE(s3c6410_mux_clks)); - samsung_clk_register_div(s3c6410_div_clks, + samsung_clk_register_div(ctx, s3c6410_div_clks, ARRAY_SIZE(s3c6410_div_clks)); - samsung_clk_register_gate(s3c6410_gate_clks, + samsung_clk_register_gate(ctx, s3c6410_gate_clks, ARRAY_SIZE(s3c6410_gate_clks)); - samsung_clk_register_alias(s3c6410_clock_aliases, + samsung_clk_register_alias(ctx, s3c6410_clock_aliases, ARRAY_SIZE(s3c6410_clock_aliases)); } - samsung_clk_register_alias(s3c64xx_clock_aliases, + samsung_clk_register_alias(ctx, s3c64xx_clock_aliases, ARRAY_SIZE(s3c64xx_clock_aliases)); s3c64xx_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 91bec3e..20de446 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -15,11 +15,6 @@ #include "clk.h" static DEFINE_SPINLOCK(lock); -static struct clk **clk_table; -static void __iomem *reg_base; -#ifdef CONFIG_OF -static struct clk_onecell_data clk_data; -#endif void samsung_clk_save(void __iomem *base, struct samsung_clk_reg_dump *rd, @@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( } /* setup the essentials required to support clock lookup using ccf */ -void __init samsung_clk_init(struct device_node *np, void __iomem *base, - unsigned long nr_clks) +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, + void __iomem *base, unsigned long nr_clks) { - reg_base = base; + struct samsung_clk_provider *ctx; + struct clk **clk_table; + int ret; + + if (!np) + return NULL; + + ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); + if (!ctx) + panic("could not allocate clock provider context.\n"); clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); if (!clk_table) panic("could not allocate clock lookup table\n"); - if (!np) - return; + ctx->reg_base = base; + ctx->clk_data.clks = clk_table; + ctx->clk_data.clk_num = nr_clks; -#ifdef CONFIG_OF - clk_data.clks = clk_table; - clk_data.clk_num = nr_clks; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -#endif + ret = of_clk_add_provider(np, of_clk_src_onecell_get, + &ctx->clk_data); + if (ret) + panic("could not register clock provide\n"); + + return ctx; } /* add a clock instance to the clock lookup table used for dt based lookup */ -void samsung_clk_add_lookup(struct clk *clk, unsigned int id) +void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, + unsigned int id) { - if (clk_table && id) - clk_table[id] = clk; + if (ctx->clk_data.clks && id) + ctx->clk_data.clks[id] = clk; } /* register a list of aliases */ -void __init samsung_clk_register_alias(struct samsung_clock_alias *list, - unsigned int nr_clk) +void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, + struct samsung_clock_alias *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; - if (!clk_table) { + if (!ctx->clk_data.clks) { pr_err("%s: clock table missing\n", __func__); return; } @@ -100,7 +108,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list, continue; } - clk = clk_table[list->id]; + clk = ctx->clk_data.clks[list->id]; if (!clk) { pr_err("%s: failed to find clock %d\n", __func__, list->id); @@ -115,7 +123,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list, } /* register a list of fixed clocks */ -void __init samsung_clk_register_fixed_rate( +void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *list, unsigned int nr_clk) { struct clk *clk; @@ -130,7 +138,7 @@ void __init samsung_clk_register_fixed_rate( continue; } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); /* * Unconditionally add a clock lookup for the fixed rate clocks. @@ -144,7 +152,7 @@ void __init samsung_clk_register_fixed_rate( } /* register a list of fixed factor clocks */ -void __init samsung_clk_register_fixed_factor( +void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, struct samsung_fixed_factor_clock *list, unsigned int nr_clk) { struct clk *clk; @@ -159,20 +167,22 @@ void __init samsung_clk_register_fixed_factor( continue; } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); } } /* register a list of mux clocks */ -void __init samsung_clk_register_mux(struct samsung_mux_clock *list, - unsigned int nr_clk) +void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, + struct samsung_mux_clock *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { clk = clk_register_mux(NULL, list->name, list->parent_names, - list->num_parents, list->flags, reg_base + list->offset, + list->num_parents, list->flags, + ctx->reg_base + list->offset, list->shift, list->width, list->mux_flags, &lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, @@ -180,7 +190,7 @@ void __init samsung_clk_register_mux(struct samsung_mux_clock *list, continue; } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); /* register a clock lookup only if a clock alias is specified */ if (list->alias) { @@ -194,8 +204,9 @@ void __init samsung_clk_register_mux(struct samsung_mux_clock *list, } /* register a list of div clocks */ -void __init samsung_clk_register_div(struct samsung_div_clock *list, - unsigned int nr_clk) +void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, + struct samsung_div_clock *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; @@ -203,22 +214,22 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list, for (idx = 0; idx < nr_clk; idx++, list++) { if (list->table) clk = clk_register_divider_table(NULL, list->name, - list->parent_name, list->flags, - reg_base + list->offset, list->shift, - list->width, list->div_flags, - list->table, &lock); + list->parent_name, list->flags, + ctx->reg_base + list->offset, + list->shift, list->width, list->div_flags, + list->table, &lock); else clk = clk_register_divider(NULL, list->name, - list->parent_name, list->flags, - reg_base + list->offset, list->shift, - list->width, list->div_flags, &lock); + list->parent_name, list->flags, + ctx->reg_base + list->offset, list->shift, + list->width, list->div_flags, &lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); continue; } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); /* register a clock lookup only if a clock alias is specified */ if (list->alias) { @@ -232,15 +243,16 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list, } /* register a list of gate clocks */ -void __init samsung_clk_register_gate(struct samsung_gate_clock *list, - unsigned int nr_clk) +void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, + struct samsung_gate_clock *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { clk = clk_register_gate(NULL, list->name, list->parent_name, - list->flags, reg_base + list->offset, + list->flags, ctx->reg_base + list->offset, list->bit_idx, list->gate_flags, &lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, @@ -257,7 +269,7 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list, __func__, list->alias); } - samsung_clk_add_lookup(clk, list->id); + samsung_clk_add_lookup(ctx, clk, list->id); } } @@ -266,21 +278,21 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list, * tree and register it */ #ifdef CONFIG_OF -void __init samsung_clk_of_register_fixed_ext( +void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *fixed_rate_clk, unsigned int nr_fixed_rate_clk, struct of_device_id *clk_matches) { const struct of_device_id *match; - struct device_node *np; + struct device_node *clk_np; u32 freq; - for_each_matching_node_and_match(np, clk_matches, &match) { - if (of_property_read_u32(np, "clock-frequency", &freq)) + for_each_matching_node_and_match(clk_np, clk_matches, &match) { + if (of_property_read_u32(clk_np, "clock-frequency", &freq)) continue; fixed_rate_clk[(u32)match->data].fixed_rate = freq; } - samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk); + samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk); } #endif diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index c7141ba..433bab3 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -21,6 +21,17 @@ #include <linux/of_address.h> #include "clk-pll.h" +/* Context node which holds information about the clock provider. */ +/** + * struct samsung_clk_provider: information about clock plovider + * @reg_base: virtual address for the register base. + * @clk_data: holds clock related data like clk* and number of clocks. + */ +struct samsung_clk_provider { + void __iomem *reg_base; + struct clk_onecell_data clk_data; +}; + /** * struct samsung_clock_alias: information about mux clock * @id: platform specific id of the clock. @@ -312,29 +323,40 @@ struct samsung_pll_clock { __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ _lock, _con, _rtable, _alias) -extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, - unsigned long nr_clks); +extern struct samsung_clk_provider *__init samsung_clk_init( + struct device_node *np, void __iomem *base, + unsigned long nr_clks); extern void __init samsung_clk_of_register_fixed_ext( + struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *fixed_rate_clk, unsigned int nr_fixed_rate_clk, struct of_device_id *clk_matches); -extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id); +extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, + struct clk *clk, unsigned int id); -extern void samsung_clk_register_alias(struct samsung_clock_alias *list, - unsigned int nr_clk); +extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, + struct samsung_clock_alias *list, + unsigned int nr_clk); extern void __init samsung_clk_register_fixed_rate( - struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); + struct samsung_clk_provider *ctx, + struct samsung_fixed_rate_clock *clk_list, + unsigned int nr_clk); extern void __init samsung_clk_register_fixed_factor( - struct samsung_fixed_factor_clock *list, unsigned int nr_clk); -extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list, + struct samsung_clk_provider *ctx, + struct samsung_fixed_factor_clock *list, + unsigned int nr_clk); +extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, + struct samsung_mux_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list, +extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, + struct samsung_div_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_gate( +extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, struct samsung_gate_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, - unsigned int nr_clk, void __iomem *base); +extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, + struct samsung_pll_clock *pll_list, + unsigned int nr_clk, void __iomem *base); extern unsigned long _get_rate(const char *clk_name); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* Re: [PATCH 4/7] clk/samsung: add support for multuple clock providers 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-11 11:15 ` Tomasz Figa -1 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-11 11:15 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open Hi Rahul, Please see my comments inline. On Friday 06 of December 2013 21:26:28 Rahul Sharma wrote: > Samsung CCF helper functions do not provide support to > register multiple Clock Providers for a given SoC. Due to > this limitation SoC platforms are not able to use these > helpers for registering mulitple clock providers and are > forced to bypass this layer. > > This layer is modified acordingly to enable the support. > > Clockfile for exynos4, exynos5250, exynos5420, exynos5440 > and S3c64xx are also modified as per changed helper functions. [snip] > diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c > index 91bec3e..20de446 100644 > --- a/drivers/clk/samsung/clk.c > +++ b/drivers/clk/samsung/clk.c > @@ -15,11 +15,6 @@ > #include "clk.h" > > static DEFINE_SPINLOCK(lock); IMHO you can also move the spinlock into samsung_clk_provider struct, to have more fine grained locking, as you shouldn't need to lock between particular providers, just multiple requests for one. > -static struct clk **clk_table; > -static void __iomem *reg_base; > -#ifdef CONFIG_OF > -static struct clk_onecell_data clk_data; > -#endif > > void samsung_clk_save(void __iomem *base, > struct samsung_clk_reg_dump *rd, > @@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( > } > > /* setup the essentials required to support clock lookup using ccf */ > -void __init samsung_clk_init(struct device_node *np, void __iomem *base, > - unsigned long nr_clks) > +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, > + void __iomem *base, unsigned long nr_clks) > { > - reg_base = base; > + struct samsung_clk_provider *ctx; > + struct clk **clk_table; > + int ret; > + > + if (!np) > + return NULL; This check is incorrect. It's completely correct to call this function with NULL np, when booted without DT and this was handled correctly before this patch. Please keep the same behavior. > + > + ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); > + if (!ctx) > + panic("could not allocate clock provider context.\n"); > > clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); > if (!clk_table) > panic("could not allocate clock lookup table\n"); > > - if (!np) > - return; > + ctx->reg_base = base; > + ctx->clk_data.clks = clk_table; > + ctx->clk_data.clk_num = nr_clks; > > -#ifdef CONFIG_OF > - clk_data.clks = clk_table; > - clk_data.clk_num = nr_clks; > - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); > -#endif > + ret = of_clk_add_provider(np, of_clk_src_onecell_get, > + &ctx->clk_data); > + if (ret) > + panic("could not register clock provide\n"); > + > + return ctx; > } [snip] > diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h > index c7141ba..433bab3 100644 > --- a/drivers/clk/samsung/clk.h > +++ b/drivers/clk/samsung/clk.h > @@ -21,6 +21,17 @@ > #include <linux/of_address.h> > #include "clk-pll.h" > > +/* Context node which holds information about the clock provider. */ > +/** > + * struct samsung_clk_provider: information about clock plovider typo: s/plovider/provider/ > + * @reg_base: virtual address for the register base. > + * @clk_data: holds clock related data like clk* and number of clocks. > + */ Why two comments? The kerneldoc one should be enough. > +struct samsung_clk_provider { > + void __iomem *reg_base; > + struct clk_onecell_data clk_data; > +}; > + > /** > * struct samsung_clock_alias: information about mux clock > * @id: platform specific id of the clock. > @@ -312,29 +323,40 @@ struct samsung_pll_clock { > __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ > _lock, _con, _rtable, _alias) > > -extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, > - unsigned long nr_clks); > +extern struct samsung_clk_provider *__init samsung_clk_init( > + struct device_node *np, void __iomem *base, > + unsigned long nr_clks); > extern void __init samsung_clk_of_register_fixed_ext( > + struct samsung_clk_provider *ctx, > struct samsung_fixed_rate_clock *fixed_rate_clk, > unsigned int nr_fixed_rate_clk, > struct of_device_id *clk_matches); > > -extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id); > +extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, > + struct clk *clk, unsigned int id); > > -extern void samsung_clk_register_alias(struct samsung_clock_alias *list, > - unsigned int nr_clk); > +extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, > + struct samsung_clock_alias *list, > + unsigned int nr_clk); > extern void __init samsung_clk_register_fixed_rate( > - struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); > + struct samsung_clk_provider *ctx, > + struct samsung_fixed_rate_clock *clk_list, > + unsigned int nr_clk); > extern void __init samsung_clk_register_fixed_factor( > - struct samsung_fixed_factor_clock *list, unsigned int nr_clk); > -extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list, > + struct samsung_clk_provider *ctx, > + struct samsung_fixed_factor_clock *list, > + unsigned int nr_clk); > +extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, > + struct samsung_mux_clock *clk_list, > unsigned int nr_clk); > -extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list, > +extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, > + struct samsung_div_clock *clk_list, > unsigned int nr_clk); > -extern void __init samsung_clk_register_gate( > +extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, > struct samsung_gate_clock *clk_list, unsigned int nr_clk); > -extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, > - unsigned int nr_clk, void __iomem *base); > +extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, > + struct samsung_pll_clock *pll_list, > + unsigned int nr_clk, void __iomem *base); > > extern unsigned long _get_rate(const char *clk_name); > nit: Please keep the indentation consistent in all the function prototypes above. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 4/7] clk/samsung: add support for multuple clock providers @ 2013-12-11 11:15 ` Tomasz Figa 0 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-11 11:15 UTC (permalink / raw) To: linux-arm-kernel Hi Rahul, Please see my comments inline. On Friday 06 of December 2013 21:26:28 Rahul Sharma wrote: > Samsung CCF helper functions do not provide support to > register multiple Clock Providers for a given SoC. Due to > this limitation SoC platforms are not able to use these > helpers for registering mulitple clock providers and are > forced to bypass this layer. > > This layer is modified acordingly to enable the support. > > Clockfile for exynos4, exynos5250, exynos5420, exynos5440 > and S3c64xx are also modified as per changed helper functions. [snip] > diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c > index 91bec3e..20de446 100644 > --- a/drivers/clk/samsung/clk.c > +++ b/drivers/clk/samsung/clk.c > @@ -15,11 +15,6 @@ > #include "clk.h" > > static DEFINE_SPINLOCK(lock); IMHO you can also move the spinlock into samsung_clk_provider struct, to have more fine grained locking, as you shouldn't need to lock between particular providers, just multiple requests for one. > -static struct clk **clk_table; > -static void __iomem *reg_base; > -#ifdef CONFIG_OF > -static struct clk_onecell_data clk_data; > -#endif > > void samsung_clk_save(void __iomem *base, > struct samsung_clk_reg_dump *rd, > @@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( > } > > /* setup the essentials required to support clock lookup using ccf */ > -void __init samsung_clk_init(struct device_node *np, void __iomem *base, > - unsigned long nr_clks) > +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, > + void __iomem *base, unsigned long nr_clks) > { > - reg_base = base; > + struct samsung_clk_provider *ctx; > + struct clk **clk_table; > + int ret; > + > + if (!np) > + return NULL; This check is incorrect. It's completely correct to call this function with NULL np, when booted without DT and this was handled correctly before this patch. Please keep the same behavior. > + > + ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); > + if (!ctx) > + panic("could not allocate clock provider context.\n"); > > clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); > if (!clk_table) > panic("could not allocate clock lookup table\n"); > > - if (!np) > - return; > + ctx->reg_base = base; > + ctx->clk_data.clks = clk_table; > + ctx->clk_data.clk_num = nr_clks; > > -#ifdef CONFIG_OF > - clk_data.clks = clk_table; > - clk_data.clk_num = nr_clks; > - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); > -#endif > + ret = of_clk_add_provider(np, of_clk_src_onecell_get, > + &ctx->clk_data); > + if (ret) > + panic("could not register clock provide\n"); > + > + return ctx; > } [snip] > diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h > index c7141ba..433bab3 100644 > --- a/drivers/clk/samsung/clk.h > +++ b/drivers/clk/samsung/clk.h > @@ -21,6 +21,17 @@ > #include <linux/of_address.h> > #include "clk-pll.h" > > +/* Context node which holds information about the clock provider. */ > +/** > + * struct samsung_clk_provider: information about clock plovider typo: s/plovider/provider/ > + * @reg_base: virtual address for the register base. > + * @clk_data: holds clock related data like clk* and number of clocks. > + */ Why two comments? The kerneldoc one should be enough. > +struct samsung_clk_provider { > + void __iomem *reg_base; > + struct clk_onecell_data clk_data; > +}; > + > /** > * struct samsung_clock_alias: information about mux clock > * @id: platform specific id of the clock. > @@ -312,29 +323,40 @@ struct samsung_pll_clock { > __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ > _lock, _con, _rtable, _alias) > > -extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, > - unsigned long nr_clks); > +extern struct samsung_clk_provider *__init samsung_clk_init( > + struct device_node *np, void __iomem *base, > + unsigned long nr_clks); > extern void __init samsung_clk_of_register_fixed_ext( > + struct samsung_clk_provider *ctx, > struct samsung_fixed_rate_clock *fixed_rate_clk, > unsigned int nr_fixed_rate_clk, > struct of_device_id *clk_matches); > > -extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id); > +extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, > + struct clk *clk, unsigned int id); > > -extern void samsung_clk_register_alias(struct samsung_clock_alias *list, > - unsigned int nr_clk); > +extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, > + struct samsung_clock_alias *list, > + unsigned int nr_clk); > extern void __init samsung_clk_register_fixed_rate( > - struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); > + struct samsung_clk_provider *ctx, > + struct samsung_fixed_rate_clock *clk_list, > + unsigned int nr_clk); > extern void __init samsung_clk_register_fixed_factor( > - struct samsung_fixed_factor_clock *list, unsigned int nr_clk); > -extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list, > + struct samsung_clk_provider *ctx, > + struct samsung_fixed_factor_clock *list, > + unsigned int nr_clk); > +extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, > + struct samsung_mux_clock *clk_list, > unsigned int nr_clk); > -extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list, > +extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, > + struct samsung_div_clock *clk_list, > unsigned int nr_clk); > -extern void __init samsung_clk_register_gate( > +extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, > struct samsung_gate_clock *clk_list, unsigned int nr_clk); > -extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, > - unsigned int nr_clk, void __iomem *base); > +extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, > + struct samsung_pll_clock *pll_list, > + unsigned int nr_clk, void __iomem *base); > > extern unsigned long _get_rate(const char *clk_name); > nit: Please keep the indentation consistent in all the function prototypes above. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 4/7] clk/samsung: add support for multuple clock providers 2013-12-11 11:15 ` Tomasz Figa @ 2014-01-06 11:35 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-06 11:35 UTC (permalink / raw) To: Tomasz Figa Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Hi Tomasz, On 11 December 2013 16:45, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Rahul, > > Please see my comments inline. > > On Friday 06 of December 2013 21:26:28 Rahul Sharma wrote: >> Samsung CCF helper functions do not provide support to >> register multiple Clock Providers for a given SoC. Due to >> this limitation SoC platforms are not able to use these >> helpers for registering mulitple clock providers and are >> forced to bypass this layer. >> >> This layer is modified acordingly to enable the support. >> >> Clockfile for exynos4, exynos5250, exynos5420, exynos5440 >> and S3c64xx are also modified as per changed helper functions. > [snip] >> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c >> index 91bec3e..20de446 100644 >> --- a/drivers/clk/samsung/clk.c >> +++ b/drivers/clk/samsung/clk.c >> @@ -15,11 +15,6 @@ >> #include "clk.h" >> >> static DEFINE_SPINLOCK(lock); > > IMHO you can also move the spinlock into samsung_clk_provider struct, to > have more fine grained locking, as you shouldn't need to lock between > particular providers, just multiple requests for one. > Done. >> -static struct clk **clk_table; >> -static void __iomem *reg_base; >> -#ifdef CONFIG_OF >> -static struct clk_onecell_data clk_data; >> -#endif >> >> void samsung_clk_save(void __iomem *base, >> struct samsung_clk_reg_dump *rd, >> @@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( >> } >> >> /* setup the essentials required to support clock lookup using ccf */ >> -void __init samsung_clk_init(struct device_node *np, void __iomem *base, >> - unsigned long nr_clks) >> +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, >> + void __iomem *base, unsigned long nr_clks) >> { >> - reg_base = base; >> + struct samsung_clk_provider *ctx; >> + struct clk **clk_table; >> + int ret; >> + >> + if (!np) >> + return NULL; > > This check is incorrect. It's completely correct to call this function > with NULL np, when booted without DT and this was handled correctly > before this patch. Please keep the same behavior. > Done. >> + >> + ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); >> + if (!ctx) >> + panic("could not allocate clock provider context.\n"); >> >> clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); >> if (!clk_table) >> panic("could not allocate clock lookup table\n"); >> >> - if (!np) >> - return; >> + ctx->reg_base = base; >> + ctx->clk_data.clks = clk_table; >> + ctx->clk_data.clk_num = nr_clks; >> >> -#ifdef CONFIG_OF >> - clk_data.clks = clk_table; >> - clk_data.clk_num = nr_clks; >> - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); >> -#endif >> + ret = of_clk_add_provider(np, of_clk_src_onecell_get, >> + &ctx->clk_data); >> + if (ret) >> + panic("could not register clock provide\n"); >> + >> + return ctx; >> } > [snip] >> diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h >> index c7141ba..433bab3 100644 >> --- a/drivers/clk/samsung/clk.h >> +++ b/drivers/clk/samsung/clk.h >> @@ -21,6 +21,17 @@ >> #include <linux/of_address.h> >> #include "clk-pll.h" >> >> +/* Context node which holds information about the clock provider. */ >> +/** >> + * struct samsung_clk_provider: information about clock plovider > > typo: s/plovider/provider/ Ok. > >> + * @reg_base: virtual address for the register base. >> + * @clk_data: holds clock related data like clk* and number of clocks. >> + */ > > Why two comments? The kerneldoc one should be enough. > >> +struct samsung_clk_provider { >> + void __iomem *reg_base; >> + struct clk_onecell_data clk_data; >> +}; >> + >> /** >> * struct samsung_clock_alias: information about mux clock >> * @id: platform specific id of the clock. >> @@ -312,29 +323,40 @@ struct samsung_pll_clock { >> __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ >> _lock, _con, _rtable, _alias) >> >> -extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, >> - unsigned long nr_clks); >> +extern struct samsung_clk_provider *__init samsung_clk_init( >> + struct device_node *np, void __iomem *base, >> + unsigned long nr_clks); >> extern void __init samsung_clk_of_register_fixed_ext( >> + struct samsung_clk_provider *ctx, >> struct samsung_fixed_rate_clock *fixed_rate_clk, >> unsigned int nr_fixed_rate_clk, >> struct of_device_id *clk_matches); >> >> -extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id); >> +extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, >> + struct clk *clk, unsigned int id); >> >> -extern void samsung_clk_register_alias(struct samsung_clock_alias *list, >> - unsigned int nr_clk); >> +extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, >> + struct samsung_clock_alias *list, >> + unsigned int nr_clk); >> extern void __init samsung_clk_register_fixed_rate( >> - struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); >> + struct samsung_clk_provider *ctx, >> + struct samsung_fixed_rate_clock *clk_list, >> + unsigned int nr_clk); >> extern void __init samsung_clk_register_fixed_factor( >> - struct samsung_fixed_factor_clock *list, unsigned int nr_clk); >> -extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list, >> + struct samsung_clk_provider *ctx, >> + struct samsung_fixed_factor_clock *list, >> + unsigned int nr_clk); >> +extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, >> + struct samsung_mux_clock *clk_list, >> unsigned int nr_clk); >> -extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list, >> +extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, >> + struct samsung_div_clock *clk_list, >> unsigned int nr_clk); >> -extern void __init samsung_clk_register_gate( >> +extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, >> struct samsung_gate_clock *clk_list, unsigned int nr_clk); >> -extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, >> - unsigned int nr_clk, void __iomem *base); >> +extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, >> + struct samsung_pll_clock *pll_list, >> + unsigned int nr_clk, void __iomem *base); >> >> extern unsigned long _get_rate(const char *clk_name); >> > > nit: Please keep the indentation consistent in all the function prototypes > above. ok. regards, Rahul Sharma. > > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 4/7] clk/samsung: add support for multuple clock providers @ 2014-01-06 11:35 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-06 11:35 UTC (permalink / raw) To: linux-arm-kernel Hi Tomasz, On 11 December 2013 16:45, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Rahul, > > Please see my comments inline. > > On Friday 06 of December 2013 21:26:28 Rahul Sharma wrote: >> Samsung CCF helper functions do not provide support to >> register multiple Clock Providers for a given SoC. Due to >> this limitation SoC platforms are not able to use these >> helpers for registering mulitple clock providers and are >> forced to bypass this layer. >> >> This layer is modified acordingly to enable the support. >> >> Clockfile for exynos4, exynos5250, exynos5420, exynos5440 >> and S3c64xx are also modified as per changed helper functions. > [snip] >> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c >> index 91bec3e..20de446 100644 >> --- a/drivers/clk/samsung/clk.c >> +++ b/drivers/clk/samsung/clk.c >> @@ -15,11 +15,6 @@ >> #include "clk.h" >> >> static DEFINE_SPINLOCK(lock); > > IMHO you can also move the spinlock into samsung_clk_provider struct, to > have more fine grained locking, as you shouldn't need to lock between > particular providers, just multiple requests for one. > Done. >> -static struct clk **clk_table; >> -static void __iomem *reg_base; >> -#ifdef CONFIG_OF >> -static struct clk_onecell_data clk_data; >> -#endif >> >> void samsung_clk_save(void __iomem *base, >> struct samsung_clk_reg_dump *rd, >> @@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( >> } >> >> /* setup the essentials required to support clock lookup using ccf */ >> -void __init samsung_clk_init(struct device_node *np, void __iomem *base, >> - unsigned long nr_clks) >> +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, >> + void __iomem *base, unsigned long nr_clks) >> { >> - reg_base = base; >> + struct samsung_clk_provider *ctx; >> + struct clk **clk_table; >> + int ret; >> + >> + if (!np) >> + return NULL; > > This check is incorrect. It's completely correct to call this function > with NULL np, when booted without DT and this was handled correctly > before this patch. Please keep the same behavior. > Done. >> + >> + ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); >> + if (!ctx) >> + panic("could not allocate clock provider context.\n"); >> >> clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); >> if (!clk_table) >> panic("could not allocate clock lookup table\n"); >> >> - if (!np) >> - return; >> + ctx->reg_base = base; >> + ctx->clk_data.clks = clk_table; >> + ctx->clk_data.clk_num = nr_clks; >> >> -#ifdef CONFIG_OF >> - clk_data.clks = clk_table; >> - clk_data.clk_num = nr_clks; >> - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); >> -#endif >> + ret = of_clk_add_provider(np, of_clk_src_onecell_get, >> + &ctx->clk_data); >> + if (ret) >> + panic("could not register clock provide\n"); >> + >> + return ctx; >> } > [snip] >> diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h >> index c7141ba..433bab3 100644 >> --- a/drivers/clk/samsung/clk.h >> +++ b/drivers/clk/samsung/clk.h >> @@ -21,6 +21,17 @@ >> #include <linux/of_address.h> >> #include "clk-pll.h" >> >> +/* Context node which holds information about the clock provider. */ >> +/** >> + * struct samsung_clk_provider: information about clock plovider > > typo: s/plovider/provider/ Ok. > >> + * @reg_base: virtual address for the register base. >> + * @clk_data: holds clock related data like clk* and number of clocks. >> + */ > > Why two comments? The kerneldoc one should be enough. > >> +struct samsung_clk_provider { >> + void __iomem *reg_base; >> + struct clk_onecell_data clk_data; >> +}; >> + >> /** >> * struct samsung_clock_alias: information about mux clock >> * @id: platform specific id of the clock. >> @@ -312,29 +323,40 @@ struct samsung_pll_clock { >> __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ >> _lock, _con, _rtable, _alias) >> >> -extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, >> - unsigned long nr_clks); >> +extern struct samsung_clk_provider *__init samsung_clk_init( >> + struct device_node *np, void __iomem *base, >> + unsigned long nr_clks); >> extern void __init samsung_clk_of_register_fixed_ext( >> + struct samsung_clk_provider *ctx, >> struct samsung_fixed_rate_clock *fixed_rate_clk, >> unsigned int nr_fixed_rate_clk, >> struct of_device_id *clk_matches); >> >> -extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id); >> +extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, >> + struct clk *clk, unsigned int id); >> >> -extern void samsung_clk_register_alias(struct samsung_clock_alias *list, >> - unsigned int nr_clk); >> +extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, >> + struct samsung_clock_alias *list, >> + unsigned int nr_clk); >> extern void __init samsung_clk_register_fixed_rate( >> - struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); >> + struct samsung_clk_provider *ctx, >> + struct samsung_fixed_rate_clock *clk_list, >> + unsigned int nr_clk); >> extern void __init samsung_clk_register_fixed_factor( >> - struct samsung_fixed_factor_clock *list, unsigned int nr_clk); >> -extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list, >> + struct samsung_clk_provider *ctx, >> + struct samsung_fixed_factor_clock *list, >> + unsigned int nr_clk); >> +extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, >> + struct samsung_mux_clock *clk_list, >> unsigned int nr_clk); >> -extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list, >> +extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, >> + struct samsung_div_clock *clk_list, >> unsigned int nr_clk); >> -extern void __init samsung_clk_register_gate( >> +extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, >> struct samsung_gate_clock *clk_list, unsigned int nr_clk); >> -extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, >> - unsigned int nr_clk, void __iomem *base); >> +extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, >> + struct samsung_pll_clock *pll_list, >> + unsigned int nr_clk, void __iomem *base); >> >> extern unsigned long _get_rate(const char *clk_name); >> > > nit: Please keep the indentation consistent in all the function prototypes > above. ok. regards, Rahul Sharma. > > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-06 15:56 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-samsung-soc, devicetree, linux-arm-kernel Cc: mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open, Rahul Sharma From: Pankaj Dubey <pankaj.dubey@samsung.com> exynos5260 use pll2520xx and it has different bitfields for P,M,S values as compared to pll2550xx. Support for pll2520xx is added here. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> --- drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 108 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index e8e8953..237a889 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } +/* + * PLL2550xx Clock Type + */ + +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL2550XX_LOCK_FACTOR (270) + +#define PLL2550XX_MDIV_MASK (0x3FF) +#define PLL2550XX_PDIV_MASK (0x3F) +#define PLL2550XX_SDIV_MASK (0x7) +#define PLL2550XX_LOCK_STAT_MASK (0x1) +#define PLL2550XX_MDIV_SHIFT (9) +#define PLL2550XX_PDIV_SHIFT (3) +#define PLL2550XX_SDIV_SHIFT (0) +#define PLL2550XX_LOCK_STAT_SHIFT (21) + +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con; + u64 fvco = parent_rate; + + pll_con = __raw_readl(pll->con_reg); + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) +{ + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & + PLL2550XX_MDIV_MASK)) || + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & + PLL2550XX_PDIV_MASK))) + return 1; + else + return 0; +} + +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = __raw_readl(pll->con_reg); + + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; + __raw_writel(tmp, pll->con_reg); + } else { + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + + /* Change PLL PMS values */ + tmp &= ~((PLL2550XX_MDIV_MASK << PLL2550XX_MDIV_SHIFT) | + (PLL2550XX_PDIV_MASK << PLL2550XX_PDIV_SHIFT) | + (PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT)); + tmp |= (rate->mdiv << PLL2550XX_MDIV_SHIFT) | + (rate->pdiv << PLL2550XX_PDIV_SHIFT) | + (rate->sdiv << PLL2550XX_SDIV_SHIFT); + __raw_writel(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK + << PLL2550XX_LOCK_STAT_SHIFT))); + } + + return 0; +} + +static const struct clk_ops samsung_pll2550xx_clk_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll2550xx_set_rate, +}; + +static const struct clk_ops samsung_pll2550xx_clk_min_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -787,6 +888,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll46xx_clk_ops; break; + case pll_2550xx: + if (!pll->rate_table) + init.ops = &samsung_pll2550xx_clk_min_ops; + else + init.ops = &samsung_pll2550xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6c39030..e106470 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -25,6 +25,7 @@ enum samsung_pll_type { pll_4650c, pll_6552, pll_6553, + pll_2550xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx @ 2013-12-06 15:56 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-arm-kernel From: Pankaj Dubey <pankaj.dubey@samsung.com> exynos5260 use pll2520xx and it has different bitfields for P,M,S values as compared to pll2550xx. Support for pll2520xx is added here. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> --- drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 108 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index e8e8953..237a889 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } +/* + * PLL2550xx Clock Type + */ + +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL2550XX_LOCK_FACTOR (270) + +#define PLL2550XX_MDIV_MASK (0x3FF) +#define PLL2550XX_PDIV_MASK (0x3F) +#define PLL2550XX_SDIV_MASK (0x7) +#define PLL2550XX_LOCK_STAT_MASK (0x1) +#define PLL2550XX_MDIV_SHIFT (9) +#define PLL2550XX_PDIV_SHIFT (3) +#define PLL2550XX_SDIV_SHIFT (0) +#define PLL2550XX_LOCK_STAT_SHIFT (21) + +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con; + u64 fvco = parent_rate; + + pll_con = __raw_readl(pll->con_reg); + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) +{ + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & + PLL2550XX_MDIV_MASK)) || + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & + PLL2550XX_PDIV_MASK))) + return 1; + else + return 0; +} + +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = __raw_readl(pll->con_reg); + + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; + __raw_writel(tmp, pll->con_reg); + } else { + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + + /* Change PLL PMS values */ + tmp &= ~((PLL2550XX_MDIV_MASK << PLL2550XX_MDIV_SHIFT) | + (PLL2550XX_PDIV_MASK << PLL2550XX_PDIV_SHIFT) | + (PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT)); + tmp |= (rate->mdiv << PLL2550XX_MDIV_SHIFT) | + (rate->pdiv << PLL2550XX_PDIV_SHIFT) | + (rate->sdiv << PLL2550XX_SDIV_SHIFT); + __raw_writel(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK + << PLL2550XX_LOCK_STAT_SHIFT))); + } + + return 0; +} + +static const struct clk_ops samsung_pll2550xx_clk_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll2550xx_set_rate, +}; + +static const struct clk_ops samsung_pll2550xx_clk_min_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -787,6 +888,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll46xx_clk_ops; break; + case pll_2550xx: + if (!pll->rate_table) + init.ops = &samsung_pll2550xx_clk_min_ops; + else + init.ops = &samsung_pll2550xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6c39030..e106470 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -25,6 +25,7 @@ enum samsung_pll_type { pll_4650c, pll_6552, pll_6553, + pll_2550xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* Re: [PATCH 5/7] clk/samsung: add support for pll2550xx 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-09 8:06 ` Sachin Kamat -1 siblings, 0 replies; 57+ messages in thread From: Sachin Kamat @ 2013-12-09 8:06 UTC (permalink / raw) To: Rahul Sharma Cc: devicetree, linux-samsung-soc, Mike Turquette, PANKAJ KUMAR DUBEY, Tomasz Figa, sunil joshi, Thomas Abraham, Young-Gun Jang, Arun Kumar, Rahul Sharma, Kukjin Kim, linux-arm-kernel Hi Rahul, On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > exynos5260 use pll2520xx and it has different bitfields > for P,M,S values as compared to pll2550xx. Support for > pll2520xx is added here. This is a bit confusing to me. The commit message says "Support for pll2520xx is added". However, the patch subject and the entire code looks to be adding support for 2550xx. -- With warm regards, Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx @ 2013-12-09 8:06 ` Sachin Kamat 0 siblings, 0 replies; 57+ messages in thread From: Sachin Kamat @ 2013-12-09 8:06 UTC (permalink / raw) To: linux-arm-kernel Hi Rahul, On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > exynos5260 use pll2520xx and it has different bitfields > for P,M,S values as compared to pll2550xx. Support for > pll2520xx is added here. This is a bit confusing to me. The commit message says "Support for pll2520xx is added". However, the patch subject and the entire code looks to be adding support for 2550xx. -- With warm regards, Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 5/7] clk/samsung: add support for pll2550xx 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-19 12:01 ` Tomasz Figa -1 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-19 12:01 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open Hi Pankaj, Rahul, Arun, On Friday 06 of December 2013 21:26:29 Rahul Sharma wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > exynos5260 use pll2520xx and it has different bitfields > for P,M,S values as compared to pll2550xx. Support for > pll2520xx is added here. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > --- > drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 108 insertions(+) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index e8e8953..237a889 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, > return clk; > } > > +/* > + * PLL2550xx Clock Type > + */ > + > +/* Maximum lock time can be 270 * PDIV cycles */ > +#define PLL2550XX_LOCK_FACTOR (270) > + > +#define PLL2550XX_MDIV_MASK (0x3FF) > +#define PLL2550XX_PDIV_MASK (0x3F) > +#define PLL2550XX_SDIV_MASK (0x7) > +#define PLL2550XX_LOCK_STAT_MASK (0x1) > +#define PLL2550XX_MDIV_SHIFT (9) > +#define PLL2550XX_PDIV_SHIFT (3) > +#define PLL2550XX_SDIV_SHIFT (0) > +#define PLL2550XX_LOCK_STAT_SHIFT (21) > + > +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct samsung_clk_pll *pll = to_clk_pll(hw); > + u32 mdiv, pdiv, sdiv, pll_con; > + u64 fvco = parent_rate; > + > + pll_con = __raw_readl(pll->con_reg); > + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; > + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; > + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; > + > + fvco *= mdiv; > + do_div(fvco, (pdiv << sdiv)); > + > + return (unsigned long)fvco; > +} > + > +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) > +{ > + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & > + PLL2550XX_MDIV_MASK)) || > + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & > + PLL2550XX_PDIV_MASK))) > + return 1; > + else > + return 0; This doesn't look too good. Can you make this consistent with implementations of this helper for other PLLs, such as samsung_pll35xx_mp_change()? > +} > + > +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, > + unsigned long prate) > +{ > + struct samsung_clk_pll *pll = to_clk_pll(hw); > + const struct samsung_pll_rate_table *rate; > + u32 tmp; > + > + /* Get required rate settings from table */ > + rate = samsung_get_pll_settings(pll, drate); > + if (!rate) { > + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, > + drate, __clk_get_name(hw->clk)); > + return -EINVAL; > + } > + > + tmp = __raw_readl(pll->con_reg); > + > + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { > + /* If only s change, change just s value only*/ > + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); > + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; > + __raw_writel(tmp, pll->con_reg); > + } else { Please make coding style of this function consistent with implementations of this operation for other PLLs, such as samsung_pll35xx_set_rate(). Otherwise the patch looks fine. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx @ 2013-12-19 12:01 ` Tomasz Figa 0 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-19 12:01 UTC (permalink / raw) To: linux-arm-kernel Hi Pankaj, Rahul, Arun, On Friday 06 of December 2013 21:26:29 Rahul Sharma wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > exynos5260 use pll2520xx and it has different bitfields > for P,M,S values as compared to pll2550xx. Support for > pll2520xx is added here. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > --- > drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 108 insertions(+) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index e8e8953..237a889 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, > return clk; > } > > +/* > + * PLL2550xx Clock Type > + */ > + > +/* Maximum lock time can be 270 * PDIV cycles */ > +#define PLL2550XX_LOCK_FACTOR (270) > + > +#define PLL2550XX_MDIV_MASK (0x3FF) > +#define PLL2550XX_PDIV_MASK (0x3F) > +#define PLL2550XX_SDIV_MASK (0x7) > +#define PLL2550XX_LOCK_STAT_MASK (0x1) > +#define PLL2550XX_MDIV_SHIFT (9) > +#define PLL2550XX_PDIV_SHIFT (3) > +#define PLL2550XX_SDIV_SHIFT (0) > +#define PLL2550XX_LOCK_STAT_SHIFT (21) > + > +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct samsung_clk_pll *pll = to_clk_pll(hw); > + u32 mdiv, pdiv, sdiv, pll_con; > + u64 fvco = parent_rate; > + > + pll_con = __raw_readl(pll->con_reg); > + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; > + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; > + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; > + > + fvco *= mdiv; > + do_div(fvco, (pdiv << sdiv)); > + > + return (unsigned long)fvco; > +} > + > +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) > +{ > + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & > + PLL2550XX_MDIV_MASK)) || > + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & > + PLL2550XX_PDIV_MASK))) > + return 1; > + else > + return 0; This doesn't look too good. Can you make this consistent with implementations of this helper for other PLLs, such as samsung_pll35xx_mp_change()? > +} > + > +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, > + unsigned long prate) > +{ > + struct samsung_clk_pll *pll = to_clk_pll(hw); > + const struct samsung_pll_rate_table *rate; > + u32 tmp; > + > + /* Get required rate settings from table */ > + rate = samsung_get_pll_settings(pll, drate); > + if (!rate) { > + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, > + drate, __clk_get_name(hw->clk)); > + return -EINVAL; > + } > + > + tmp = __raw_readl(pll->con_reg); > + > + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { > + /* If only s change, change just s value only*/ > + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); > + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; > + __raw_writel(tmp, pll->con_reg); > + } else { Please make coding style of this function consistent with implementations of this operation for other PLLs, such as samsung_pll35xx_set_rate(). Otherwise the patch looks fine. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 5/7] clk/samsung: add support for pll2550xx 2013-12-19 12:01 ` Tomasz Figa @ 2014-01-06 11:36 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-06 11:36 UTC (permalink / raw) To: Tomasz Figa Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Hi Tomasz, On 19 December 2013 17:31, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Pankaj, Rahul, Arun, > > On Friday 06 of December 2013 21:26:29 Rahul Sharma wrote: >> From: Pankaj Dubey <pankaj.dubey@samsung.com> >> >> exynos5260 use pll2520xx and it has different bitfields >> for P,M,S values as compared to pll2550xx. Support for >> pll2520xx is added here. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> >> --- >> drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ >> drivers/clk/samsung/clk-pll.h | 1 + >> 2 files changed, 108 insertions(+) >> >> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c >> index e8e8953..237a889 100644 >> --- a/drivers/clk/samsung/clk-pll.c >> +++ b/drivers/clk/samsung/clk-pll.c >> @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, >> return clk; >> } >> >> +/* >> + * PLL2550xx Clock Type >> + */ >> + >> +/* Maximum lock time can be 270 * PDIV cycles */ >> +#define PLL2550XX_LOCK_FACTOR (270) >> + >> +#define PLL2550XX_MDIV_MASK (0x3FF) >> +#define PLL2550XX_PDIV_MASK (0x3F) >> +#define PLL2550XX_SDIV_MASK (0x7) >> +#define PLL2550XX_LOCK_STAT_MASK (0x1) >> +#define PLL2550XX_MDIV_SHIFT (9) >> +#define PLL2550XX_PDIV_SHIFT (3) >> +#define PLL2550XX_SDIV_SHIFT (0) >> +#define PLL2550XX_LOCK_STAT_SHIFT (21) >> + >> +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, >> + unsigned long parent_rate) >> +{ >> + struct samsung_clk_pll *pll = to_clk_pll(hw); >> + u32 mdiv, pdiv, sdiv, pll_con; >> + u64 fvco = parent_rate; >> + >> + pll_con = __raw_readl(pll->con_reg); >> + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; >> + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; >> + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; >> + >> + fvco *= mdiv; >> + do_div(fvco, (pdiv << sdiv)); >> + >> + return (unsigned long)fvco; >> +} >> + >> +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) >> +{ >> + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & >> + PLL2550XX_MDIV_MASK)) || >> + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & >> + PLL2550XX_PDIV_MASK))) >> + return 1; >> + else >> + return 0; > > This doesn't look too good. Can you make this consistent with > implementations of this helper for other PLLs, such as > samsung_pll35xx_mp_change()? I have changed this in V2. > >> +} >> + >> +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, >> + unsigned long prate) >> +{ >> + struct samsung_clk_pll *pll = to_clk_pll(hw); >> + const struct samsung_pll_rate_table *rate; >> + u32 tmp; >> + >> + /* Get required rate settings from table */ >> + rate = samsung_get_pll_settings(pll, drate); >> + if (!rate) { >> + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, >> + drate, __clk_get_name(hw->clk)); >> + return -EINVAL; >> + } >> + >> + tmp = __raw_readl(pll->con_reg); >> + >> + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { >> + /* If only s change, change just s value only*/ >> + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); >> + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; >> + __raw_writel(tmp, pll->con_reg); >> + } else { > > Please make coding style of this function consistent with implementations > of this operation for other PLLs, such as samsung_pll35xx_set_rate(). > > Otherwise the patch looks fine. Ok. Regards, Rahul Sharma. > > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx @ 2014-01-06 11:36 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-06 11:36 UTC (permalink / raw) To: linux-arm-kernel Hi Tomasz, On 19 December 2013 17:31, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Pankaj, Rahul, Arun, > > On Friday 06 of December 2013 21:26:29 Rahul Sharma wrote: >> From: Pankaj Dubey <pankaj.dubey@samsung.com> >> >> exynos5260 use pll2520xx and it has different bitfields >> for P,M,S values as compared to pll2550xx. Support for >> pll2520xx is added here. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> >> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> >> --- >> drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ >> drivers/clk/samsung/clk-pll.h | 1 + >> 2 files changed, 108 insertions(+) >> >> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c >> index e8e8953..237a889 100644 >> --- a/drivers/clk/samsung/clk-pll.c >> +++ b/drivers/clk/samsung/clk-pll.c >> @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, >> return clk; >> } >> >> +/* >> + * PLL2550xx Clock Type >> + */ >> + >> +/* Maximum lock time can be 270 * PDIV cycles */ >> +#define PLL2550XX_LOCK_FACTOR (270) >> + >> +#define PLL2550XX_MDIV_MASK (0x3FF) >> +#define PLL2550XX_PDIV_MASK (0x3F) >> +#define PLL2550XX_SDIV_MASK (0x7) >> +#define PLL2550XX_LOCK_STAT_MASK (0x1) >> +#define PLL2550XX_MDIV_SHIFT (9) >> +#define PLL2550XX_PDIV_SHIFT (3) >> +#define PLL2550XX_SDIV_SHIFT (0) >> +#define PLL2550XX_LOCK_STAT_SHIFT (21) >> + >> +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, >> + unsigned long parent_rate) >> +{ >> + struct samsung_clk_pll *pll = to_clk_pll(hw); >> + u32 mdiv, pdiv, sdiv, pll_con; >> + u64 fvco = parent_rate; >> + >> + pll_con = __raw_readl(pll->con_reg); >> + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; >> + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; >> + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; >> + >> + fvco *= mdiv; >> + do_div(fvco, (pdiv << sdiv)); >> + >> + return (unsigned long)fvco; >> +} >> + >> +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) >> +{ >> + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & >> + PLL2550XX_MDIV_MASK)) || >> + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & >> + PLL2550XX_PDIV_MASK))) >> + return 1; >> + else >> + return 0; > > This doesn't look too good. Can you make this consistent with > implementations of this helper for other PLLs, such as > samsung_pll35xx_mp_change()? I have changed this in V2. > >> +} >> + >> +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, >> + unsigned long prate) >> +{ >> + struct samsung_clk_pll *pll = to_clk_pll(hw); >> + const struct samsung_pll_rate_table *rate; >> + u32 tmp; >> + >> + /* Get required rate settings from table */ >> + rate = samsung_get_pll_settings(pll, drate); >> + if (!rate) { >> + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, >> + drate, __clk_get_name(hw->clk)); >> + return -EINVAL; >> + } >> + >> + tmp = __raw_readl(pll->con_reg); >> + >> + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { >> + /* If only s change, change just s value only*/ >> + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); >> + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; >> + __raw_writel(tmp, pll->con_reg); >> + } else { > > Please make coding style of this function consistent with implementations > of this operation for other PLLs, such as samsung_pll35xx_set_rate(). > > Otherwise the patch looks fine. Ok. Regards, Rahul Sharma. > > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-06 15:56 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-samsung-soc, devicetree, linux-arm-kernel Cc: mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open, Rahul Sharma Add support for pll2650xx in samsung pll file. This pll variant is close to pll36xx but uses CON2 registers instead of CON1. Aud_pll in Exynos5260 is pll2650xx and uses this code. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> --- drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 2 +- 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 237a889..60c5679 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -811,6 +811,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = { .recalc_rate = samsung_pll2550xx_recalc_rate, }; +/* + * PLL2650XX Clock Type + */ + +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL2650XX_LOCK_FACTOR (3000) + +#define PLL2650XX_MDIV_SHIFT (9) +#define PLL2650XX_PDIV_SHIFT (3) +#define PLL2650XX_SDIV_SHIFT (0) +#define PLL2650XX_KDIV_SHIFT (0) +#define PLL2650XX_MDIV_MASK (0x1ff) +#define PLL2650XX_PDIV_MASK (0x3f) +#define PLL2650XX_SDIV_MASK (0x7) +#define PLL2650XX_KDIV_MASK (0xffff) +#define PLL2650XX_PLL_ENABLE_SHIFT (23) +#define PLL2650XX_PLL_LOCKTIME_SHIFT (21) +#define PLL2650XX_PLL_FOUTMASK_SHIFT (31) + +static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; + s16 kdiv; + u64 fvco = parent_rate; + + pll_con0 = __raw_readl(pll->con_reg); + pll_con2 = __raw_readl(pll->con_reg + 8); + mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; + pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; + sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; + kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK); + + fvco *= (mdiv << 16) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>= 16; + + return (unsigned long)fvco; +} + +static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp, pll_con0, pll_con2; + const struct samsung_pll_rate_table *rate; + + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + pll_con0 = __raw_readl(pll->con_reg); + pll_con2 = __raw_readl(pll->con_reg + 8); + + /* Change PLL PMS values */ + pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | + PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT | + PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); + pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; + pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; + pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; + pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; + pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; + + pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT); + pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) + << PLL2650XX_KDIV_SHIFT; + + /* Set PLL lock time. */ + __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); + + __raw_writel(pll_con0, pll->con_reg); + __raw_writel(pll_con2, pll->con_reg + 8); + + do { + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT))); + + return 0; +} + +static const struct clk_ops samsung_pll2650xx_clk_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, + .set_rate = samsung_pll2650xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll2650xx_clk_min_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -894,6 +989,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll2550xx_clk_ops; break; + case pll_2650xx: + if (!pll->rate_table) + init.ops = &samsung_pll2650xx_clk_min_ops; + else + init.ops = &samsung_pll2650xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index e106470..b326e94 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -26,6 +26,7 @@ enum samsung_pll_type { pll_6552, pll_6553, pll_2550xx, + pll_2650xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ @@ -93,5 +94,4 @@ struct samsung_pll_rate_table { extern struct clk * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset); - #endif /* __SAMSUNG_CLK_PLL_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx @ 2013-12-06 15:56 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw) To: linux-arm-kernel Add support for pll2650xx in samsung pll file. This pll variant is close to pll36xx but uses CON2 registers instead of CON1. Aud_pll in Exynos5260 is pll2650xx and uses this code. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> --- drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 2 +- 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 237a889..60c5679 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -811,6 +811,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = { .recalc_rate = samsung_pll2550xx_recalc_rate, }; +/* + * PLL2650XX Clock Type + */ + +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL2650XX_LOCK_FACTOR (3000) + +#define PLL2650XX_MDIV_SHIFT (9) +#define PLL2650XX_PDIV_SHIFT (3) +#define PLL2650XX_SDIV_SHIFT (0) +#define PLL2650XX_KDIV_SHIFT (0) +#define PLL2650XX_MDIV_MASK (0x1ff) +#define PLL2650XX_PDIV_MASK (0x3f) +#define PLL2650XX_SDIV_MASK (0x7) +#define PLL2650XX_KDIV_MASK (0xffff) +#define PLL2650XX_PLL_ENABLE_SHIFT (23) +#define PLL2650XX_PLL_LOCKTIME_SHIFT (21) +#define PLL2650XX_PLL_FOUTMASK_SHIFT (31) + +static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; + s16 kdiv; + u64 fvco = parent_rate; + + pll_con0 = __raw_readl(pll->con_reg); + pll_con2 = __raw_readl(pll->con_reg + 8); + mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; + pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; + sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; + kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK); + + fvco *= (mdiv << 16) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>= 16; + + return (unsigned long)fvco; +} + +static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp, pll_con0, pll_con2; + const struct samsung_pll_rate_table *rate; + + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + pll_con0 = __raw_readl(pll->con_reg); + pll_con2 = __raw_readl(pll->con_reg + 8); + + /* Change PLL PMS values */ + pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | + PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT | + PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); + pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; + pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; + pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; + pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; + pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; + + pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT); + pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) + << PLL2650XX_KDIV_SHIFT; + + /* Set PLL lock time. */ + __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); + + __raw_writel(pll_con0, pll->con_reg); + __raw_writel(pll_con2, pll->con_reg + 8); + + do { + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT))); + + return 0; +} + +static const struct clk_ops samsung_pll2650xx_clk_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, + .set_rate = samsung_pll2650xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll2650xx_clk_min_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -894,6 +989,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll2550xx_clk_ops; break; + case pll_2650xx: + if (!pll->rate_table) + init.ops = &samsung_pll2650xx_clk_min_ops; + else + init.ops = &samsung_pll2650xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index e106470..b326e94 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -26,6 +26,7 @@ enum samsung_pll_type { pll_6552, pll_6553, pll_2550xx, + pll_2650xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ @@ -93,5 +94,4 @@ struct samsung_pll_rate_table { extern struct clk * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset); - #endif /* __SAMSUNG_CLK_PLL_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 57+ messages in thread
* Re: [PATCH 6/7] clk/samsung: add support for pll2650xx 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-09 8:09 ` Sachin Kamat -1 siblings, 0 replies; 57+ messages in thread From: Sachin Kamat @ 2013-12-09 8:09 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar, Rahul Sharma Hi Rahul, On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: > Add support for pll2650xx in samsung pll file. This pll variant > is close to pll36xx but uses CON2 registers instead of CON1. > > Aud_pll in Exynos5260 is pll2650xx and uses this code. > > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > --- > drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 2 +- > 2 files changed, 102 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index 237a889..60c5679 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -811,6 +811,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = { > .recalc_rate = samsung_pll2550xx_recalc_rate, > }; > > +/* > + * PLL2650XX Clock Type > + */ > + > +/* Maximum lock time can be 3000 * PDIV cycles */ > +#define PLL2650XX_LOCK_FACTOR (3000) > + > +#define PLL2650XX_MDIV_SHIFT (9) > +#define PLL2650XX_PDIV_SHIFT (3) > +#define PLL2650XX_SDIV_SHIFT (0) > +#define PLL2650XX_KDIV_SHIFT (0) > +#define PLL2650XX_MDIV_MASK (0x1ff) > +#define PLL2650XX_PDIV_MASK (0x3f) > +#define PLL2650XX_SDIV_MASK (0x7) > +#define PLL2650XX_KDIV_MASK (0xffff) > +#define PLL2650XX_PLL_ENABLE_SHIFT (23) > +#define PLL2650XX_PLL_LOCKTIME_SHIFT (21) > +#define PLL2650XX_PLL_FOUTMASK_SHIFT (31) nit: Braces are unnecessary. -- With warm regards, Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx @ 2013-12-09 8:09 ` Sachin Kamat 0 siblings, 0 replies; 57+ messages in thread From: Sachin Kamat @ 2013-12-09 8:09 UTC (permalink / raw) To: linux-arm-kernel Hi Rahul, On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote: > Add support for pll2650xx in samsung pll file. This pll variant > is close to pll36xx but uses CON2 registers instead of CON1. > > Aud_pll in Exynos5260 is pll2650xx and uses this code. > > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > --- > drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 2 +- > 2 files changed, 102 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index 237a889..60c5679 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -811,6 +811,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = { > .recalc_rate = samsung_pll2550xx_recalc_rate, > }; > > +/* > + * PLL2650XX Clock Type > + */ > + > +/* Maximum lock time can be 3000 * PDIV cycles */ > +#define PLL2650XX_LOCK_FACTOR (3000) > + > +#define PLL2650XX_MDIV_SHIFT (9) > +#define PLL2650XX_PDIV_SHIFT (3) > +#define PLL2650XX_SDIV_SHIFT (0) > +#define PLL2650XX_KDIV_SHIFT (0) > +#define PLL2650XX_MDIV_MASK (0x1ff) > +#define PLL2650XX_PDIV_MASK (0x3f) > +#define PLL2650XX_SDIV_MASK (0x7) > +#define PLL2650XX_KDIV_MASK (0xffff) > +#define PLL2650XX_PLL_ENABLE_SHIFT (23) > +#define PLL2650XX_PLL_LOCKTIME_SHIFT (21) > +#define PLL2650XX_PLL_FOUTMASK_SHIFT (31) nit: Braces are unnecessary. -- With warm regards, Sachin ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 6/7] clk/samsung: add support for pll2650xx 2013-12-06 15:56 ` Rahul Sharma @ 2013-12-19 11:45 ` Tomasz Figa -1 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-19 11:45 UTC (permalink / raw) To: Rahul Sharma Cc: linux-samsung-soc, devicetree, linux-arm-kernel, mturquette, kgene.kim, thomas.ab, tomasz.figa, joshi, pankaj.dubey, yg1004.jang, arun.kk, r.sh.open Hi Rahul, On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote: > Add support for pll2650xx in samsung pll file. This pll variant > is close to pll36xx but uses CON2 registers instead of CON1. If the ops are otherwise idential, why not reuse the ops for pll36xx and use CON1 or CON2 register conditionally based on pll->type field? (Just as it is already done for pll4600, 4650 and 4650c.) Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx @ 2013-12-19 11:45 ` Tomasz Figa 0 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2013-12-19 11:45 UTC (permalink / raw) To: linux-arm-kernel Hi Rahul, On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote: > Add support for pll2650xx in samsung pll file. This pll variant > is close to pll36xx but uses CON2 registers instead of CON1. If the ops are otherwise idential, why not reuse the ops for pll36xx and use CON1 or CON2 register conditionally based on pll->type field? (Just as it is already done for pll4600, 4650 and 4650c.) Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 6/7] clk/samsung: add support for pll2650xx 2013-12-19 11:45 ` Tomasz Figa @ 2014-01-06 11:44 ` Rahul Sharma -1 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-06 11:44 UTC (permalink / raw) To: Tomasz Figa Cc: Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, Tomasz Figa, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar Hi Tomasz, On 19 December 2013 17:15, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Rahul, > > On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote: >> Add support for pll2650xx in samsung pll file. This pll variant >> is close to pll36xx but uses CON2 registers instead of CON1. > > If the ops are otherwise idential, why not reuse the ops for pll36xx > and use CON1 or CON2 register conditionally based on pll->type field? > (Just as it is already done for pll4600, 4650 and 4650c.) > I verified the difference and found that pll2650xx is fairly different in terms of Bit Fields, Con2 register, and additional PLL config bits than pll36xx. Due to this, I have to add lot of if-else code based on pll type which doesn't looks clean. Regards, Rahul Sharma. > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx @ 2014-01-06 11:44 ` Rahul Sharma 0 siblings, 0 replies; 57+ messages in thread From: Rahul Sharma @ 2014-01-06 11:44 UTC (permalink / raw) To: linux-arm-kernel Hi Tomasz, On 19 December 2013 17:15, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Rahul, > > On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote: >> Add support for pll2650xx in samsung pll file. This pll variant >> is close to pll36xx but uses CON2 registers instead of CON1. > > If the ops are otherwise idential, why not reuse the ops for pll36xx > and use CON1 or CON2 register conditionally based on pll->type field? > (Just as it is already done for pll4600, 4650 and 4650c.) > I verified the difference and found that pll2650xx is fairly different in terms of Bit Fields, Con2 register, and additional PLL config bits than pll36xx. Due to this, I have to add lot of if-else code based on pll type which doesn't looks clean. Regards, Rahul Sharma. > Best regards, > Tomasz > ^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH 6/7] clk/samsung: add support for pll2650xx 2014-01-06 11:44 ` Rahul Sharma @ 2014-01-08 0:37 ` Tomasz Figa -1 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2014-01-08 0:37 UTC (permalink / raw) To: Rahul Sharma Cc: Tomasz Figa, Rahul Sharma, linux-samsung-soc, devicetree, linux-arm-kernel, Mike Turquette, Kukjin Kim, Thomas Abraham, sunil joshi, PANKAJ KUMAR DUBEY, Young-Gun Jang, Arun Kumar On Monday 06 of January 2014 17:14:48 Rahul Sharma wrote: > Hi Tomasz, > > On 19 December 2013 17:15, Tomasz Figa <t.figa@samsung.com> wrote: > > Hi Rahul, > > > > On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote: > >> Add support for pll2650xx in samsung pll file. This pll variant > >> is close to pll36xx but uses CON2 registers instead of CON1. > > > > If the ops are otherwise idential, why not reuse the ops for pll36xx > > and use CON1 or CON2 register conditionally based on pll->type field? > > (Just as it is already done for pll4600, 4650 and 4650c.) > > > > I verified the difference and found that pll2650xx is fairly > different in terms of > Bit Fields, Con2 register, and additional PLL config bits than pll36xx. Due to > this, I have to add lot of if-else code based on pll type which > doesn't looks clean. Fair enough. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx @ 2014-01-08 0:37 ` Tomasz Figa 0 siblings, 0 replies; 57+ messages in thread From: Tomasz Figa @ 2014-01-08 0:37 UTC (permalink / raw) To: linux-arm-kernel On Monday 06 of January 2014 17:14:48 Rahul Sharma wrote: > Hi Tomasz, > > On 19 December 2013 17:15, Tomasz Figa <t.figa@samsung.com> wrote: > > Hi Rahul, > > > > On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote: > >> Add support for pll2650xx in samsung pll file. This pll variant > >> is close to pll36xx but uses CON2 registers instead of CON1. > > > > If the ops are otherwise idential, why not reuse the ops for pll36xx > > and use CON1 or CON2 register conditionally based on pll->type field? > > (Just as it is already done for pll4600, 4650 and 4650c.) > > > > I verified the difference and found that pll2650xx is fairly > different in terms of > Bit Fields, Con2 register, and additional PLL config bits than pll36xx. Due to > this, I have to add lot of if-else code based on pll type which > doesn't looks clean. Fair enough. Best regards, Tomasz ^ permalink raw reply [flat|nested] 57+ messages in thread
end of thread, other threads:[~2014-01-08 0:37 UTC | newest]
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2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma
2013-12-06 15:56 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 1/7] ARM: EXYNOS: initial board " Rahul Sharma
2013-12-06 15:56 ` Rahul Sharma
2013-12-09 6:23 ` Sachin Kamat
2013-12-09 6:23 ` Sachin Kamat
2013-12-09 6:33 ` Rahul Sharma
2013-12-09 6:33 ` Rahul Sharma
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2013-12-23 4:39 ` Rahul Sharma
2013-12-23 4:39 ` Rahul Sharma
2013-12-10 15:57 ` Tomasz Figa
2013-12-10 15:57 ` Tomasz Figa
2014-01-03 9:24 ` Rahul Sharma
2014-01-03 9:24 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data Rahul Sharma
2013-12-06 15:56 ` Rahul Sharma
2013-12-09 4:51 ` Sachin Kamat
2013-12-09 4:51 ` Sachin Kamat
2013-12-09 6:36 ` Rahul Sharma
2013-12-09 6:36 ` Rahul Sharma
2014-01-03 9:25 ` Rahul Sharma
2014-01-03 9:25 ` Rahul Sharma
2013-12-10 16:04 ` Tomasz Figa
2013-12-10 16:04 ` Tomasz Figa
2014-01-03 9:26 ` Rahul Sharma
2014-01-03 9:26 ` Rahul Sharma
[not found] ` <1386345391-23482-1-git-send-email-rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2013-12-06 15:56 ` [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC Rahul Sharma
2013-12-06 15:56 ` Rahul Sharma
2013-12-10 17:10 ` Tomasz Figa
2013-12-10 17:10 ` Tomasz Figa
2014-01-06 9:40 ` Rahul Sharma
2014-01-06 9:40 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 7/7] clk/exynos5260: add clock file for exynos5260 Rahul Sharma
2013-12-06 15:56 ` [PATCH 4/7] clk/samsung: add support for multuple clock providers Rahul Sharma
2013-12-06 15:56 ` Rahul Sharma
2013-12-11 11:15 ` Tomasz Figa
2013-12-11 11:15 ` Tomasz Figa
2014-01-06 11:35 ` Rahul Sharma
2014-01-06 11:35 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 5/7] clk/samsung: add support for pll2550xx Rahul Sharma
2013-12-06 15:56 ` Rahul Sharma
2013-12-09 8:06 ` Sachin Kamat
2013-12-09 8:06 ` Sachin Kamat
2013-12-19 12:01 ` Tomasz Figa
2013-12-19 12:01 ` Tomasz Figa
2014-01-06 11:36 ` Rahul Sharma
2014-01-06 11:36 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 6/7] clk/samsung: add support for pll2650xx Rahul Sharma
2013-12-06 15:56 ` Rahul Sharma
2013-12-09 8:09 ` Sachin Kamat
2013-12-09 8:09 ` Sachin Kamat
2013-12-19 11:45 ` Tomasz Figa
2013-12-19 11:45 ` Tomasz Figa
2014-01-06 11:44 ` Rahul Sharma
2014-01-06 11:44 ` Rahul Sharma
2014-01-08 0:37 ` Tomasz Figa
2014-01-08 0:37 ` Tomasz Figa
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.