* [PATCH 1/6] drm/i915: Extract out gamma table and CSC to their own file
2016-01-21 15:03 [PATCH 0/6] Pipe level color management Lionel Landwerlin
@ 2016-01-21 15:03 ` Lionel Landwerlin
2016-01-21 15:24 ` Daniel Stone
2016-01-21 15:03 ` [PATCH 2/6] drm: introduce color correction properties Lionel Landwerlin
` (6 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Lionel Landwerlin @ 2016-01-21 15:03 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_color.c | 174 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 163 +++-----------------------------
drivers/gpu/drm/i915/intel_drv.h | 10 ++
4 files changed, 197 insertions(+), 151 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_color.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..0516300 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -55,6 +55,7 @@ i915-y += intel_audio.o \
intel_atomic.o \
intel_atomic_plane.o \
intel_bios.o \
+ intel_color.o \
intel_display.o \
intel_fbc.o \
intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
new file mode 100644
index 0000000..39ca215
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+/*
+ * Set up the pipe CSC unit.
+ *
+ * Currently only full range RGB to limited range RGB conversion
+ * is supported, but eventually this should handle various
+ * RGB<->YCbCr scenarios as well.
+ */
+static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ uint16_t coeff = 0x7800; /* 1.0 */
+
+ /*
+ * TODO: Check what kind of values actually come out of the pipe
+ * with these coeff/postoff values and adjust to get the best
+ * accuracy. Perhaps we even need to take the bpc value into
+ * consideration.
+ */
+
+ if (intel_crtc->config->limited_color_range)
+ coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
+
+ /*
+ * GY/GU and RY/RU should be the other way around according
+ * to BSpec, but reality doesn't agree. Just set them up in
+ * a way that results in the correct picture.
+ */
+ I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
+ I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
+
+ I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
+ I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
+
+ I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
+ I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
+
+ I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
+ I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
+ I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
+
+ if (INTEL_INFO(dev)->gen > 6) {
+ uint16_t postoff = 0;
+
+ if (intel_crtc->config->limited_color_range)
+ postoff = (16 * (1 << 12) / 255) & 0x1fff;
+
+ I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
+ I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
+ I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
+
+ I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+ } else {
+ uint32_t mode = CSC_MODE_YUV_TO_RGB;
+
+ if (intel_crtc->config->limited_color_range)
+ mode |= CSC_BLACK_SCREEN_OFFSET;
+
+ I915_WRITE(PIPE_CSC_MODE(pipe), mode);
+ }
+}
+
+void intel_color_set_csc(struct drm_crtc *crtc)
+{
+ i9xx_load_csc_matrix(crtc);
+}
+
+/** Loads the palette/gamma unit for the CRTC with the prepared values on */
+static void i9xx_load_legacy_gamma_lut(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ int i;
+ bool reenable_ips = false;
+
+ if (HAS_GMCH_DISPLAY(dev)) {
+ if (intel_crtc->config->has_dsi_encoder)
+ assert_dsi_pll_enabled(dev_priv);
+ else
+ assert_pll_enabled(dev_priv, pipe);
+ }
+
+ /* Workaround : Do not read or write the pipe palette/gamma data while
+ * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+ */
+ if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
+ ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_SPLIT)) {
+ hsw_disable_ips(intel_crtc);
+ reenable_ips = true;
+ }
+
+ for (i = 0; i < 256; i++) {
+ uint32_t word = (intel_crtc->lut_r[i] << 16) |
+ (intel_crtc->lut_g[i] << 8) |
+ intel_crtc->lut_b[i];
+ if (HAS_GMCH_DISPLAY(dev))
+ I915_WRITE(PALETTE(pipe, i), word);
+ else
+ I915_WRITE(LGC_PALETTE(pipe, i), word);
+ }
+
+ I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
+
+ if (reenable_ips)
+ hsw_enable_ips(intel_crtc);
+}
+
+void intel_color_load_gamma_lut(struct drm_crtc *crtc)
+{
+ /* The clocks have to be on to load the palette. */
+ if (!crtc->state->active)
+ return;
+
+ i9xx_load_legacy_gamma_lut(crtc);
+}
+
+void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
+ u16 *blue, uint32_t start, uint32_t size)
+{
+ int end = (start + size > 256) ? 256 : start + size, i;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ for (i = start; i < end; i++) {
+ intel_crtc->lut_r[i] = red[i] >> 8;
+ intel_crtc->lut_g[i] = green[i] >> 8;
+ intel_crtc->lut_b[i] = blue[i] >> 8;
+ }
+
+ intel_color_load_gamma_lut(crtc);
+}
+
+void intel_color_init(struct drm_crtc *crtc)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int i;
+
+ drm_mode_crtc_set_gamma_size(crtc, 256);
+ for (i = 0; i < 256; i++) {
+ intel_crtc->lut_r[i] = i;
+ intel_crtc->lut_g[i] = i;
+ intel_crtc->lut_b[i] = i;
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8104511..a0ebc85 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -101,7 +101,6 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m2_n2);
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipeconf(struct drm_crtc *crtc);
-static void intel_set_pipe_csc(struct drm_crtc *crtc);
static void vlv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
static void chv_prepare_pll(struct intel_crtc *crtc,
@@ -1165,7 +1164,7 @@ void assert_pll(struct drm_i915_private *dev_priv,
}
/* XXX: the dsi pll is shared between MIPI DSI ports */
-static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
+void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
{
u32 val;
bool cur_state;
@@ -1179,8 +1178,6 @@ static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
"DSI PLL state assertion failure (expected %s, current %s)\n",
onoff(state), onoff(cur_state));
}
-#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
-#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
struct intel_shared_dpll *
intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
@@ -3315,7 +3312,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
pipe_config->pipe_src_w, pipe_config->pipe_src_h);
if (HAS_DDI(dev))
- intel_set_pipe_csc(&crtc->base);
+ intel_color_set_csc(&crtc->base);
/*
* Update pipe size and adjust fitter if needed: the reason for this is
@@ -4626,55 +4623,6 @@ void hsw_disable_ips(struct intel_crtc *crtc)
intel_wait_for_vblank(dev, crtc->pipe);
}
-/** Loads the palette/gamma unit for the CRTC with the prepared values */
-static void intel_crtc_load_lut(struct drm_crtc *crtc)
-{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
- int i;
- bool reenable_ips = false;
-
- /* The clocks have to be on to load the palette. */
- if (!crtc->state->active)
- return;
-
- if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
- if (intel_crtc->config->has_dsi_encoder)
- assert_dsi_pll_enabled(dev_priv);
- else
- assert_pll_enabled(dev_priv, pipe);
- }
-
- /* Workaround : Do not read or write the pipe palette/gamma data while
- * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
- */
- if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
- ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
- GAMMA_MODE_MODE_SPLIT)) {
- hsw_disable_ips(intel_crtc);
- reenable_ips = true;
- }
-
- for (i = 0; i < 256; i++) {
- i915_reg_t palreg;
-
- if (HAS_GMCH_DISPLAY(dev))
- palreg = PALETTE(pipe, i);
- else
- palreg = LGC_PALETTE(pipe, i);
-
- I915_WRITE(palreg,
- (intel_crtc->lut_r[i] << 16) |
- (intel_crtc->lut_g[i] << 8) |
- intel_crtc->lut_b[i]);
- }
-
- if (reenable_ips)
- hsw_enable_ips(intel_crtc);
-}
-
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
{
if (intel_crtc->overlay) {
@@ -4910,7 +4858,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_crtc_load_lut(crtc);
+ intel_color_load_gamma_lut(crtc);
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
@@ -4978,7 +4926,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
haswell_set_pipeconf(crtc);
- intel_set_pipe_csc(crtc);
+ intel_color_set_csc(crtc);
intel_crtc->active = true;
@@ -5007,7 +4955,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_crtc_load_lut(crtc);
+ intel_color_load_gamma_lut(crtc);
intel_ddi_set_pipe_settings(crtc);
if (!intel_crtc->config->has_dsi_encoder)
@@ -6228,7 +6176,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
i9xx_pfit_enable(intel_crtc);
- intel_crtc_load_lut(crtc);
+ intel_color_load_gamma_lut(crtc);
intel_enable_pipe(intel_crtc);
@@ -6281,7 +6229,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
i9xx_pfit_enable(intel_crtc);
- intel_crtc_load_lut(crtc);
+ intel_color_load_gamma_lut(crtc);
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
@@ -8769,70 +8717,6 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
POSTING_READ(PIPECONF(pipe));
}
-/*
- * Set up the pipe CSC unit.
- *
- * Currently only full range RGB to limited range RGB conversion
- * is supported, but eventually this should handle various
- * RGB<->YCbCr scenarios as well.
- */
-static void intel_set_pipe_csc(struct drm_crtc *crtc)
-{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
- uint16_t coeff = 0x7800; /* 1.0 */
-
- /*
- * TODO: Check what kind of values actually come out of the pipe
- * with these coeff/postoff values and adjust to get the best
- * accuracy. Perhaps we even need to take the bpc value into
- * consideration.
- */
-
- if (intel_crtc->config->limited_color_range)
- coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
-
- /*
- * GY/GU and RY/RU should be the other way around according
- * to BSpec, but reality doesn't agree. Just set them up in
- * a way that results in the correct picture.
- */
- I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
- I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
-
- I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
- I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
-
- I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
- I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
-
- I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
- I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
- I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
-
- if (INTEL_INFO(dev)->gen > 6) {
- uint16_t postoff = 0;
-
- if (intel_crtc->config->limited_color_range)
- postoff = (16 * (1 << 12) / 255) & 0x1fff;
-
- I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
- I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
- I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
-
- I915_WRITE(PIPE_CSC_MODE(pipe), 0);
- } else {
- uint32_t mode = CSC_MODE_YUV_TO_RGB;
-
- if (intel_crtc->config->limited_color_range)
- mode |= CSC_BLACK_SCREEN_OFFSET;
-
- I915_WRITE(PIPE_CSC_MODE(pipe), mode);
- }
-}
-
static void haswell_set_pipeconf(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -8855,9 +8739,6 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
I915_WRITE(PIPECONF(cpu_transcoder), val);
POSTING_READ(PIPECONF(cpu_transcoder));
- I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
- POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
-
if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
val = 0;
@@ -10248,21 +10129,6 @@ static bool cursor_size_ok(struct drm_device *dev,
return true;
}
-static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
- u16 *blue, uint32_t start, uint32_t size)
-{
- int end = (start + size > 256) ? 256 : start + size, i;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
- for (i = start; i < end; i++) {
- intel_crtc->lut_r[i] = red[i] >> 8;
- intel_crtc->lut_g[i] = green[i] >> 8;
- intel_crtc->lut_b[i] = blue[i] >> 8;
- }
-
- intel_crtc_load_lut(crtc);
-}
-
/* VESA 640x480x72Hz mode to set on the pipe */
static struct drm_display_mode load_detect_mode = {
DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
@@ -12071,7 +11937,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
static const struct drm_crtc_helper_funcs intel_helper_funcs = {
.mode_set_base_atomic = intel_pipe_set_base_atomic,
- .load_lut = intel_crtc_load_lut,
+ .load_lut = intel_color_load_gamma_lut,
.atomic_begin = intel_begin_crtc_commit,
.atomic_flush = intel_finish_crtc_commit,
.atomic_check = intel_crtc_atomic_check,
@@ -13684,7 +13550,7 @@ out:
#undef for_each_intel_crtc_masked
static const struct drm_crtc_funcs intel_crtc_funcs = {
- .gamma_set = intel_crtc_gamma_set,
+ .gamma_set = intel_color_legacy_gamma_set,
.set_config = drm_atomic_helper_set_config,
.destroy = intel_crtc_destroy,
.page_flip = intel_crtc_page_flip,
@@ -14289,7 +14155,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
struct intel_crtc_state *crtc_state = NULL;
struct drm_plane *primary = NULL;
struct drm_plane *cursor = NULL;
- int i, ret;
+ int ret;
intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
if (intel_crtc == NULL)
@@ -14325,13 +14191,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
if (ret)
goto fail;
- drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
- for (i = 0; i < 256; i++) {
- intel_crtc->lut_r[i] = i;
- intel_crtc->lut_g[i] = i;
- intel_crtc->lut_b[i] = i;
- }
-
/*
* On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
* is hooked to pipe B. Hence we want plane A feeding pipe B.
@@ -14356,6 +14215,8 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
+ intel_color_init(&intel_crtc->base);
+
WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
return;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bc97012..abc128a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1165,6 +1165,9 @@ void assert_pll(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state);
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
+void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
+#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
+#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state);
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
@@ -1611,4 +1614,11 @@ void intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state);
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
+/* intel_color.c */
+void intel_color_init(struct drm_crtc *crtc);
+void intel_color_set_csc(struct drm_crtc *crtc);
+void intel_color_load_gamma_lut(struct drm_crtc *crtc);
+void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
+ u16 *blue, uint32_t start, uint32_t size);
+
#endif /* __INTEL_DRV_H__ */
--
2.6.4
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] drm/i915: Extract out gamma table and CSC to their own file
2016-01-21 15:03 ` [PATCH 1/6] drm/i915: Extract out gamma table and CSC to their own file Lionel Landwerlin
@ 2016-01-21 15:24 ` Daniel Stone
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Stone @ 2016-01-21 15:24 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
Hi Lionel,
On 21 January 2016 at 15:03, Lionel Landwerlin
<lionel.g.landwerlin@intel.com> wrote:
> + /* Workaround : Do not read or write the pipe palette/gamma data while
> + * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> + */
> + if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
> + ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
> + GAMMA_MODE_MODE_SPLIT)) {
> + hsw_disable_ips(intel_crtc);
> + reenable_ips = true;
> + }
Obviously this one isn't your fault, but this should be inspecting
software state rather than hardware register state.
Cheers,
Daniel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] drm: introduce color correction properties
2016-01-21 15:03 [PATCH 0/6] Pipe level color management Lionel Landwerlin
2016-01-21 15:03 ` [PATCH 1/6] drm/i915: Extract out gamma table and CSC to their own file Lionel Landwerlin
@ 2016-01-21 15:03 ` Lionel Landwerlin
2016-01-21 19:20 ` Matt Roper
2016-01-21 15:03 ` [PATCH 3/6] drm/i915: enable CSC for pipe C Lionel Landwerlin
` (5 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Lionel Landwerlin @ 2016-01-21 15:03 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
Documentation/DocBook/gpu.tmpl | 48 +++++++++++++++++
drivers/gpu/drm/drm_atomic.c | 102 +++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/drm_atomic_helper.c | 10 ++++
drivers/gpu/drm/drm_crtc.c | 35 +++++++++++++
drivers/gpu/drm/drm_crtc_helper.c | 33 ++++++++++++
include/drm/drm_crtc.h | 43 ++++++++++++++-
include/drm/drm_crtc_helper.h | 3 ++
include/uapi/drm/drm_mode.h | 15 ++++++
8 files changed, 286 insertions(+), 3 deletions(-)
diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index 351e801..d2f682c 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -2092,6 +2092,54 @@ void intel_crt_init(struct drm_device *dev)
<td valign="top" >TBD</td>
</tr>
<tr>
+ <td valign="top" >“DEGAMMA_LUT”</td>
+ <td valign="top" >BLOB</td>
+ <td valign="top" ></td>
+ <td valign="top" >CRTC</td>
+ <td valign="top" >DRM property to set the degamma LUT mapping
+ pixel data from the framebuffer before it is given to the
+ transformation matrix. The data is an interpreted as an array
+ of struct drm_color_lut elements.</td>
+ </tr>
+ <tr>
+ <td valign="top" >“DEGAMMA_LUT_SIZE”</td>
+ <td valign="top" >IMMUTABLE</td>
+ <td valign="top" ></td>
+ <td valign="top" >CRTC</td>
+ <td valign="top" >DRM property to gives the size of the LUT to
+ be set on the DEGAMMA_LUT property (the size depends on the
+ underlying hardware).</td>
+ </tr>
+ <tr>
+ <td valign="top" >“CTM_MATRIX”</td>
+ <td valign="top" >BLOB</td>
+ <td valign="top" ></td>
+ <td valign="top" >CRTC</td>
+ <td valign="top" >DRM property to set the transformation
+ matrix apply to pixel data after the lookup through the
+ degamma LUT and before the lookup through the gamma LUT. The
+ data is an interpreted as a struct drm_color_ctm.</td>
+ </tr>
+ <tr>
+ <td valign="top" >“GAMMA_LUT”</td>
+ <td valign="top" >BLOB</td>
+ <td valign="top" ></td>
+ <td valign="top" >CRTC</td>
+ <td valign="top" >DRM property to set the gamma LUT mapping
+ pixel data after to the transformation matrix to data sent to
+ the connector. The data is an interpreted as an array
+ of struct drm_color_lut elements.</td>
+ </tr>
+ <tr>
+ <td valign="top" >“GAMMA_LUT_SIZE”</td>
+ <td valign="top" >IMMUTABLE</td>
+ <td valign="top" ></td>
+ <td valign="top" >CRTC</td>
+ <td valign="top" >DRM property to gives the size of the LUT to
+ be set on the GAMMA_LUT property (the size depends on the
+ underlying hardware).</td>
+ </tr>
+ <tr>
<td rowspan="20" valign="top" >i915</td>
<td rowspan="2" valign="top" >Generic</td>
<td valign="top" >"Broadcast RGB"</td>
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 3f74193..5287416 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -28,6 +28,7 @@
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
+#include <drm/drm_mode.h>
#include <drm/drm_plane_helper.h>
/**
@@ -388,6 +389,58 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc);
/**
+ * drm_atomic_replace_property_blob - replace a blob property
+ * @blob: a pointer to the member blob to be replaced
+ * @new_blob: the new blob to replace with
+ * @expected_size: the expected size of the new blob
+ * @replaced: whether the blob has been replaced
+ *
+ * RETURNS:
+ * Zero on success, error code on failure
+ */
+static int
+drm_atomic_replace_property_blob(struct drm_property_blob **blob,
+ struct drm_property_blob *new_blob,
+ size_t expected_size,
+ bool *replaced)
+{
+ struct drm_property_blob *old_blob = *blob;
+
+ if (old_blob == new_blob)
+ return 0;
+
+ if (new_blob != NULL && new_blob->length != expected_size)
+ return -EINVAL;
+
+ if (old_blob != NULL)
+ drm_property_unreference_blob(old_blob);
+ *blob = new_blob;
+ *replaced = true;
+
+ return 0;
+}
+
+static int
+drm_atomic_replace_property_blob_from_id(struct drm_crtc *crtc,
+ struct drm_property_blob **blob,
+ uint64_t blob_id,
+ size_t expected_size,
+ bool *replaced)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_property_blob *new_blob = NULL;
+
+ if (blob_id != 0) {
+ new_blob = drm_property_lookup_blob(dev, blob_id);
+ if (new_blob == NULL)
+ return -EINVAL;
+ }
+
+ return drm_atomic_replace_property_blob(blob, new_blob,
+ expected_size, replaced);
+}
+
+/**
* drm_atomic_crtc_set_property - set property on CRTC
* @crtc: the drm CRTC to set a property on
* @state: the state object to update with the new property value
@@ -419,8 +472,47 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
ret = drm_atomic_set_mode_prop_for_crtc(state, mode);
drm_property_unreference_blob(mode);
return ret;
- }
- else if (crtc->funcs->atomic_set_property)
+ } else if (property == config->degamma_lut_property) {
+ bool replaced = false;
+ uint64_t lut_size = 0;
+
+ ret = drm_object_property_get_value(&crtc->base,
+ config->degamma_lut_size_property,
+ &lut_size);
+ if (ret == 0)
+ ret = drm_atomic_replace_property_blob_from_id(crtc,
+ &state->degamma_lut,
+ val,
+ lut_size * sizeof(struct drm_color_lut),
+ &replaced);
+ state->color_mgmt_changed = replaced;
+ return ret;
+ } else if (property == config->ctm_matrix_property) {
+ bool replaced = false;
+
+ ret = drm_atomic_replace_property_blob_from_id(crtc,
+ &state->ctm_matrix,
+ val,
+ sizeof(struct drm_color_ctm),
+ &replaced);
+ state->color_mgmt_changed = replaced;
+ return ret;
+ } else if (property == config->gamma_lut_property) {
+ bool replaced = false;
+ uint64_t lut_size = 0;
+
+ ret = drm_object_property_get_value(&crtc->base,
+ config->gamma_lut_size_property,
+ &lut_size);
+ if (ret == 0)
+ ret = drm_atomic_replace_property_blob_from_id(crtc,
+ &state->gamma_lut,
+ val,
+ lut_size * sizeof(struct drm_color_lut),
+ &replaced);
+ state->color_mgmt_changed = replaced;
+ return ret;
+ } else if (crtc->funcs->atomic_set_property)
return crtc->funcs->atomic_set_property(crtc, state, property, val);
else
return -EINVAL;
@@ -456,6 +548,12 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = state->active;
else if (property == config->prop_mode_id)
*val = (state->mode_blob) ? state->mode_blob->base.id : 0;
+ else if (property == config->degamma_lut_property)
+ *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0;
+ else if (property == config->ctm_matrix_property)
+ *val = (state->ctm_matrix) ? state->ctm_matrix->base.id : 0;
+ else if (property == config->gamma_lut_property)
+ *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
else if (crtc->funcs->atomic_get_property)
return crtc->funcs->atomic_get_property(crtc, state, property, val);
else
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index f0c3984..e4a5755 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2454,10 +2454,17 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
if (state->mode_blob)
drm_property_reference_blob(state->mode_blob);
+ if (state->degamma_lut)
+ drm_property_reference_blob(state->degamma_lut);
+ if (state->ctm_matrix)
+ drm_property_reference_blob(state->ctm_matrix);
+ if (state->gamma_lut)
+ drm_property_reference_blob(state->gamma_lut);
state->mode_changed = false;
state->active_changed = false;
state->planes_changed = false;
state->connectors_changed = false;
+ state->color_mgmt_changed = false;
state->event = NULL;
}
EXPORT_SYMBOL(__drm_atomic_helper_crtc_duplicate_state);
@@ -2498,6 +2505,9 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
drm_property_unreference_blob(state->mode_blob);
+ drm_property_unreference_blob(state->degamma_lut);
+ drm_property_unreference_blob(state->ctm_matrix);
+ drm_property_unreference_blob(state->gamma_lut);
}
EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index d40bab2..6f96c04 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1542,6 +1542,41 @@ static int drm_mode_create_standard_properties(struct drm_device *dev)
return -ENOMEM;
dev->mode_config.prop_mode_id = prop;
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_BLOB,
+ "DEGAMMA_LUT", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.degamma_lut_property = prop;
+
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_IMMUTABLE,
+ "DEGAMMA_LUT_SIZE", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.degamma_lut_size_property = prop;
+
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_BLOB,
+ "CTM_MATRIX", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.ctm_matrix_property = prop;
+
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_BLOB,
+ "GAMMA_LUT", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.gamma_lut_property = prop;
+
+ prop = drm_property_create(dev,
+ DRM_MODE_PROP_IMMUTABLE,
+ "GAMMA_LUT_SIZE", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.gamma_lut_size_property = prop;
+
return 0;
}
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 5d4bc64..b9b1929 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -1064,3 +1064,36 @@ int drm_helper_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
return drm_plane_helper_commit(plane, plane_state, old_fb);
}
EXPORT_SYMBOL(drm_helper_crtc_mode_set_base);
+
+/**
+ * drm_helper_crtc_enable_color_mgmt - enable color management properties
+ * @crtc: DRM CRTC
+ * @degamma_lut_size: the size of the degamma lut (before CSC)
+ * @gamma_lut_size: the size of the gamma lut (after CSC)
+ *
+ * This function lets the driver enable the color correction properties on a
+ * CRTC. This includes 3 degamma, csc and gamma properties that userspace can
+ * set and 2 size properties to inform the userspace of the lut sizes.
+ */
+void drm_helper_crtc_enable_color_mgmt(struct drm_crtc *crtc,
+ int degamma_lut_size,
+ int gamma_lut_size)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_mode_config *config = &dev->mode_config;
+
+ drm_object_attach_property(&crtc->base,
+ config->degamma_lut_property, 0);
+ drm_object_attach_property(&crtc->base,
+ config->ctm_matrix_property, 0);
+ drm_object_attach_property(&crtc->base,
+ config->gamma_lut_property, 0);
+
+ drm_object_attach_property(&crtc->base,
+ config->degamma_lut_size_property,
+ degamma_lut_size);
+ drm_object_attach_property(&crtc->base,
+ config->gamma_lut_size_property,
+ gamma_lut_size);
+}
+EXPORT_SYMBOL(drm_helper_crtc_enable_color_mgmt);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index c65a212..967d646 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -305,12 +305,19 @@ struct drm_plane_helper_funcs;
* @mode_changed: crtc_state->mode or crtc_state->enable has been changed
* @active_changed: crtc_state->active has been toggled.
* @connectors_changed: connectors to this crtc have been updated
+ * @color_mgmt_changed: color management properties have changed (degamma or
+ * gamma LUT or CSC matrix)
* @plane_mask: bitmask of (1 << drm_plane_index(plane)) of attached planes
* @connector_mask: bitmask of (1 << drm_connector_index(connector)) of attached connectors
* @last_vblank_count: for helpers and drivers to capture the vblank of the
* update to ensure framebuffer cleanup isn't done too early
* @adjusted_mode: for use by helpers and drivers to compute adjusted mode timings
* @mode: current mode timings
+ * @degamma_lut: Lookup table for converting framebuffer pixel data
+ * before apply the conversion matrix
+ * @ctm_matrix: Transformation matrix
+ * @gamma_lut: Lookup table for converting pixel data after the
+ * conversion matrix
* @event: optional pointer to a DRM event to signal upon completion of the
* state update
* @state: backpointer to global drm_atomic_state
@@ -332,6 +339,7 @@ struct drm_crtc_state {
bool mode_changed : 1;
bool active_changed : 1;
bool connectors_changed : 1;
+ bool color_mgmt_changed : 1;
/* attached planes bitmask:
* WARNING: transitional helpers do not maintain plane_mask so
@@ -353,6 +361,11 @@ struct drm_crtc_state {
/* blob property to expose current mode to atomic userspace */
struct drm_property_blob *mode_blob;
+ /* blob property to expose color management to userspace */
+ struct drm_property_blob *degamma_lut;
+ struct drm_property_blob *ctm_matrix;
+ struct drm_property_blob *gamma_lut;
+
struct drm_pending_vblank_event *event;
struct drm_atomic_state *state;
@@ -755,7 +768,7 @@ struct drm_crtc {
int x, y;
const struct drm_crtc_funcs *funcs;
- /* CRTC gamma size for reporting to userspace */
+ /* Legacy FB CRTC gamma size for reporting to userspace */
uint32_t gamma_size;
uint16_t *gamma_store;
@@ -2023,6 +2036,15 @@ struct drm_mode_config_funcs {
* @property_blob_list: list of all the blob property objects
* @blob_lock: mutex for blob property allocation and management
* @*_property: core property tracking
+ * @degamma_lut_property: LUT used to convert the framebuffer's colors to linear
+ * gamma
+ * @degamma_lut_size_property: size of the degamma LUT as supported by the
+ * driver (read-only)
+ * @ctm_matrix_property: Matrix used to convert colors after the lookup in the
+ * degamma LUT
+ * @gamma_lut_property: LUT used to convert the colors, after the CSC matrix, to
+ * the gamma space of the connected screen (read-only)
+ * @gamma_lut_size_property: size of the gamma LUT as supported by the driver
* @preferred_depth: preferred RBG pixel depth, used by fb helpers
* @prefer_shadow: hint to userspace to prefer shadow-fb rendering
* @async_page_flip: does this device support async flips on the primary plane?
@@ -2124,6 +2146,13 @@ struct drm_mode_config {
struct drm_property *aspect_ratio_property;
struct drm_property *dirty_info_property;
+ /* Optional color correction properties */
+ struct drm_property *degamma_lut_property;
+ struct drm_property *degamma_lut_size_property;
+ struct drm_property *ctm_matrix_property;
+ struct drm_property *gamma_lut_property;
+ struct drm_property *gamma_lut_size_property;
+
/* properties for virtual machine layout */
struct drm_property *suggested_x_property;
struct drm_property *suggested_y_property;
@@ -2530,6 +2559,18 @@ static inline struct drm_property *drm_property_find(struct drm_device *dev,
return mo ? obj_to_property(mo) : NULL;
}
+/*
+ * Extract a degamma/gamma LUT value provided by user and round it to the
+ * precision supported by the hardware.
+ */
+static inline uint32_t drm_color_lut_get_value(uint32_t user_input,
+ uint32_t bit_precision)
+{
+ uint32_t val = (user_input << 1) + (1 << (16 - bit_precision));
+
+ return val >> (16 - bit_precision + 1);
+}
+
/* Plane list iterator for legacy (overlay only) planes. */
#define drm_for_each_legacy_plane(plane, dev) \
list_for_each_entry(plane, &(dev)->mode_config.plane_list, head) \
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
index 4b37afa..97fa894 100644
--- a/include/drm/drm_crtc_helper.h
+++ b/include/drm/drm_crtc_helper.h
@@ -48,6 +48,9 @@ extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode,
int x, int y,
struct drm_framebuffer *old_fb);
+extern void drm_helper_crtc_enable_color_mgmt(struct drm_crtc *crtc,
+ int degamma_lut_size,
+ int gamma_lut_size);
extern bool drm_helper_crtc_in_use(struct drm_crtc *crtc);
extern bool drm_helper_encoder_in_use(struct drm_encoder *encoder);
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 50adb46..c021743 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -487,6 +487,21 @@ struct drm_mode_crtc_lut {
__u64 blue;
};
+struct drm_color_ctm {
+ /* Conversion matrix in S31.32 format. */
+ __s64 matrix[9];
+};
+
+struct drm_color_lut {
+ /*
+ * Data is U0.16 fixed point format.
+ */
+ __u16 red;
+ __u16 green;
+ __u16 blue;
+ __u16 reserved;
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
--
2.6.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] drm: introduce color correction properties
2016-01-21 15:03 ` [PATCH 2/6] drm: introduce color correction properties Lionel Landwerlin
@ 2016-01-21 19:20 ` Matt Roper
2016-01-22 10:20 ` Lionel Landwerlin
0 siblings, 1 reply; 17+ messages in thread
From: Matt Roper @ 2016-01-21 19:20 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
On Thu, Jan 21, 2016 at 03:03:49PM +0000, Lionel Landwerlin wrote:
...
> diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
> index 351e801..d2f682c 100644
> --- a/Documentation/DocBook/gpu.tmpl
> +++ b/Documentation/DocBook/gpu.tmpl
> @@ -2092,6 +2092,54 @@ void intel_crt_init(struct drm_device *dev)
> <td valign="top" >TBD</td>
> </tr>
> <tr>
> + <td valign="top" >“DEGAMMA_LUT”</td>
> + <td valign="top" >BLOB</td>
> + <td valign="top" ></td>
> + <td valign="top" >CRTC</td>
> + <td valign="top" >DRM property to set the degamma LUT mapping
> + pixel data from the framebuffer before it is given to the
> + transformation matrix. The data is an interpreted as an array
> + of struct drm_color_lut elements.</td>
> + </tr>
> + <tr>
> + <td valign="top" >“DEGAMMA_LUT_SIZE”</td>
> + <td valign="top" >IMMUTABLE</td>
IMMUTABLE by itself isn't a property type, just a flag that you can
apply in addition to the type. You probably want "RANGE | IMMUTABLE"
here (and also on GAMMA_LUT_SIZE below).
...snip...
> + <td valign="top" >“GAMMA_LUT_SIZE”</td>
> + <td valign="top" >IMMUTABLE</td>
> + <td valign="top" ></td>
> + <td valign="top" >CRTC</td>
> + <td valign="top" >DRM property to gives the size of the LUT to
> + be set on the GAMMA_LUT property (the size depends on the
> + underlying hardware).</td>
> + </tr>
> + <tr>
> <td rowspan="20" valign="top" >i915</td>
> <td rowspan="2" valign="top" >Generic</td>
> <td valign="top" >"Broadcast RGB"</td>
...snip...
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index d40bab2..6f96c04 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -1542,6 +1542,41 @@ static int drm_mode_create_standard_properties(struct drm_device *dev)
> return -ENOMEM;
> dev->mode_config.prop_mode_id = prop;
>
> + prop = drm_property_create(dev,
> + DRM_MODE_PROP_BLOB,
> + "DEGAMMA_LUT", 0);
> + if (!prop)
> + return -ENOMEM;
> + dev->mode_config.degamma_lut_property = prop;
> +
> + prop = drm_property_create(dev,
> + DRM_MODE_PROP_IMMUTABLE,
As noted above, you still need to OR in a valid property type (in this
case DRM_MODE_PROP_RANGE); otherwise you'll trip over the the check in
drm_property_type_valid() that gets called at the end of
drm_property_create().
Matt
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/6] drm: introduce color correction properties
2016-01-21 19:20 ` Matt Roper
@ 2016-01-22 10:20 ` Lionel Landwerlin
0 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2016-01-22 10:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On 21/01/16 19:20, Matt Roper wrote:
> On Thu, Jan 21, 2016 at 03:03:49PM +0000, Lionel Landwerlin wrote:
> ...
>> diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
>> index 351e801..d2f682c 100644
>> --- a/Documentation/DocBook/gpu.tmpl
>> +++ b/Documentation/DocBook/gpu.tmpl
>> @@ -2092,6 +2092,54 @@ void intel_crt_init(struct drm_device *dev)
>> <td valign="top" >TBD</td>
>> </tr>
>> <tr>
>> + <td valign="top" >“DEGAMMA_LUT”</td>
>> + <td valign="top" >BLOB</td>
>> + <td valign="top" ></td>
>> + <td valign="top" >CRTC</td>
>> + <td valign="top" >DRM property to set the degamma LUT mapping
>> + pixel data from the framebuffer before it is given to the
>> + transformation matrix. The data is an interpreted as an array
>> + of struct drm_color_lut elements.</td>
>> + </tr>
>> + <tr>
>> + <td valign="top" >“DEGAMMA_LUT_SIZE”</td>
>> + <td valign="top" >IMMUTABLE</td>
> IMMUTABLE by itself isn't a property type, just a flag that you can
> apply in addition to the type. You probably want "RANGE | IMMUTABLE"
> here (and also on GAMMA_LUT_SIZE below).
>
> ...snip...
>> + <td valign="top" >“GAMMA_LUT_SIZE”</td>
>> + <td valign="top" >IMMUTABLE</td>
>> + <td valign="top" ></td>
>> + <td valign="top" >CRTC</td>
>> + <td valign="top" >DRM property to gives the size of the LUT to
>> + be set on the GAMMA_LUT property (the size depends on the
>> + underlying hardware).</td>
>> + </tr>
>> + <tr>
>> <td rowspan="20" valign="top" >i915</td>
>> <td rowspan="2" valign="top" >Generic</td>
>> <td valign="top" >"Broadcast RGB"</td>
> ...snip...
>> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
>> index d40bab2..6f96c04 100644
>> --- a/drivers/gpu/drm/drm_crtc.c
>> +++ b/drivers/gpu/drm/drm_crtc.c
>> @@ -1542,6 +1542,41 @@ static int drm_mode_create_standard_properties(struct drm_device *dev)
>> return -ENOMEM;
>> dev->mode_config.prop_mode_id = prop;
>>
>> + prop = drm_property_create(dev,
>> + DRM_MODE_PROP_BLOB,
>> + "DEGAMMA_LUT", 0);
>> + if (!prop)
>> + return -ENOMEM;
>> + dev->mode_config.degamma_lut_property = prop;
>> +
>> + prop = drm_property_create(dev,
>> + DRM_MODE_PROP_IMMUTABLE,
> As noted above, you still need to OR in a valid property type (in this
> case DRM_MODE_PROP_RANGE); otherwise you'll trip over the the check in
> drm_property_type_valid() that gets called at the end of
> drm_property_create().
>
>
> Matt
>
Thanks Matt,
Just realized that yesterday while talking to Damien.
Will fix in v2.
-
Lionel
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/6] drm/i915: enable CSC for pipe C
2016-01-21 15:03 [PATCH 0/6] Pipe level color management Lionel Landwerlin
2016-01-21 15:03 ` [PATCH 1/6] drm/i915: Extract out gamma table and CSC to their own file Lionel Landwerlin
2016-01-21 15:03 ` [PATCH 2/6] drm: introduce color correction properties Lionel Landwerlin
@ 2016-01-21 15:03 ` Lionel Landwerlin
2016-01-21 15:03 ` [PATCH 4/6] drm/i915: enable legacy palette " Lionel Landwerlin
` (4 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2016-01-21 15:03 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++++++++++++++++++++-------------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a98889..63c4283 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7608,19 +7608,33 @@ enum skl_disp_power_wells {
#define _PIPE_B_CSC_POSTOFF_ME 0x49144
#define _PIPE_B_CSC_POSTOFF_LO 0x49148
-#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
-#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
-#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
-#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
-#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
-#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
-#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
-#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
-#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
-#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
-#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
-#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
-#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
+#define _PIPE_C_CSC_COEFF_RY_GY 0x49210
+#define _PIPE_C_CSC_COEFF_BY 0x49214
+#define _PIPE_C_CSC_COEFF_RU_GU 0x49218
+#define _PIPE_C_CSC_COEFF_BU 0x4921c
+#define _PIPE_C_CSC_COEFF_RV_GV 0x49220
+#define _PIPE_C_CSC_COEFF_BV 0x49224
+#define _PIPE_C_CSC_MODE 0x49228
+#define _PIPE_C_CSC_PREOFF_HI 0x49230
+#define _PIPE_C_CSC_PREOFF_ME 0x49234
+#define _PIPE_C_CSC_PREOFF_LO 0x49238
+#define _PIPE_C_CSC_POSTOFF_HI 0x49240
+#define _PIPE_C_CSC_POSTOFF_ME 0x49244
+#define _PIPE_C_CSC_POSTOFF_LO 0x49248
+
+#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY, _PIPE_C_CSC_COEFF_RY_GY)
+#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY, _PIPE_C_CSC_COEFF_BY)
+#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU, _PIPE_C_CSC_COEFF_RU_GU)
+#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU, _PIPE_C_CSC_COEFF_BU)
+#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV, _PIPE_C_CSC_COEFF_RV_GV)
+#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV, _PIPE_C_CSC_COEFF_BV)
+#define PIPE_CSC_MODE(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE, _PIPE_C_CSC_MODE)
+#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI, _PIPE_C_CSC_PREOFF_HI)
+#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME, _PIPE_C_CSC_PREOFF_ME)
+#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO, _PIPE_C_CSC_PREOFF_LO)
+#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI, _PIPE_C_CSC_POSTOFF_HI)
+#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME, _PIPE_C_CSC_POSTOFF_ME)
+#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO, _PIPE_C_CSC_POSTOFF_LO)
/* MIPI DSI registers */
--
2.6.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 4/6] drm/i915: enable legacy palette for pipe C
2016-01-21 15:03 [PATCH 0/6] Pipe level color management Lionel Landwerlin
` (2 preceding siblings ...)
2016-01-21 15:03 ` [PATCH 3/6] drm/i915: enable CSC for pipe C Lionel Landwerlin
@ 2016-01-21 15:03 ` Lionel Landwerlin
2016-01-21 15:03 ` [PATCH 5/6] drm/i915: Implement color management on bdw/skl/bxt/kbl Lionel Landwerlin
` (3 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2016-01-21 15:03 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 63c4283..46143f8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5753,7 +5753,8 @@ enum skl_disp_power_wells {
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
-#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
+#define _LGC_PALETTE_C 0x4b000
+#define LGC_PALETTE(pipe, i) _MMIO(_PIPE3(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B, _LGC_PALETTE_C) + (i) * 4)
#define _GAMMA_MODE_A 0x4a480
#define _GAMMA_MODE_B 0x4ac80
--
2.6.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5/6] drm/i915: Implement color management on bdw/skl/bxt/kbl
2016-01-21 15:03 [PATCH 0/6] Pipe level color management Lionel Landwerlin
` (3 preceding siblings ...)
2016-01-21 15:03 ` [PATCH 4/6] drm/i915: enable legacy palette " Lionel Landwerlin
@ 2016-01-21 15:03 ` Lionel Landwerlin
2016-01-21 15:03 ` [PATCH 6/6] drm/i915: Implement color management on chv Lionel Landwerlin
` (2 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2016-01-21 15:03 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
Documentation/DocBook/gpu.tmpl | 12 +-
drivers/gpu/drm/i915/i915_drv.c | 24 ++-
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/i915_reg.h | 22 +++
drivers/gpu/drm/i915/intel_color.c | 345 ++++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_display.c | 22 ++-
drivers/gpu/drm/i915/intel_drv.h | 4 +-
7 files changed, 375 insertions(+), 63 deletions(-)
diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index d2f682c..e436376 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -2068,7 +2068,7 @@ void intel_crt_init(struct drm_device *dev)
<td valign="top" >property to suggest an Y offset for a connector</td>
</tr>
<tr>
- <td rowspan="3" valign="top" >Optional</td>
+ <td rowspan="8" valign="top" >Optional</td>
<td valign="top" >“scaling mode”</td>
<td valign="top" >ENUM</td>
<td valign="top" >{ "None", "Full", "Center", "Full aspect" }</td>
@@ -2094,7 +2094,7 @@ void intel_crt_init(struct drm_device *dev)
<tr>
<td valign="top" >“DEGAMMA_LUT”</td>
<td valign="top" >BLOB</td>
- <td valign="top" ></td>
+ <td valign="top" >0</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to set the degamma LUT mapping
pixel data from the framebuffer before it is given to the
@@ -2104,7 +2104,7 @@ void intel_crt_init(struct drm_device *dev)
<tr>
<td valign="top" >“DEGAMMA_LUT_SIZE”</td>
<td valign="top" >IMMUTABLE</td>
- <td valign="top" ></td>
+ <td valign="top" >0</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to gives the size of the LUT to
be set on the DEGAMMA_LUT property (the size depends on the
@@ -2113,7 +2113,7 @@ void intel_crt_init(struct drm_device *dev)
<tr>
<td valign="top" >“CTM_MATRIX”</td>
<td valign="top" >BLOB</td>
- <td valign="top" ></td>
+ <td valign="top" >0</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to set the transformation
matrix apply to pixel data after the lookup through the
@@ -2123,7 +2123,7 @@ void intel_crt_init(struct drm_device *dev)
<tr>
<td valign="top" >“GAMMA_LUT”</td>
<td valign="top" >BLOB</td>
- <td valign="top" ></td>
+ <td valign="top" >0</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to set the gamma LUT mapping
pixel data after to the transformation matrix to data sent to
@@ -2133,7 +2133,7 @@ void intel_crt_init(struct drm_device *dev)
<tr>
<td valign="top" >“GAMMA_LUT_SIZE”</td>
<td valign="top" >IMMUTABLE</td>
- <td valign="top" ></td>
+ <td valign="top" >0</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to gives the size of the LUT to
be set on the GAMMA_LUT property (the size depends on the
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 706b8ea..1978fe5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -63,6 +63,9 @@ static struct drm_driver driver;
#define IVB_CURSOR_OFFSETS \
.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
+#define BDW_COLORS \
+ .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+
static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
@@ -285,24 +288,28 @@ static const struct intel_device_info intel_haswell_m_info = {
.is_mobile = 1,
};
+#define BDW_FEATURES \
+ HSW_FEATURES, \
+ BDW_COLORS
+
static const struct intel_device_info intel_broadwell_d_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.gen = 8,
};
static const struct intel_device_info intel_broadwell_m_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.gen = 8, .is_mobile = 1,
};
static const struct intel_device_info intel_broadwell_gt3d_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.gen = 8,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
static const struct intel_device_info intel_broadwell_gt3m_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.gen = 8, .is_mobile = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
@@ -318,13 +325,13 @@ static const struct intel_device_info intel_cherryview_info = {
};
static const struct intel_device_info intel_skylake_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
};
static const struct intel_device_info intel_skylake_gt3_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
@@ -342,17 +349,18 @@ static const struct intel_device_info intel_broxton_info = {
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
+ BDW_COLORS,
};
static const struct intel_device_info intel_kabylake_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.is_preliminary = 1,
.is_kabylake = 1,
.gen = 9,
};
static const struct intel_device_info intel_kabylake_gt3_info = {
- HSW_FEATURES,
+ BDW_FEATURES,
.is_preliminary = 1,
.is_kabylake = 1,
.gen = 9,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 204661f..4a38b15 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -659,6 +659,10 @@ struct drm_i915_display_funcs {
/* render clock increase/decrease */
/* display clock increase/decrease */
/* pll clock increase/decrease */
+
+ void (*load_degamma_lut)(struct drm_crtc *crtc);
+ void (*load_csc_matrix)(struct drm_crtc *crtc);
+ void (*load_gamma_lut)(struct drm_crtc *crtc);
};
enum forcewake_domain_id {
@@ -806,6 +810,11 @@ struct intel_device_info {
u8 has_slice_pg:1;
u8 has_subslice_pg:1;
u8 has_eu_pg:1;
+
+ struct color_luts {
+ u16 degamma_lut_size;
+ u16 gamma_lut_size;
+ } color;
};
#undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 46143f8..ccbcf63 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7637,6 +7637,28 @@ enum skl_disp_power_wells {
#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME, _PIPE_C_CSC_POSTOFF_ME)
#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE3(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO, _PIPE_C_CSC_POSTOFF_LO)
+/* pipe degamma/gamma LUTs on IVB+ */
+#define _PAL_PREC_INDEX_A 0x4A400
+#define _PAL_PREC_INDEX_B 0x4AC00
+#define _PAL_PREC_INDEX_C 0x4B400
+#define PAL_PREC_10_12_BIT (0 << 31)
+#define PAL_PREC_SPLIT_MODE (1 << 31)
+#define PAL_PREC_AUTO_INCREMENT (1 << 15)
+#define _PAL_PREC_DATA_A 0x4A404
+#define _PAL_PREC_DATA_B 0x4AC04
+#define _PAL_PREC_DATA_C 0x4B404
+#define _PAL_PREC_GC_MAX_A 0x4A410
+#define _PAL_PREC_GC_MAX_B 0x4AC10
+#define _PAL_PREC_GC_MAX_C 0x4B410
+#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
+#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
+#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
+
+#define PREC_PAL_INDEX(pipe) _MMIO_PIPE3(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B, _PAL_PREC_INDEX_C)
+#define PREC_PAL_DATA(pipe) _MMIO_PIPE3(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B, _PAL_PREC_DATA_C)
+#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE3(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B, _PAL_PREC_GC_MAX_C) + (i) * 4)
+#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE3(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B, _PAL_PREC_EXT_GC_MAX_C) + (i) * 4)
+
/* MIPI DSI registers */
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 39ca215..bbf84cc 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -24,44 +24,169 @@
#include "intel_drv.h"
+#define CTM_COEFF_SIGN (1ULL << 63)
+
+#define CTM_COEFF_1_0 (1ULL << 32)
+#define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
+#define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
+#define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
+#define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
+#define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
+
+#define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
+
+#define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
+#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
+
+/*
+ * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
+ * format). This macro takes the coefficient we want transformed and the
+ * number of fractional bits.
+ *
+ * We only have a 9 bits precision window which slides depending on the value
+ * of the CTM coefficient and we write the value from bit 3. We also round the
+ * value.
+ */
+#define I9XX_CSC_COEFF_FP(coeff, fbits) \
+ (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
+
+#define I9XX_CSC_COEFF_LIMITED_RANGE \
+ I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
+#define I9XX_CSC_COEFF_1_0 \
+ ((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
+
+/*
+ * When using limited range, multiply the matrix given by userspace by
+ * the matrix that we would use for the limited range. We do the
+ * multiplication in U2.30 format.
+ */
+static void ctm_matrix_mult_by_limited(uint64_t *result,
+ int64_t *input)
+{
+ int i, j;
+ uint64_t limited_coeffs[9] = { CTM_COEFF_LIMITED_RANGE, 0, 0,
+ 0, CTM_COEFF_LIMITED_RANGE, 0,
+ 0, 0, CTM_COEFF_LIMITED_RANGE };
+
+ for (i = 0; i < ARRAY_SIZE(limited_coeffs); i++) {
+ int column = i % 3, row = i / 3;
+ int negative = 0;
+
+ input[i] = 0;
+ for (j = 0; j < 3; j++) {
+ int64_t user_coeff = input[j * 3 + column];
+ uint64_t limited_coeff =
+ limited_coeffs[row * 3 + j] >> 2;
+ uint64_t abs_coeff =
+ clamp_val(CTM_COEFF_ABS(user_coeff),
+ 0,
+ CTM_COEFF_4_0 - 1) >> 2;
+
+ if (CTM_COEFF_NEGATIVE(user_coeff))
+ negative = !negative;
+ result[i] += limited_coeff * abs_coeff;
+ }
+
+ result[i] >>= 27;
+ if (negative)
+ result[i] |= CTM_COEFF_SIGN;
+ }
+}
+
/*
* Set up the pipe CSC unit.
*
- * Currently only full range RGB to limited range RGB conversion
- * is supported, but eventually this should handle various
- * RGB<->YCbCr scenarios as well.
+ * Currently only full range RGB to limited range RGB conversion is supported,
+ * but eventually this should handle various RGB<->YCbCr scenarios as well.
*/
static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
+ struct drm_crtc_state *crtc_state = crtc->state;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
- uint16_t coeff = 0x7800; /* 1.0 */
+ int i, pipe = intel_crtc->pipe;
+ uint16_t coeffs[9] = { 0, };
- /*
- * TODO: Check what kind of values actually come out of the pipe
- * with these coeff/postoff values and adjust to get the best
- * accuracy. Perhaps we even need to take the bpc value into
- * consideration.
- */
+ if (crtc_state->ctm_matrix) {
+ struct drm_color_ctm *ctm =
+ (struct drm_color_ctm *)crtc_state->ctm_matrix->data;
+ uint64_t input[9] = { 0, };
+
+ if (intel_crtc->config->limited_color_range)
+ ctm_matrix_mult_by_limited(input, ctm->matrix);
+ else {
+ for (i = 0; i < ARRAY_SIZE(input); i++)
+ input[i] = ctm->matrix[i];
+ }
- if (intel_crtc->config->limited_color_range)
- coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
+
+ /*
+ * Convert fixed point S31.32 input to format supported by the
+ * hardware.
+ */
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+ uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];
+
+ /*
+ * Clamp input value to min/max supported by
+ * hardware.
+ */
+ abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+ /* sign bit */
+ if (CTM_COEFF_NEGATIVE(input[i]))
+ coeffs[i] |= 1 << 15;
+
+ if (abs_coeff < CTM_COEFF_0_125)
+ coeffs[i] |= (3 << 12) |
+ I9XX_CSC_COEFF_FP(abs_coeff, 12);
+ else if (abs_coeff < CTM_COEFF_0_25)
+ coeffs[i] |= (2 << 12) |
+ I9XX_CSC_COEFF_FP(abs_coeff, 11);
+ else if (abs_coeff < CTM_COEFF_0_5)
+ coeffs[i] |= (1 << 12) |
+ I9XX_CSC_COEFF_FP(abs_coeff, 10);
+ else if (abs_coeff < CTM_COEFF_1_0)
+ coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9);
+ else if (abs_coeff < CTM_COEFF_2_0)
+ coeffs[i] |= (7 << 12) |
+ I9XX_CSC_COEFF_FP(abs_coeff, 8);
+ else
+ coeffs[i] |= (6 << 12) |
+ I9XX_CSC_COEFF_FP(abs_coeff, 7);
+ }
+ } else {
+ /*
+ * Load an identify matrix if no coefficients are provided.
+ *
+ * TODO: Check what kind of values actually come out of the
+ * pipe with these coeff/postoff values and adjust to get the
+ * best accuracy. Perhaps we even need to take the bpc value
+ * into consideration.
+ */
+ for (i = 0; i < 3; i++) {
+ if (intel_crtc->config->limited_color_range)
+ coeffs[i * 3 + i] =
+ I9XX_CSC_COEFF_LIMITED_RANGE;
+ else
+ coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0;
+ }
+ }
/*
* GY/GU and RY/RU should be the other way around according
* to BSpec, but reality doesn't agree. Just set them up in
* a way that results in the correct picture.
*/
- I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
- I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
+ I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
+ I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
- I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
- I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
+ I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
+ I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
- I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
- I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
+ I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
+ I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
@@ -88,21 +213,127 @@ static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
}
}
-void intel_color_set_csc(struct drm_crtc *crtc)
+/** Loads the legacy palette/gamma unit for the CRTC with the prepared
+ * values.
+ */
+static void i9xx_load_legacy_gamma_lut(struct drm_crtc *crtc)
{
- i9xx_load_csc_matrix(crtc);
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ int i;
+
+ for (i = 0; i < 256; i++) {
+ uint32_t word = (intel_crtc->lut_r[i] << 16) |
+ (intel_crtc->lut_g[i] << 8) |
+ intel_crtc->lut_b[i];
+ if (HAS_GMCH_DISPLAY(dev))
+ I915_WRITE(PALETTE(pipe, i), word);
+ else
+ I915_WRITE(LGC_PALETTE(pipe, i), word);
+ }
+
+ I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
}
-/** Loads the palette/gamma unit for the CRTC with the prepared values on */
-static void i9xx_load_legacy_gamma_lut(struct drm_crtc *crtc)
+static void broadwell_load_degamma_lut(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc_state *state = crtc->state;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
+
+ I915_WRITE(PREC_PAL_INDEX(pipe),
+ PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
+
+ if (state->degamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *) state->degamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ uint32_t word =
+ drm_color_lut_get_value(lut[i].red, 10) << 20 |
+ drm_color_lut_get_value(lut[i].green, 10) << 10 |
+ drm_color_lut_get_value(lut[i].blue, 10);
+
+ I915_WRITE(PREC_PAL_DATA(pipe), word);
+ }
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
+
+ I915_WRITE(PREC_PAL_DATA(pipe),
+ (v << 20) | (v << 10) | v);
+ }
+ }
+
+ I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
+ POSTING_READ(GAMMA_MODE(pipe));
+
+ /* Reset the index, otherwise it prevents the legacy palette to be
+ * written properly.
+ */
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+}
+
+static void broadwell_load_gamma_lut(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc_state *state = crtc->state;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ uint32_t i, lut_offset = INTEL_INFO(dev)->color.degamma_lut_size,
+ lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
+
+
+ I915_WRITE(PREC_PAL_INDEX(pipe),
+ PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT | lut_offset);
+
+ if (state->gamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *) state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ uint32_t word =
+ (drm_color_lut_get_value(lut[i].red, 10) << 20) |
+ (drm_color_lut_get_value(lut[i].green, 10) << 10) |
+ drm_color_lut_get_value(lut[i].blue, 10);
+
+ I915_WRITE(PREC_PAL_DATA(pipe), word);
+ }
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
+
+ I915_WRITE(PREC_PAL_DATA(pipe),
+ (v << 20) | (v << 10) | v);
+ }
+ }
+
+ I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
+ POSTING_READ(GAMMA_MODE(pipe));
+
+ /* Reset the index, otherwise it prevents the legacy palette to be
+ * written properly.
+ */
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+}
+
+static void intel_color_load_luts_internal(struct drm_crtc *crtc,
+ bool legacy)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
- int i;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
bool reenable_ips = false;
+ /* The clocks have to be on to load the palette. */
+ if (!crtc->state->active)
+ return;
+
if (HAS_GMCH_DISPLAY(dev)) {
if (intel_crtc->config->has_dsi_encoder)
assert_dsi_pll_enabled(dev_priv);
@@ -120,36 +351,27 @@ static void i9xx_load_legacy_gamma_lut(struct drm_crtc *crtc)
reenable_ips = true;
}
- for (i = 0; i < 256; i++) {
- uint32_t word = (intel_crtc->lut_r[i] << 16) |
- (intel_crtc->lut_g[i] << 8) |
- intel_crtc->lut_b[i];
- if (HAS_GMCH_DISPLAY(dev))
- I915_WRITE(PALETTE(pipe, i), word);
- else
- I915_WRITE(LGC_PALETTE(pipe, i), word);
+ if (legacy)
+ i9xx_load_legacy_gamma_lut(crtc);
+ else {
+ dev_priv->display.load_degamma_lut(crtc);
+ dev_priv->display.load_gamma_lut(crtc);
}
- I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
-
if (reenable_ips)
hsw_enable_ips(intel_crtc);
}
-void intel_color_load_gamma_lut(struct drm_crtc *crtc)
+void intel_color_legacy_load_lut(struct drm_crtc *crtc)
{
- /* The clocks have to be on to load the palette. */
- if (!crtc->state->active)
- return;
-
- i9xx_load_legacy_gamma_lut(crtc);
+ intel_color_load_luts_internal(crtc, true);
}
void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
u16 *blue, uint32_t start, uint32_t size)
{
- int end = (start + size > 256) ? 256 : start + size, i;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int end = (start + size > 256) ? 256 : start + size, i;
for (i = start; i < end; i++) {
intel_crtc->lut_r[i] = red[i] >> 8;
@@ -157,11 +379,29 @@ void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
intel_crtc->lut_b[i] = blue[i] >> 8;
}
- intel_color_load_gamma_lut(crtc);
+ intel_color_load_luts_internal(crtc, true);
+}
+
+void intel_color_load_luts(struct drm_crtc *crtc)
+{
+ intel_color_load_luts_internal(crtc,
+ !crtc->state->degamma_lut &&
+ !crtc->state->gamma_lut);
+}
+
+void intel_color_set_csc(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (dev_priv->display.load_csc_matrix)
+ dev_priv->display.load_csc_matrix(crtc);
}
void intel_color_init(struct drm_crtc *crtc)
{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int i;
@@ -171,4 +411,23 @@ void intel_color_init(struct drm_crtc *crtc)
intel_crtc->lut_g[i] = i;
intel_crtc->lut_b[i] = i;
}
+
+ if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
+ IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.load_degamma_lut = broadwell_load_degamma_lut;
+ dev_priv->display.load_gamma_lut = broadwell_load_gamma_lut;
+ dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
+ } else {
+ dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
+ }
+
+ if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
+ INTEL_INFO(dev)->color.gamma_lut_size != 0) {
+ WARN_ON(!dev_priv->display.load_degamma_lut ||
+ !dev_priv->display.load_gamma_lut ||
+ !dev_priv->display.load_csc_matrix);
+ drm_helper_crtc_enable_color_mgmt(crtc,
+ INTEL_INFO(dev)->color.degamma_lut_size,
+ INTEL_INFO(dev)->color.gamma_lut_size);
+ }
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a0ebc85..eaa8e5c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4858,7 +4858,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_gamma_lut(crtc);
+ intel_color_load_luts(crtc);
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
@@ -4955,7 +4955,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_gamma_lut(crtc);
+ intel_color_load_luts(crtc);
intel_ddi_set_pipe_settings(crtc);
if (!intel_crtc->config->has_dsi_encoder)
@@ -6176,7 +6176,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
i9xx_pfit_enable(intel_crtc);
- intel_color_load_gamma_lut(crtc);
+ intel_color_load_luts(crtc);
intel_enable_pipe(intel_crtc);
@@ -6229,7 +6229,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
i9xx_pfit_enable(intel_crtc);
- intel_color_load_gamma_lut(crtc);
+ intel_color_load_luts(crtc);
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
@@ -11937,7 +11937,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
static const struct drm_crtc_helper_funcs intel_helper_funcs = {
.mode_set_base_atomic = intel_pipe_set_base_atomic,
- .load_lut = intel_color_load_gamma_lut,
+ .load_lut = intel_color_legacy_load_lut,
.atomic_begin = intel_begin_crtc_commit,
.atomic_flush = intel_finish_crtc_commit,
.atomic_check = intel_crtc_atomic_check,
@@ -13464,6 +13464,17 @@ static int intel_atomic_commit(struct drm_device *dev,
hw_check = true;
}
+ if (!modeset &&
+ crtc->state->active &&
+ crtc->state->color_mgmt_changed) {
+ /* Only update color management when not doing
+ * a modeset as this will be done by
+ * crtc_enable already.
+ */
+ intel_color_set_csc(crtc);
+ intel_color_load_luts(crtc);
+ }
+
if (!modeset)
intel_pre_plane_update(intel_crtc);
@@ -13552,6 +13563,7 @@ out:
static const struct drm_crtc_funcs intel_crtc_funcs = {
.gamma_set = intel_color_legacy_gamma_set,
.set_config = drm_atomic_helper_set_config,
+ .set_property = drm_atomic_helper_crtc_set_property,
.destroy = intel_crtc_destroy,
.page_flip = intel_crtc_page_flip,
.atomic_duplicate_state = intel_crtc_duplicate_state,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index abc128a..ff4e643 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1616,9 +1616,11 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
/* intel_color.c */
void intel_color_init(struct drm_crtc *crtc);
+void intel_color_update(struct drm_crtc *crtc);
void intel_color_set_csc(struct drm_crtc *crtc);
-void intel_color_load_gamma_lut(struct drm_crtc *crtc);
+void intel_color_load_luts(struct drm_crtc *crtc);
void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
u16 *blue, uint32_t start, uint32_t size);
+void intel_color_legacy_load_lut(struct drm_crtc *crtc);
#endif /* __INTEL_DRV_H__ */
--
2.6.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 6/6] drm/i915: Implement color management on chv
2016-01-21 15:03 [PATCH 0/6] Pipe level color management Lionel Landwerlin
` (4 preceding siblings ...)
2016-01-21 15:03 ` [PATCH 5/6] drm/i915: Implement color management on bdw/skl/bxt/kbl Lionel Landwerlin
@ 2016-01-21 15:03 ` Lionel Landwerlin
2016-01-21 15:42 ` ✗ Fi.CI.BAT: warning for Pipe level color management Patchwork
2016-01-22 15:04 ` [PATCH 0/6] " Daniel Stone
7 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2016-01-21 15:03 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++++
drivers/gpu/drm/i915/intel_color.c | 139 ++++++++++++++++++++++++++++++++++++-
3 files changed, 180 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1978fe5..1e7a567 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -65,6 +65,8 @@ static struct drm_driver driver;
#define BDW_COLORS \
.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+#define CHV_COLORS \
+ .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
@@ -322,6 +324,7 @@ static const struct intel_device_info intel_cherryview_info = {
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
+ CHV_COLORS,
};
static const struct intel_device_info intel_skylake_info = {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ccbcf63..1b81b44 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7659,6 +7659,46 @@ enum skl_disp_power_wells {
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE3(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B, _PAL_PREC_GC_MAX_C) + (i) * 4)
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE3(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B, _PAL_PREC_EXT_GC_MAX_C) + (i) * 4)
+/* pipe CSC & degamma/gamma LUTs on CHV */
+#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
+#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
+#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
+#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
+#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
+#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
+#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
+#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
+#define CGM_PIPE_MODE_GAMMA (1 << 2)
+#define CGM_PIPE_MODE_CSC (1 << 1)
+#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
+
+#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
+#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
+#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
+#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
+#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
+#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
+#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
+#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
+
+#define _CGM_PIPE_C_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x6B900)
+#define _CGM_PIPE_C_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x6B904)
+#define _CGM_PIPE_C_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x6B908)
+#define _CGM_PIPE_C_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6B90C)
+#define _CGM_PIPE_C_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x6B910)
+#define _CGM_PIPE_C_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000)
+#define _CGM_PIPE_C_GAMMA (VLV_DISPLAY_BASE + 0x6B000)
+#define _CGM_PIPE_C_MODE (VLV_DISPLAY_BASE + 0x6BA00)
+
+#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01, _CGM_PIPE_C_CSC_COEFF01)
+#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23, _CGM_PIPE_C_CSC_COEFF23)
+#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45, _CGM_PIPE_C_CSC_COEFF45)
+#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67, _CGM_PIPE_C_CSC_COEFF67)
+#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8, _CGM_PIPE_C_CSC_COEFF8)
+#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE3(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA, _CGM_PIPE_C_DEGAMMA) + (i) * 4 + (w) * 4)
+#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE3(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA, _CGM_PIPE_C_GAMMA) + (i) * 4 + (w) * 4)
+#define CGM_PIPE_MODE(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE, _CGM_PIPE_C_MODE)
+
/* MIPI DSI registers */
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index bbf84cc..baa7fe9 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -213,6 +213,54 @@ static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
}
}
+/*
+ * Set up the pipe CSC unit on CherryView.
+ */
+static void cherryview_load_csc_matrix(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_crtc_state *crtc_state = crtc->state;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+
+
+ if (crtc_state->ctm_matrix) {
+ struct drm_color_ctm *ctm =
+ (struct drm_color_ctm *)crtc_state->ctm_matrix->data;
+ uint16_t coeffs[9] = { 0, };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+ uint64_t abs_coeff =
+ ((1ULL << 63) - 1) & ctm->matrix[i];
+
+ abs_coeff = clamp_val(abs_coeff, 0, (1 << 15) - 1);
+
+ /* Write coefficients in S3.12 format. */
+ if (ctm->matrix[i] & (1ULL << 63))
+ coeffs[i] = 1 << 15;
+ coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
+ coeffs[i] |= (((abs_coeff >> 19) + 1) >> 1) & 0xfff;
+ }
+
+ I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
+ coeffs[1] << 16 | coeffs[0]);
+ I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
+ coeffs[3] << 16 | coeffs[2]);
+ I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
+ coeffs[5] << 16 | coeffs[4]);
+ I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
+ coeffs[7] << 16 | coeffs[6]);
+ I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
+ }
+
+ I915_WRITE(CGM_PIPE_MODE(pipe),
+ (crtc_state->ctm_matrix ? CGM_PIPE_MODE_CSC : 0) |
+ (crtc_state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
+ (crtc_state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
+}
+
/** Loads the legacy palette/gamma unit for the CRTC with the prepared
* values.
*/
@@ -278,6 +326,47 @@ static void broadwell_load_degamma_lut(struct drm_crtc *crtc)
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
+static void cherryview_load_degamma_lut(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc_state *state = crtc->state;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+ if (state->degamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *) state->degamma_lut->data;
+ uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
+ uint32_t word0, word1;
+
+ for (i = 0; i < lut_size; i++) {
+ /* Write LUT in U0.14 format. */
+ word0 =
+ (drm_color_lut_get_value(lut[i].green, 14) << 16) |
+ drm_color_lut_get_value(lut[i].blue, 14);
+ word1 = drm_color_lut_get_value(lut[i].red, 14);
+
+ I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
+ I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
+ }
+ /* Write the 65's entry of the LUT with the last entry given
+ * by user space to clamp values > 1.0.
+ */
+ word0 =
+ (drm_color_lut_get_value(lut[lut_size - 1].green, 14) << 16) |
+ drm_color_lut_get_value(lut[lut_size - 1].blue, 14);
+ word1 = drm_color_lut_get_value(lut[lut_size - 1].red, 14);
+
+ I915_WRITE(CGM_PIPE_DEGAMMA(pipe, lut_size, 0), word0);
+ I915_WRITE(CGM_PIPE_DEGAMMA(pipe, lut_size, 1), word1);
+ }
+
+ I915_WRITE(CGM_PIPE_MODE(pipe),
+ (state->ctm_matrix ? CGM_PIPE_MODE_CSC : 0) |
+ (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
+ (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
+}
+
static void broadwell_load_gamma_lut(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -321,6 +410,47 @@ static void broadwell_load_gamma_lut(struct drm_crtc *crtc)
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
+static void cherryview_load_gamma_lut(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc_state *state = crtc->state;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+ if (state->gamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *) state->gamma_lut->data;
+ uint32_t i, lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
+ uint32_t word0, word1;
+
+ for (i = 0; i < lut_size; i++) {
+ /* Write LUT in U0.10 format. */
+ word0 =
+ (drm_color_lut_get_value(lut[i].green, 10) << 16) |
+ drm_color_lut_get_value(lut[i].blue, 10);
+ word1 = drm_color_lut_get_value(lut[i].red, 10);
+
+ I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
+ I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
+ }
+ /* Write the 257's entry of the LUT with the last entry given
+ * by user space to clamp values > 1.0.
+ */
+ word0 =
+ (drm_color_lut_get_value(lut[lut_size - 1].green, 10) << 16) |
+ drm_color_lut_get_value(lut[lut_size - 1].blue, 10);
+ word1 = drm_color_lut_get_value(lut[lut_size - 1].red, 10);
+
+ I915_WRITE(CGM_PIPE_GAMMA(pipe, lut_size, 0), word0);
+ I915_WRITE(CGM_PIPE_GAMMA(pipe, lut_size, 1), word1);
+ }
+
+ I915_WRITE(CGM_PIPE_MODE(pipe),
+ (state->ctm_matrix ? CGM_PIPE_MODE_CSC : 0) |
+ (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
+ (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
+}
+
static void intel_color_load_luts_internal(struct drm_crtc *crtc,
bool legacy)
{
@@ -412,8 +542,13 @@ void intel_color_init(struct drm_crtc *crtc)
intel_crtc->lut_b[i] = i;
}
- if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
- IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
+ if (IS_CHERRYVIEW(dev)) {
+ dev_priv->display.load_degamma_lut =
+ cherryview_load_degamma_lut;
+ dev_priv->display.load_gamma_lut = cherryview_load_gamma_lut;
+ dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
+ } else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
+ IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
dev_priv->display.load_degamma_lut = broadwell_load_degamma_lut;
dev_priv->display.load_gamma_lut = broadwell_load_gamma_lut;
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
--
2.6.4
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* ✗ Fi.CI.BAT: warning for Pipe level color management
2016-01-21 15:03 [PATCH 0/6] Pipe level color management Lionel Landwerlin
` (5 preceding siblings ...)
2016-01-21 15:03 ` [PATCH 6/6] drm/i915: Implement color management on chv Lionel Landwerlin
@ 2016-01-21 15:42 ` Patchwork
2016-01-22 15:04 ` [PATCH 0/6] " Daniel Stone
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2016-01-21 15:42 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly: 2016y-01m-21d-11h-02m-42s UTC integration manifest
Test drv_module_reload_basic:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (hsw-gt2)
pass -> DMESG-WARN (bdw-ultra)
pass -> DMESG-WARN (ivb-t430s)
pass -> DMESG-WARN (byt-nuc)
pass -> DMESG-WARN (snb-x220t)
pass -> DMESG-WARN (snb-dellxps)
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (bdw-nuci7)
bdw-nuci7 total:140 pass:130 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:143 pass:136 dwarn:1 dfail:0 fail:0 skip:6
bsw-nuc-2 total:143 pass:118 dwarn:1 dfail:0 fail:0 skip:24
byt-nuc total:143 pass:127 dwarn:1 dfail:0 fail:0 skip:15
hsw-brixbox total:143 pass:135 dwarn:1 dfail:0 fail:0 skip:7
hsw-gt2 total:143 pass:138 dwarn:1 dfail:0 fail:0 skip:4
ilk-hp8440p total:143 pass:104 dwarn:1 dfail:0 fail:0 skip:38
ivb-t430s total:143 pass:136 dwarn:1 dfail:0 fail:0 skip:6
skl-i5k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:143 pass:128 dwarn:1 dfail:0 fail:0 skip:14
snb-x220t total:143 pass:128 dwarn:1 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1239/
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/6] Pipe level color management
2016-01-21 15:03 [PATCH 0/6] Pipe level color management Lionel Landwerlin
` (6 preceding siblings ...)
2016-01-21 15:42 ` ✗ Fi.CI.BAT: warning for Pipe level color management Patchwork
@ 2016-01-22 15:04 ` Daniel Stone
2016-01-22 15:38 ` [Intel-gfx] " Deucher, Alexander
` (2 more replies)
7 siblings, 3 replies; 17+ messages in thread
From: Daniel Stone @ 2016-01-22 15:04 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: Alex Deucher, intel-gfx, Thierry Reding, dri-devel
Hi Lionel,
On 21 January 2016 at 15:03, Lionel Landwerlin
<lionel.g.landwerlin@intel.com> wrote:
> Hi,
>
> This serie introduces pipe level color management through a set of properties
> attached to the CRTC. It also provides an implementation for some Intel
> platforms.
>
> This serie is based of a previous set of patches by Shashank Sharma and takes
> into account of the comments by Daniel Stone & Daniel Vetter.
This is a lot more tractable than previous series, thanks! I think a
lot of the confusion I had around this was from the number of
hardware-specific features stuffed into this, and the manner in which
they were stuffed in. For example, with the previous series, it looks
like you could configure both PRE_CTM and POST_CTM LUTs in 12-bit
mode, which is impossible as the PRM suggests the only way to have
both LUTs active is with split-gamma mode. (For anyone else looking at
the Broadwell PRM, note the split-gamma mode describes the two LUTs
completely backwards: the only thing that makes sense is for the
pre-CTM LUT to have a range of 0..1.0, and the post-CTM LUT to have a
range of -3.0..3.0, rather than the other way around.)
Now with everything just using split-gamma mode, I'm much happier with
how this is looking. I took a look at some other architectures to see
how this would fit, and also had a chat with Richard Hughes to clear
some things up. AMD seems to support every possible mode under the
sun, so should support any API we came up with. Most other
architectures only implemented a single gamma table (equivalent to
legacy gamma ramp), but there was one I have fairly detailed
documentation for and also supports everything.
The degamma/colour-transform-matrix/gamma model is definitely a good
one, and it seems like everyone agrees on a 3x3 matrix for CTM. So
far, so good. What I worry about is the _values_ we put into the CTM.
Intel supports two quite fun properties of matrix output. Firstly, the
range is (-3.0..3.0) rather than the (0.0..1.0) you might expect.
Negative values are axis-mirrored, i.e. lut2_index =
fabs(matrix_output), thus giving us a LUT range of (0.0..3.0).
Secondly, whilst (0.0..1.0) is represented by linear LUT entries, the
LUT values for (1.0..3.0) are calculated by a linear interpolation
between LUT entry #512 (i.e. that for 1.0) and a bonus entry #513
(value for 3.0). I haven't seen this supported anywhere else, so would
tend towards mirroring the last value into the extra supernumerary
entry, i.e. emulate saturation for matrix output values to 1.0.
I don't really know what to do about negative values as CTM output,
since the doc I have here is silent on whether negative values are
similarly axis-mirrored/sign-stripped, or whether they are instead
clamped to 0.0. Either way, I'm not really sure it's behaviour we can
rely upon to be portable.
As a detail, the architecture I'm looking at has mixed granularity for
the second (post-CTM) LUT: lower RGB-value entries have higher
granularity (precision in LUT indexing), with lower granularity for
higher entries. I don't think this is a problem though, since we can
just decimate in the kernel (i.e. ignore every n'th LUT entry, to
write a smaller LUT to hardware than we received to userspace).
Anyway, beyond that, it seems there are a few things we agree on:
- optional pre-matrix ('degamma') per-channel LUT of variable
length, but (from a userspace point of view) fixed precision, input &
output ranges 0.0..1.0
- optional 3x3 matrix with input range [0.0,1.0], with output values
saturating to 1.0, and negative values producing undefined behaviour
- optional post-matrix ('gamma') per-channel LUT of variable length,
but (from a userspace point of view) fixed precision, input & output
ranges 0.0..1.0
This would mean missing some Intel-specific features, but whether or
not this is actually required I don't really know. At least it seems
like it would be enough to implement standard ICC profile correction
from Weston in a hardware-independent manner.
Thierry, Alex, did you have any comments or ideas on this?
Cheers,
Daniel
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [Intel-gfx] [PATCH 0/6] Pipe level color management
2016-01-22 15:04 ` [PATCH 0/6] " Daniel Stone
@ 2016-01-22 15:38 ` Deucher, Alexander
2016-01-22 16:06 ` Lionel Landwerlin
2016-01-26 12:18 ` [Intel-gfx] " Daniel Stone
2 siblings, 0 replies; 17+ messages in thread
From: Deucher, Alexander @ 2016-01-22 15:38 UTC (permalink / raw)
To: 'Daniel Stone', Lionel Landwerlin, Wentland, Harry
Cc: intel-gfx, dri-devel
> -----Original Message-----
> From: Daniel Stone [mailto:daniel@fooishbar.org]
> Sent: Friday, January 22, 2016 10:05 AM
> To: Lionel Landwerlin
> Cc: intel-gfx; Thierry Reding; Deucher, Alexander; dri-devel
> Subject: Re: [Intel-gfx] [PATCH 0/6] Pipe level color management
>
> Hi Lionel,
>
> On 21 January 2016 at 15:03, Lionel Landwerlin
> <lionel.g.landwerlin@intel.com> wrote:
> > Hi,
> >
> > This serie introduces pipe level color management through a set of
> properties
> > attached to the CRTC. It also provides an implementation for some Intel
> > platforms.
> >
> > This serie is based of a previous set of patches by Shashank Sharma and
> takes
> > into account of the comments by Daniel Stone & Daniel Vetter.
>
> This is a lot more tractable than previous series, thanks! I think a
> lot of the confusion I had around this was from the number of
> hardware-specific features stuffed into this, and the manner in which
> they were stuffed in. For example, with the previous series, it looks
> like you could configure both PRE_CTM and POST_CTM LUTs in 12-bit
> mode, which is impossible as the PRM suggests the only way to have
> both LUTs active is with split-gamma mode. (For anyone else looking at
> the Broadwell PRM, note the split-gamma mode describes the two LUTs
> completely backwards: the only thing that makes sense is for the
> pre-CTM LUT to have a range of 0..1.0, and the post-CTM LUT to have a
> range of -3.0..3.0, rather than the other way around.)
>
> Now with everything just using split-gamma mode, I'm much happier with
> how this is looking. I took a look at some other architectures to see
> how this would fit, and also had a chat with Richard Hughes to clear
> some things up. AMD seems to support every possible mode under the
> sun, so should support any API we came up with. Most other
> architectures only implemented a single gamma table (equivalent to
> legacy gamma ramp), but there was one I have fairly detailed
> documentation for and also supports everything.
>
> The degamma/colour-transform-matrix/gamma model is definitely a good
> one, and it seems like everyone agrees on a 3x3 matrix for CTM. So
> far, so good. What I worry about is the _values_ we put into the CTM.
>
> Intel supports two quite fun properties of matrix output. Firstly, the
> range is (-3.0..3.0) rather than the (0.0..1.0) you might expect.
> Negative values are axis-mirrored, i.e. lut2_index =
> fabs(matrix_output), thus giving us a LUT range of (0.0..3.0).
> Secondly, whilst (0.0..1.0) is represented by linear LUT entries, the
> LUT values for (1.0..3.0) are calculated by a linear interpolation
> between LUT entry #512 (i.e. that for 1.0) and a bonus entry #513
> (value for 3.0). I haven't seen this supported anywhere else, so would
> tend towards mirroring the last value into the extra supernumerary
> entry, i.e. emulate saturation for matrix output values to 1.0.
>
> I don't really know what to do about negative values as CTM output,
> since the doc I have here is silent on whether negative values are
> similarly axis-mirrored/sign-stripped, or whether they are instead
> clamped to 0.0. Either way, I'm not really sure it's behaviour we can
> rely upon to be portable.
>
> As a detail, the architecture I'm looking at has mixed granularity for
> the second (post-CTM) LUT: lower RGB-value entries have higher
> granularity (precision in LUT indexing), with lower granularity for
> higher entries. I don't think this is a problem though, since we can
> just decimate in the kernel (i.e. ignore every n'th LUT entry, to
> write a smaller LUT to hardware than we received to userspace).
>
> Anyway, beyond that, it seems there are a few things we agree on:
> - optional pre-matrix ('degamma') per-channel LUT of variable
> length, but (from a userspace point of view) fixed precision, input &
> output ranges 0.0..1.0
> - optional 3x3 matrix with input range [0.0,1.0], with output values
> saturating to 1.0, and negative values producing undefined behaviour
> - optional post-matrix ('gamma') per-channel LUT of variable length,
> but (from a userspace point of view) fixed precision, input & output
> ranges 0.0..1.0
>
> This would mean missing some Intel-specific features, but whether or
> not this is actually required I don't really know. At least it seems
> like it would be enough to implement standard ICC profile correction
> from Weston in a hardware-independent manner.
>
> Thierry, Alex, did you have any comments or ideas on this?
Adding Harry to comment as he's more familiar with our display hardware color management.
Alex
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/6] Pipe level color management
2016-01-22 15:04 ` [PATCH 0/6] " Daniel Stone
2016-01-22 15:38 ` [Intel-gfx] " Deucher, Alexander
@ 2016-01-22 16:06 ` Lionel Landwerlin
2016-01-22 16:21 ` Daniel Vetter
2016-01-26 12:18 ` [Intel-gfx] " Daniel Stone
2 siblings, 1 reply; 17+ messages in thread
From: Lionel Landwerlin @ 2016-01-22 16:06 UTC (permalink / raw)
To: Daniel Stone; +Cc: Alex Deucher, intel-gfx, Thierry Reding, dri-devel
On 22/01/16 15:04, Daniel Stone wrote:
> Hi Lionel,
>
> On 21 January 2016 at 15:03, Lionel Landwerlin
> <lionel.g.landwerlin@intel.com> wrote:
>> Hi,
>>
>> This serie introduces pipe level color management through a set of properties
>> attached to the CRTC. It also provides an implementation for some Intel
>> platforms.
>>
>> This serie is based of a previous set of patches by Shashank Sharma and takes
>> into account of the comments by Daniel Stone & Daniel Vetter.
> This is a lot more tractable than previous series, thanks! I think a
> lot of the confusion I had around this was from the number of
> hardware-specific features stuffed into this, and the manner in which
> they were stuffed in. For example, with the previous series, it looks
> like you could configure both PRE_CTM and POST_CTM LUTs in 12-bit
> mode, which is impossible as the PRM suggests the only way to have
> both LUTs active is with split-gamma mode. (For anyone else looking at
> the Broadwell PRM, note the split-gamma mode describes the two LUTs
> completely backwards: the only thing that makes sense is for the
> pre-CTM LUT to have a range of 0..1.0, and the post-CTM LUT to have a
> range of -3.0..3.0, rather than the other way around.)
>
> Now with everything just using split-gamma mode, I'm much happier with
> how this is looking. I took a look at some other architectures to see
> how this would fit, and also had a chat with Richard Hughes to clear
> some things up. AMD seems to support every possible mode under the
> sun, so should support any API we came up with. Most other
> architectures only implemented a single gamma table (equivalent to
> legacy gamma ramp), but there was one I have fairly detailed
> documentation for and also supports everything.
There might be some interest from others to have a single 12bits post
csc gamma LUT.
So I was going to submit another serie to enable this as a special case
just for some generations of the Intel hardware once this work lands.
Obviously in order to program the hardware in that mode you would need
to a userspace specially tuned for the particular platform on which it's
running. This mode wouldn't be exposed through the current set of
properties.
>
> The degamma/colour-transform-matrix/gamma model is definitely a good
> one, and it seems like everyone agrees on a 3x3 matrix for CTM. So
> far, so good. What I worry about is the _values_ we put into the CTM.
>
> Intel supports two quite fun properties of matrix output. Firstly, the
> range is (-3.0..3.0) rather than the (0.0..1.0) you might expect.
> Negative values are axis-mirrored, i.e. lut2_index =
> fabs(matrix_output), thus giving us a LUT range of (0.0..3.0).
> Secondly, whilst (0.0..1.0) is represented by linear LUT entries, the
> LUT values for (1.0..3.0) are calculated by a linear interpolation
> between LUT entry #512 (i.e. that for 1.0) and a bonus entry #513
> (value for 3.0). I haven't seen this supported anywhere else, so would
> tend towards mirroring the last value into the extra supernumerary
> entry, i.e. emulate saturation for matrix output values to 1.0.
It's good you mention this, because I wrote a test assuming negative
values would be clamped to (0.0..1.0) and the test passes :/
So maybe there is something fishy here...
>
> I don't really know what to do about negative values as CTM output,
> since the doc I have here is silent on whether negative values are
> similarly axis-mirrored/sign-stripped, or whether they are instead
> clamped to 0.0. Either way, I'm not really sure it's behaviour we can
> rely upon to be portable.
Maybe we should compute both and verify at least one works?
We also discussed briefly the multiplication results. My tests show the
Intel hardware seems to clamp the results.
Let's say you have a 255 pixel going through a 0.5 coefficient, you
should get 127.5 which would be rounded to 128.
Intel hardware gives us 127.
Same for a pixel at 255 and a coefficient of 0.25. You would get 63.75
so 64 rounded and my results show 63.
Again, computing both hypothesis might be a solution.
>
> As a detail, the architecture I'm looking at has mixed granularity for
> the second (post-CTM) LUT: lower RGB-value entries have higher
> granularity (precision in LUT indexing), with lower granularity for
> higher entries. I don't think this is a problem though, since we can
> just decimate in the kernel (i.e. ignore every n'th LUT entry, to
> write a smaller LUT to hardware than we received to userspace).
>
> Anyway, beyond that, it seems there are a few things we agree on:
> - optional pre-matrix ('degamma') per-channel LUT of variable
> length, but (from a userspace point of view) fixed precision, input &
> output ranges 0.0..1.0
> - optional 3x3 matrix with input range [0.0,1.0], with output values
> saturating to 1.0, and negative values producing undefined behaviour
> - optional post-matrix ('gamma') per-channel LUT of variable length,
> but (from a userspace point of view) fixed precision, input & output
> ranges 0.0..1.0
>
> This would mean missing some Intel-specific features, but whether or
> not this is actually required I don't really know. At least it seems
> like it would be enough to implement standard ICC profile correction
> from Weston in a hardware-independent manner.
>
> Thierry, Alex, did you have any comments or ideas on this?
>
> Cheers,
> Daniel
>
Thanks for your feedback!
-
Lionel
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/6] Pipe level color management
2016-01-22 16:06 ` Lionel Landwerlin
@ 2016-01-22 16:21 ` Daniel Vetter
2016-01-22 17:07 ` Daniel Stone
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2016-01-22 16:21 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: Alex Deucher, intel-gfx, Thierry Reding, dri-devel
On Fri, Jan 22, 2016 at 04:06:15PM +0000, Lionel Landwerlin wrote:
> On 22/01/16 15:04, Daniel Stone wrote:
> >Hi Lionel,
> >
> >On 21 January 2016 at 15:03, Lionel Landwerlin
> ><lionel.g.landwerlin@intel.com> wrote:
> >>Hi,
> >>
> >>This serie introduces pipe level color management through a set of properties
> >>attached to the CRTC. It also provides an implementation for some Intel
> >>platforms.
> >>
> >>This serie is based of a previous set of patches by Shashank Sharma and takes
> >>into account of the comments by Daniel Stone & Daniel Vetter.
> >This is a lot more tractable than previous series, thanks! I think a
> >lot of the confusion I had around this was from the number of
> >hardware-specific features stuffed into this, and the manner in which
> >they were stuffed in. For example, with the previous series, it looks
> >like you could configure both PRE_CTM and POST_CTM LUTs in 12-bit
> >mode, which is impossible as the PRM suggests the only way to have
> >both LUTs active is with split-gamma mode. (For anyone else looking at
> >the Broadwell PRM, note the split-gamma mode describes the two LUTs
> >completely backwards: the only thing that makes sense is for the
> >pre-CTM LUT to have a range of 0..1.0, and the post-CTM LUT to have a
> >range of -3.0..3.0, rather than the other way around.)
> >
> >Now with everything just using split-gamma mode, I'm much happier with
> >how this is looking. I took a look at some other architectures to see
> >how this would fit, and also had a chat with Richard Hughes to clear
> >some things up. AMD seems to support every possible mode under the
> >sun, so should support any API we came up with. Most other
> >architectures only implemented a single gamma table (equivalent to
> >legacy gamma ramp), but there was one I have fairly detailed
> >documentation for and also supports everything.
>
> There might be some interest from others to have a single 12bits post csc
> gamma LUT.
> So I was going to submit another serie to enable this as a special case just
> for some generations of the Intel hardware once this work lands.
>
> Obviously in order to program the hardware in that mode you would need to a
> userspace specially tuned for the particular platform on which it's running.
> This mode wouldn't be exposed through the current set of properties.
Yeah, the idea there is that we don't tell this userspace explicitly, but
it can be used, i.e.
a) in the config properties we advertise the sizes of the split gamma
table
b) but when userspace supplies an atomic request that matches the larger
12bit gamma, and no pre-ctm gamma, then we'll use that.
> >The degamma/colour-transform-matrix/gamma model is definitely a good
> >one, and it seems like everyone agrees on a 3x3 matrix for CTM. So
> >far, so good. What I worry about is the _values_ we put into the CTM.
> >
> >Intel supports two quite fun properties of matrix output. Firstly, the
> >range is (-3.0..3.0) rather than the (0.0..1.0) you might expect.
> >Negative values are axis-mirrored, i.e. lut2_index =
> >fabs(matrix_output), thus giving us a LUT range of (0.0..3.0).
> >Secondly, whilst (0.0..1.0) is represented by linear LUT entries, the
> >LUT values for (1.0..3.0) are calculated by a linear interpolation
> >between LUT entry #512 (i.e. that for 1.0) and a bonus entry #513
> >(value for 3.0). I haven't seen this supported anywhere else, so would
> >tend towards mirroring the last value into the extra supernumerary
> >entry, i.e. emulate saturation for matrix output values to 1.0.
>
> It's good you mention this, because I wrote a test assuming negative values
> would be clamped to (0.0..1.0) and the test passes :/
> So maybe there is something fishy here...
>
> >
> >I don't really know what to do about negative values as CTM output,
> >since the doc I have here is silent on whether negative values are
> >similarly axis-mirrored/sign-stripped, or whether they are instead
> >clamped to 0.0. Either way, I'm not really sure it's behaviour we can
> >rely upon to be portable.
>
> Maybe we should compute both and verify at least one works?
>
> We also discussed briefly the multiplication results. My tests show the
> Intel hardware seems to clamp the results.
> Let's say you have a 255 pixel going through a 0.5 coefficient, you should
> get 127.5 which would be rounded to 128.
> Intel hardware gives us 127.
> Same for a pixel at 255 and a coefficient of 0.25. You would get 63.75 so 64
> rounded and my results show 63.
>
> Again, computing both hypothesis might be a solution.
>
> >
> >As a detail, the architecture I'm looking at has mixed granularity for
> >the second (post-CTM) LUT: lower RGB-value entries have higher
> >granularity (precision in LUT indexing), with lower granularity for
> >higher entries. I don't think this is a problem though, since we can
> >just decimate in the kernel (i.e. ignore every n'th LUT entry, to
> >write a smaller LUT to hardware than we received to userspace).
This was the original plan (iirc one of the byt luts is like this too).
> >Anyway, beyond that, it seems there are a few things we agree on:
> > - optional pre-matrix ('degamma') per-channel LUT of variable
> >length, but (from a userspace point of view) fixed precision, input &
> >output ranges 0.0..1.0
> > - optional 3x3 matrix with input range [0.0,1.0], with output values
> >saturating to 1.0, and negative values producing undefined behaviour
> > - optional post-matrix ('gamma') per-channel LUT of variable length,
> >but (from a userspace point of view) fixed precision, input & output
> >ranges 0.0..1.0
Yeah I thought same here, we'll support 0.0..1.0 and anything that
overshoots is platform-defined. I have no idea what to do with the
overshoot lut table entries, so I guess we'll just leave those until
someone screams badly ;-)
> >This would mean missing some Intel-specific features, but whether or
> >not this is actually required I don't really know. At least it seems
> >like it would be enough to implement standard ICC profile correction
> >from Weston in a hardware-independent manner.
> >
> >Thierry, Alex, did you have any comments or ideas on this?
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/6] Pipe level color management
2016-01-22 16:21 ` Daniel Vetter
@ 2016-01-22 17:07 ` Daniel Stone
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Stone @ 2016-01-22 17:07 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Alex Deucher, intel-gfx, Thierry Reding, dri-devel
Hi,
On 22 January 2016 at 16:21, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Fri, Jan 22, 2016 at 04:06:15PM +0000, Lionel Landwerlin wrote:
>> On 22/01/16 15:04, Daniel Stone wrote:
>> >Now with everything just using split-gamma mode, I'm much happier with
>> >how this is looking. I took a look at some other architectures to see
>> >how this would fit, and also had a chat with Richard Hughes to clear
>> >some things up. AMD seems to support every possible mode under the
>> >sun, so should support any API we came up with. Most other
>> >architectures only implemented a single gamma table (equivalent to
>> >legacy gamma ramp), but there was one I have fairly detailed
>> >documentation for and also supports everything.
>>
>> There might be some interest from others to have a single 12bits post csc
>> gamma LUT.
>> So I was going to submit another serie to enable this as a special case just
>> for some generations of the Intel hardware once this work lands.
>>
>> Obviously in order to program the hardware in that mode you would need to a
>> userspace specially tuned for the particular platform on which it's running.
>> This mode wouldn't be exposed through the current set of properties.
>
> Yeah, the idea there is that we don't tell this userspace explicitly, but
> it can be used, i.e.
> a) in the config properties we advertise the sizes of the split gamma
> table
> b) but when userspace supplies an atomic request that matches the larger
> 12bit gamma, and no pre-ctm gamma, then we'll use that.
Right, exactly. My concern was mainly that it seemed incredibly easy
to program broken state (12-bit LUT seemingly active both pre- and
post-CTM). I honestly wasn't sure whether the code or my expectations
were wrong though. But adding it back properly is just fine.
>> >Intel supports two quite fun properties of matrix output. Firstly, the
>> >range is (-3.0..3.0) rather than the (0.0..1.0) you might expect.
>> >Negative values are axis-mirrored, i.e. lut2_index =
>> >fabs(matrix_output), thus giving us a LUT range of (0.0..3.0).
>> >Secondly, whilst (0.0..1.0) is represented by linear LUT entries, the
>> >LUT values for (1.0..3.0) are calculated by a linear interpolation
>> >between LUT entry #512 (i.e. that for 1.0) and a bonus entry #513
>> >(value for 3.0). I haven't seen this supported anywhere else, so would
>> >tend towards mirroring the last value into the extra supernumerary
>> >entry, i.e. emulate saturation for matrix output values to 1.0.
>>
>> It's good you mention this, because I wrote a test assuming negative values
>> would be clamped to (0.0..1.0) and the test passes :/
>> So maybe there is something fishy here...
Hmm, the doc explicitly mentions the axis-mirroring/sign-stripping,
but is either so weird or so incorrect that I think you'd probably
only be able to tell empirically. ;)
>> >I don't really know what to do about negative values as CTM output,
>> >since the doc I have here is silent on whether negative values are
>> >similarly axis-mirrored/sign-stripped, or whether they are instead
>> >clamped to 0.0. Either way, I'm not really sure it's behaviour we can
>> >rely upon to be portable.
>>
>> Maybe we should compute both and verify at least one works?
Well, I'd have to write the entire CM support for that platform first,
which might be a little while ... ;)
>> We also discussed briefly the multiplication results. My tests show the
>> Intel hardware seems to clamp the results.
>> Let's say you have a 255 pixel going through a 0.5 coefficient, you should
>> get 127.5 which would be rounded to 128.
>> Intel hardware gives us 127.
>> Same for a pixel at 255 and a coefficient of 0.25. You would get 63.75 so 64
>> rounded and my results show 63.
>>
>> Again, computing both hypothesis might be a solution.
The docs I have here are silent on what happens. Not much we can do
about it really, so I think we can just leave it as
platform-dependent.
>> >As a detail, the architecture I'm looking at has mixed granularity for
>> >the second (post-CTM) LUT: lower RGB-value entries have higher
>> >granularity (precision in LUT indexing), with lower granularity for
>> >higher entries. I don't think this is a problem though, since we can
>> >just decimate in the kernel (i.e. ignore every n'th LUT entry, to
>> >write a smaller LUT to hardware than we received to userspace).
>
> This was the original plan (iirc one of the byt luts is like this too).
Cool; it's the only thing I could think of which made any sense.
>> >Anyway, beyond that, it seems there are a few things we agree on:
>> > - optional pre-matrix ('degamma') per-channel LUT of variable
>> >length, but (from a userspace point of view) fixed precision, input &
>> >output ranges 0.0..1.0
>> > - optional 3x3 matrix with input range [0.0,1.0], with output values
>> >saturating to 1.0, and negative values producing undefined behaviour
>> > - optional post-matrix ('gamma') per-channel LUT of variable length,
>> >but (from a userspace point of view) fixed precision, input & output
>> >ranges 0.0..1.0
>
> Yeah I thought same here, we'll support 0.0..1.0 and anything that
> overshoots is platform-defined. I have no idea what to do with the
> overshoot lut table entries, so I guess we'll just leave those until
> someone screams badly ;-)
Program the overshoot register (LUT entry #513) to the same as the
final LUT entry (#512), and overshoot becomes saturation, i.e. desired
semantics. Not really sure what to do with undershoot (clamp to 0 or
mirror axes), but given that's completely hardware dependent and there
doesn't seem much we can do about it, I'd leave it at documenting
'don't do that'.
Cheers,
Daniel
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Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 0/6] Pipe level color management
2016-01-22 15:04 ` [PATCH 0/6] " Daniel Stone
2016-01-22 15:38 ` [Intel-gfx] " Deucher, Alexander
2016-01-22 16:06 ` Lionel Landwerlin
@ 2016-01-26 12:18 ` Daniel Stone
2 siblings, 0 replies; 17+ messages in thread
From: Daniel Stone @ 2016-01-26 12:18 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: Alex Deucher, intel-gfx, dri-devel
Hi,
On 22 January 2016 at 15:04, Daniel Stone <daniel@fooishbar.org> wrote:
> On 21 January 2016 at 15:03, Lionel Landwerlin
> <lionel.g.landwerlin@intel.com> wrote:
>> Hi,
>>
>> This serie introduces pipe level color management through a set of properties
>> attached to the CRTC. It also provides an implementation for some Intel
>> platforms.
>>
>> This serie is based of a previous set of patches by Shashank Sharma and takes
>> into account of the comments by Daniel Stone & Daniel Vetter.
>
> This is a lot more tractable than previous series, thanks!
One subtlety which did just come up on IRC and should probably be
documented, is the interaction with the 'Broadcast Mode' property.
Currently, Broadcast Mode logically sits on top of colour management:
all tables passed into CM are assumed to be for 0-255 colour ranges,
and setting limited BM instead clamps these tables at apply time to
16-235 (by manually adjusting them in the driver).
It'd be nice to document this, so someone doesn't implement this the
other way around, or assuming that CM trumps BM, or ...
Cheers,
Daniel
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^ permalink raw reply [flat|nested] 17+ messages in thread