[PATCH 0/3] Support pwm driver for aspeed ast26xx

[PATCH 0/3] Support pwm driver for aspeed ast26xx

[Billy Tsai]

This series adds driver support for the PWM controller found in
Aspeed's AST2600 BMC SoCs, but isn't compatible with the AST2400
and AST2500.

Billy Tsai (3):
  pwm: Add Aspeed ast2600 PWM support
  pinctrl: Add the pinctrl setting for PWM.
  ARM: dts: ast2600: Add PWM to device tree

 arch/arm/dts/ast2600-evb.dts             |  20 ++
 arch/arm/dts/ast2600.dtsi                |  95 +++++++++
 drivers/pinctrl/aspeed/pinctrl_ast2600.c | 120 +++++++++++
 drivers/pwm/Kconfig                      |   8 +
 drivers/pwm/Makefile                     |   1 +
 drivers/pwm/pwm-aspeed.c                 | 251 +++++++++++++++++++++++
 6 files changed, 495 insertions(+)
 create mode 100644 drivers/pwm/pwm-aspeed.c

-- 
2.25.1

[PATCH 1/3] pwm: Add Aspeed ast2600 PWM support

[Billy Tsai]

This patch add the support of PWM controller which can be found at aspeed
ast2600 soc. The pwm supoorts up to 16 channels and it's part function
of multi-function device "pwm-tach controller".

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
 drivers/pwm/Kconfig      |   8 ++
 drivers/pwm/Makefile     |   1 +
 drivers/pwm/pwm-aspeed.c | 251 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 260 insertions(+)
 create mode 100644 drivers/pwm/pwm-aspeed.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 669d3fa4fc..6be612d58a 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,6 +9,14 @@ config DM_PWM
 	  frequency/period can be controlled along with the proportion of that
 	  time that the signal is high.
 
+config PWM_ASPEED
+	bool "Enable support for the Aspeed PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on Ast2600 SoCs. It supports a programmable period
+	  and duty cycle. It provides 16 channels which can be independently
+	  programmed.
+
 config PWM_AT91
 	bool "Enable support for PWM found on AT91 SoC's"
 	depends on DM_PWM && ARCH_AT91
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 55f2bc081d..5d31812d52 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -10,6 +10,7 @@
 
 obj-$(CONFIG_DM_PWM)		+= pwm-uclass.o
 
+obj-$(CONFIG_PWM_ASPEED)	+= pwm-aspeed.o
 obj-$(CONFIG_PWM_AT91)		+= pwm-at91.o
 obj-$(CONFIG_PWM_CROS_EC)	+= cros_ec_pwm.o
 obj-$(CONFIG_PWM_EXYNOS)	+= exynos_pwm.o
diff --git a/drivers/pwm/pwm-aspeed.c b/drivers/pwm/pwm-aspeed.c
new file mode 100644
index 0000000000..ba98641c86
--- /dev/null
+++ b/drivers/pwm/pwm-aspeed.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Aspeed Technology Inc.
+ *
+ * PWM controller driver for Aspeed ast2600 SoCs.
+ * This drivers doesn't support earlier version of the IP.
+ *
+ * The formula of pwm period duration:
+ * period duration = ((DIV_L + 1) * (PERIOD + 1) << DIV_H) / input-clk
+ *
+ * The formula of pwm duty cycle duration:
+ * duty cycle duration = period duration * DUTY_CYCLE_FALLING_POINT / (PERIOD + 1)
+ * = ((DIV_L + 1) * DUTY_CYCLE_FALLING_POINT << DIV_H) / input-clk
+ *
+ * The software driver fixes the period to 255, which causes the high-frequency
+ * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
+ *
+ * Register usage:
+ * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
+ * Use to determine whether the PWM channel is enabled or disabled
+ * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
+ * output low to the PIN_ENABLE mux after that the driver can still change the pwm period
+ * and duty and the value will apply when CLK_ENABLE be set again.
+ * Use to determine whether duty_cycle bigger than 0.
+ * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
+ * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
+ * values are equal it means the duty cycle = 100%.
+ *
+ * Limitations:
+ * - When changing both duty cycle and period, we cannot prevent in
+ *   software that the output might produce a period with mixed
+ *   settings.
+ * - Disabling the PWM doesn't complete the current period.
+ *
+ * Improvements:
+ * - When only changing one of duty cycle or period, our pwm controller will not
+ *   generate the glitch, the configure will change at next cycle of pwm.
+ *   This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <pwm.h>
+#include <clk.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <dm/device_compat.h>
+#include <linux/math64.h>
+#include <linux/bitfield.h>
+#include <asm/io.h>
+
+/* The channel number of Aspeed pwm controller */
+#define PWM_ASPEED_NR_PWMS 16
+
+/* PWM Control Register */
+#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
+#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
+#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
+#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
+#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
+#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
+#define PWM_ASPEED_CTRL_INVERSE BIT(14)
+#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
+#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
+#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
+#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
+
+/* PWM Duty Cycle Register */
+#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
+#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
+#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
+#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
+#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
+
+/* PWM fixed value */
+#define PWM_ASPEED_FIXED_PERIOD 0xff
+
+#define NSEC_PER_SEC			1000000000L
+
+struct aspeed_pwm_priv {
+	struct clk clk;
+	struct regmap *regmap;
+	struct reset_ctl reset;
+};
+
+static int aspeed_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
+{
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+
+	if (channel >= PWM_ASPEED_NR_PWMS)
+		return -EINVAL;
+
+	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
+			   PWM_ASPEED_CTRL_INVERSE,
+			   FIELD_PREP(PWM_ASPEED_CTRL_INVERSE,
+				      polarity));
+	return 0;
+}
+
+static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+
+	if (channel >= PWM_ASPEED_NR_PWMS)
+		return -EINVAL;
+
+	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
+			   PWM_ASPEED_CTRL_PIN_ENABLE,
+			   enable ? PWM_ASPEED_CTRL_PIN_ENABLE : 0);
+	return 0;
+}
+
+static int aspeed_pwm_set_config(struct udevice *dev, uint channel,
+				 uint period_ns, uint duty_ns)
+{
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+	u32 duty_pt;
+	unsigned long rate;
+	u64 div_h, div_l, divisor;
+	bool clk_en;
+
+	if (channel >= PWM_ASPEED_NR_PWMS)
+		return -EINVAL;
+	dev_dbg(dev, "expect period: %dns, duty_cycle: %dns\n", period_ns,
+		duty_ns);
+
+	rate = clk_get_rate(&priv->clk);
+	/*
+	 * Pick the smallest value for div_h so that div_l can be the biggest
+	 * which results in a finer resolution near the target period value.
+	 */
+	divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
+		  (PWM_ASPEED_CTRL_CLK_DIV_L + 1);
+	div_h = order_base_2(div64_u64((u64)rate * period_ns + divisor - 1, divisor));
+	if (div_h > 0xf)
+		div_h = 0xf;
+
+	divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
+	div_l = div64_u64((u64)rate * period_ns, divisor);
+
+	if (div_l == 0)
+		return -ERANGE;
+
+	div_l -= 1;
+
+	if (div_l > 255)
+		div_l = 255;
+
+	dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
+		div_l);
+	/* duty_pt = duty_cycle * (PERIOD + 1) / period */
+	duty_pt = div64_u64(duty_ns * (u64)rate,
+			    (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
+	dev_dbg(dev, "duty_cycle = %d, duty_pt = %d\n", duty_ns,
+		duty_pt);
+
+	if (duty_pt == 0) {
+		clk_en = 0;
+	} else {
+		clk_en = 1;
+		if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
+			duty_pt = 0;
+		/*
+		 * Fixed DUTY_CYCLE_PERIOD to its max value to get a
+		 * fine-grained resolution for duty_cycle at the expense of a
+		 * coarser period resolution.
+		 */
+		regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(channel),
+				   PWM_ASPEED_DUTY_CYCLE_PERIOD |
+				       PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
+				       PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+				   FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
+					      PWM_ASPEED_FIXED_PERIOD) |
+				       FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+						  duty_pt));
+	}
+
+	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
+			   PWM_ASPEED_CTRL_CLK_DIV_H |
+			       PWM_ASPEED_CTRL_CLK_DIV_L |
+			       PWM_ASPEED_CTRL_CLK_ENABLE,
+			   FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
+			       FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
+			       FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en));
+	return 0;
+}
+
+static int aspeed_pwm_probe(struct udevice *dev)
+{
+	int ret;
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+	struct udevice *parent_dev = dev_get_parent(dev);
+
+	priv->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));
+	if (IS_ERR(priv->regmap)) {
+		dev_err(dev, "Couldn't get regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	ret = clk_get_by_index(parent_dev, 0, &priv->clk);
+	if (ret < 0) {
+		dev_err(dev, "get clock failed\n");
+		return ret;
+	}
+
+	ret = reset_get_by_index(parent_dev, 0, &priv->reset);
+	if (ret) {
+		dev_err(dev, "get reset failed\n");
+		return ret;
+	}
+	ret = reset_deassert(&priv->reset);
+	if (ret) {
+		dev_err(dev, "cannot deassert reset control: %pe\n",
+			ERR_PTR(ret));
+		return ret;
+	}
+
+	return 0;
+}
+
+static int aspeed_pwm_remove(struct udevice *dev)
+{
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+
+	reset_assert(&priv->reset);
+
+	return 0;
+}
+
+static const struct pwm_ops aspeed_pwm_ops = {
+	.set_invert	= aspeed_pwm_set_invert,
+	.set_config	= aspeed_pwm_set_config,
+	.set_enable	= aspeed_pwm_set_enable,
+};
+
+static const struct udevice_id aspeed_pwm_ids[] = {
+	{ .compatible = "aspeed,ast2600-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(aspeed_pwm) = {
+	.name = "aspeed_pwm",
+	.id = UCLASS_PWM,
+	.of_match = aspeed_pwm_ids,
+	.ops = &aspeed_pwm_ops,
+	.probe = aspeed_pwm_probe,
+	.remove = aspeed_pwm_remove,
+	.priv_auto = sizeof(struct aspeed_pwm_priv),
+};
-- 
2.25.1

[PATCH 2/3] pinctrl: Add the pinctrl setting for PWM.

[Billy Tsai]

This patchs add the signal description array for PWM pinctrl settings.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
 arch/arm/dts/ast2600.dtsi                |  80 +++++++++++++++
 drivers/pinctrl/aspeed/pinctrl_ast2600.c | 120 +++++++++++++++++++++++
 2 files changed, 200 insertions(+)

diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 98840ce7b0..ce006a3759 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -1626,6 +1626,86 @@
 		groups = "PWM7";
 	};
 
+	pinctrl_pwm8g0_default: pwm8g0_default {
+		function = "PWM8G0";
+		groups = "PWM8G0";
+	};
+
+	pinctrl_pwm8g1_default: pwm8g1_default {
+		function = "PWM8G1";
+		groups = "PWM8G1";
+	};
+
+	pinctrl_pwm9g0_default: pwm9g0_default {
+		function = "PWM9G0";
+		groups = "PWM9G0";
+	};
+
+	pinctrl_pwm9g1_default: pwm9g1_default {
+		function = "PWM9G1";
+		groups = "PWM9G1";
+	};
+
+	pinctrl_pwm10g0_default: pwm10g0_default {
+		function = "PWM10G0";
+		groups = "PWM10G0";
+	};
+
+	pinctrl_pwm10g1_default: pwm10g1_default {
+		function = "PWM10G1";
+		groups = "PWM10G1";
+	};
+
+	pinctrl_pwm11g0_default: pwm11g0_default {
+		function = "PWM11G0";
+		groups = "PWM11G0";
+	};
+
+	pinctrl_pwm11g1_default: pwm11g1_default {
+		function = "PWM11G1";
+		groups = "PWM11G1";
+	};
+
+	pinctrl_pwm12g0_default: pwm12g0_default {
+		function = "PWM12G0";
+		groups = "PWM12G0";
+	};
+
+	pinctrl_pwm12g1_default: pwm12g1_default {
+		function = "PWM12G1";
+		groups = "PWM12G1";
+	};
+
+	pinctrl_pwm13g0_default: pwm13g0_default {
+		function = "PWM13G0";
+		groups = "PWM13G0";
+	};
+
+	pinctrl_pwm13g1_default: pwm13g1_default {
+		function = "PWM13G1";
+		groups = "PWM13G1";
+	};
+
+	pinctrl_pwm14g0_default: pwm14g0_default {
+		function = "PWM14G0";
+		groups = "PWM14G0";
+	};
+
+	pinctrl_pwm14g1_default: pwm14g1_default {
+		function = "PWM14G1";
+		groups = "PWM14G1";
+	};
+
+	pinctrl_pwm15g0_default: pwm15g0_default {
+		function = "PWM15G0";
+		groups = "PWM15G0";
+	};
+
+	pinctrl_pwm15g1_default: pwm15g1_default {
+		function = "PWM15G1";
+		groups = "PWM15G1";
+	};
+
 	pinctrl_rgmii1_default: rgmii1_default {
 		function = "RGMII1";
 		groups = "RGMII1";
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
index 12cba83f6c..97e8b4ec9b 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
@@ -335,6 +335,102 @@ static struct aspeed_sig_desc pcie1rc_link[] = {
 	{ 0x500, BIT(24), 0 }, /* dedicate rc reset */
 };
 
+static struct aspeed_sig_desc pwm0[] = {
+	{0x41c, BIT(16), 0},
+};
+
+static struct aspeed_sig_desc pwm1[] = {
+	{0x41c, BIT(17), 0},
+};
+
+static struct aspeed_sig_desc pwm2[] = {
+	{0x41c, BIT(18), 0},
+};
+
+static struct aspeed_sig_desc pwm3[] = {
+	{0x41c, BIT(19), 0},
+};
+
+static struct aspeed_sig_desc pwm4[] = {
+	{0x41c, BIT(20), 0},
+};
+
+static struct aspeed_sig_desc pwm5[] = {
+	{0x41c, BIT(21), 0},
+};
+
+static struct aspeed_sig_desc pwm6[] = {
+	{0x41c, BIT(22), 0},
+};
+
+static struct aspeed_sig_desc pwm7[] = {
+	{0x41c, BIT(23), 0},
+};
+
+static struct aspeed_sig_desc pwm8g0[] = {
+	{0x4B4, BIT(8), 0},
+};
+
+static struct aspeed_sig_desc pwm8g1[] = {
+	{0x41c, BIT(24), 0},
+};
+
+static struct aspeed_sig_desc pwm9g0[] = {
+	{0x4B4, BIT(9), 0},
+};
+
+static struct aspeed_sig_desc pwm9g1[] = {
+	{0x41c, BIT(25), 0},
+};
+
+static struct aspeed_sig_desc pwm10g0[] = {
+	{0x4B4, BIT(10), 0},
+};
+
+static struct aspeed_sig_desc pwm10g1[] = {
+	{0x41c, BIT(26), 0},
+};
+
+static struct aspeed_sig_desc pwm11g0[] = {
+	{0x4B4, BIT(11), 0},
+};
+
+static struct aspeed_sig_desc pwm11g1[] = {
+	{0x41c, BIT(27), 0},
+};
+
+static struct aspeed_sig_desc pwm12g0[] = {
+	{0x4B4, BIT(12), 0},
+};
+
+static struct aspeed_sig_desc pwm12g1[] = {
+	{0x41c, BIT(28), 0},
+};
+
+static struct aspeed_sig_desc pwm13g0[] = {
+	{0x4B4, BIT(13), 0},
+};
+
+static struct aspeed_sig_desc pwm13g1[] = {
+	{0x41c, BIT(29), 0},
+};
+
+static struct aspeed_sig_desc pwm14g0[] = {
+	{0x4B4, BIT(14), 0},
+};
+
+static struct aspeed_sig_desc pwm14g1[] = {
+	{0x41c, BIT(30), 0},
+};
+
+static struct aspeed_sig_desc pwm15g0[] = {
+	{0x4B4, BIT(15), 0},
+};
+
+static struct aspeed_sig_desc pwm15g1[] = {
+	{0x41c, BIT(31), 0},
+};
+
 static const struct aspeed_group_config ast2600_groups[] = {
 	{ "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
 	{ "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
@@ -394,6 +490,30 @@ static const struct aspeed_group_config ast2600_groups[] = {
 	{ "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link },
 	{ "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link },
 	{ "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link },
+	{ "PWM0", ARRAY_SIZE(pwm0), pwm0 },
+	{ "PWM1", ARRAY_SIZE(pwm1), pwm1 },
+	{ "PWM2", ARRAY_SIZE(pwm2), pwm2 },
+	{ "PWM3", ARRAY_SIZE(pwm3), pwm3 },
+	{ "PWM4", ARRAY_SIZE(pwm4), pwm4 },
+	{ "PWM5", ARRAY_SIZE(pwm5), pwm5 },
+	{ "PWM6", ARRAY_SIZE(pwm6), pwm6 },
+	{ "PWM7", ARRAY_SIZE(pwm7), pwm7 },
+	{ "PWM8G0", ARRAY_SIZE(pwm8g0), pwm8g0 },
+	{ "PWM8G1", ARRAY_SIZE(pwm8g1), pwm8g1 },
+	{ "PWM9G0", ARRAY_SIZE(pwm9g0), pwm9g0 },
+	{ "PWM9G1", ARRAY_SIZE(pwm9g1), pwm9g1 },
+	{ "PWM10G0", ARRAY_SIZE(pwm10g0), pwm10g0 },
+	{ "PWM10G1", ARRAY_SIZE(pwm10g1), pwm10g1 },
+	{ "PWM11G0", ARRAY_SIZE(pwm11g0), pwm11g0 },
+	{ "PWM11G1", ARRAY_SIZE(pwm11g1), pwm11g1 },
+	{ "PWM12G0", ARRAY_SIZE(pwm12g0), pwm12g0 },
+	{ "PWM12G1", ARRAY_SIZE(pwm12g1), pwm12g1 },
+	{ "PWM13G0", ARRAY_SIZE(pwm13g0), pwm13g0 },
+	{ "PWM13G1", ARRAY_SIZE(pwm13g1), pwm13g1 },
+	{ "PWM14G0", ARRAY_SIZE(pwm14g0), pwm14g0 },
+	{ "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 },
+	{ "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 },
+	{ "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 },
 };
 
 static int ast2600_pinctrl_get_groups_count(struct udevice *dev)
-- 
2.25.1

[PATCH 3/3] ARM: dts: ast2600: Add PWM to device tree

[Billy Tsai]

Add the PWM node and enable it for AST2600 EVB

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
 arch/arm/dts/ast2600-evb.dts | 20 ++++++++++++++++++++
 arch/arm/dts/ast2600.dtsi    | 15 +++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index c17988ec3c..0d65054313 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -37,6 +37,26 @@
 	};
 };
 
+&pwm {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_default
+			&pinctrl_pwm1_default
+			&pinctrl_pwm2_default
+			&pinctrl_pwm3_default
+			&pinctrl_pwm4_default
+			&pinctrl_pwm5_default
+			&pinctrl_pwm6_default
+			&pinctrl_pwm7_default
+			&pinctrl_pwm8g1_default
+			&pinctrl_pwm9g1_default
+			&pinctrl_pwm10g1_default
+			&pinctrl_pwm11g1_default
+			&pinctrl_pwm12g1_default
+			&pinctrl_pwm13g1_default
+			&pinctrl_pwm14g1_default>;
+};
+
 &uart5 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index ce006a3759..64074309b7 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -113,6 +113,21 @@
 			reg = < 0x1e600000 0x100>;
 		};
 
+		pwm_tach: pwm_tach@1e610000 {
+			compatible = "aspeed,ast2600-pwm-tach", "simple-mfd", "syscon";
+			reg = <0x1e610000 0x100>;
+			clocks = <&scu ASPEED_CLK_AHB>;
+			resets = <&rst ASPEED_RESET_PWM>;
+
+			pwm: pwm {
+				compatible = "aspeed,ast2600-pwm";
+				#pwm-cells = <3>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		fmc: flash-controller@1e620000 {
 			reg = < 0x1e620000 0xc4
 				0x20000000 0x10000000 >;
-- 
2.25.1

Re: [PATCH 1/3] pwm: Add Aspeed ast2600 PWM support

[Simon Glass]

On Mon, 7 Mar 2022 at 20:02, Billy Tsai <billy_tsai@aspeedtech.com> wrote:
>
> This patch add the support of PWM controller which can be found at aspeed
> ast2600 soc. The pwm supoorts up to 16 channels and it's part function
> of multi-function device "pwm-tach controller".
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
>  drivers/pwm/Kconfig      |   8 ++
>  drivers/pwm/Makefile     |   1 +
>  drivers/pwm/pwm-aspeed.c | 251 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 260 insertions(+)
>  create mode 100644 drivers/pwm/pwm-aspeed.c

Reviewed-by: Simon Glass <sjg@chromium.org>

Re: [PATCH 2/3] pinctrl: Add the pinctrl setting for PWM.

[Simon Glass]

On Mon, 7 Mar 2022 at 20:02, Billy Tsai <billy_tsai@aspeedtech.com> wrote:
>
> This patchs add the signal description array for PWM pinctrl settings.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
>  arch/arm/dts/ast2600.dtsi                |  80 +++++++++++++++
>  drivers/pinctrl/aspeed/pinctrl_ast2600.c | 120 +++++++++++++++++++++++
>  2 files changed, 200 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

Re: [PATCH 3/3] ARM: dts: ast2600: Add PWM to device tree

[Simon Glass]

On Mon, 7 Mar 2022 at 20:02, Billy Tsai <billy_tsai@aspeedtech.com> wrote:
>
> Add the PWM node and enable it for AST2600 EVB
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
>  arch/arm/dts/ast2600-evb.dts | 20 ++++++++++++++++++++
>  arch/arm/dts/ast2600.dtsi    | 15 +++++++++++++++
>  2 files changed, 35 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

RE: [PATCH 1/3] pwm: Add Aspeed ast2600 PWM support

[ChiaWei Wang]

> From: Simon Glass <sjg@chromium.org>
> Sent: Saturday, March 12, 2022 10:44 AM
> 
> On Mon, 7 Mar 2022 at 20:02, Billy Tsai <billy_tsai@aspeedtech.com> wrote:
> >
> > This patch add the support of PWM controller which can be found at
> > aspeed
> > ast2600 soc. The pwm supoorts up to 16 channels and it's part function
> > of multi-function device "pwm-tach controller".
> >
> > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> > ---
> >  drivers/pwm/Kconfig      |   8 ++
> >  drivers/pwm/Makefile     |   1 +
> >  drivers/pwm/pwm-aspeed.c | 251
> > +++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 260 insertions(+)
> >  create mode 100644 drivers/pwm/pwm-aspeed.c
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

RE: [PATCH 2/3] pinctrl: Add the pinctrl setting for PWM.

[ChiaWei Wang]

> From: Simon Glass <sjg@chromium.org>
> Sent: Saturday, March 12, 2022 10:44 AM
> 
> On Mon, 7 Mar 2022 at 20:02, Billy Tsai <billy_tsai@aspeedtech.com> wrote:
> >
> > This patchs add the signal description array for PWM pinctrl settings.
> >
> > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> > ---
> >  arch/arm/dts/ast2600.dtsi                |  80 +++++++++++++++
> >  drivers/pinctrl/aspeed/pinctrl_ast2600.c | 120 +++++++++++++++++++++++
> >  2 files changed, 200 insertions(+)
> >
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

RE: [PATCH 3/3] ARM: dts: ast2600: Add PWM to device tree

[ChiaWei Wang]

> From: Simon Glass <sjg@chromium.org>
> Sent: Saturday, March 12, 2022 10:44 AM
> 
> On Mon, 7 Mar 2022 at 20:02, Billy Tsai <billy_tsai@aspeedtech.com> wrote:
> >
> > Add the PWM node and enable it for AST2600 EVB
> >
> > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> > ---
> >  arch/arm/dts/ast2600-evb.dts | 20 ++++++++++++++++++++
> >  arch/arm/dts/ast2600.dtsi    | 15 +++++++++++++++
> >  2 files changed, 35 insertions(+)
> >
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

Re: [PATCH 1/3] pwm: Add Aspeed ast2600 PWM support

[Tom Rini]

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On Tue, Mar 08, 2022 at 11:04:05AM +0800, Billy Tsai wrote:

> This patch add the support of PWM controller which can be found at aspeed
> ast2600 soc. The pwm supoorts up to 16 channels and it's part function
> of multi-function device "pwm-tach controller".
> 
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH 2/3] pinctrl: Add the pinctrl setting for PWM.

[Tom Rini]

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On Tue, Mar 08, 2022 at 11:04:06AM +0800, Billy Tsai wrote:

> This patchs add the signal description array for PWM pinctrl settings.
> 
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH 3/3] ARM: dts: ast2600: Add PWM to device tree

[Tom Rini]

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On Tue, Mar 08, 2022 at 11:04:07AM +0800, Billy Tsai wrote:

> Add the PWM node and enable it for AST2600 EVB
> 
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

Applied to u-boot/next, thanks!

-- 
Tom

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