[U-Boot] [PATCH] EXYNOS: SPI: Minimise access to SPI FIFO level

From: Simon Glass <sjg@chromium.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] EXYNOS: SPI: Minimise access to SPI FIFO level
Date: Sat, 11 May 2013 09:09:07 -0600	[thread overview]
Message-ID: <CAPnjgZ07gqj9bs1qmO9PoqT2XNaEfDz25fAejRJRMbv=+k8_Hw@mail.gmail.com> (raw)
In-Reply-To: <1363961377-18835-1-git-send-email-rajeshwari.s@samsung.com>

On Fri, Mar 22, 2013 at 8:09 AM, Rajeshwari Shinde
<rajeshwari.s@samsung.com> wrote:
> Accessing SPI registers is slow, but access to the FIFO level register
> in particular seems to be extraordinarily expensive (I measure up to
> 600ns). Perhaps it is required to synchronise with the SPI byte output
> logic which might run at 1/8th of the 40MHz SPI speed (just a guess).
>
> Reduce access to this register by filling up and emptying FIFOs
> more completely, rather than just one word each time around the inner
> loop.
>
> Since the rxfifo value will now likely be much greater that what we read
> before we fill the txfifo, we only fill the txfifo halfway. This is
> because if the txfifo is empty, but the rxfifo has data in it, then writing
> too much data to the txfifo may overflow the rxfifo as data arrives.
>
> This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>

Acked-by: Simon Glass <sjg@chromium.org>