* [U-Boot] [PATCH] board: sama5d4ek: fix DD2 configuration
@ 2017-03-23 6:35 Wenyou Yang
2017-04-22 3:07 ` sjg at google.com
0 siblings, 1 reply; 2+ messages in thread
From: Wenyou Yang @ 2017-03-23 6:35 UTC (permalink / raw)
To: u-boot
Fix the DDR2 configuration to make SPL work.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 7 ++++++-
board/atmel/sama5d4ek/sama5d4ek.c | 16 +++++++++++++++-
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index f6bcecda38..803501f5cf 100644
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -186,9 +186,14 @@ int ddr3_init(const unsigned int base,
#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6
#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7
-#define ATMEL_MPDDRC_IO_CALIBR_TZQIO 0x7f
+#define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8)
#define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8)
+#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16)
+#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16)
+#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20)
+#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20)
+
#define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4)
/* Bit field in Read Data Path Register */
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index d1b5ff5797..8eec0e88a5 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -349,7 +349,6 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
ATMEL_MPDDRC_CR_NR_ROW_14 |
ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
ATMEL_MPDDRC_CR_NB_8BANKS |
- ATMEL_MPDDRC_CR_NDQS_DISABLED |
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
@@ -379,6 +378,8 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
void mem_init(void)
{
struct atmel_mpddrc_config ddr2;
+ const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ u32 tmp;
ddr2_conf(&ddr2);
@@ -386,6 +387,19 @@ void mem_init(void)
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
at91_system_clk_enable(AT91_PMC_DDR);
+ tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
+ writel(tmp, &mpddr->rd_data_path);
+
+ tmp = readl(&mpddr->io_calibr);
+ tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
+ ATMEL_MPDDRC_IO_CALIBR_TZQIO |
+ ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
+ ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
+ ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
+ ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
+ ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
+ writel(tmp, &mpddr->io_calibr);
+
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
}
--
2.11.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] board: sama5d4ek: fix DD2 configuration
2017-03-23 6:35 [U-Boot] [PATCH] board: sama5d4ek: fix DD2 configuration Wenyou Yang
@ 2017-04-22 3:07 ` sjg at google.com
0 siblings, 0 replies; 2+ messages in thread
From: sjg at google.com @ 2017-04-22 3:07 UTC (permalink / raw)
To: u-boot
Fix the DDR2 configuration to make SPL work.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 7 ++++++-
board/atmel/sama5d4ek/sama5d4ek.c | 16 +++++++++++++++-
2 files changed, 21 insertions(+), 2 deletions(-)
Applied to u-boot-dm/next, thanks!
^ permalink raw reply [flat|nested] 2+ messages in thread
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2017-03-23 6:35 [U-Boot] [PATCH] board: sama5d4ek: fix DD2 configuration Wenyou Yang
2017-04-22 3:07 ` sjg at google.com
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