* [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
@ 2017-05-08 2:52 Bin Meng
2017-05-08 2:52 ` [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins Bin Meng
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Bin Meng @ 2017-05-08 2:52 UTC (permalink / raw)
To: u-boot
Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).
Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.
This also resolves the 'gpio clear | set' command warning like:
"Warning: value of pin is still 0"
Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/dts/bayleybay.dts | 6 ++++++
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 6 ++++++
arch/x86/dts/conga-qeval20-qa3-e3845.dts | 6 ++++++
arch/x86/dts/dfi-bt700.dtsi | 6 ++++++
arch/x86/dts/minnowmax.dts | 6 ++++++
drivers/gpio/intel_ich6_gpio.c | 30 ++++++++++++++++++++++-----
6 files changed, 55 insertions(+), 5 deletions(-)
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 18b310d..1ae058d 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -189,6 +189,7 @@
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
+ use-lvl-write-cache;
};
gpiob {
@@ -196,6 +197,7 @@
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
+ use-lvl-write-cache;
};
gpioc {
@@ -203,6 +205,7 @@
u-boot,dm-pre-reloc;
reg = <0x40 0x20>;
bank-name = "C";
+ use-lvl-write-cache;
};
gpiod {
@@ -210,6 +213,7 @@
u-boot,dm-pre-reloc;
reg = <0x60 0x20>;
bank-name = "D";
+ use-lvl-write-cache;
};
gpioe {
@@ -217,6 +221,7 @@
u-boot,dm-pre-reloc;
reg = <0x80 0x20>;
bank-name = "E";
+ use-lvl-write-cache;
};
gpiof {
@@ -224,6 +229,7 @@
u-boot,dm-pre-reloc;
reg = <0xA0 0x20>;
bank-name = "F";
+ use-lvl-write-cache;
};
};
};
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index e1d81a7..aa8bfb8 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -212,6 +212,7 @@
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
+ use-lvl-write-cache;
};
gpiob {
@@ -219,6 +220,7 @@
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
+ use-lvl-write-cache;
};
gpioc {
@@ -226,6 +228,7 @@
u-boot,dm-pre-reloc;
reg = <0x40 0x20>;
bank-name = "C";
+ use-lvl-write-cache;
};
gpiod {
@@ -233,6 +236,7 @@
u-boot,dm-pre-reloc;
reg = <0x60 0x20>;
bank-name = "D";
+ use-lvl-write-cache;
};
gpioe {
@@ -240,6 +244,7 @@
u-boot,dm-pre-reloc;
reg = <0x80 0x20>;
bank-name = "E";
+ use-lvl-write-cache;
};
gpiof {
@@ -247,6 +252,7 @@
u-boot,dm-pre-reloc;
reg = <0xA0 0x20>;
bank-name = "F";
+ use-lvl-write-cache;
};
};
};
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index f0efe90..898e9c9 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -199,6 +199,7 @@
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
+ use-lvl-write-cache;
};
gpiob {
@@ -206,6 +207,7 @@
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
+ use-lvl-write-cache;
};
gpioc {
@@ -213,6 +215,7 @@
u-boot,dm-pre-reloc;
reg = <0x40 0x20>;
bank-name = "C";
+ use-lvl-write-cache;
};
gpiod {
@@ -220,6 +223,7 @@
u-boot,dm-pre-reloc;
reg = <0x60 0x20>;
bank-name = "D";
+ use-lvl-write-cache;
};
gpioe {
@@ -227,6 +231,7 @@
u-boot,dm-pre-reloc;
reg = <0x80 0x20>;
bank-name = "E";
+ use-lvl-write-cache;
};
gpiof {
@@ -234,6 +239,7 @@
u-boot,dm-pre-reloc;
reg = <0xA0 0x20>;
bank-name = "F";
+ use-lvl-write-cache;
};
};
};
diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi
index 75ee6ad..546981a 100644
--- a/arch/x86/dts/dfi-bt700.dtsi
+++ b/arch/x86/dts/dfi-bt700.dtsi
@@ -201,6 +201,7 @@
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
+ use-lvl-write-cache;
};
gpiob {
@@ -208,6 +209,7 @@
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
+ use-lvl-write-cache;
};
gpioc {
@@ -215,6 +217,7 @@
u-boot,dm-pre-reloc;
reg = <0x40 0x20>;
bank-name = "C";
+ use-lvl-write-cache;
};
gpiod {
@@ -222,6 +225,7 @@
u-boot,dm-pre-reloc;
reg = <0x60 0x20>;
bank-name = "D";
+ use-lvl-write-cache;
};
gpioe {
@@ -229,6 +233,7 @@
u-boot,dm-pre-reloc;
reg = <0x80 0x20>;
bank-name = "E";
+ use-lvl-write-cache;
};
gpiof {
@@ -236,6 +241,7 @@
u-boot,dm-pre-reloc;
reg = <0xA0 0x20>;
bank-name = "F";
+ use-lvl-write-cache;
};
};
};
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index d51318b..bc382a8 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -218,6 +218,7 @@
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
+ use-lvl-write-cache;
};
gpiob {
@@ -225,6 +226,7 @@
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
+ use-lvl-write-cache;
};
gpioc {
@@ -232,6 +234,7 @@
u-boot,dm-pre-reloc;
reg = <0x40 0x20>;
bank-name = "C";
+ use-lvl-write-cache;
};
gpiod {
@@ -239,6 +242,7 @@
u-boot,dm-pre-reloc;
reg = <0x60 0x20>;
bank-name = "D";
+ use-lvl-write-cache;
};
gpioe {
@@ -246,6 +250,7 @@
u-boot,dm-pre-reloc;
reg = <0x80 0x20>;
bank-name = "E";
+ use-lvl-write-cache;
};
gpiof {
@@ -253,6 +258,7 @@
u-boot,dm-pre-reloc;
reg = <0xA0 0x20>;
bank-name = "F";
+ use-lvl-write-cache;
};
};
};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 8b78226..0a9eb03 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -46,22 +46,31 @@ struct ich6_bank_priv {
uint16_t use_sel;
uint16_t io_sel;
uint16_t lvl;
+ u32 lvl_write_cache;
+ bool use_lvl_write_cache;
};
#define GPIO_USESEL_OFFSET(x) (x)
#define GPIO_IOSEL_OFFSET(x) (x + 4)
#define GPIO_LVL_OFFSET(x) (x + 8)
-static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
+static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset,
+ int value)
{
u32 val;
- val = inl(base);
+ if (bank->use_lvl_write_cache)
+ val = bank->lvl_write_cache;
+ else
+ val = inl(bank->lvl);
+
if (value)
val |= (1UL << offset);
else
val &= ~(1UL << offset);
- outl(val, base);
+ outl(val, bank->lvl);
+ if (bank->use_lvl_write_cache)
+ bank->lvl_write_cache = val;
return 0;
}
@@ -112,6 +121,7 @@ static int ich6_gpio_probe(struct udevice *dev)
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
+ const void *prop;
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
@@ -119,6 +129,14 @@ static int ich6_gpio_probe(struct udevice *dev)
bank->io_sel = plat->base_addr + 4;
bank->lvl = plat->base_addr + 8;
+ prop = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ "use-lvl-write-cache", NULL);
+ if (prop)
+ bank->use_lvl_write_cache = true;
+ else
+ bank->use_lvl_write_cache = false;
+ bank->lvl_write_cache = 0;
+
return 0;
}
@@ -160,7 +178,7 @@ static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
if (ret)
return ret;
- return _ich6_gpio_set_value(bank->lvl, offset, value);
+ return _ich6_gpio_set_value(bank, offset, value);
}
static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
@@ -170,6 +188,8 @@ static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
int r;
tmplong = inl(bank->lvl);
+ if (bank->use_lvl_write_cache)
+ tmplong |= bank->lvl_write_cache;
r = (tmplong & (1UL << offset)) ? 1 : 0;
return r;
}
@@ -178,7 +198,7 @@ static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
struct ich6_bank_priv *bank = dev_get_priv(dev);
- return _ich6_gpio_set_value(bank->lvl, offset, value);
+ return _ich6_gpio_set_value(bank, offset, value);
}
static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
--
2.9.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins
2017-05-08 2:52 [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode Bin Meng
@ 2017-05-08 2:52 ` Bin Meng
2017-05-08 5:34 ` Stefan Roese
2017-05-15 3:02 ` Simon Glass
2017-05-08 5:34 ` [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode Stefan Roese
2017-05-15 3:02 ` Simon Glass
2 siblings, 2 replies; 8+ messages in thread
From: Bin Meng @ 2017-05-08 2:52 UTC (permalink / raw)
To: u-boot
Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
wrong. Correct value should be added by 0x2000, but since they
are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/dts/minnowmax.dts | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index bc382a8..af64c68 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -35,7 +35,6 @@
/* GPIO E0 */
soc_gpio_s5_0 at 0 {
gpio-offset = <0x80 0>;
- pad-offset = <0x1d0>;
mode-gpio;
output-value = <0>;
direction = <PIN_OUTPUT>;
@@ -44,7 +43,6 @@
/* GPIO E1 */
soc_gpio_s5_1 at 0 {
gpio-offset = <0x80 1>;
- pad-offset = <0x210>;
mode-gpio;
output-value = <0>;
direction = <PIN_OUTPUT>;
@@ -53,7 +51,6 @@
/* GPIO E2 */
soc_gpio_s5_2 at 0 {
gpio-offset = <0x80 2>;
- pad-offset = <0x1e0>;
mode-gpio;
output-value = <0>;
direction = <PIN_OUTPUT>;
@@ -61,7 +58,6 @@
pin_usb_host_en0 at 0 {
gpio-offset = <0x80 8>;
- pad-offset = <0x260>;
mode-gpio;
output-value = <1>;
direction = <PIN_OUTPUT>;
@@ -69,7 +65,6 @@
pin_usb_host_en1 at 0 {
gpio-offset = <0x80 9>;
- pad-offset = <0x250>;
mode-gpio;
output-value = <1>;
direction = <PIN_OUTPUT>;
--
2.9.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
2017-05-08 2:52 [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode Bin Meng
2017-05-08 2:52 ` [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins Bin Meng
@ 2017-05-08 5:34 ` Stefan Roese
2017-05-15 3:02 ` Simon Glass
2 siblings, 0 replies; 8+ messages in thread
From: Stefan Roese @ 2017-05-08 5:34 UTC (permalink / raw)
To: u-boot
On 08.05.2017 04:52, Bin Meng wrote:
> Add a device-tree property use-lvl-write-cache that will cause
> writes to lvl to be cached instead of read from lvl before each
> write. This is required on some platforms that have the register
> implemented as dual read/write (such as Baytrail).
>
> Prior to this fix the blue USB port on the Minnowboard Max was
> unusable since USB_HOST_EN0 was set high then immediately set
> low when USB_HOST_EN1 was written.
>
> This also resolves the 'gpio clear | set' command warning like:
> "Warning: value of pin is still 0"
>
> Signed-off-by: George McCollister <george.mccollister@gmail.com>
> <rebased on latest origin/master, fixed all baytrail boards>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins
2017-05-08 2:52 ` [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins Bin Meng
@ 2017-05-08 5:34 ` Stefan Roese
2017-05-15 3:02 ` Simon Glass
1 sibling, 0 replies; 8+ messages in thread
From: Stefan Roese @ 2017-05-08 5:34 UTC (permalink / raw)
To: u-boot
On 08.05.2017 04:52, Bin Meng wrote:
> Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
> pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
> wrong. Correct value should be added by 0x2000, but since they
> are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
2017-05-08 2:52 [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode Bin Meng
2017-05-08 2:52 ` [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins Bin Meng
2017-05-08 5:34 ` [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode Stefan Roese
@ 2017-05-15 3:02 ` Simon Glass
2017-05-17 9:15 ` Bin Meng
2 siblings, 1 reply; 8+ messages in thread
From: Simon Glass @ 2017-05-15 3:02 UTC (permalink / raw)
To: u-boot
On 7 May 2017 at 20:52, Bin Meng <bmeng.cn@gmail.com> wrote:
> Add a device-tree property use-lvl-write-cache that will cause
> writes to lvl to be cached instead of read from lvl before each
> write. This is required on some platforms that have the register
> implemented as dual read/write (such as Baytrail).
>
> Prior to this fix the blue USB port on the Minnowboard Max was
> unusable since USB_HOST_EN0 was set high then immediately set
> low when USB_HOST_EN1 was written.
>
> This also resolves the 'gpio clear | set' command warning like:
> "Warning: value of pin is still 0"
>
> Signed-off-by: George McCollister <george.mccollister@gmail.com>
> <rebased on latest origin/master, fixed all baytrail boards>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> arch/x86/dts/bayleybay.dts | 6 ++++++
> arch/x86/dts/baytrail_som-db5800-som-6867.dts | 6 ++++++
> arch/x86/dts/conga-qeval20-qa3-e3845.dts | 6 ++++++
> arch/x86/dts/dfi-bt700.dtsi | 6 ++++++
> arch/x86/dts/minnowmax.dts | 6 ++++++
> drivers/gpio/intel_ich6_gpio.c | 30 ++++++++++++++++++++++-----
> 6 files changed, 55 insertions(+), 5 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
I think we need a binding file for intel,ich6-gpio.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins
2017-05-08 2:52 ` [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins Bin Meng
2017-05-08 5:34 ` Stefan Roese
@ 2017-05-15 3:02 ` Simon Glass
2017-05-17 9:15 ` Bin Meng
1 sibling, 1 reply; 8+ messages in thread
From: Simon Glass @ 2017-05-15 3:02 UTC (permalink / raw)
To: u-boot
On 7 May 2017 at 20:52, Bin Meng <bmeng.cn@gmail.com> wrote:
> Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
> pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
> wrong. Correct value should be added by 0x2000, but since they
> are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/dts/minnowmax.dts | 5 -----
> 1 file changed, 5 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
2017-05-15 3:02 ` Simon Glass
@ 2017-05-17 9:15 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2017-05-17 9:15 UTC (permalink / raw)
To: u-boot
On Mon, May 15, 2017 at 11:02 AM, Simon Glass <sjg@chromium.org> wrote:
> On 7 May 2017 at 20:52, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Add a device-tree property use-lvl-write-cache that will cause
>> writes to lvl to be cached instead of read from lvl before each
>> write. This is required on some platforms that have the register
>> implemented as dual read/write (such as Baytrail).
>>
>> Prior to this fix the blue USB port on the Minnowboard Max was
>> unusable since USB_HOST_EN0 was set high then immediately set
>> low when USB_HOST_EN1 was written.
>>
>> This also resolves the 'gpio clear | set' command warning like:
>> "Warning: value of pin is still 0"
>>
>> Signed-off-by: George McCollister <george.mccollister@gmail.com>
>> <rebased on latest origin/master, fixed all baytrail boards>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>> arch/x86/dts/bayleybay.dts | 6 ++++++
>> arch/x86/dts/baytrail_som-db5800-som-6867.dts | 6 ++++++
>> arch/x86/dts/conga-qeval20-qa3-e3845.dts | 6 ++++++
>> arch/x86/dts/dfi-bt700.dtsi | 6 ++++++
>> arch/x86/dts/minnowmax.dts | 6 ++++++
>> drivers/gpio/intel_ich6_gpio.c | 30 ++++++++++++++++++++++-----
>> 6 files changed, 55 insertions(+), 5 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> I think we need a binding file for intel,ich6-gpio.
Yes!
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins
2017-05-15 3:02 ` Simon Glass
@ 2017-05-17 9:15 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2017-05-17 9:15 UTC (permalink / raw)
To: u-boot
On Mon, May 15, 2017 at 11:02 AM, Simon Glass <sjg@chromium.org> wrote:
> On 7 May 2017 at 20:52, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
>> pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
>> wrong. Correct value should be added by 0x2000, but since they
>> are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> arch/x86/dts/minnowmax.dts | 5 -----
>> 1 file changed, 5 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 8+ messages in thread
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2017-05-08 2:52 [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode Bin Meng
2017-05-08 2:52 ` [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins Bin Meng
2017-05-08 5:34 ` Stefan Roese
2017-05-15 3:02 ` Simon Glass
2017-05-17 9:15 ` Bin Meng
2017-05-08 5:34 ` [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode Stefan Roese
2017-05-15 3:02 ` Simon Glass
2017-05-17 9:15 ` Bin Meng
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