[U-Boot] [PATCH 0/14] ARM: UniPhier: bug fixes, refactorings and new features

[U-Boot] [PATCH 0/14] ARM: UniPhier: bug fixes, refactorings and new features

[Masahiro Yamada]

This series contains:
 - bug fixes and refactoring of SBC init code
 - add missing reset controls
 - support 1CS support card for all the SoCs
 - add xHCI driver



Masahiro Yamada (14):
  ARM: UniPhier: fix comments in PH1-Pro4 SBC code
  ARM: UniPhier: fix SBC init code
  ARM: UniPhier: split clkrst_init() into two functions
  ARM: UniPhier: enable STDMAC for EHCI
  ARM: UniPhier: remove EHCI platform devices
  ARM: UniPhier: move uniphier_ehci_reset() function
  ARM: UniPhier: replace "usb-ehci" with "generic-ehci"
  ARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4
  ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4
  ARM: UniPhier: add xHCI device nodes to PH1-Pro4 device tree
  usb: UniPhier: add UniPhier on-chip xHCI host driver support
  ARM: UniPhier: switch to xHCI for PH1-Pro4
  ARM: UniPhier: support 1CS support card for all the UniPhier SoCs
  ARM: UniPhier: consolidate MEMCONF setting code

 arch/arm/cpu/armv7/uniphier/Makefile               |   1 +
 arch/arm/cpu/armv7/uniphier/board_early_init_f.c   |   5 +
 arch/arm/cpu/armv7/uniphier/memconf.c              | 104 ++++++++++++++++++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile       |   6 +-
 arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c  |  25 +++--
 .../cpu/armv7/uniphier/ph1-ld4/early_clkrst_init.c |   1 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c   |  14 +--
 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c     |  52 +--------
 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init_3cs.c |  50 +++++++++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c      |  11 +-
 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile      |   6 +-
 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c |  40 +++++--
 .../armv7/uniphier/ph1-pro4/early_clkrst_init.c    |  26 +++++
 arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c     |   7 ++
 arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c  |  11 +-
 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c    |  38 +------
 .../arm/cpu/armv7/uniphier/ph1-pro4/sbc_init_3cs.c |  43 ++++++++
 arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c     |  11 +-
 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile      |   6 +-
 arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c |  30 +-----
 .../armv7/uniphier/ph1-sld8/early_clkrst_init.c    |   1 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c  |  14 +--
 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c    |  59 +---------
 .../arm/cpu/armv7/uniphier/ph1-sld8/sbc_init_3cs.c |  58 ++++++++++
 arch/arm/cpu/armv7/uniphier/spl.c                  |  13 ++-
 arch/arm/dts/uniphier-ph1-ld4.dtsi                 |   8 +-
 arch/arm/dts/uniphier-ph1-pro4-ref.dts             |   4 -
 arch/arm/dts/uniphier-ph1-pro4.dtsi                |  22 +++-
 arch/arm/dts/uniphier-ph1-sld3.dtsi                |  10 +-
 arch/arm/dts/uniphier-ph1-sld8.dtsi                |   8 +-
 arch/arm/include/asm/arch-uniphier/ehci-uniphier.h |  33 ------
 arch/arm/include/asm/arch-uniphier/platdevice.h    |   2 -
 arch/arm/include/asm/arch-uniphier/sc-regs.h       |  13 ++-
 arch/arm/include/asm/arch-uniphier/sg-regs.h       | 119 +--------------------
 configs/ph1_pro4_defconfig                         |   2 +-
 doc/README.uniphier                                |   3 +-
 drivers/usb/host/Kconfig                           |  10 +-
 drivers/usb/host/Makefile                          |   1 +
 drivers/usb/host/ehci-uniphier.c                   |  25 ++---
 drivers/usb/host/xhci-uniphier.c                   |  85 +++++++++++++++
 include/configs/uniphier.h                         |   3 +
 41 files changed, 538 insertions(+), 442 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/uniphier/memconf.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/early_clkrst_init.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init_3cs.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init_3cs.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/early_clkrst_init.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init_3cs.c
 delete mode 100644 arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
 create mode 100644 drivers/usb/host/xhci-uniphier.c

-- 
1.9.1

[U-Boot] [PATCH 01/14] ARM: UniPhier: fix comments in PH1-Pro4 SBC code

[Masahiro Yamada]

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
index 3c82a1a..6877029 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -35,8 +35,8 @@ void sbc_init(void)
 		/*
 		 * Boot Swap Off: boot from mask ROM
 		 * 0x00000000-0x01ffffff: mask ROM
-		 * 0x02000000-0x3effffff: memory bank (31MB)
-		 * 0x03f00000-0x3fffffff: peripherals (1MB)
+		 * 0x02000000-0x03efffff: memory bank (31MB)
+		 * 0x03f00000-0x03ffffff: peripherals (1MB)
 		 */
 		writel(0x0000be01, SBBASE0); /* dummy */
 		writel(0x0200be01, SBBASE1);
-- 
1.9.1

[U-Boot] [PATCH 02/14] ARM: UniPhier: fix SBC init code

[Masahiro Yamada]

Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c  | 11 +++++-----
 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c | 10 ++++-----
 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c | 28 ++++++++++++-------------
 3 files changed, 24 insertions(+), 25 deletions(-)

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
index 4839c94..3246465 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -25,13 +25,12 @@ void sbc_init(void)
 	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
 	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
 
-#if !defined(CONFIG_SPL_BUILD)
 	/* XECS0: boot/sub memory (boot swap = off/on) */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
 	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
 	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
 	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
+
 	/* XECS3: peripherals */
 	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
 	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
@@ -43,9 +42,9 @@ void sbc_init(void)
 	writel(0x0400bc01, SBBASE1);
 	writel(0x0800bf01, SBBASE3);
 
-#if !defined(CONFIG_SPL_BUILD)
 	/* enable access to sub memory when boot swap is on */
-	sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-#endif
+	if (boot_is_swapped())
+		sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
+
 	sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
 }
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
index 6877029..be2d8fe 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
@@ -42,13 +42,12 @@ void sbc_init(void)
 		writel(0x0200be01, SBBASE1);
 	}
 #elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-#if !defined(CONFIG_SPL_BUILD)
 	/* XECS0: boot/sub memory (boot swap = off/on) */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
 	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
 	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
 	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
+
 	/* XECS1: sub/boot memory (boot swap = off/on) */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
 	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
@@ -65,9 +64,10 @@ void sbc_init(void)
 	writel(0x0400bc01, SBBASE1); /* sub memory */
 	writel(0x0800bf01, SBBASE3); /* peripherals */
 
-#if !defined(CONFIG_SPL_BUILD)
-	sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-#endif
+	/* enable access to sub memory when boot swap is on */
+	if (boot_is_swapped())
+		sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
+
 	sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
 	writel(0x00000001, SG_LOADPINCTRL);
 
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
index 5efee9c..a2ba5dc 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,18 +19,18 @@ void sbc_init(void)
 	tmp &= 0xfffffcff;
 	writel(tmp, PC0CTRL);
 
-#if !defined(CONFIG_SPL_BUILD)
-	/* XECS0 : dummy */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
-	/* XECS1 : boot memory (always boot swap = on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+	/*
+	 * SBCTRL0* does not need settings because PH1-sLD8 has no support for
+	 * XECS0.  The boot swap must be enabled to boot from the support card.
+	 */
+
+	if (boot_is_swapped()) {
+		/* XECS1 : boot memory if boot swap is on */
+		writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+		writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+		writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+		writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+	}
 
 	/* XECS4 : sub memory */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
@@ -54,5 +54,5 @@ void sbc_init(void)
 	sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
 
 	/* dummy read to assure write process */
-	readl(SG_PINCTRL(33));
+	readl(SG_PINCTRL(0));
 }
-- 
1.9.1

[U-Boot] [PATCH 03/14] ARM: UniPhier: split clkrst_init() into two functions

[Masahiro Yamada]

Split the current clkrst_init() into two functions:

 - early_clkrst_init(): called from SPL
  Deassert the reset signals of the memory controller and some other
  basic cores.

 - clkrst_init(): called from main U-boot
  Deassert the reset signals that are necessary for the access to
  peripherals etc.

This commit fixes a bug of Denali NAND controller initialization
for PH1-LD4.  For that SoC, NAND I/O pins must be set up before
deasserting the NAND core reset signal.  Otherwise, the NAND core
hangs up.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/board_early_init_f.c   |  5 ++++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile       |  4 +--
 arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c  | 22 +++++++++++-----
 .../cpu/armv7/uniphier/ph1-ld4/early_clkrst_init.c |  1 +
 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile      |  4 +--
 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 22 +++++++++++-----
 .../armv7/uniphier/ph1-pro4/early_clkrst_init.c    | 26 +++++++++++++++++++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile      |  4 +--
 arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c | 30 +---------------------
 .../armv7/uniphier/ph1-sld8/early_clkrst_init.c    |  1 +
 arch/arm/cpu/armv7/uniphier/spl.c                  |  4 +--
 11 files changed, 74 insertions(+), 49 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/early_clkrst_init.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/early_clkrst_init.c

diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c b/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
index d25bbae..2aaebef 100644
--- a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
+++ b/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
@@ -9,6 +9,7 @@
 #include <asm/arch/board.h>
 
 void pin_init(void);
+void clkrst_init(void);
 
 int board_early_init_f(void)
 {
@@ -18,5 +19,9 @@ int board_early_init_f(void)
 
 	led_write(U, 1, , );
 
+	clkrst_init();
+
+	led_write(U, 2, , );
+
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index 72f4663..927640a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -4,10 +4,10 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
 	pll_spectrum.o umc_init.o ddrphy_init.o
 else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 endif
 
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
index 18965a9..00a21f5 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
 #include <asm/io.h>
 #include <asm/arch/sc-regs.h>
 
@@ -15,15 +14,26 @@ void clkrst_init(void)
 
 	/* deassert reset */
 	tmp = readl(SC_RSTCTRL);
-	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+#ifdef CONFIG_UNIPHIER_ETH
+	tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
 	writel(tmp, SC_RSTCTRL);
 	readl(SC_RSTCTRL); /* dummy read */
 
 	/* privide clocks */
 	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+#ifdef CONFIG_UNIPHIER_ETH
+	tmp |= SC_CLKCTRL_CLK_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	tmp |= SC_CLKCTRL_CLK_MIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_CLKCTRL_CLK_NAND;
+#endif
 	writel(tmp, SC_CLKCTRL);
 	readl(SC_CLKCTRL); /* dummy read */
 }
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/early_clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/early_clkrst_init.c
new file mode 100644
index 0000000..d7ef16b
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/early_clkrst_init.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/early_clkrst_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index e330fda..0390506 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -4,10 +4,10 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+obj-y += sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
 	pll_spectrum.o umc_init.o ddrphy_init.o
 else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 endif
 
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
index 18965a9..00a21f5 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
 #include <asm/io.h>
 #include <asm/arch/sc-regs.h>
 
@@ -15,15 +14,26 @@ void clkrst_init(void)
 
 	/* deassert reset */
 	tmp = readl(SC_RSTCTRL);
-	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+#ifdef CONFIG_UNIPHIER_ETH
+	tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
 	writel(tmp, SC_RSTCTRL);
 	readl(SC_RSTCTRL); /* dummy read */
 
 	/* privide clocks */
 	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+#ifdef CONFIG_UNIPHIER_ETH
+	tmp |= SC_CLKCTRL_CLK_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	tmp |= SC_CLKCTRL_CLK_MIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_CLKCTRL_CLK_NAND;
+#endif
 	writel(tmp, SC_CLKCTRL);
 	readl(SC_CLKCTRL); /* dummy read */
 }
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c
new file mode 100644
index 0000000..b5a4623
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+
+void early_clkrst_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL);
+	tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
+	writel(tmp, SC_RSTCTRL);
+	readl(SC_RSTCTRL); /* dummy read */
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CLK_UMC | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+	writel(tmp, SC_CLKCTRL);
+	readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index 72f4663..927640a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -4,10 +4,10 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
 	pll_spectrum.o umc_init.o ddrphy_init.o
 else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 endif
 
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
index 18965a9..8d3435d 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
@@ -1,29 +1 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
-	u32 tmp;
-
-	/* deassert reset */
-	tmp = readl(SC_RSTCTRL);
-	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
-	writel(tmp, SC_RSTCTRL);
-	readl(SC_RSTCTRL); /* dummy read */
-
-	/* privide clocks */
-	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
-	writel(tmp, SC_CLKCTRL);
-	readl(SC_CLKCTRL); /* dummy read */
-}
+#include "../ph1-ld4/clkrst_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/early_clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/early_clkrst_init.c
new file mode 100644
index 0000000..dd236b7
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/early_clkrst_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/early_clkrst_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/cpu/armv7/uniphier/spl.c
index 8a4eafc..ee6cce3 100644
--- a/arch/arm/cpu/armv7/uniphier/spl.c
+++ b/arch/arm/cpu/armv7/uniphier/spl.c
@@ -18,7 +18,7 @@ void sbc_init(void);
 void sg_init(void);
 void pll_init(void);
 void pin_init(void);
-void clkrst_init(void);
+void early_clkrst_init(void);
 int umc_init(void);
 void enable_dpll_ssc(void);
 
@@ -38,7 +38,7 @@ void spl_board_init(void)
 
 	led_write(L, 0, , );
 
-	clkrst_init();
+	early_clkrst_init();
 
 	led_write(L, 1, , );
 
-- 
1.9.1

[U-Boot] [PATCH 04/14] ARM: UniPhier: enable STDMAC for EHCI

[Masahiro Yamada]

Deassert the reset signal and provide the clock for STDMAC core.
This is necessary for the USB 2.0 host controllers.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c  | 5 ++++-
 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 5 ++++-
 arch/arm/include/asm/arch-uniphier/sc-regs.h       | 2 ++
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
index 00a21f5..fe9936a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
@@ -17,6 +17,9 @@ void clkrst_init(void)
 #ifdef CONFIG_UNIPHIER_ETH
 	tmp |= SC_RSTCTRL_NRST_ETHER;
 #endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
@@ -29,7 +32,7 @@ void clkrst_init(void)
 	tmp |= SC_CLKCTRL_CLK_ETHER;
 #endif
 #ifdef CONFIG_USB_EHCI_UNIPHIER
-	tmp |= SC_CLKCTRL_CLK_MIO;
+	tmp |= SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_STDMAC;
 #endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_CLKCTRL_CLK_NAND;
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
index 00a21f5..fe9936a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
@@ -17,6 +17,9 @@ void clkrst_init(void)
 #ifdef CONFIG_UNIPHIER_ETH
 	tmp |= SC_RSTCTRL_NRST_ETHER;
 #endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
@@ -29,7 +32,7 @@ void clkrst_init(void)
 	tmp |= SC_CLKCTRL_CLK_ETHER;
 #endif
 #ifdef CONFIG_USB_EHCI_UNIPHIER
-	tmp |= SC_CLKCTRL_CLK_MIO;
+	tmp |= SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_STDMAC;
 #endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_CLKCTRL_CLK_NAND;
diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h
index 1197bb5..daeeec9 100644
--- a/arch/arm/include/asm/arch-uniphier/sc-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h
@@ -39,6 +39,7 @@
 
 #define SC_RSTCTRL			(SC_BASE_ADDR | 0x2000)
 #define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
+#define SC_RSTCTRL_NRST_STDMAC		(0x1 << 10)
 #define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
 #define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
 #define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
@@ -49,6 +50,7 @@
 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
 #define SC_CLKCTRL_CLK_ETHER		(0x1 << 12)
 #define SC_CLKCTRL_CLK_MIO		(0x1 << 11)
+#define SC_CLKCTRL_CLK_STDMAC		(0x1 << 10)
 #define SC_CLKCTRL_CLK_UMC		(0x1 <<  4)
 #define SC_CLKCTRL_CLK_NAND		(0x1 <<  2)
 #define SC_CLKCTRL_CLK_SBC		(0x1 <<  1)
-- 
1.9.1

[U-Boot] [PATCH 05/14] ARM: UniPhier: remove EHCI platform devices

[Masahiro Yamada]

Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig).  Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers.  We still keep UART platform devices because they might
be useful for CONFIG_SPL_DM.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c   | 14 +-------------
 arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c  | 11 +----------
 arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c  | 14 +-------------
 arch/arm/include/asm/arch-uniphier/ehci-uniphier.h |  8 +-------
 arch/arm/include/asm/arch-uniphier/platdevice.h    |  2 --
 drivers/usb/host/Kconfig                           |  2 +-
 drivers/usb/host/ehci-uniphier.c                   | 14 +-------------
 7 files changed, 6 insertions(+), 59 deletions(-)

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
index 9d51299..6b69d3c 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -13,15 +13,3 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
 SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
 SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
 SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
-	{
-		.base = 0x5a800100,
-	},
-	{
-		.base = 0x5a810100,
-	},
-	{
-		.base = 0x5a820100,
-	},
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
index 31ee2a2..8625255 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -13,12 +13,3 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
 SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
 SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
 SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
-	{
-		.base = 0x5a800100,
-	},
-	{
-		.base = 0x5a810100,
-	},
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
index ea0691d..b3847d4 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -13,15 +13,3 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
 SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
 SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
 SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
-	{
-		.base = 0x5a800100,
-	},
-	{
-		.base = 0x5a810100,
-	},
-	{
-		.base = 0x5a820100,
-	},
-};
diff --git a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
index e9c5fb4..3ba3183 100644
--- a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
+++ b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -12,12 +12,6 @@
 #include <asm/io.h>
 #include "mio-regs.h"
 
-struct uniphier_ehci_platform_data {
-	unsigned long base;
-};
-
-extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[];
-
 static inline void uniphier_ehci_reset(int index, int on)
 {
 	u32 tmp;
diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/include/asm/arch-uniphier/platdevice.h
index 62a5126..cdf7d13 100644
--- a/arch/arm/include/asm/arch-uniphier/platdevice.h
+++ b/arch/arm/include/asm/arch-uniphier/platdevice.h
@@ -21,6 +21,4 @@ U_BOOT_DEVICE(serial##n) = {						\
 	.platdata = &serial_device##n					\
 };
 
-#include <asm/arch/ehci-uniphier.h>
-
 #endif /* ARCH_PLATDEVICE_H */
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 30d1457..0e005c2 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -47,7 +47,7 @@ if USB_EHCI_HCD
 
 config USB_EHCI_UNIPHIER
 	bool "Support for Panasonic UniPhier on-chip EHCI USB controller"
-	depends on ARCH_UNIPHIER
+	depends on ARCH_UNIPHIER && OF_CONTROL
 	default y
 	---help---
 	  Enables support for the on-chip EHCI controller on Panasonic
diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c
index 32a4375..d40b540 100644
--- a/drivers/usb/host/ehci-uniphier.c
+++ b/drivers/usb/host/ehci-uniphier.c
@@ -9,10 +9,9 @@
 #include <linux/err.h>
 #include <usb.h>
 #include <asm/arch/ehci-uniphier.h>
+#include <fdtdec.h>
 #include "ehci.h"
 
-#ifdef CONFIG_OF_CONTROL
-#include <fdtdec.h>
 DECLARE_GLOBAL_DATA_PTR;
 
 #define FDT		gd->fdt_blob
@@ -35,18 +34,7 @@ static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
 
 	return -ENODEV; /* not found */
 }
-#else
-static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
-{
-	*base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base;
-	return 0;
-}
-#endif
 
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
 int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
 		  struct ehci_hcor **hcor)
 {
-- 
1.9.1

[U-Boot] [PATCH 06/14] ARM: UniPhier: move uniphier_ehci_reset() function

[Masahiro Yamada]

Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/include/asm/arch-uniphier/ehci-uniphier.h | 27 ----------------------
 drivers/usb/host/ehci-uniphier.c                   | 15 +++++++++++-
 2 files changed, 14 insertions(+), 28 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-uniphier/ehci-uniphier.h

diff --git a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
deleted file mode 100644
index 3ba3183..0000000
--- a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PLAT_UNIPHIER_EHCI_H
-#define __PLAT_UNIPHIER_EHCI_H
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include "mio-regs.h"
-
-static inline void uniphier_ehci_reset(int index, int on)
-{
-	u32 tmp;
-
-	tmp = readl(MIO_USB_RSTCTRL(index));
-	if (on)
-		tmp &= ~MIO_USB_RSTCTRL_XRST;
-	else
-		tmp |= MIO_USB_RSTCTRL_XRST;
-	writel(tmp, MIO_USB_RSTCTRL(index));
-}
-
-#endif /* __PLAT_UNIPHIER_EHCI_H */
diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c
index d40b540..f5ea075 100644
--- a/drivers/usb/host/ehci-uniphier.c
+++ b/drivers/usb/host/ehci-uniphier.c
@@ -7,8 +7,9 @@
 
 #include <common.h>
 #include <linux/err.h>
+#include <asm/io.h>
 #include <usb.h>
-#include <asm/arch/ehci-uniphier.h>
+#include <asm/arch/mio-regs.h>
 #include <fdtdec.h>
 #include "ehci.h"
 
@@ -35,6 +36,18 @@ static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
 	return -ENODEV; /* not found */
 }
 
+static void uniphier_ehci_reset(int index, int on)
+{
+	u32 tmp;
+
+	tmp = readl(MIO_USB_RSTCTRL(index));
+	if (on)
+		tmp &= ~MIO_USB_RSTCTRL_XRST;
+	else
+		tmp |= MIO_USB_RSTCTRL_XRST;
+	writel(tmp, MIO_USB_RSTCTRL(index));
+}
+
 int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
 		  struct ehci_hcor **hcor)
 {
-- 
1.9.1

[U-Boot] [PATCH 07/14] ARM: UniPhier: replace "usb-ehci" with "generic-ehci"

[Masahiro Yamada]

EHCI host controllers have a common register interface.
We may wish to implement a generic EHCI driver someday.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/dts/uniphier-ph1-ld4.dtsi  |  8 ++++----
 arch/arm/dts/uniphier-ph1-pro4.dtsi |  6 +++---
 arch/arm/dts/uniphier-ph1-sld3.dtsi | 10 +++++-----
 arch/arm/dts/uniphier-ph1-sld8.dtsi |  8 ++++----
 4 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 2a3dd73..8ed7bbf 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for UniPhier PH1-LD4 SoC
  *
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -94,19 +94,19 @@
 		};
 
 		usb0: usb at 5a800100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a800100 0x100>;
 		};
 
 		usb1: usb at 5a810100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a810100 0x100>;
 		};
 
 		usb2: usb at 5a820100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a820100 0x100>;
 		};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 49e375e..3f1001b 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for UniPhier PH1-Pro4 SoC
  *
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -120,13 +120,13 @@
 		};
 
 		usb0: usb at 5a800100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a800100 0x100>;
 		};
 
 		usb1: usb at 5a810100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a810100 0x100>;
 		};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index f5529d2..88322c6 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for UniPhier PH1-sLD3 SoC
  *
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -93,25 +93,25 @@
 		};
 
 		usb0: usb at 5a800100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a800100 0x100>;
 		};
 
 		usb1: usb at 5a810100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a810100 0x100>;
 		};
 
 		usb2: usb at 5a820100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a820100 0x100>;
 		};
 
 		usb3: usb at 5a830100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a830100 0x100>;
 		};
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index 0ea76e5..1b3eb22 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for UniPhier PH1-sLD8 SoC
  *
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -94,19 +94,19 @@
 		};
 
 		usb0: usb at 5a800100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a800100 0x100>;
 		};
 
 		usb1: usb at 5a810100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a810100 0x100>;
 		};
 
 		usb2: usb at 5a820100 {
-			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a820100 0x100>;
 		};
-- 
1.9.1

[U-Boot] [PATCH 08/14] ARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4

[Masahiro Yamada]

This is necessary to use the xHCI core for PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
index 4e3d476..3335fb3 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
@@ -41,6 +41,13 @@ void pin_init(void)
 	sg_set_pinsel(54, 0);	/* NRYBY0 -> NRYBY0 */
 #endif
 
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	sg_set_pinsel(180, 0);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(181, 0);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(182, 0);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(183, 0);	/* USB1OD   -> USB1OD */
+#endif
+
 #ifdef CONFIG_USB_EHCI_UNIPHIER
 	sg_set_pinsel(184, 0);	/* USB2VBUS -> USB2VBUS */
 	sg_set_pinsel(185, 0);	/* USB2OD   -> USB2OD */
-- 
1.9.1

[U-Boot] [PATCH 09/14] ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4

[Masahiro Yamada]

This is necessary to use the USB 3.0 host controller on PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 15 +++++++++++++++
 arch/arm/include/asm/arch-uniphier/sc-regs.h       | 11 ++++++++++-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
index fe9936a..f735a9c 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
@@ -14,6 +14,10 @@ void clkrst_init(void)
 
 	/* deassert reset */
 	tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
+		SC_RSTCTRL_NRST_GIO;
+#endif
 #ifdef CONFIG_UNIPHIER_ETH
 	tmp |= SC_RSTCTRL_NRST_ETHER;
 #endif
@@ -26,6 +30,13 @@ void clkrst_init(void)
 	writel(tmp, SC_RSTCTRL);
 	readl(SC_RSTCTRL); /* dummy read */
 
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp = readl(SC_RSTCTRL2);
+	tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
+	writel(tmp, SC_RSTCTRL2);
+	readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
 	/* privide clocks */
 	tmp = readl(SC_CLKCTRL);
 #ifdef CONFIG_UNIPHIER_ETH
@@ -34,6 +45,10 @@ void clkrst_init(void)
 #ifdef CONFIG_USB_EHCI_UNIPHIER
 	tmp |= SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_STDMAC;
 #endif
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp |= SC_CLKCTRL_CLK_USB31 | SC_CLKCTRL_CLK_USB30 |
+		SC_CLKCTRL_CLK_GIO;
+#endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_CLKCTRL_CLK_NAND;
 #endif
diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h
index daeeec9..397ace8 100644
--- a/arch/arm/include/asm/arch-uniphier/sc-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h
@@ -1,7 +1,7 @@
 /*
  * UniPhier SC (System Control) block registers
  *
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -38,19 +38,28 @@
 #define SC_VPLL27BCTRL3			(SC_BASE_ADDR | 0x1298)
 
 #define SC_RSTCTRL			(SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL_NRST_USB3B0		(0x1 << 17)
+#define SC_RSTCTRL_NRST_USB3C0		(0x1 << 16)
 #define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
 #define SC_RSTCTRL_NRST_STDMAC		(0x1 << 10)
+#define SC_RSTCTRL_NRST_GIO		(0x1 <<  6)
 #define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
 #define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
 #define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
 
 #define SC_RSTCTRL2			(SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL2_NRST_USB3B1		(0x1 << 17)
+#define SC_RSTCTRL2_NRST_USB3C1		(0x1 << 16)
+
 #define SC_RSTCTRL3			(SC_BASE_ADDR | 0x2008)
 
 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL_CLK_USB31		(0x1 << 17)
+#define SC_CLKCTRL_CLK_USB30		(0x1 << 16)
 #define SC_CLKCTRL_CLK_ETHER		(0x1 << 12)
 #define SC_CLKCTRL_CLK_MIO		(0x1 << 11)
 #define SC_CLKCTRL_CLK_STDMAC		(0x1 << 10)
+#define SC_CLKCTRL_CLK_GIO		(0x1 <<  6)
 #define SC_CLKCTRL_CLK_UMC		(0x1 <<  4)
 #define SC_CLKCTRL_CLK_NAND		(0x1 <<  2)
 #define SC_CLKCTRL_CLK_SBC		(0x1 <<  1)
-- 
1.9.1

[U-Boot] [PATCH 10/14] ARM: UniPhier: add xHCI device nodes to PH1-Pro4 device tree

[Masahiro Yamada]

Each USB port corresponds to the following IP core:
 port0: xHCI (0x65a00000) SS+HS
 port1: xHCI (0x65c00000) HS (SS PHY is not implemented)
 port2: EHCI (0x5a800100) HS
 port3: EHCI (0x5a810100) HS

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/dts/uniphier-ph1-pro4-ref.dts |  4 ----
 arch/arm/dts/uniphier-ph1-pro4.dtsi    | 16 ++++++++++++++--
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index d9e7a8c..685b5a6 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -54,7 +54,3 @@
 &usb0 {
 	status = "okay";
 };
-
-&usb1 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 3f1001b..1247779 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -119,18 +119,30 @@
 			status = "ok";
 		};
 
-		usb0: usb at 5a800100 {
+		usb2: usb at 5a800100 {
 			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a800100 0x100>;
 		};
 
-		usb1: usb at 5a810100 {
+		usb3: usb at 5a810100 {
 			compatible = "panasonic,uniphier-ehci", "generic-ehci";
 			status = "disabled";
 			reg = <0x5a810100 0x100>;
 		};
 
+		usb0: usb at 65a00000 {
+			compatible = "panasonic,uniphier-xhci", "generic-xhci";
+			status = "disabled";
+			reg = <0x65a00000 0x100>;
+		};
+
+		usb1: usb at 65c00000 {
+			compatible = "panasonic,uniphier-xhci", "generic-xhci";
+			status = "disabled";
+			reg = <0x65c00000 0x100>;
+		};
+
 		nand: nand at 68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
-- 
1.9.1

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Masahiro Yamada]

Support xHCI host driver used on Panasonic UniPhier platform.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---
Hi Marek,

I want apply this patch onto u-boot-uniphier/master
to avoid conflicts.

If you are OK with it, could you issue your Acked-by tag, please?

Thanks,
Masahiro


 doc/README.uniphier              |  3 +-
 drivers/usb/host/Kconfig         |  8 ++++
 drivers/usb/host/Makefile        |  1 +
 drivers/usb/host/xhci-uniphier.c | 85 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 96 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/host/xhci-uniphier.c

diff --git a/doc/README.uniphier b/doc/README.uniphier
index aaeb50c..4902533 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -73,7 +73,8 @@ Supported devices
 
  - UART (on-chip)
  - NAND
- - USB (2.0)
+ - USB 2.0 (EHCI)
+ - USB 3.0 (xHCI)
  - LAN (on-board SMSC9118)
  - I2C
  - EEPROM (connected to the on-board I2C bus)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0e005c2..24a595f 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -17,6 +17,14 @@ config USB_XHCI
 
 if USB_XHCI_HCD
 
+config USB_XHCI_UNIPHIER
+	bool "Support for Panasonic UniPhier on-chip xHCI USB controller"
+	depends on ARCH_UNIPHIER
+	default y
+	---help---
+	  Enables support for the on-chip xHCI controller on Panasonic
+	  UniPhier SoCs.
+
 endif
 
 config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 66d6e9a..eb6f34b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
+obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
 
 # designware
 obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c
new file mode 100644
index 0000000..9bbd65f
--- /dev/null
+++ b/drivers/usb/host/xhci-uniphier.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2015 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <usb.h>
+#include <fdtdec.h>
+#include "xhci.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FDT		gd->fdt_blob
+#define COMPAT		"panasonic,uniphier-xhci"
+
+static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
+{
+	int offset;
+
+	for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
+	     offset >= 0;
+	     offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
+		if (index == 0) {
+			*base = (struct xhci_hccr *)
+					fdtdec_get_addr(FDT, offset, "reg");
+			return 0;
+		}
+		index--;
+	}
+
+	return -ENODEV; /* not found */
+}
+
+#define USB3_RST_CTRL		0x00100040
+#define IOMMU_RST_N		(1 << 5)
+#define LINK_RST_N		(1 << 4)
+
+static void uniphier_xhci_reset(void __iomem *base, int on)
+{
+	u32 tmp;
+
+	tmp = readl(base + USB3_RST_CTRL);
+
+	if (on)
+		tmp &= ~(IOMMU_RST_N | LINK_RST_N);
+	else
+		tmp |= IOMMU_RST_N | LINK_RST_N;
+
+	writel(tmp, base + USB3_RST_CTRL);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+	int ret;
+	struct xhci_hccr *cr;
+	struct xhci_hcor *or;
+
+	ret = get_uniphier_xhci_base(index, &cr);
+	if (ret < 0)
+		return ret;
+
+	uniphier_xhci_reset(cr, 0);
+
+	or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
+
+	*hccr = cr;
+	*hcor = or;
+
+	return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+	int ret;
+	struct xhci_hccr *cr;
+
+	ret = get_uniphier_xhci_base(index, &cr);
+	if (ret < 0)
+		return;
+
+	uniphier_xhci_reset(cr, 1);
+}
-- 
1.9.1

[U-Boot] [PATCH 12/14] ARM: UniPhier: switch to xHCI for PH1-Pro4

[Masahiro Yamada]

PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously.  Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 configs/ph1_pro4_defconfig | 2 +-
 include/configs/uniphier.h | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index 242bcf9..42a7a65 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -37,6 +37,6 @@ CONFIG_DM_SERIAL=y
 CONFIG_UNIPHIER_SERIAL=y
 CONFIG_DM_I2C=y
 CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_STORAGE=y
 S:CONFIG_SPL_NAND_DENALI=y
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 9420e6b..efb67d4 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -90,6 +90,8 @@
 /* #define CONFIG_SYS_ICACHE_OFF */
 /* #define CONFIG_SYS_DCACHE_OFF */
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /* Comment out the following to enable L2 cache */
 #define CONFIG_UNIPHIER_L2CACHE_ON
 
@@ -188,6 +190,7 @@
 
 /* USB */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		2
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
 #define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
 #define CONFIG_DOS_PARTITION
-- 
1.9.1

[U-Boot] [PATCH 13/14] ARM: UniPhier: support 1CS support card for all the UniPhier SoCs

[Masahiro Yamada]

Two support card variants are used with UniPhier reference boards:
 - 1 chip select support card (original CPLD)
 - 3 chip selects support card (ARIMA-compatible CPLD)

Currently, the former is only supported on PH1-Pro4, but it can be
expanded for PH1-LD4, PH1-sLD8 without any code change.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile       |  4 +-
 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c     | 51 +------------------
 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init_3cs.c | 50 ++++++++++++++++++
 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile      |  4 +-
 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c    | 32 ------------
 .../arm/cpu/armv7/uniphier/ph1-pro4/sbc_init_3cs.c | 43 ++++++++++++++++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile      |  4 +-
 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c    | 59 +---------------------
 .../arm/cpu/armv7/uniphier/ph1-sld8/sbc_init_3cs.c | 58 +++++++++++++++++++++
 9 files changed, 162 insertions(+), 143 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init_3cs.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init_3cs.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init_3cs.c

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index 927640a..5ce3d8a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -4,8 +4,10 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
+obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
 	pll_spectrum.o umc_init.o ddrphy_init.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
 else
 obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
index 3246465..656d7d7 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
@@ -1,50 +1 @@
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
-	u32 tmp;
-
-	/* system bus output enable */
-	tmp = readl(PC0CTRL);
-	tmp &= 0xfffffcff;
-	writel(tmp, PC0CTRL);
-
-	/* XECS1: sub/boot memory (boot swap = off/on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-	/* XECS0: boot/sub memory (boot swap = off/on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-
-	/* XECS3: peripherals */
-	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
-	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
-	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
-	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
-	/* base address regsiters */
-	writel(0x0000bc01, SBBASE0);
-	writel(0x0400bc01, SBBASE1);
-	writel(0x0800bf01, SBBASE3);
-
-	/* enable access to sub memory when boot swap is on */
-	if (boot_is_swapped())
-		sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-
-	sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
-}
+#include "../ph1-pro4/sbc_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init_3cs.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init_3cs.c
new file mode 100644
index 0000000..3246465
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init_3cs.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void sbc_init(void)
+{
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
+	/* XECS1: sub/boot memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+	/* XECS0: boot/sub memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+
+	/* XECS3: peripherals */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+	/* base address regsiters */
+	writel(0x0000bc01, SBBASE0);
+	writel(0x0400bc01, SBBASE1);
+	writel(0x0800bf01, SBBASE3);
+
+	/* enable access to sub memory when boot swap is on */
+	if (boot_is_swapped())
+		sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
+
+	sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index 0390506..b88525c 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -4,8 +4,10 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
+obj-y += sg_init.o pll_init.o early_clkrst_init.o \
 	pll_spectrum.o umc_init.o ddrphy_init.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
 else
 obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
index be2d8fe..fa51e40 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
@@ -12,7 +12,6 @@
 
 void sbc_init(void)
 {
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
 	/*
 	 * Only CS1 is connected to support card.
 	 * BKSZ[1:0] should be set to "01".
@@ -41,35 +40,4 @@ void sbc_init(void)
 		writel(0x0000be01, SBBASE0); /* dummy */
 		writel(0x0200be01, SBBASE1);
 	}
-#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-	/* XECS0: boot/sub memory (boot swap = off/on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-
-	/* XECS1: sub/boot memory (boot swap = off/on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-	/* XECS3: peripherals */
-	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
-	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
-	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
-	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
-	writel(0x0000bc01, SBBASE0); /* boot memory */
-	writel(0x0400bc01, SBBASE1); /* sub memory */
-	writel(0x0800bf01, SBBASE3); /* peripherals */
-
-	/* enable access to sub memory when boot swap is on */
-	if (boot_is_swapped())
-		sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-
-	sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
-	writel(0x00000001, SG_LOADPINCTRL);
-
-#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
 }
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init_3cs.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init_3cs.c
new file mode 100644
index 0000000..eaab17c
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init_3cs.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void sbc_init(void)
+{
+	/* XECS0: boot/sub memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+
+	/* XECS1: sub/boot memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+	/* XECS3: peripherals */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+	writel(0x0000bc01, SBBASE0); /* boot memory */
+	writel(0x0400bc01, SBBASE1); /* sub memory */
+	writel(0x0800bf01, SBBASE3); /* peripherals */
+
+	/* enable access to sub memory when boot swap is on */
+	if (boot_is_swapped())
+		sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
+
+	sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
+	writel(0x00000001, SG_LOADPINCTRL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index 927640a..5ce3d8a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -4,8 +4,10 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
+obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
 	pll_spectrum.o umc_init.o ddrphy_init.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
 else
 obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
index a2ba5dc..225c0d2 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
@@ -1,58 +1 @@
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
-	u32 tmp;
-
-	/* system bus output enable */
-	tmp = readl(PC0CTRL);
-	tmp &= 0xfffffcff;
-	writel(tmp, PC0CTRL);
-
-	/*
-	 * SBCTRL0* does not need settings because PH1-sLD8 has no support for
-	 * XECS0.  The boot swap must be enabled to boot from the support card.
-	 */
-
-	if (boot_is_swapped()) {
-		/* XECS1 : boot memory if boot swap is on */
-		writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-		writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-		writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-		writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-	}
-
-	/* XECS4 : sub memory */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
-
-	/* XECS5 : peripherals */
-	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
-	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
-	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
-	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
-
-	/* base address regsiters */
-	writel(0x0000bc01, SBBASE0); /* boot memory */
-	writel(0x0900bfff, SBBASE1); /* dummy */
-	writel(0x0400bc01, SBBASE4); /* sub memory */
-	writel(0x0800bf01, SBBASE5); /* peripherals */
-
-	sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
-	sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
-
-	/* dummy read to assure write process */
-	readl(SG_PINCTRL(0));
-}
+#include "../ph1-ld4/sbc_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init_3cs.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init_3cs.c
new file mode 100644
index 0000000..a2ba5dc
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init_3cs.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void sbc_init(void)
+{
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
+	/*
+	 * SBCTRL0* does not need settings because PH1-sLD8 has no support for
+	 * XECS0.  The boot swap must be enabled to boot from the support card.
+	 */
+
+	if (boot_is_swapped()) {
+		/* XECS1 : boot memory if boot swap is on */
+		writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+		writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+		writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+		writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+	}
+
+	/* XECS4 : sub memory */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
+
+	/* XECS5 : peripherals */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
+
+	/* base address regsiters */
+	writel(0x0000bc01, SBBASE0); /* boot memory */
+	writel(0x0900bfff, SBBASE1); /* dummy */
+	writel(0x0400bc01, SBBASE4); /* sub memory */
+	writel(0x0800bf01, SBBASE5); /* peripherals */
+
+	sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
+	sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
+
+	/* dummy read to assure write process */
+	readl(SG_PINCTRL(0));
+}
-- 
1.9.1

[U-Boot] [PATCH 14/14] ARM: UniPhier: consolidate MEMCONF setting code

[Masahiro Yamada]

This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.

The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/Makefile           |   1 +
 arch/arm/cpu/armv7/uniphier/memconf.c          | 104 +++++++++++++++++++++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c  |  11 +--
 arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c |  11 +--
 arch/arm/cpu/armv7/uniphier/spl.c              |  11 ++-
 arch/arm/include/asm/arch-uniphier/sg-regs.h   | 119 +------------------------
 6 files changed, 116 insertions(+), 141 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/uniphier/memconf.c

diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
index df418dd..e7a801b 100644
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -7,6 +7,7 @@ ifdef CONFIG_SPL_BUILD
 obj-y += lowlevel_init.o
 obj-y += init_page_table.o
 obj-y += spl.o
+obj-y += memconf.o
 obj-y += ddrphy_training.o
 
 else
diff --git a/arch/arm/cpu/armv7/uniphier/memconf.c b/arch/arm/cpu/armv7/uniphier/memconf.c
new file mode 100644
index 0000000..63ae735
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/memconf.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
+{
+	int size_mb = size / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case SZ_64M:
+		ret = SG_MEMCONF_CH0_SZ_64M;
+		break;
+	case SZ_128M:
+		ret = SG_MEMCONF_CH0_SZ_128M;
+		break;
+	case SZ_256M:
+		ret = SG_MEMCONF_CH0_SZ_256M;
+		break;
+	case SZ_512M:
+		ret = SG_MEMCONF_CH0_SZ_512M;
+		break;
+	case SZ_1G:
+		ret = SG_MEMCONF_CH0_SZ_1G;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH0_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH0_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+
+static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
+{
+	int size_mb = size / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case SZ_64M:
+		ret = SG_MEMCONF_CH1_SZ_64M;
+		break;
+	case SZ_128M:
+		ret = SG_MEMCONF_CH1_SZ_128M;
+		break;
+	case SZ_256M:
+		ret = SG_MEMCONF_CH1_SZ_256M;
+		break;
+	case SZ_512M:
+		ret = SG_MEMCONF_CH1_SZ_512M;
+		break;
+	case SZ_1G:
+		ret = SG_MEMCONF_CH1_SZ_1G;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH1_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH1_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+
+void memconf_init(void)
+{
+	u32 tmp;
+
+	/* Set DDR size */
+	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
+	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
+	tmp |= SG_MEMCONF_SPARSEMEM;
+#endif
+	writel(tmp, SG_MEMCONF);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
index 2cc5df6..ee2289f 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
 #include <asm/io.h>
 #include <asm/arch/sg-regs.h>
 
@@ -13,14 +12,6 @@ void sg_init(void)
 {
 	u32 tmp;
 
-	/* Set DDR size */
-	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
-	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
-	tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
-	writel(tmp, SG_MEMCONF);
-
 	/* Input ports must be enabled before deasserting reset of cores */
 	tmp = readl(SG_IECTRL);
 	tmp |= 0x1;
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
index b7c4b10..92c9190 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
 #include <asm/io.h>
 #include <asm/arch/sg-regs.h>
 
@@ -13,14 +12,6 @@ void sg_init(void)
 {
 	u32 tmp;
 
-	/* Set DDR size */
-	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
-	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
-	tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
-	writel(tmp, SG_MEMCONF);
-
 	/* Input ports must be enabled before deasserting reset of cores */
 	tmp = readl(SG_IECTRL);
 	tmp |= 1 << 6;
diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/cpu/armv7/uniphier/spl.c
index ee6cce3..2bcdbd6 100644
--- a/arch/arm/cpu/armv7/uniphier/spl.c
+++ b/arch/arm/cpu/armv7/uniphier/spl.c
@@ -18,6 +18,7 @@ void sbc_init(void);
 void sg_init(void);
 void pll_init(void);
 void pin_init(void);
+void memconf_init(void);
 void early_clkrst_init(void);
 int umc_init(void);
 void enable_dpll_ssc(void);
@@ -38,10 +39,14 @@ void spl_board_init(void)
 
 	led_write(L, 0, , );
 
-	early_clkrst_init();
+	memconf_init();
 
 	led_write(L, 1, , );
 
+	early_clkrst_init();
+
+	led_write(L, 2, , );
+
 	{
 		int res;
 
@@ -51,9 +56,9 @@ void spl_board_init(void)
 				;
 		}
 	}
-	led_write(L, 2, , );
+	led_write(L, 3, , );
 
 	enable_dpll_ssc();
 
-	led_write(L, 3, , );
+	led_write(L, 4, , );
 }
diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h
index 4ae67c8..63408d5 100644
--- a/arch/arm/include/asm/arch-uniphier/sg-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h
@@ -1,7 +1,7 @@
 /*
  * UniPhier SG (SoC Glue) block registers
  *
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -108,7 +108,6 @@
 #else
 
 #include <linux/types.h>
-#include <linux/sizes.h>
 #include <asm/io.h>
 
 static inline void sg_set_pinsel(int n, int value)
@@ -117,122 +116,6 @@ static inline void sg_set_pinsel(int n, int value)
 	       | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
 }
 
-static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
-{
-	int size_mb = size / num;
-	u32 ret;
-
-	switch (size_mb) {
-	case SZ_64M:
-		ret = SG_MEMCONF_CH0_SZ_64M;
-		break;
-	case SZ_128M:
-		ret = SG_MEMCONF_CH0_SZ_128M;
-		break;
-	case SZ_256M:
-		ret = SG_MEMCONF_CH0_SZ_256M;
-		break;
-	case SZ_512M:
-		ret = SG_MEMCONF_CH0_SZ_512M;
-		break;
-	case SZ_1G:
-		ret = SG_MEMCONF_CH0_SZ_1G;
-		break;
-	default:
-		BUG();
-		break;
-	}
-
-	switch (num) {
-	case 1:
-		ret |= SG_MEMCONF_CH0_NUM_1;
-		break;
-	case 2:
-		ret |= SG_MEMCONF_CH0_NUM_2;
-		break;
-	default:
-		BUG();
-		break;
-	}
-	return ret;
-}
-
-static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
-{
-	int size_mb = size / num;
-	u32 ret;
-
-	switch (size_mb) {
-	case SZ_64M:
-		ret = SG_MEMCONF_CH1_SZ_64M;
-		break;
-	case SZ_128M:
-		ret = SG_MEMCONF_CH1_SZ_128M;
-		break;
-	case SZ_256M:
-		ret = SG_MEMCONF_CH1_SZ_256M;
-		break;
-	case SZ_512M:
-		ret = SG_MEMCONF_CH1_SZ_512M;
-		break;
-	case SZ_1G:
-		ret = SG_MEMCONF_CH1_SZ_1G;
-		break;
-	default:
-		BUG();
-		break;
-	}
-
-	switch (num) {
-	case 1:
-		ret |= SG_MEMCONF_CH1_NUM_1;
-		break;
-	case 2:
-		ret |= SG_MEMCONF_CH1_NUM_2;
-		break;
-	default:
-		BUG();
-		break;
-	}
-	return ret;
-}
-
-static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
-{
-	int size_mb = size / num;
-	u32 ret;
-
-	switch (size_mb) {
-	case SZ_64M:
-		ret = SG_MEMCONF_CH2_SZ_64M;
-		break;
-	case SZ_128M:
-		ret = SG_MEMCONF_CH2_SZ_128M;
-		break;
-	case SZ_256M:
-		ret = SG_MEMCONF_CH2_SZ_256M;
-		break;
-	case SZ_512M:
-		ret = SG_MEMCONF_CH2_SZ_512M;
-		break;
-	default:
-		BUG();
-		break;
-	}
-
-	switch (num) {
-	case 1:
-		ret |= SG_MEMCONF_CH2_NUM_1;
-		break;
-	case 2:
-		ret |= SG_MEMCONF_CH2_NUM_2;
-		break;
-	default:
-		BUG();
-		break;
-	}
-	return ret;
-}
 #endif /* __ASSEMBLY__ */
 
 #endif /* ARCH_SG_REGS_H */
-- 
1.9.1

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Marek Vasut]

On Tuesday, February 17, 2015 at 08:00:27 AM, Masahiro Yamada wrote:
> Support xHCI host driver used on Panasonic UniPhier platform.
> 
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> ---
> Hi Marek,
> 
> I want apply this patch onto u-boot-uniphier/master
> to avoid conflicts.
> 
> If you are OK with it, could you issue your Acked-by tag, please?

[...]

> +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
> +{
> +	int offset;
> +
> +	for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
> +	     offset >= 0;
> +	     offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
> +		if (index == 0) {
> +			*base = (struct xhci_hccr *)
> +					fdtdec_get_addr(FDT, offset, "reg");

Hi!

does it make sense to check if the value returned by fdtdec_get_addr() is
valid here?

Otherwise,

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Simon Glass]

Hi Masahiro,

On 17 February 2015 at 00:00, Masahiro Yamada <yamada.m@jp.panasonic.com> wrote:
> Support xHCI host driver used on Panasonic UniPhier platform.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> ---
> Hi Marek,
>
> I want apply this patch onto u-boot-uniphier/master
> to avoid conflicts.
>
> If you are OK with it, could you issue your Acked-by tag, please?
>
> Thanks,
> Masahiro
>
>
>  doc/README.uniphier              |  3 +-
>  drivers/usb/host/Kconfig         |  8 ++++
>  drivers/usb/host/Makefile        |  1 +
>  drivers/usb/host/xhci-uniphier.c | 85 ++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 96 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/usb/host/xhci-uniphier.c
>
> diff --git a/doc/README.uniphier b/doc/README.uniphier
> index aaeb50c..4902533 100644
> --- a/doc/README.uniphier
> +++ b/doc/README.uniphier
> @@ -73,7 +73,8 @@ Supported devices
>
>   - UART (on-chip)
>   - NAND
> - - USB (2.0)
> + - USB 2.0 (EHCI)
> + - USB 3.0 (xHCI)
>   - LAN (on-board SMSC9118)
>   - I2C
>   - EEPROM (connected to the on-board I2C bus)
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 0e005c2..24a595f 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -17,6 +17,14 @@ config USB_XHCI
>
>  if USB_XHCI_HCD
>
> +config USB_XHCI_UNIPHIER
> +       bool "Support for Panasonic UniPhier on-chip xHCI USB controller"
> +       depends on ARCH_UNIPHIER
> +       default y
> +       ---help---
> +         Enables support for the on-chip xHCI controller on Panasonic
> +         UniPhier SoCs.
> +
>  endif
>
>  config USB_EHCI_HCD
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 66d6e9a..eb6f34b 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -48,6 +48,7 @@ obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
>  obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
>  obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
>  obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
> +obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
>
>  # designware
>  obj-$(CONFIG_USB_DWC2) += dwc2.o
> diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c
> new file mode 100644
> index 0000000..9bbd65f
> --- /dev/null
> +++ b/drivers/usb/host/xhci-uniphier.c
> @@ -0,0 +1,85 @@
> +/*
> + * Copyright (C) 2015 Panasonic Corporation
> + *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <linux/err.h>
> +#include <usb.h>
> +#include <fdtdec.h>
> +#include "xhci.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define FDT            gd->fdt_blob

Ick, please don't do this. Just use a local variable if you like.

> +#define COMPAT         "panasonic,uniphier-xhci"

This too.

> +
> +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
> +{
> +       int offset;
> +
> +       for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
> +            offset >= 0;
> +            offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
> +               if (index == 0) {
> +                       *base = (struct xhci_hccr *)
> +                                       fdtdec_get_addr(FDT, offset, "reg");
> +                       return 0;
> +               }
> +               index--;
> +       }

How about this"

count = fdtdec_find_aliasses_for_id(gd->fdt_blob, "usb",
COMPAT_PANASONIC_XHCI, node_list, 4);
if (index >= count)
   return -ENOENT;
offset = node_list[index];

then aliases will work. You need to ad the COMPAT to
include/fdtdec.h/c.  See ehci-tegra.c for an example.

> +
> +       return -ENODEV; /* not found */
> +}
> +
> +#define USB3_RST_CTRL          0x00100040
> +#define IOMMU_RST_N            (1 << 5)
> +#define LINK_RST_N             (1 << 4)
> +
> +static void uniphier_xhci_reset(void __iomem *base, int on)
> +{
> +       u32 tmp;
> +
> +       tmp = readl(base + USB3_RST_CTRL);
> +
> +       if (on)
> +               tmp &= ~(IOMMU_RST_N | LINK_RST_N);
> +       else
> +               tmp |= IOMMU_RST_N | LINK_RST_N;
> +
> +       writel(tmp, base + USB3_RST_CTRL);
> +}
> +
> +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
> +{
> +       int ret;
> +       struct xhci_hccr *cr;
> +       struct xhci_hcor *or;
> +
> +       ret = get_uniphier_xhci_base(index, &cr);
> +       if (ret < 0)
> +               return ret;
> +
> +       uniphier_xhci_reset(cr, 0);
> +
> +       or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
> +
> +       *hccr = cr;
> +       *hcor = or;
> +
> +       return 0;
> +}
> +
> +void xhci_hcd_stop(int index)
> +{
> +       int ret;
> +       struct xhci_hccr *cr;
> +
> +       ret = get_uniphier_xhci_base(index, &cr);
> +       if (ret < 0)
> +               return;
> +
> +       uniphier_xhci_reset(cr, 1);
> +}
> --
> 1.9.1
>

Regards,
Simon

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Masahiro Yamada]

Hi Simon,



On Tue, 17 Feb 2015 22:01:53 -0700
Simon Glass <sjg@chromium.org> wrote:

> > +#include <common.h>
> > +#include <linux/err.h>
> > +#include <usb.h>
> > +#include <fdtdec.h>
> > +#include "xhci.h"
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define FDT            gd->fdt_blob
> 
> Ick, please don't do this. Just use a local variable if you like.
>
> > +#define COMPAT         "panasonic,uniphier-xhci"
> 
> This too.

Why?
Each of them appears twice in the code.

Also, if I directly write the strings here, the line exceeds 80 columns
and the code gets unreadable for line-wrapping.


Anyway, this is not a big deal.
You have already posted DM USB patch series.
Once it is merged into the mainline, I will not have to scan a device tree
in my own driver.


> > +
> > +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
> > +{
> > +       int offset;
> > +
> > +       for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
> > +            offset >= 0;
> > +            offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
> > +               if (index == 0) {
> > +                       *base = (struct xhci_hccr *)
> > +                                       fdtdec_get_addr(FDT, offset, "reg");
> > +                       return 0;
> > +               }
> > +               index--;
> > +       }
> 
> How about this"
> 
> count = fdtdec_find_aliasses_for_id(gd->fdt_blob, "usb",
> COMPAT_PANASONIC_XHCI, node_list, 4);
> if (index >= count)
>    return -ENOENT;
> offset = node_list[index];
> 
> then aliases will work. You need to ad the COMPAT to
> include/fdtdec.h/c.  See ehci-tegra.c for an example.


I do not like this idea.


fdt_compat_id is one of what I think should be removed asap because:

  - The two separete tables,  enum fdt_compat_id  and compat_names[],
    must be maintained in sync.  If someone modifies just one of them,
    it gets broken.  Anybody who checks those two tables are arranged
     in the same order?

  - It seems ridiculous to collect many devices from various platforms
     into the common place.
    If everyone starts to follow this way, the table grows too big soon.


Moreover, I am not happy about adding aliases to my device tree again.

Rather, I am searching for an idea to avoid adding an alias to every device, like this.
http://patchwork.ozlabs.org/patch/441922/



Best Regards
Masahiro Yamada

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Masahiro Yamada]

Hi Marek,


On Tue, 17 Feb 2015 20:51:48 +0100
Marek Vasut <marex@denx.de> wrote:

> On Tuesday, February 17, 2015 at 08:00:27 AM, Masahiro Yamada wrote:
> > Support xHCI host driver used on Panasonic UniPhier platform.
> > 
> > Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> > ---
> > Hi Marek,
> > 
> > I want apply this patch onto u-boot-uniphier/master
> > to avoid conflicts.
> > 
> > If you are OK with it, could you issue your Acked-by tag, please?
> 
> [...]
> 
> > +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
> > +{
> > +	int offset;
> > +
> > +	for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
> > +	     offset >= 0;
> > +	     offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
> > +		if (index == 0) {
> > +			*base = (struct xhci_hccr *)
> > +					fdtdec_get_addr(FDT, offset, "reg");
> 
> Hi!
> 
> does it make sense to check if the value returned by fdtdec_get_addr() is
> valid here?

Yes.
I knew it, but was lazy.
Finally, I fixed it in v2.


BTW, why did we invent FDT_ADDR_T_NONE?

We had already had the suitable error code, FDT_ERR_NOTFOUND in libfdt.h
(or Linux error code in include/asm-generic/errno.h)

I do not think fdtdec functions are well-implemented.




Best Regards
Masahiro Yamada

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Marek Vasut]

On Friday, February 20, 2015 at 02:04:54 PM, Masahiro Yamada wrote:
> Hi Marek,

Hi!

> On Tue, 17 Feb 2015 20:51:48 +0100
> 
> Marek Vasut <marex@denx.de> wrote:
> > On Tuesday, February 17, 2015 at 08:00:27 AM, Masahiro Yamada wrote:
> > > Support xHCI host driver used on Panasonic UniPhier platform.
> > > 
> > > Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> > > ---
> > > Hi Marek,
> > > 
> > > I want apply this patch onto u-boot-uniphier/master
> > > to avoid conflicts.
> > > 
> > > If you are OK with it, could you issue your Acked-by tag, please?
> > 
> > [...]
> > 
> > > +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
> > > +{
> > > +	int offset;
> > > +
> > > +	for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
> > > +	     offset >= 0;
> > > +	     offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
> > > +		if (index == 0) {
> > > +			*base = (struct xhci_hccr *)
> > > +					fdtdec_get_addr(FDT, offset, "reg");
> > 
> > Hi!
> > 
> > does it make sense to check if the value returned by fdtdec_get_addr() is
> > valid here?
> 
> Yes.
> I knew it, but was lazy.
> Finally, I fixed it in v2.

Thank you ! :)

> BTW, why did we invent FDT_ADDR_T_NONE?
> 
> We had already had the suitable error code, FDT_ERR_NOTFOUND in libfdt.h
> (or Linux error code in include/asm-generic/errno.h)
> 
> I do not think fdtdec functions are well-implemented.

That's for Simon to answer.

Best regards,
Marek Vasut

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Simon Glass]

Hi Masahiro,

On 20 February 2015 at 05:12, Masahiro Yamada <yamada.m@jp.panasonic.com> wrote:
> Hi Simon,
>
>
>
> On Tue, 17 Feb 2015 22:01:53 -0700
> Simon Glass <sjg@chromium.org> wrote:
>
>> > +#include <common.h>
>> > +#include <linux/err.h>
>> > +#include <usb.h>
>> > +#include <fdtdec.h>
>> > +#include "xhci.h"
>> > +
>> > +DECLARE_GLOBAL_DATA_PTR;
>> > +
>> > +#define FDT            gd->fdt_blob
>>
>> Ick, please don't do this. Just use a local variable if you like.
>>
>> > +#define COMPAT         "panasonic,uniphier-xhci"
>>
>> This too.
>
> Why?
> Each of them appears twice in the code.

In the first case you could just a local variable as is done elsewhere
in the code:

const void *blob = gd->fdt_blob;

Then use 'blob'.

In the second case, you could easily restructure your loop to remove
the duplication. But really you should use the alias function in
fdtdec until you convert to driver model.

>
> Also, if I directly write the strings here, the line exceeds 80 columns
> and the code gets unreadable for line-wrapping.
>
>
> Anyway, this is not a big deal.
> You have already posted DM USB patch series.
> Once it is merged into the mainline, I will not have to scan a device tree
> in my own driver.

Even now you don't need to do that, as above.

>
>
>> > +
>> > +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
>> > +{
>> > +       int offset;
>> > +
>> > +       for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
>> > +            offset >= 0;
>> > +            offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
>> > +               if (index == 0) {
>> > +                       *base = (struct xhci_hccr *)
>> > +                                       fdtdec_get_addr(FDT, offset, "reg");
>> > +                       return 0;
>> > +               }
>> > +               index--;
>> > +       }
>>
>> How about this"
>>
>> count = fdtdec_find_aliasses_for_id(gd->fdt_blob, "usb",
>> COMPAT_PANASONIC_XHCI, node_list, 4);
>> if (index >= count)
>>    return -ENOENT;
>> offset = node_list[index];
>>
>> then aliases will work. You need to ad the COMPAT to
>> include/fdtdec.h/c.  See ehci-tegra.c for an example.
>
>
> I do not like this idea.
>
>
> fdt_compat_id is one of what I think should be removed asap because:
>
>   - The two separete tables,  enum fdt_compat_id  and compat_names[],
>     must be maintained in sync.  If someone modifies just one of them,
>     it gets broken.  Anybody who checks those two tables are arranged
>      in the same order?
>
>   - It seems ridiculous to collect many devices from various platforms
>      into the common place.
>     If everyone starts to follow this way, the table grows too big soon.

The purpose is that we then know which drivers are directly looking at
the device tree. As we add driver model support, we remove these
strings. When the table is empty, we can remove all that support from
fdtdec, including aliases.

>
>
> Moreover, I am not happy about adding aliases to my device tree again.
>
> Rather, I am searching for an idea to avoid adding an alias to every device, like this.
> http://patchwork.ozlabs.org/patch/441922/

This is up to you.

Bu why? It allows people to make adjustments if needed. The numbering
of devices is an important thing in U-Boot - most commands use this
although I would like one day to allow devices to be named (just use
dev->name with device tree).

Anyway this is up to you.

Regards,
Simon

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Masahiro Yamada]

Hi Simon,


On Fri, 20 Feb 2015 10:21:27 -0700
Simon Glass <sjg@chromium.org> wrote:

> Hi Masahiro,
> 
> On 20 February 2015 at 05:12, Masahiro Yamada <yamada.m@jp.panasonic.com> wrote:
> > Hi Simon,
> >
> >
> >
> > On Tue, 17 Feb 2015 22:01:53 -0700
> > Simon Glass <sjg@chromium.org> wrote:
> >
> >> > +#include <common.h>
> >> > +#include <linux/err.h>
> >> > +#include <usb.h>
> >> > +#include <fdtdec.h>
> >> > +#include "xhci.h"
> >> > +
> >> > +DECLARE_GLOBAL_DATA_PTR;
> >> > +
> >> > +#define FDT            gd->fdt_blob
> >>
> >> Ick, please don't do this. Just use a local variable if you like.
> >>
> >> > +#define COMPAT         "panasonic,uniphier-xhci"
> >>
> >> This too.
> >
> > Why?
> > Each of them appears twice in the code.
> 
> In the first case you could just a local variable as is done elsewhere
> in the code:
> 
> const void *blob = gd->fdt_blob;
> 
> Then use 'blob'.

Sounds reasonable.


> In the second case, you could easily restructure your loop to remove
> the duplication. But really you should use the alias function in
> fdtdec until you convert to driver model.
> 
> >
> > Also, if I directly write the strings here, the line exceeds 80 columns
> > and the code gets unreadable for line-wrapping.
> >
> >
> > Anyway, this is not a big deal.
> > You have already posted DM USB patch series.
> > Once it is merged into the mainline, I will not have to scan a device tree
> > in my own driver.
> 
> Even now you don't need to do that, as above.

OK.

I am still not convinced with one thing of the fdtdec_find_aliases_for_id().

I think it could take the compatibility string directly like this:

   node_offset =  fdtdec_find_aliases_for_id(gd->fdt_blob, "usb", "panasonic,uniphier-xhci", index);


Anyway, that is OK if it is temporal.

I used this helper function in v4.
http://patchwork.ozlabs.org/patch/442791/

I hope DM USB is supported in the mainline soon.



> >
> >
> >> > +
> >> > +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
> >> > +{
> >> > +       int offset;
> >> > +
> >> > +       for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
> >> > +            offset >= 0;
> >> > +            offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
> >> > +               if (index == 0) {
> >> > +                       *base = (struct xhci_hccr *)
> >> > +                                       fdtdec_get_addr(FDT, offset, "reg");
> >> > +                       return 0;
> >> > +               }
> >> > +               index--;
> >> > +       }
> >>
> >> How about this"
> >>
> >> count = fdtdec_find_aliasses_for_id(gd->fdt_blob, "usb",
> >> COMPAT_PANASONIC_XHCI, node_list, 4);
> >> if (index >= count)
> >>    return -ENOENT;
> >> offset = node_list[index];
> >>
> >> then aliases will work. You need to ad the COMPAT to
> >> include/fdtdec.h/c.  See ehci-tegra.c for an example.
> >
> >
> > I do not like this idea.
> >
> >
> > fdt_compat_id is one of what I think should be removed asap because:
> >
> >   - The two separete tables,  enum fdt_compat_id  and compat_names[],
> >     must be maintained in sync.  If someone modifies just one of them,
> >     it gets broken.  Anybody who checks those two tables are arranged
> >      in the same order?
> >
> >   - It seems ridiculous to collect many devices from various platforms
> >      into the common place.
> >     If everyone starts to follow this way, the table grows too big soon.
> 
> The purpose is that we then know which drivers are directly looking at
> the device tree. As we add driver model support, we remove these
> strings. When the table is empty, we can remove all that support from
> fdtdec, including aliases.
> 

OK.  If you assume this tabile is like a TODO list, it makes sense.




> >
> > Moreover, I am not happy about adding aliases to my device tree again.
> >
> > Rather, I am searching for an idea to avoid adding an alias to every device, like this.
> > http://patchwork.ozlabs.org/patch/441922/
> 
> This is up to you.
> 
> Bu why? It allows people to make adjustments if needed. The numbering
> of devices is an important thing in U-Boot - most commands use this
> although I would like one day to allow devices to be named (just use
> dev->name with device tree).
> 
> Anyway this is up to you.

I read your explanation and I am convinced.

Let's do not apply this series.



Best Regards
Masahiro Yamada

[U-Boot] [PATCH 11/14] usb: UniPhier: add UniPhier on-chip xHCI host driver support

[Simon Glass]

Hi Masahiro,

On 23 February 2015 at 21:54, Masahiro Yamada <yamada.m@jp.panasonic.com> wrote:
> Hi Simon,
>
>
> On Fri, 20 Feb 2015 10:21:27 -0700
> Simon Glass <sjg@chromium.org> wrote:
>
>> Hi Masahiro,
>>
>> On 20 February 2015 at 05:12, Masahiro Yamada <yamada.m@jp.panasonic.com> wrote:
>> > Hi Simon,
>> >
>> >
>> >
>> > On Tue, 17 Feb 2015 22:01:53 -0700
>> > Simon Glass <sjg@chromium.org> wrote:
>> >
>> >> > +#include <common.h>
>> >> > +#include <linux/err.h>
>> >> > +#include <usb.h>
>> >> > +#include <fdtdec.h>
>> >> > +#include "xhci.h"
>> >> > +
>> >> > +DECLARE_GLOBAL_DATA_PTR;
>> >> > +
>> >> > +#define FDT            gd->fdt_blob
>> >>
>> >> Ick, please don't do this. Just use a local variable if you like.
>> >>
>> >> > +#define COMPAT         "panasonic,uniphier-xhci"
>> >>
>> >> This too.
>> >
>> > Why?
>> > Each of them appears twice in the code.
>>
>> In the first case you could just a local variable as is done elsewhere
>> in the code:
>>
>> const void *blob = gd->fdt_blob;
>>
>> Then use 'blob'.
>
> Sounds reasonable.
>
>
>> In the second case, you could easily restructure your loop to remove
>> the duplication. But really you should use the alias function in
>> fdtdec until you convert to driver model.
>>
>> >
>> > Also, if I directly write the strings here, the line exceeds 80 columns
>> > and the code gets unreadable for line-wrapping.
>> >
>> >
>> > Anyway, this is not a big deal.
>> > You have already posted DM USB patch series.
>> > Once it is merged into the mainline, I will not have to scan a device tree
>> > in my own driver.
>>
>> Even now you don't need to do that, as above.
>
> OK.
>
> I am still not convinced with one thing of the fdtdec_find_aliases_for_id().
>
> I think it could take the compatibility string directly like this:
>
>    node_offset =  fdtdec_find_aliases_for_id(gd->fdt_blob, "usb", "panasonic,uniphier-xhci", index);
>
>
> Anyway, that is OK if it is temporal.

Yes it could - the current approach is really just to mark what needs
conversion.

>
> I used this helper function in v4.
> http://patchwork.ozlabs.org/patch/442791/
>
> I hope DM USB is supported in the mainline soon.

I think it will be. I posted a series a few weeks back and Vivek
posted a different one. I'll ping him to see if he's had a look.

>
>
>
>> >
>> >
>> >> > +
>> >> > +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
>> >> > +{
>> >> > +       int offset;
>> >> > +
>> >> > +       for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
>> >> > +            offset >= 0;
>> >> > +            offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
>> >> > +               if (index == 0) {
>> >> > +                       *base = (struct xhci_hccr *)
>> >> > +                                       fdtdec_get_addr(FDT, offset, "reg");
>> >> > +                       return 0;
>> >> > +               }
>> >> > +               index--;
>> >> > +       }
>> >>
>> >> How about this"
>> >>
>> >> count = fdtdec_find_aliasses_for_id(gd->fdt_blob, "usb",
>> >> COMPAT_PANASONIC_XHCI, node_list, 4);
>> >> if (index >= count)
>> >>    return -ENOENT;
>> >> offset = node_list[index];
>> >>
>> >> then aliases will work. You need to ad the COMPAT to
>> >> include/fdtdec.h/c.  See ehci-tegra.c for an example.
>> >
>> >
>> > I do not like this idea.
>> >
>> >
>> > fdt_compat_id is one of what I think should be removed asap because:
>> >
>> >   - The two separete tables,  enum fdt_compat_id  and compat_names[],
>> >     must be maintained in sync.  If someone modifies just one of them,
>> >     it gets broken.  Anybody who checks those two tables are arranged
>> >      in the same order?
>> >
>> >   - It seems ridiculous to collect many devices from various platforms
>> >      into the common place.
>> >     If everyone starts to follow this way, the table grows too big soon.
>>
>> The purpose is that we then know which drivers are directly looking at
>> the device tree. As we add driver model support, we remove these
>> strings. When the table is empty, we can remove all that support from
>> fdtdec, including aliases.
>>
>
> OK.  If you assume this tabile is like a TODO list, it makes sense.

Yes, we should remove it. I am chipping away at it - this morning I
sent a series that removed two fo them.

>
>
>
>
>> >
>> > Moreover, I am not happy about adding aliases to my device tree again.
>> >
>> > Rather, I am searching for an idea to avoid adding an alias to every device, like this.
>> > http://patchwork.ozlabs.org/patch/441922/
>>
>> This is up to you.
>>
>> Bu why? It allows people to make adjustments if needed. The numbering
>> of devices is an important thing in U-Boot - most commands use this
>> although I would like one day to allow devices to be named (just use
>> dev->name with device tree).
>>
>> Anyway this is up to you.
>
> I read your explanation and I am convinced.
>
> Let's do not apply this series.

OK.

Regards,
Simon