[U-Boot] [PATCH 1/5] mmc: dw_mmc: rockchip: select proper card clock

[U-Boot] [PATCH 1/5] mmc: dw_mmc: rockchip: select proper card clock

[Ziyuan Xu]

As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
used for communication between host and card devices. The real bus clock
is ciu, so let's rectify it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
---

 drivers/mmc/rockchip_dw_mmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index c36eda0..b0e52b0 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -44,7 +44,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
 
 	ret = clk_set_rate(&priv->clk, freq);
 	if (ret < 0) {
-		debug("%s: err=%d\n", __func__, ret);
+		printf("%s: err=%d\n", __func__, ret);
 		return ret;
 	}
 
@@ -109,7 +109,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	if (ret < 0)
 		return ret;
 #else
-	ret = clk_get_by_index(dev, 0, &priv->clk);
+	ret = clk_get_by_name(dev, "ciu", &priv->clk);
 	if (ret < 0)
 		return ret;
 #endif
-- 
2.7.4

[U-Boot] [PATCH 2/5] rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3036.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 7e3bf96..d866d0b 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -228,11 +228,13 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
 
 	switch (periph) {
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		con = readl(&cru->cru_clksel_con[12]);
 		mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 		div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 		break;
 	case HCLK_SDIO:
+	case SCLK_SDIO:
 		con = readl(&cru->cru_clksel_con[12]);
 		mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 		div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
@@ -265,6 +267,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
 
 	switch (periph) {
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
 			     EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 			     EMMC_DIV_MASK << EMMC_DIV_SHIFT,
@@ -272,6 +275,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
 		break;
 	case HCLK_SDIO:
+	case SCLK_SDIO:
 		rk_clrsetreg(&cru->cru_clksel_con[11],
 			     MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 			     MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@@ -307,6 +311,7 @@ static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
 	case 0 ... 63:
 		return 0;
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
 						clk->id, rate);
 		break;
-- 
2.7.4

[U-Boot] [PATCH 3/5] rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3188.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index d36cf8f..b32491d 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -269,14 +269,17 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 
 	switch (periph) {
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		con = readl(&cru->cru_clksel_con[12]);
 		div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 		break;
 	case HCLK_SDMMC:
+	case SCLK_SDMMC:
 		con = readl(&cru->cru_clksel_con[11]);
 		div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 		break;
 	case HCLK_SDIO:
+	case SCLK_SDIO:
 		con = readl(&cru->cru_clksel_con[12]);
 		div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
 		break;
@@ -298,16 +301,19 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
 
 	switch (periph) {
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
 			     EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 			     src_clk_div << EMMC_DIV_SHIFT);
 		break;
 	case HCLK_SDMMC:
+	case SCLK_SDMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[11],
 			     MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 			     src_clk_div << MMC0_DIV_SHIFT);
 		break;
 	case HCLK_SDIO:
+	case SCLK_SDIO:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
 			     SDIO_DIV_MASK << SDIO_DIV_SHIFT,
 			     src_clk_div << SDIO_DIV_SHIFT);
@@ -466,6 +472,9 @@ static ulong rk3188_clk_get_rate(struct clk *clk)
 	case HCLK_EMMC:
 	case HCLK_SDMMC:
 	case HCLK_SDIO:
+	case SCLK_EMMC:
+	case SCLK_SDMMC:
+	case SCLK_SDIO:
 		new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
 						clk->id);
 		break;
@@ -505,6 +514,9 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
 	case HCLK_EMMC:
 	case HCLK_SDMMC:
 	case HCLK_SDIO:
+	case SCLK_EMMC:
+	case SCLK_SDMMC:
+	case SCLK_SDIO:
 		new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
 						clk->id, rate);
 		break;
-- 
2.7.4

[U-Boot] [PATCH 4/5] rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3288.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 7835676..fc369dd 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -513,16 +513,19 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 
 	switch (periph) {
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		con = readl(&cru->cru_clksel_con[12]);
 		mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 		div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 		break;
 	case HCLK_SDMMC:
+	case SCLK_SDMMC:
 		con = readl(&cru->cru_clksel_con[11]);
 		mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 		div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 		break;
 	case HCLK_SDIO0:
+	case SCLK_SDIO0:
 		con = readl(&cru->cru_clksel_con[12]);
 		mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
 		div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
@@ -556,6 +559,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 	}
 	switch (periph) {
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
 			     EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 			     EMMC_DIV_MASK << EMMC_DIV_SHIFT,
@@ -563,6 +567,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
 		break;
 	case HCLK_SDMMC:
+	case SCLK_SDMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[11],
 			     MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 			     MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@@ -570,6 +575,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
 		break;
 	case HCLK_SDIO0:
+	case SCLK_SDIO0:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
 			     SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
 			     SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
@@ -662,6 +668,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
 	case HCLK_EMMC:
 	case HCLK_SDMMC:
 	case HCLK_SDIO0:
+	case SCLK_EMMC:
+	case SCLK_SDMMC:
+	case SCLK_SDIO0:
 		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 		break;
 	case SCLK_SPI0:
@@ -706,6 +715,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 	case HCLK_EMMC:
 	case HCLK_SDMMC:
 	case HCLK_SDIO0:
+	case SCLK_EMMC:
+	case SCLK_SDMMC:
+	case SCLK_SDIO0:
 		new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 		break;
 	case SCLK_SPI0:
-- 
2.7.4

[U-Boot] [PATCH 5/5] rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3328.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 0ff1e30..8ec1574 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -397,9 +397,11 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
 
 	switch (clk_id) {
 	case HCLK_SDMMC:
+	case SCLK_SDMMC:
 		con_id = 30;
 		break;
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		con_id = 32;
 		break;
 	default:
@@ -423,9 +425,11 @@ static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
 
 	switch (clk_id) {
 	case HCLK_SDMMC:
+	case SCLK_SDMMC:
 		con_id = 30;
 		break;
 	case HCLK_EMMC:
+	case SCLK_EMMC:
 		con_id = 32;
 		break;
 	default:
@@ -483,6 +487,8 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
 		return 0;
 	case HCLK_SDMMC:
 	case HCLK_EMMC:
+	case SCLK_SDMMC:
+	case SCLK_EMMC:
 		rate = rk3328_mmc_get_clk(priv->cru, clk->id);
 		break;
 	case SCLK_I2C0:
@@ -511,6 +517,8 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
 		return 0;
 	case HCLK_SDMMC:
 	case HCLK_EMMC:
+	case SCLK_SDMMC:
+	case SCLK_EMMC:
 		ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
 		break;
 	case SCLK_I2C0:
-- 
2.7.4

[U-Boot] [PATCH 1/5] mmc: dw_mmc: rockchip: select proper card clock

[Simon Glass]

On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
> used for communication between host and card devices. The real bus clock
> is ciu, so let's rectify it.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
> ---
>
>  drivers/mmc/rockchip_dw_mmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 2/5] rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

[Simon Glass]

On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
> ---
>
>  drivers/clk/rockchip/clk_rk3036.c | 5 +++++
>  1 file changed, 5 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/5] rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

[Simon Glass]

On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
> it.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
> ---
>
>  drivers/clk/rockchip/clk_rk3188.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 4/5] rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO

[Simon Glass]

On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
> it.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
> ---
>
>  drivers/clk/rockchip/clk_rk3288.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 5/5] rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

[Simon Glass]

On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
> ---
>
>  drivers/clk/rockchip/clk_rk3328.c | 8 ++++++++
>  1 file changed, 8 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 1/5] mmc: dw_mmc: rockchip: select proper card clock

[Simon Glass]

On 16 April 2017 at 13:34, Simon Glass <sjg@chromium.org> wrote:
> On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
>> used for communication between host and card devices. The real bus clock
>> is ciu, so let's rectify it.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>> ---
>>
>>  drivers/mmc/rockchip_dw_mmc.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH 2/5] rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

[Simon Glass]

On 16 April 2017 at 13:34, Simon Glass <sjg@chromium.org> wrote:
> On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>> ---
>>
>>  drivers/clk/rockchip/clk_rk3036.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH 3/5] rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

[Simon Glass]

On 16 April 2017 at 13:34, Simon Glass <sjg@chromium.org> wrote:
> On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
>> it.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>> ---
>>
>>  drivers/clk/rockchip/clk_rk3188.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH 4/5] rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO

[Simon Glass]

On 16 April 2017 at 13:34, Simon Glass <sjg@chromium.org> wrote:
> On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
>> it.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>> ---
>>
>>  drivers/clk/rockchip/clk_rk3288.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH 5/5] rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

[Simon Glass]

On 16 April 2017 at 13:34, Simon Glass <sjg@chromium.org> wrote:
> On 16 April 2017 at 03:44, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>> ---
>>
>>  drivers/clk/rockchip/clk_rk3328.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!