* [U-Boot] [PATCH 0/4] Tegra210 support for P2571
@ 2015-06-03 20:35 Tom Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210 Tom Warren
` (4 more replies)
0 siblings, 5 replies; 21+ messages in thread
From: Tom Warren @ 2015-06-03 20:35 UTC (permalink / raw)
To: u-boot
Adds support for Tegra210 SoC and P2571 NVIDIA board.
Largely based on T124/Venice2. This is a baseline
patchset - more will follow to make things more T210-
specific as P2571 peripherals/devices are brought up.
Tom Warren (4):
ARM: Tegra210: Add SoC code/include files for T210
ARM: Tegra210: Add support to common Tegra source/config files
P2572: dts: Add DT files for Tegra210/P2572 board
T210: Add support for T210-based P2571 board
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/tegra210-p2571.dts | 106 ++
arch/arm/dts/tegra210.dtsi | 511 ++++++++++
arch/arm/include/asm/arch-tegra/ap.h | 6 +-
arch/arm/include/asm/arch-tegra/clk_rst.h | 28 +-
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 3 +-
arch/arm/include/asm/arch-tegra/pmc.h | 7 +-
arch/arm/include/asm/arch-tegra/tegra.h | 4 +-
arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++
arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++++++++++
arch/arm/include/asm/arch-tegra210/clock.h | 27 +
arch/arm/include/asm/arch-tegra210/flow.h | 45 +
arch/arm/include/asm/arch-tegra210/funcmux.h | 23 +
arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++
arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++++++
arch/arm/include/asm/arch-tegra210/hardware.h | 16 +
arch/arm/include/asm/arch-tegra210/mc.h | 72 ++
arch/arm/include/asm/arch-tegra210/pmu.h | 14 +
arch/arm/include/asm/arch-tegra210/powergate.h | 12 +
arch/arm/include/asm/arch-tegra210/sysctr.h | 26 +
arch/arm/include/asm/arch-tegra210/tegra.h | 32 +
arch/arm/mach-tegra/Kconfig | 4 +
arch/arm/mach-tegra/Makefile | 4 +-
arch/arm/mach-tegra/ap.c | 9 +-
arch/arm/mach-tegra/clock.c | 3 +-
arch/arm/mach-tegra/cpu.c | 55 +-
arch/arm/mach-tegra/cpu.h | 10 +-
arch/arm/mach-tegra/tegra210/Kconfig | 18 +
arch/arm/mach-tegra/tegra210/Makefile | 13 +
arch/arm/mach-tegra/tegra210/clock.c | 1086 +++++++++++++++++++++
arch/arm/mach-tegra/tegra210/cpu.c | 328 +++++++
arch/arm/mach-tegra/tegra210/funcmux.c | 71 ++
arch/arm/mach-tegra/tegra210/xusb-padctl.c | 494 ++++++++++
board/nvidia/p2571/Kconfig | 12 +
board/nvidia/p2571/MAINTAINERS | 6 +
board/nvidia/p2571/Makefile | 9 +
board/nvidia/p2571/max77620_init.c | 47 +
board/nvidia/p2571/max77620_init.h | 14 +
board/nvidia/p2571/p2571.c | 29 +
board/nvidia/p2571/pinmux-config-p2571.h | 235 +++++
configs/p2571_defconfig | 5 +
include/configs/p2571.h | 72 ++
include/configs/tegra210-common.h | 73 ++
include/dt-bindings/clock/tegra210-car.h | 342 +++++++
include/fdtdec.h | 4 +
lib/fdtdec.c | 3 +
46 files changed, 4878 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/dts/tegra210-p2571.dts
create mode 100644 arch/arm/dts/tegra210.dtsi
create mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock-tables.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock.h
create mode 100644 arch/arm/include/asm/arch-tegra210/flow.h
create mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h
create mode 100644 arch/arm/include/asm/arch-tegra210/hardware.h
create mode 100644 arch/arm/include/asm/arch-tegra210/mc.h
create mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h
create mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h
create mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h
create mode 100644 arch/arm/mach-tegra/tegra210/Kconfig
create mode 100644 arch/arm/mach-tegra/tegra210/Makefile
create mode 100644 arch/arm/mach-tegra/tegra210/clock.c
create mode 100644 arch/arm/mach-tegra/tegra210/cpu.c
create mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c
create mode 100644 arch/arm/mach-tegra/tegra210/xusb-padctl.c
create mode 100644 board/nvidia/p2571/Kconfig
create mode 100644 board/nvidia/p2571/MAINTAINERS
create mode 100644 board/nvidia/p2571/Makefile
create mode 100644 board/nvidia/p2571/max77620_init.c
create mode 100644 board/nvidia/p2571/max77620_init.h
create mode 100644 board/nvidia/p2571/p2571.c
create mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
create mode 100644 configs/p2571_defconfig
create mode 100644 include/configs/p2571.h
create mode 100644 include/configs/tegra210-common.h
create mode 100644 include/dt-bindings/clock/tegra210-car.h
--
1.8.2.1.610.g562af5b
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
2015-06-03 20:35 [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Tom Warren
@ 2015-06-03 20:35 ` Tom Warren
2015-06-15 17:11 ` Stephen Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 2/4] ARM: Tegra210: Add support to common Tegra source/config files Tom Warren
` (3 subsequent siblings)
4 siblings, 1 reply; 21+ messages in thread
From: Tom Warren @ 2015-06-03 20:35 UTC (permalink / raw)
To: u-boot
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++
arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++++++++++
arch/arm/include/asm/arch-tegra210/clock.h | 27 +
arch/arm/include/asm/arch-tegra210/flow.h | 45 +
arch/arm/include/asm/arch-tegra210/funcmux.h | 23 +
arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++
arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++++++
arch/arm/include/asm/arch-tegra210/hardware.h | 16 +
arch/arm/include/asm/arch-tegra210/mc.h | 72 ++
arch/arm/include/asm/arch-tegra210/pmu.h | 14 +
arch/arm/include/asm/arch-tegra210/powergate.h | 12 +
arch/arm/include/asm/arch-tegra210/sysctr.h | 26 +
arch/arm/include/asm/arch-tegra210/tegra.h | 32 +
arch/arm/mach-tegra/tegra210/Kconfig | 11 +
arch/arm/mach-tegra/tegra210/Makefile | 13 +
arch/arm/mach-tegra/tegra210/clock.c | 1086 +++++++++++++++++++++
arch/arm/mach-tegra/tegra210/cpu.c | 328 +++++++
arch/arm/mach-tegra/tegra210/funcmux.c | 71 ++
arch/arm/mach-tegra/tegra210/xusb-padctl.c | 494 ++++++++++
include/dt-bindings/clock/tegra210-car.h | 342 +++++++
20 files changed, 3646 insertions(+)
create mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock-tables.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock.h
create mode 100644 arch/arm/include/asm/arch-tegra210/flow.h
create mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h
create mode 100644 arch/arm/include/asm/arch-tegra210/hardware.h
create mode 100644 arch/arm/include/asm/arch-tegra210/mc.h
create mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h
create mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h
create mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h
create mode 100644 arch/arm/mach-tegra/tegra210/Kconfig
create mode 100644 arch/arm/mach-tegra/tegra210/Makefile
create mode 100644 arch/arm/mach-tegra/tegra210/clock.c
create mode 100644 arch/arm/mach-tegra/tegra210/cpu.c
create mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c
create mode 100644 arch/arm/mach-tegra/tegra210/xusb-padctl.c
create mode 100644 include/dt-bindings/clock/tegra210-car.h
diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h b/arch/arm/include/asm/arch-tegra210/ahb.h
new file mode 100644
index 0000000..3a37af4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/ahb.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_AHB_H_
+#define _TEGRA210_AHB_H_
+
+struct ahb_ctlr {
+ u32 reserved0; /* 00h */
+ u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
+ u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
+ u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
+ u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
+ u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
+ u32 reserved6[2]; /* 18h, 1ch */
+ u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
+ u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
+ u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
+ u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
+ u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */
+ u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
+ u32 reserved13[2]; /* 38h, 3ch */
+ u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
+ u32 reserved15; /* 44h */
+ u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
+ u32 reserved17; /* 4ch */
+ u32 gizmo_se; /* _GIZMO_SE_0, 50h */
+ u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */
+ u32 reserved20[3]; /* 58h, 5ch, 60h */
+ u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
+ u32 reserved22[3]; /* 68h, 6ch, 70h */
+ u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
+ u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */
+ u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */
+ u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */
+ u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */
+ u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */
+ u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */
+ u32 reserved30[13]; /* 90h ~ c0h */
+ u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */
+ u32 reserved32[5]; /* c8h ~ d8h */
+ u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */
+ u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */
+ u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */
+ u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */
+ u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */
+ u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */
+ u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */
+ u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */
+ /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+ u32 arbitration_ahb_mem_wrque_mst_id;
+ u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+ u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+ u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+ u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+ u32 reserved46[4]; /* 110h ~ 11ch */
+ u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */
+ u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */
+ u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */
+ u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */
+ u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */
+ u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+ /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */
+ u32 axicif_fastsync0_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+ u32 axicif_fastsync1_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+ u32 axicif_fastsync2_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+ u32 axicif_fastsync0_mcclk_to_cpuclk;
+ /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+ u32 axicif_fastsync1_mcclk_to_cpuclk;
+ /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+ u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE (1 << 2)
+
+#define GIZ_ENABLE_SPLIT (1 << 0)
+#define GIZ_ENB_FAST_REARB (1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR (1 << 7)
+
+#define GIZ_USB_IMMEDIATE (1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2)
+
+#endif /* _TEGRA210_AHB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h
new file mode 100644
index 0000000..b62e070
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h
@@ -0,0 +1,566 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra210 clock PLL tables */
+
+#ifndef _TEGRA210_CLOCK_TABLES_H_
+#define _TEGRA210_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+ CLOCK_ID_FIRST,
+ CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+ CLOCK_ID_MEMORY,
+ CLOCK_ID_PERIPH,
+ CLOCK_ID_AUDIO,
+ CLOCK_ID_USB,
+ CLOCK_ID_DISPLAY,
+
+ /* now the simple ones */
+ CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_EPCI,
+ CLOCK_ID_SFROM32KHZ,
+
+ /* These are the base clocks (inputs to the Tegra SoC) */
+ CLOCK_ID_32KHZ,
+ CLOCK_ID_OSC,
+
+ CLOCK_ID_COUNT, /* number of PLLs */
+
+ /*
+ * These are clock IDs that are used in table clock_source[][]
+ * but will not be assigned as a clock source for any peripheral.
+ */
+ CLOCK_ID_DISPLAY2,
+ CLOCK_ID_CGENERAL_0,
+ CLOCK_ID_CGENERAL_1,
+ CLOCK_ID_CGENERAL2,
+ CLOCK_ID_CGENERAL3,
+ CLOCK_ID_CGENERAL4_0,
+ CLOCK_ID_CGENERAL4_1,
+ CLOCK_ID_CGENERAL4_2,
+ CLOCK_ID_MEMORY2,
+ CLOCK_ID_SRC2,
+
+ CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+ PERIPH_ID_FIRST,
+
+ /* Low word: 31:0 (DEVICES_L) */
+ PERIPH_ID_CPU = PERIPH_ID_FIRST,
+ PERIPH_ID_COP,
+ PERIPH_ID_TRIGSYS,
+ PERIPH_ID_ISPB,
+ PERIPH_ID_RESERVED4,
+ PERIPH_ID_TMR,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+
+ /* 8 */
+ PERIPH_ID_GPIO,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_RESERVED13,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC4,
+
+ /* 16 */
+ PERIPH_ID_TCW,
+ PERIPH_ID_PWM,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_RESERVED19,
+ PERIPH_ID_VI,
+ PERIPH_ID_RESERVED21,
+ PERIPH_ID_USBD,
+ PERIPH_ID_ISP,
+
+ /* 24 */
+ PERIPH_ID_RESERVED24,
+ PERIPH_ID_RESERVED25,
+ PERIPH_ID_DISP2,
+ PERIPH_ID_DISP1,
+ PERIPH_ID_HOST1X,
+ PERIPH_ID_VCP,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_CACHE2,
+
+ /* Middle word: 63:32 (DEVICES_H) */
+ PERIPH_ID_MEM,
+ PERIPH_ID_AHBDMA,
+ PERIPH_ID_APBDMA,
+ PERIPH_ID_RESERVED35,
+ PERIPH_ID_RESERVED36,
+ PERIPH_ID_STAT_MON,
+ PERIPH_ID_RESERVED38,
+ PERIPH_ID_FUSE,
+
+ /* 40 */
+ PERIPH_ID_KFUSE,
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SNOR,
+ PERIPH_ID_RESERVED43,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_XIO,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_I2C5,
+
+ /* 48 */
+ PERIPH_ID_DSI,
+ PERIPH_ID_RESERVED49,
+ PERIPH_ID_HSI,
+ PERIPH_ID_HDMI,
+ PERIPH_ID_CSI,
+ PERIPH_ID_RESERVED53,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_UART3,
+
+ /* 56 */
+ PERIPH_ID_MIPI_CAL,
+ PERIPH_ID_EMC,
+ PERIPH_ID_USB2,
+ PERIPH_ID_USB3,
+ PERIPH_ID_RESERVED60,
+ PERIPH_ID_VDE,
+ PERIPH_ID_BSEA,
+ PERIPH_ID_BSEV,
+
+ /* Upper word 95:64 (DEVICES_U) */
+ PERIPH_ID_RESERVED64,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_PCIE,
+ PERIPH_ID_OWR,
+
+ /* 72 */
+ PERIPH_ID_AFI,
+ PERIPH_ID_CORESIGHT,
+ PERIPH_ID_PCIEXCLK,
+ PERIPH_ID_AVPUCQ,
+ PERIPH_ID_LA,
+ PERIPH_ID_TRACECLKIN,
+ PERIPH_ID_SOC_THERM,
+ PERIPH_ID_DTV,
+
+ /* 80 */
+ PERIPH_ID_RESERVED80,
+ PERIPH_ID_I2CSLOW,
+ PERIPH_ID_DSIB,
+ PERIPH_ID_TSEC,
+ PERIPH_ID_RESERVED84,
+ PERIPH_ID_RESERVED85,
+ PERIPH_ID_RESERVED86,
+ PERIPH_ID_EMUCIF,
+
+ /* 88 */
+ PERIPH_ID_RESERVED88,
+ PERIPH_ID_XUSB_HOST,
+ PERIPH_ID_RESERVED90,
+ PERIPH_ID_MSENC,
+ PERIPH_ID_RESERVED92,
+ PERIPH_ID_RESERVED93,
+ PERIPH_ID_RESERVED94,
+ PERIPH_ID_XUSB_DEV,
+
+ PERIPH_ID_VW_FIRST,
+ /* V word: 31:0 */
+ PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+ PERIPH_ID_CPULP,
+ PERIPH_ID_V_RESERVED2,
+ PERIPH_ID_MSELECT,
+ PERIPH_ID_V_RESERVED4,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_I2S5,
+ PERIPH_ID_I2C4,
+
+ /* 104 */
+ PERIPH_ID_SBC5,
+ PERIPH_ID_SBC6,
+ PERIPH_ID_AHUB,
+ PERIPH_ID_APB2APE,
+ PERIPH_ID_V_RESERVED12,
+ PERIPH_ID_V_RESERVED13,
+ PERIPH_ID_V_RESERVED14,
+ PERIPH_ID_HDA2CODEC2X,
+
+ /* 112 */
+ PERIPH_ID_ATOMICS,
+ PERIPH_ID_V_RESERVED17,
+ PERIPH_ID_V_RESERVED18,
+ PERIPH_ID_V_RESERVED19,
+ PERIPH_ID_V_RESERVED20,
+ PERIPH_ID_V_RESERVED21,
+ PERIPH_ID_V_RESERVED22,
+ PERIPH_ID_ACTMON,
+
+ /* 120 */
+ PERIPH_ID_EXTPERIPH1,
+ PERIPH_ID_EXTPERIPH2,
+ PERIPH_ID_EXTPERIPH3,
+ PERIPH_ID_OOB,
+ PERIPH_ID_SATA,
+ PERIPH_ID_HDA,
+ PERIPH_ID_V_RESERVED30,
+ PERIPH_ID_V_RESERVED31,
+
+ /* W word: 31:0 */
+ PERIPH_ID_HDA2HDMICODEC,
+ PERIPH_ID_SATACOLD,
+ PERIPH_ID_W_RESERVED2,
+ PERIPH_ID_W_RESERVED3,
+ PERIPH_ID_W_RESERVED4,
+ PERIPH_ID_W_RESERVED5,
+ PERIPH_ID_W_RESERVED6,
+ PERIPH_ID_W_RESERVED7,
+
+ /* 136 */
+ PERIPH_ID_CEC,
+ PERIPH_ID_W_RESERVED9,
+ PERIPH_ID_W_RESERVED10,
+ PERIPH_ID_W_RESERVED11,
+ PERIPH_ID_W_RESERVED12,
+ PERIPH_ID_W_RESERVED13,
+ PERIPH_ID_XUSB_PADCTL,
+ PERIPH_ID_W_RESERVED15,
+
+ /* 144 */
+ PERIPH_ID_W_RESERVED16,
+ PERIPH_ID_W_RESERVED17,
+ PERIPH_ID_W_RESERVED18,
+ PERIPH_ID_W_RESERVED19,
+ PERIPH_ID_W_RESERVED20,
+ PERIPH_ID_ENTROPY,
+ PERIPH_ID_DDS,
+ PERIPH_ID_W_RESERVED23,
+
+ /* 152 */
+ PERIPH_ID_W_RESERVED24,
+ PERIPH_ID_W_RESERVED25,
+ PERIPH_ID_W_RESERVED26,
+ PERIPH_ID_DVFS,
+ PERIPH_ID_XUSB_SS,
+ PERIPH_ID_W_RESERVED29,
+ PERIPH_ID_W_RESERVED30,
+ PERIPH_ID_W_RESERVED31,
+
+ PERIPH_ID_X_FIRST,
+ /* X word: 31:0 */
+ PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+ PERIPH_ID_X_RESERVED1,
+ PERIPH_ID_X_RESERVED2,
+ PERIPH_ID_X_RESERVED3,
+ PERIPH_ID_CAM_MCLK,
+ PERIPH_ID_CAM_MCLK2,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_X_RESERVED7,
+
+ /* 168 */
+ PERIPH_ID_X_RESERVED8,
+ PERIPH_ID_X_RESERVED9,
+ PERIPH_ID_X_RESERVED10,
+ PERIPH_ID_VIM2_CLK,
+ PERIPH_ID_X_RESERVED12,
+ PERIPH_ID_X_RESERVED13,
+ PERIPH_ID_EMC_DLL,
+ PERIPH_ID_X_RESERVED15,
+
+ /* 176 */
+ PERIPH_ID_HDMI_AUDIO,
+ PERIPH_ID_CLK72MHZ,
+ PERIPH_ID_VIC,
+ PERIPH_ID_X_RESERVED19,
+ PERIPH_ID_X_RESERVED20,
+ PERIPH_ID_DPAUX,
+ PERIPH_ID_SOR0,
+ PERIPH_ID_X_RESERVED23,
+
+ /* 184 */
+ PERIPH_ID_GPU,
+ PERIPH_ID_X_RESERVED25,
+ PERIPH_ID_X_RESERVED26,
+ PERIPH_ID_X_RESERVED27,
+ PERIPH_ID_X_RESERVED28,
+ PERIPH_ID_X_RESERVED29,
+ PERIPH_ID_X_RESERVED30,
+ PERIPH_ID_X_RESERVED31,
+
+ PERIPH_ID_Y_FIRST,
+ /* Y word: 31:0 (192:223) */
+ PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST,
+ PERIPH_ID_Y_RESERVED1,
+ PERIPH_ID_Y_RESERVED2,
+ PERIPH_ID_Y_RESERVED3,
+ PERIPH_ID_Y_RESERVED4,
+ PERIPH_ID_Y_RESERVED5,
+ PERIPH_ID_APE,
+ PERIPH_ID_Y_RESERVED7,
+
+ /* 200 */
+ PERIPH_ID_MC_CDPA,
+ PERIPH_ID_Y_RESERVED9,
+ PERIPH_ID_Y_RESERVED10,
+ PERIPH_ID_Y_RESERVED11,
+ PERIPH_ID_Y_RESERVED12,
+ PERIPH_ID_PEX_USB_UPHY,
+ PERIPH_ID_Y_RESERVED14,
+ PERIPH_ID_Y_RESERVED15,
+
+ /* 208 */
+ PERIPH_ID_VI_I2C,
+ PERIPH_ID_Y_RESERVED17,
+ PERIPH_ID_Y_RESERVED18,
+ PERIPH_ID_QSPI,
+ PERIPH_ID_Y_RESERVED20,
+ PERIPH_ID_Y_RESERVED21,
+ PERIPH_ID_Y_RESERVED22,
+ PERIPH_ID_Y_RESERVED23,
+
+ /* 216 */
+ PERIPH_ID_Y_RESERVED24,
+ PERIPH_ID_Y_RESERVED25,
+ PERIPH_ID_Y_RESERVED26,
+ PERIPH_ID_Y_RESERVED27,
+ PERIPH_ID_Y_RESERVED28,
+ PERIPH_ID_Y_RESERVED29,
+ PERIPH_ID_Y_RESERVED30,
+ PERIPH_ID_Y_RESERVED31,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+ /* 0x00 */
+ PERIPHC_I2S2,
+ PERIPHC_I2S3,
+ PERIPHC_SPDIF_OUT,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_PWM,
+ PERIPHC_05h,
+ PERIPHC_SBC2,
+ PERIPHC_SBC3,
+
+ /* 0x08 */
+ PERIPHC_08h,
+ PERIPHC_I2C1,
+ PERIPHC_I2C5,
+ PERIPHC_0bh,
+ PERIPHC_0ch,
+ PERIPHC_SBC1,
+ PERIPHC_DISP1,
+ PERIPHC_DISP2,
+
+ /* 0x10 */
+ PERIPHC_10h,
+ PERIPHC_11h,
+ PERIPHC_VI,
+ PERIPHC_13h,
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC2,
+ PERIPHC_G3D,
+ PERIPHC_G2D,
+
+ /* 0x18 */
+ PERIPHC_18h,
+ PERIPHC_SDMMC4,
+ PERIPHC_VFIR,
+ PERIPHC_1Bh,
+ PERIPHC_1Ch,
+ PERIPHC_HSI,
+ PERIPHC_UART1,
+ PERIPHC_UART2,
+
+ /* 0x20 */
+ PERIPHC_HOST1X,
+ PERIPHC_21h,
+ PERIPHC_22h,
+ PERIPHC_HDMI,
+ PERIPHC_24h,
+ PERIPHC_25h,
+ PERIPHC_I2C2,
+ PERIPHC_EMC,
+
+ /* 0x28 */
+ PERIPHC_UART3,
+ PERIPHC_29h,
+ PERIPHC_VI_SENSOR,
+ PERIPHC_2bh,
+ PERIPHC_2ch,
+ PERIPHC_SBC4,
+ PERIPHC_I2C3,
+ PERIPHC_SDMMC3,
+
+ /* 0x30 */
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_VDE,
+ PERIPHC_OWR,
+ PERIPHC_NOR,
+ PERIPHC_CSITE,
+ PERIPHC_I2S1,
+ PERIPHC_DTV,
+
+ /* 0x38 */
+ PERIPHC_38h,
+ PERIPHC_39h,
+ PERIPHC_3ah,
+ PERIPHC_3bh,
+ PERIPHC_MSENC,
+ PERIPHC_TSEC,
+ PERIPHC_3eh,
+ PERIPHC_OSC,
+
+ PERIPHC_VW_FIRST,
+ /* 0x40 */
+ PERIPHC_40h = PERIPHC_VW_FIRST,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S4,
+ PERIPHC_I2S5,
+ PERIPHC_I2C4,
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+
+ /* 0x48 */
+ PERIPHC_AUDIO,
+ PERIPHC_49h,
+ PERIPHC_4ah,
+ PERIPHC_4bh,
+ PERIPHC_4ch,
+ PERIPHC_HDA2CODEC2X,
+ PERIPHC_ACTMON,
+ PERIPHC_EXTPERIPH1,
+
+ /* 0x50 */
+ PERIPHC_EXTPERIPH2,
+ PERIPHC_EXTPERIPH3,
+ PERIPHC_52h,
+ PERIPHC_I2CSLOW,
+ PERIPHC_SYS,
+ PERIPHC_55h,
+ PERIPHC_56h,
+ PERIPHC_57h,
+
+ /* 0x58 */
+ PERIPHC_58h,
+ PERIPHC_59h,
+ PERIPHC_5ah,
+ PERIPHC_5bh,
+ PERIPHC_SATAOOB,
+ PERIPHC_SATA,
+ PERIPHC_HDA, /* 0x428 */
+ PERIPHC_5fh,
+
+ PERIPHC_X_FIRST,
+ /* 0x60 */
+ PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
+ PERIPHC_XUSB_FALCON,
+ PERIPHC_XUSB_FS,
+ PERIPHC_XUSB_CORE_DEV,
+ PERIPHC_XUSB_SS,
+ PERIPHC_CILAB,
+ PERIPHC_CILCD,
+ PERIPHC_CILE,
+
+ /* 0x68 */
+ PERIPHC_DSIA_LP,
+ PERIPHC_DSIB_LP,
+ PERIPHC_ENTROPY,
+ PERIPHC_DVFS_REF,
+ PERIPHC_DVFS_SOC,
+ PERIPHC_TRACECLKIN,
+ PERIPHC_6Eh,
+ PERIPHC_6Fh,
+
+ /* 0x70 */
+ PERIPHC_EMC_LATENCY,
+ PERIPHC_SOC_THERM,
+ PERIPHC_72h,
+ PERIPHC_73h,
+ PERIPHC_74h,
+ PERIPHC_75h,
+ PERIPHC_VI_SENSOR2,
+ PERIPHC_I2C6,
+
+ /* 0x78 */
+ PERIPHC_78h,
+ PERIPHC_EMC_DLL,
+ PERIPHC_7ah,
+ PERIPHC_CLK72MHZ,
+ PERIPHC_7ch,
+ PERIPHC_7dh,
+ PERIPHC_VIC,
+ PERIPHC_7fh,
+
+ PERIPHC_Y_FIRST,
+ /* 0x80 */
+ PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */
+ PERIPHC_NVDEC, /* 0x698 */
+ PERIPHC_NVJPG, /* 0x69c */
+ PERIPHC_NVENC, /* 0x6a0 */
+ PERIPHC_84h,
+ PERIPHC_85h,
+ PERIPHC_86h,
+ PERIPHC_87h,
+
+ /* 0x88 */
+ PERIPHC_88h,
+ PERIPHC_89h,
+ PERIPHC_DMIC3, /* 0x6bc: */
+ PERIPHC_APE, /* 0x6c0: */
+ PERIPHC_QSPI, /* 0x6c4: */
+ PERIPHC_VI_I2C, /* 0x6c8: */
+ PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */
+ PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */
+
+ /* 0x90 */
+ PERIPHC_MAUD, /* 0x6d4: */
+ PERIPHC_TSECB, /* 0x6d8: */
+
+ PERIPHC_COUNT,
+ PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+ (id < PERIPH_ID_VW_FIRST) ? \
+ ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+ (id) < PERIPH_ID_COUNT)
+
+#endif /* _TEGRA210_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/include/asm/arch-tegra210/clock.h
new file mode 100644
index 0000000..e615618
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/clock.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra210 clock control definitions */
+
+#ifndef _TEGRA210_CLOCK_H_
+#define _TEGRA210_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT 28
+#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+
+/* PLL bits that differ from generic clk_rst.h */
+#define PLLC_RESET 30
+#define PLLC_IDDQ 27
+#define PLLD_ENABLE_CLK 21
+#define PLLD_EN_LCKDET 28
+
+int tegra_plle_enable(void);
+
+#endif /* _TEGRA210_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/flow.h b/arch/arm/include/asm/arch-tegra210/flow.h
new file mode 100644
index 0000000..e2301ae
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/flow.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_FLOW_H_
+#define _TEGRA210_FLOW_H_
+
+struct flow_ctlr {
+ u32 halt_cpu_events; /* offset 0x00 */
+ u32 halt_cop_events; /* offset 0x04 */
+ u32 cpu_csr; /* offset 0x08 */
+ u32 cop_csr; /* offset 0x0c */
+ u32 xrq_events; /* offset 0x10 */
+ u32 halt_cpu1_events; /* offset 0x14 */
+ u32 cpu1_csr; /* offset 0x18 */
+ u32 halt_cpu2_events; /* offset 0x1c */
+ u32 cpu2_csr; /* offset 0x20 */
+ u32 halt_cpu3_events; /* offset 0x24 */
+ u32 cpu3_csr; /* offset 0x28 */
+ u32 cluster_control; /* offset 0x2c */
+ u32 halt_cop1_events; /* offset 0x30 */
+ u32 halt_cop1_csr; /* offset 0x34 */
+ u32 cpu_pwr_csr; /* offset 0x38 */
+ u32 mpid; /* offset 0x3c */
+ u32 ram_repair; /* offset 0x40 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC (1 << 24)
+#define EVENT_USEC (1 << 25)
+#define EVENT_JTAG (1 << 28)
+#define EVENT_MODE_STOP (2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP (1 << 0)
+
+/* CPUn_CSR_0 */
+#define CSR_ENABLE (1 << 0)
+#define CSR_IMMEDIATE_WAKE (1 << 3)
+#define CSR_WAIT_WFI_SHIFT 8
+
+#endif /* _TEGRA210_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h b/arch/arm/include/asm/arch-tegra210/funcmux.h
new file mode 100644
index 0000000..7ad116a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/funcmux.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra210 high-level function multiplexing */
+
+#ifndef _TEGRA210_FUNCMUX_H_
+#define _TEGRA210_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+ FUNCMUX_DEFAULT = 0, /* default config */
+
+ /* UART configs */
+ FUNCMUX_UART1_KBC = 0,
+ FUNCMUX_UART4_GPIO = 0,
+};
+#endif /* _TEGRA210_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h
new file mode 100644
index 0000000..fb69baf
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_GP_PADCTRL_H_
+#define _TEGRA210_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+ u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
+ u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
+ u32 reserved0[22]; /* 0x08 - 0x5C: */
+ u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
+ u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+ u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+ u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+ u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+ u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+ u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+ u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+ u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+ u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+ u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+ u32 reserved1; /* 0x8C: */
+ u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+ u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+ u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+ u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+ u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+ u32 reserved2[3]; /* 0xA4 - 0xAC: */
+ u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+ u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+ u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+ u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+ u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+ u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+ u32 reserved3[9]; /* 0xC8-0xE8: */
+ u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+ u32 reserved4[3]; /* 0xF0-0xF8: */
+ u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+ u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+ u32 reserved5[3]; /* 0x104-0x10C: */
+ u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+ u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+ u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+ u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+ u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+ u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+ u32 reserved6; /* 0x128: */
+ u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+ u32 reserved7[2]; /* 0x130 - 0x134: */
+ u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+ u32 reserved8[22]; /* 0x13C - 0x190: */
+ u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+ u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+ u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+ u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+ u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+ u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+ u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF 0
+#define SDIOCFG_DRVDN_SLWR 0
+#define SDIOCFG_DRVUP 0x24
+#define SDIOCFG_DRVDN 0x14
+
+#endif /* _TEGRA210_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h
new file mode 100644
index 0000000..71af423
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/gpio.h
@@ -0,0 +1,303 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_GPIO_H_
+#define _TEGRA210_GPIO_H_
+
+/*
+ * The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+ uint gpio_masked_config[TEGRA_GPIO_PORTS];
+ uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_in[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+ GPIO_PA0 = 0, /* pin 0 */
+ GPIO_PA1,
+ GPIO_PA2,
+ GPIO_PA3,
+ GPIO_PA4,
+ GPIO_PA5,
+ GPIO_PA6,
+ GPIO_PA7,
+ GPIO_PB0, /* pin 8 */
+ GPIO_PB1,
+ GPIO_PB2,
+ GPIO_PB3,
+ GPIO_PB4,
+ GPIO_PB5,
+ GPIO_PB6,
+ GPIO_PB7,
+ GPIO_PC0, /* pin 16 */
+ GPIO_PC1,
+ GPIO_PC2,
+ GPIO_PC3,
+ GPIO_PC4,
+ GPIO_PC5,
+ GPIO_PC6,
+ GPIO_PC7,
+ GPIO_PD0, /* pin 24 */
+ GPIO_PD1,
+ GPIO_PD2,
+ GPIO_PD3,
+ GPIO_PD4,
+ GPIO_PD5,
+ GPIO_PD6,
+ GPIO_PD7,
+ GPIO_PE0, /* pin 32 */
+ GPIO_PE1,
+ GPIO_PE2,
+ GPIO_PE3,
+ GPIO_PE4,
+ GPIO_PE5,
+ GPIO_PE6,
+ GPIO_PE7,
+ GPIO_PF0, /* pin 40 */
+ GPIO_PF1,
+ GPIO_PF2,
+ GPIO_PF3,
+ GPIO_PF4,
+ GPIO_PF5,
+ GPIO_PF6,
+ GPIO_PF7,
+ GPIO_PG0, /* pin 48 */
+ GPIO_PG1,
+ GPIO_PG2,
+ GPIO_PG3,
+ GPIO_PG4,
+ GPIO_PG5,
+ GPIO_PG6,
+ GPIO_PG7,
+ GPIO_PH0, /* pin 56 */
+ GPIO_PH1,
+ GPIO_PH2,
+ GPIO_PH3,
+ GPIO_PH4,
+ GPIO_PH5,
+ GPIO_PH6,
+ GPIO_PH7,
+ GPIO_PI0, /* pin 64 */
+ GPIO_PI1,
+ GPIO_PI2,
+ GPIO_PI3,
+ GPIO_PI4,
+ GPIO_PI5,
+ GPIO_PI6,
+ GPIO_PI7,
+ GPIO_PJ0, /* pin 72 */
+ GPIO_PJ1,
+ GPIO_PJ2,
+ GPIO_PJ3,
+ GPIO_PJ4,
+ GPIO_PJ5,
+ GPIO_PJ6,
+ GPIO_PJ7,
+ GPIO_PK0, /* pin 80 */
+ GPIO_PK1,
+ GPIO_PK2,
+ GPIO_PK3,
+ GPIO_PK4,
+ GPIO_PK5,
+ GPIO_PK6,
+ GPIO_PK7,
+ GPIO_PL0, /* pin 88 */
+ GPIO_PL1,
+ GPIO_PL2,
+ GPIO_PL3,
+ GPIO_PL4,
+ GPIO_PL5,
+ GPIO_PL6,
+ GPIO_PL7,
+ GPIO_PM0, /* pin 96 */
+ GPIO_PM1,
+ GPIO_PM2,
+ GPIO_PM3,
+ GPIO_PM4,
+ GPIO_PM5,
+ GPIO_PM6,
+ GPIO_PM7,
+ GPIO_PN0, /* pin 104 */
+ GPIO_PN1,
+ GPIO_PN2,
+ GPIO_PN3,
+ GPIO_PN4,
+ GPIO_PN5,
+ GPIO_PN6,
+ GPIO_PN7,
+ GPIO_PO0, /* pin 112 */
+ GPIO_PO1,
+ GPIO_PO2,
+ GPIO_PO3,
+ GPIO_PO4,
+ GPIO_PO5,
+ GPIO_PO6,
+ GPIO_PO7,
+ GPIO_PP0, /* pin 120 */
+ GPIO_PP1,
+ GPIO_PP2,
+ GPIO_PP3,
+ GPIO_PP4,
+ GPIO_PP5,
+ GPIO_PP6,
+ GPIO_PP7,
+ GPIO_PQ0, /* pin 128 */
+ GPIO_PQ1,
+ GPIO_PQ2,
+ GPIO_PQ3,
+ GPIO_PQ4,
+ GPIO_PQ5,
+ GPIO_PQ6,
+ GPIO_PQ7,
+ GPIO_PR0, /* pin 136 */
+ GPIO_PR1,
+ GPIO_PR2,
+ GPIO_PR3,
+ GPIO_PR4,
+ GPIO_PR5,
+ GPIO_PR6,
+ GPIO_PR7,
+ GPIO_PS0, /* pin 144 */
+ GPIO_PS1,
+ GPIO_PS2,
+ GPIO_PS3,
+ GPIO_PS4,
+ GPIO_PS5,
+ GPIO_PS6,
+ GPIO_PS7,
+ GPIO_PT0, /* pin 152 */
+ GPIO_PT1,
+ GPIO_PT2,
+ GPIO_PT3,
+ GPIO_PT4,
+ GPIO_PT5,
+ GPIO_PT6,
+ GPIO_PT7,
+ GPIO_PU0, /* pin 160 */
+ GPIO_PU1,
+ GPIO_PU2,
+ GPIO_PU3,
+ GPIO_PU4,
+ GPIO_PU5,
+ GPIO_PU6,
+ GPIO_PU7,
+ GPIO_PV0, /* pin 168 */
+ GPIO_PV1,
+ GPIO_PV2,
+ GPIO_PV3,
+ GPIO_PV4,
+ GPIO_PV5,
+ GPIO_PV6,
+ GPIO_PV7,
+ GPIO_PW0, /* pin 176 */
+ GPIO_PW1,
+ GPIO_PW2,
+ GPIO_PW3,
+ GPIO_PW4,
+ GPIO_PW5,
+ GPIO_PW6,
+ GPIO_PW7,
+ GPIO_PX0, /* pin 184 */
+ GPIO_PX1,
+ GPIO_PX2,
+ GPIO_PX3,
+ GPIO_PX4,
+ GPIO_PX5,
+ GPIO_PX6,
+ GPIO_PX7,
+ GPIO_PY0, /* pin 192 */
+ GPIO_PY1,
+ GPIO_PY2,
+ GPIO_PY3,
+ GPIO_PY4,
+ GPIO_PY5,
+ GPIO_PY6,
+ GPIO_PY7,
+ GPIO_PZ0, /* pin 200 */
+ GPIO_PZ1,
+ GPIO_PZ2,
+ GPIO_PZ3,
+ GPIO_PZ4,
+ GPIO_PZ5,
+ GPIO_PZ6,
+ GPIO_PZ7,
+ GPIO_PAA0, /* pin 208 */
+ GPIO_PAA1,
+ GPIO_PAA2,
+ GPIO_PAA3,
+ GPIO_PAA4,
+ GPIO_PAA5,
+ GPIO_PAA6,
+ GPIO_PAA7,
+ GPIO_PBB0, /* pin 216 */
+ GPIO_PBB1,
+ GPIO_PBB2,
+ GPIO_PBB3,
+ GPIO_PBB4,
+ GPIO_PBB5,
+ GPIO_PBB6,
+ GPIO_PBB7,
+ GPIO_PCC0, /* pin 224 */
+ GPIO_PCC1,
+ GPIO_PCC2,
+ GPIO_PCC3,
+ GPIO_PCC4,
+ GPIO_PCC5,
+ GPIO_PCC6,
+ GPIO_PCC7,
+ GPIO_PDD0, /* pin 232 */
+ GPIO_PDD1,
+ GPIO_PDD2,
+ GPIO_PDD3,
+ GPIO_PDD4,
+ GPIO_PDD5,
+ GPIO_PDD6,
+ GPIO_PDD7,
+ GPIO_PEE0, /* pin 240 */
+ GPIO_PEE1,
+ GPIO_PEE2,
+ GPIO_PEE3,
+ GPIO_PEE4,
+ GPIO_PEE5,
+ GPIO_PEE6,
+ GPIO_PEE7,
+ GPIO_PFF0, /* pin 248 */
+ GPIO_PFF1,
+ GPIO_PFF2,
+ GPIO_PFF3,
+ GPIO_PFF4,
+ GPIO_PFF5,
+ GPIO_PFF6,
+ GPIO_PFF7, /* pin 255 */
+};
+
+#endif /* _TEGRA210_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h b/arch/arm/include/asm/arch-tegra210/hardware.h
new file mode 100644
index 0000000..68691cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/hardware.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_HARDWARE_H_
+#define _TEGRA210_HARDWARE_H_
+
+/*
+ * Include Tegra-specific hardware definitions
+ * Nothing needed currently for Tegra210
+ */
+
+#endif /* _TEGRA210_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h
new file mode 100644
index 0000000..77e9aa5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/mc.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_MC_H_
+#define _TEGRA210_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+ u32 reserved0[4]; /* offset 0x00 - 0x0C */
+ u32 mc_smmu_config; /* offset 0x10 */
+ u32 mc_smmu_tlb_config; /* offset 0x14 */
+ u32 mc_smmu_ptc_config; /* offset 0x18 */
+ u32 mc_smmu_ptb_asid; /* offset 0x1C */
+ u32 mc_smmu_ptb_data; /* offset 0x20 */
+ u32 reserved1[3]; /* offset 0x24 - 0x2C */
+ u32 mc_smmu_tlb_flush; /* offset 0x30 */
+ u32 mc_smmu_ptc_flush; /* offset 0x34 */
+ u32 reserved2[6]; /* offset 0x38 - 0x4C */
+ u32 mc_emem_cfg; /* offset 0x50 */
+ u32 mc_emem_adr_cfg; /* offset 0x54 */
+ u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
+ u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
+ u32 reserved3[4]; /* offset 0x60 - 0x6C */
+ u32 mc_security_cfg0; /* offset 0x70 */
+ u32 mc_security_cfg1; /* offset 0x74 */
+ u32 reserved4[6]; /* offset 0x7C - 0x8C */
+ u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
+ u32 reserved5[74]; /* offset 0x100 - 0x224 */
+ u32 mc_smmu_translation_enable_0; /* offset 0x228 */
+ u32 mc_smmu_translation_enable_1; /* offset 0x22C */
+ u32 mc_smmu_translation_enable_2; /* offset 0x230 */
+ u32 mc_smmu_translation_enable_3; /* offset 0x234 */
+ u32 mc_smmu_afi_asid; /* offset 0x238 */
+ u32 mc_smmu_avpc_asid; /* offset 0x23C */
+ u32 mc_smmu_dc_asid; /* offset 0x240 */
+ u32 mc_smmu_dcb_asid; /* offset 0x244 */
+ u32 reserved6[2]; /* offset 0x248 - 0x24C */
+ u32 mc_smmu_hc_asid; /* offset 0x250 */
+ u32 mc_smmu_hda_asid; /* offset 0x254 */
+ u32 mc_smmu_isp2_asid; /* offset 0x258 */
+ u32 reserved7[2]; /* offset 0x25C - 0x260 */
+ u32 mc_smmu_msenc_asid; /* offset 0x264 */
+ u32 mc_smmu_nv_asid; /* offset 0x268 */
+ u32 mc_smmu_nv2_asid; /* offset 0x26C */
+ u32 mc_smmu_ppcs_asid; /* offset 0x270 */
+ u32 mc_smmu_sata_asid; /* offset 0x274 */
+ u32 reserved8[1]; /* offset 0x278 */
+ u32 mc_smmu_vde_asid; /* offset 0x27C */
+ u32 mc_smmu_vi_asid; /* offset 0x280 */
+ u32 mc_smmu_vic_asid; /* offset 0x284 */
+ u32 mc_smmu_xusb_host_asid; /* offset 0x288 */
+ u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */
+ u32 reserved9[1]; /* offset 0x290 */
+ u32 mc_smmu_tsec_asid; /* offset 0x294 */
+ u32 mc_smmu_ppcs1_asid; /* offset 0x298 */
+ u32 reserved10[235]; /* offset 0x29C - 0x644 */
+ u32 mc_video_protect_bom; /* offset 0x648 */
+ u32 mc_video_protect_size_mb; /* offset 0x64c */
+ u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
+};
+
+#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
+
+#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0)
+#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)
+
+#endif /* _TEGRA210_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/pmu.h b/arch/arm/include/asm/arch-tegra210/pmu.h
new file mode 100644
index 0000000..1e5f388
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/pmu.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_PMU_H_
+#define _TEGRA210_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA210_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/powergate.h b/arch/arm/include/asm/arch-tegra210/powergate.h
new file mode 100644
index 0000000..df6f91d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/powergate.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_POWERGATE_H_
+#define _TEGRA210_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA210_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/sysctr.h b/arch/arm/include/asm/arch-tegra210/sysctr.h
new file mode 100644
index 0000000..e8a13b5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/sysctr.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_SYSCTR_H_
+#define _TEGRA210_SYSCTR_H_
+
+struct sysctr_ctlr {
+ u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
+ u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
+ u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+ u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+ u32 reserved1[4]; /* 0x10 - 0x1C */
+ u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+ u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+ u32 reserved2[1002]; /* 0x28 - 0xFCC */
+ u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
+#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
+
+#endif /* _TEGRA210_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h
new file mode 100644
index 0000000..837ac81
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/tegra.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_TEGRA_H_
+#define _TEGRA210_TEGRA_H_
+
+#define GICD_BASE 0x50041000 /* Generic Interrupt Controller Distrib */
+#define GICC_BASE 0x50042000 /* Generic Interrupt Controller CPU I/F */
+#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
+#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
+#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_SDRAM_BASE 0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU 4
+#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE 0x7D000000
+
+#endif /* _TEGRA210_TEGRA_H_ */
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
new file mode 100644
index 0000000..f2a0059
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -0,0 +1,11 @@
+if TEGRA210
+
+choice
+ prompt "Tegra210 board select"
+
+endchoice
+
+config SYS_SOC
+ default "tegra210"
+
+endif
diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile
new file mode 100644
index 0000000..a4d6327
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra210/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2013-2015
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += cpu.o
+
+obj-y += clock.o
+obj-y += funcmux.o
+obj-y += pinmux.o
+obj-y += xusb-padctl.o
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
new file mode 100644
index 0000000..d5f412f
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -0,0 +1,1086 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra210 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra210 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+ CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
+ CLOCK_TYPE_MCPA, /* and so on */
+ CLOCK_TYPE_MCPT,
+ CLOCK_TYPE_PCM,
+ CLOCK_TYPE_PCMT,
+ CLOCK_TYPE_PDCT,
+ CLOCK_TYPE_ACPT,
+ CLOCK_TYPE_ASPTE,
+ CLOCK_TYPE_PMDACD2T,
+ CLOCK_TYPE_PCST,
+
+ CLOCK_TYPE_PC2CC3M,
+ CLOCK_TYPE_PC2CC3S_T,
+ CLOCK_TYPE_PC2CC3M_T,
+ CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
+ CLOCK_TYPE_MC2CC3P_A,
+ CLOCK_TYPE_M,
+ CLOCK_TYPE_MCPTM2C2C3,
+ CLOCK_TYPE_PC2CC3T_S,
+ CLOCK_TYPE_AC2CC3P_TS2,
+ CLOCK_TYPE_PC01C00_C42C41TC40,
+
+ CLOCK_TYPE_COUNT,
+ CLOCK_TYPE_NONE = -1, /* invalid clock type */
+};
+
+enum {
+ CLOCK_MAX_MUX = 8 /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ * The extra column in each clock source array is used to store the mask
+ * bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+ { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
+ CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
+ CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_28},
+
+ /* Additional clock types on Tegra114+ */
+ /* CLOCK_TYPE_PC2CC3M */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3S_T */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3M_T */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_MC2CC3P_A */
+ { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_M */
+ { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ /* CLOCK_TYPE_MCPTM2C2C3 */
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3T_S */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_AC2CC3P_TS2 */
+ { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC01C00_C42C41TC40 */
+ { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
+ CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
+ MASK_BITS_31_29},
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+ /* 0x00 */
+ TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
+ TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x08 */
+ TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
+
+ /* 0x10 */
+ TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
+
+ /* 0x18 */
+ TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x20 */
+ TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_23h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
+
+ /* 0x28 */
+ TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x30 */
+ TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
+
+ /* 0x38 */
+ TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
+
+ /* 0x40 */
+ TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
+ TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
+ TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x48 */
+ TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+ /* 0x50 */
+ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
+
+ /* 0x58 */
+ TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
+
+ /* 0x60 */
+ TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
+
+ /* 0x68 */
+ TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE),
+
+ /* 0x70 */
+ TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
+
+ /* 0x78 */
+ TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
+ TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
+
+ /* 0x80 */
+ TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_84h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_85h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_86h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_87h, CLOCK_TYPE_NONE),
+
+ /* 0x88 */
+ TYPE(PERIPHC_88h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_89h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
+ TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_USB2_HSIC_TRK,CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_PEX_SATA_USB_RX_BYP,CLOCK_TYPE_NONE),
+
+ /* 0x90 */
+ TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ * uint vi_sensor; _VI_SENSOR_0, 0x1A8
+ * SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+#define INTERNAL_ID(id) (id & 0x000000ff)
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+ /* Low word: 31:0 */
+ NONE(CPU),
+ NONE(COP),
+ NONE(TRIGSYS),
+ NONE(ISPB),
+ NONE(RESERVED4),
+ NONE(TMR),
+ PERIPHC_UART1,
+ PERIPHC_UART2, /* and vfir 0x68 */
+
+ /* 8 */
+ NONE(GPIO),
+ PERIPHC_SDMMC2,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_I2S2,
+ PERIPHC_I2C1,
+ NONE(RESERVED13),
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC4,
+
+ /* 16 */
+ NONE(TCW),
+ PERIPHC_PWM,
+ PERIPHC_I2S3,
+ NONE(RESERVED19),
+ PERIPHC_VI,
+ NONE(RESERVED21),
+ NONE(USBD),
+ NONE(ISP),
+
+ /* 24 */
+ NONE(RESERVED24),
+ NONE(RESERVED25),
+ PERIPHC_DISP2,
+ PERIPHC_DISP1,
+ PERIPHC_HOST1X,
+ NONE(VCP),
+ PERIPHC_I2S1,
+ NONE(CACHE2),
+
+ /* Middle word: 63:32 */
+ NONE(MEM),
+ NONE(AHBDMA),
+ NONE(APBDMA),
+ NONE(RESERVED35),
+ NONE(RESERVED36),
+ NONE(STAT_MON),
+ NONE(RESERVED38),
+ NONE(FUSE),
+
+ /* 40 */
+ NONE(KFUSE),
+ PERIPHC_SBC1, /* SBCx = SPIx */
+ PERIPHC_NOR,
+ NONE(RESERVED43),
+ PERIPHC_SBC2,
+ NONE(XIO),
+ PERIPHC_SBC3,
+ PERIPHC_I2C5,
+
+ /* 48 */
+ NONE(DSI),
+ NONE(RESERVED49),
+ PERIPHC_HSI,
+ NONE(RESERVED51),
+ NONE(CSI),
+ NONE(RESERVED53),
+ PERIPHC_I2C2,
+ PERIPHC_UART3,
+
+ /* 56 */
+ NONE(MIPI_CAL),
+ PERIPHC_EMC,
+ NONE(USB2),
+ NONE(USB3),
+ NONE(RESERVED60),
+ PERIPHC_VDE,
+ NONE(BSEA),
+ NONE(BSEV),
+
+ /* Upper word 95:64 */
+ NONE(RESERVED64),
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_I2C3,
+ PERIPHC_SBC4,
+ PERIPHC_SDMMC3,
+ NONE(PCIE),
+ PERIPHC_OWR,
+
+ /* 72 */
+ NONE(AFI),
+ PERIPHC_CSITE,
+ NONE(PCIEXCLK),
+ NONE(AVPUCQ),
+ NONE(LA),
+ NONE(TRACECLKIN),
+ NONE(SOC_THERM),
+ NONE(DTV),
+
+ /* 80 */
+ NONE(RESERVED80),
+ PERIPHC_I2CSLOW,
+ NONE(DSIB),
+ PERIPHC_TSEC,
+ NONE(RESERVED84),
+ NONE(RESERVED85),
+ NONE(RESERVED86),
+ NONE(EMUCIF),
+
+ /* 88 */
+ NONE(RESERVED88),
+ NONE(XUSB_HOST),
+ NONE(RESERVED90),
+ PERIPHC_MSENC,
+ NONE(RESERVED92),
+ NONE(RESERVED93),
+ NONE(RESERVED94),
+ NONE(XUSB_DEV),
+
+ /* V word: 31:0 */
+ NONE(CPUG),
+ NONE(CPULP),
+ NONE(V_RESERVED2),
+ PERIPHC_MSELECT,
+ NONE(V_RESERVED4),
+ PERIPHC_I2S4,
+ PERIPHC_I2S5,
+ PERIPHC_I2C4,
+
+ /* 104 */
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+ PERIPHC_AUDIO,
+ NONE(APBIF),
+ NONE(V_RESERVED12),
+ NONE(V_RESERVED13),
+ NONE(V_RESERVED14),
+ PERIPHC_HDA2CODEC2X,
+
+ /* 112 */
+ NONE(ATOMICS),
+ NONE(V_RESERVED17),
+ NONE(V_RESERVED18),
+ NONE(V_RESERVED19),
+ NONE(V_RESERVED20),
+ NONE(V_RESERVED21),
+ NONE(V_RESERVED22),
+ PERIPHC_ACTMON,
+
+ /* 120 */
+ NONE(EXTPERIPH1),
+ NONE(EXTPERIPH2),
+ NONE(EXTPERIPH3),
+ NONE(OOB),
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+ NONE(TZRAM),
+ NONE(SE),
+
+ /* W word: 31:0 */
+ NONE(HDA2HDMICODEC),
+ NONE(SATACOLD),
+ NONE(W_RESERVED2),
+ NONE(W_RESERVED3),
+ NONE(W_RESERVED4),
+ NONE(W_RESERVED5),
+ NONE(W_RESERVED6),
+ NONE(W_RESERVED7),
+
+ /* 136 */
+ NONE(CEC),
+ NONE(W_RESERVED9),
+ NONE(W_RESERVED10),
+ NONE(W_RESERVED11),
+ NONE(W_RESERVED12),
+ NONE(W_RESERVED13),
+ NONE(XUSB_PADCTL),
+ NONE(W_RESERVED15),
+
+ /* 144 */
+ NONE(W_RESERVED16),
+ NONE(W_RESERVED17),
+ NONE(W_RESERVED18),
+ NONE(W_RESERVED19),
+ NONE(W_RESERVED20),
+ NONE(ENTROPY),
+ NONE(DDS),
+ NONE(W_RESERVED23),
+
+ /* 152 */
+ NONE(W_RESERVED24),
+ NONE(W_RESERVED25),
+ NONE(W_RESERVED26),
+ NONE(DVFS),
+ NONE(XUSB_SS),
+ NONE(W_RESERVED29),
+ NONE(W_RESERVED30),
+ NONE(W_RESERVED31),
+
+ /* X word: 31:0 */
+ NONE(SPARE),
+ NONE(X_RESERVED1),
+ NONE(X_RESERVED2),
+ NONE(X_RESERVED3),
+ NONE(CAM_MCLK),
+ NONE(CAM_MCLK2),
+ PERIPHC_I2C6,
+ NONE(X_RESERVED7),
+
+ /* 168 */
+ NONE(X_RESERVED8),
+ NONE(X_RESERVED9),
+ NONE(X_RESERVED10),
+ NONE(VIM2_CLK),
+ NONE(X_RESERVED12),
+ NONE(X_RESERVED13),
+ NONE(EMC_DLL),
+ NONE(X_RESERVED15),
+
+ /* 176 */
+ NONE(X_RESERVED16),
+ NONE(CLK72MHZ),
+ NONE(VIC),
+ NONE(X_RESERVED19),
+ NONE(X_RESERVED20),
+ NONE(DPAUX),
+ NONE(SOR0),
+ NONE(X_RESERVED23),
+
+ /* 184 */
+ NONE(GPU),
+ NONE(X_RESERVED25),
+ NONE(X_RESERVED26),
+ NONE(X_RESERVED27),
+ NONE(X_RESERVED28),
+ NONE(X_RESERVED29),
+ NONE(X_RESERVED30),
+ NONE(X_RESERVED31),
+
+ /* Y: 192 (192 - 223) */
+ NONE(Y_RESERVED0),
+ PERIPHC_SDMMC_LEGACY_TM,
+ PERIPHC_NVDEC,
+ PERIPHC_NVJPG,
+ NONE(Y_RESERVED4),
+ PERIPHC_DMIC3, /* 197 */
+ PERIPHC_APE, /* 198 */
+ NONE(Y_RESERVED7),
+
+ /* 200 */
+ NONE(Y_RESERVED8),
+ NONE(Y_RESERVED9),
+ NONE(Y_RESERVED10),
+ NONE(Y_RESERVED11),
+ NONE(Y_RESERVED12),
+ NONE(Y_RESERVED13),
+ NONE(Y_RESERVED14),
+ NONE(Y_RESERVED15),
+
+ /* 208 */
+ PERIPHC_VI_I2C, /* 208 */
+ NONE(Y_RESERVED17),
+ NONE(Y_RESERVED18),
+ PERIPHC_QSPI, /* 211 */
+ NONE(Y_RESERVED20),
+ NONE(Y_RESERVED21),
+ NONE(Y_RESERVED22),
+ NONE(Y_RESERVED23),
+
+ /* 216 */
+ NONE(Y_RESERVED24),
+ NONE(Y_RESERVED25),
+ NONE(Y_RESERVED26),
+ PERIPHC_NVENC, /* 219 */
+ NONE(Y_RESERVED28),
+ NONE(Y_RESERVED29),
+ NONE(Y_RESERVED30),
+ NONE(Y_RESERVED31),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that Tegra30+ support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ reg = readl(&clkrst->crc_osc_ctrl);
+ reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+ /*
+ * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
+ * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
+ */
+ if (reg == 5) {
+ debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
+ /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
+ return 4;
+ }
+
+ /*
+ * Map to most common (T20) freqs (except 38.4, handled above):
+ * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
+ */
+ return reg >> 2;
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ enum periphc_internal_id internal_id;
+
+ /* Coresight is a special case */
+ if (periph_id == PERIPH_ID_CSI)
+ return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+ assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+ internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
+ assert(internal_id != -1);
+
+ if (internal_id < PERIPHC_VW_FIRST)
+ /* L, H, U */
+ return &clkrst->crc_clk_src[internal_id];
+
+ if (internal_id < PERIPHC_X_FIRST) {
+ /* VW */
+ internal_id -= PERIPHC_VW_FIRST;
+ return &clkrst->crc_clk_src_vw[internal_id];
+ }
+
+ if (internal_id < PERIPHC_Y_FIRST) {
+ /* X */
+ internal_id -= PERIPHC_X_FIRST;
+ return &clkrst->crc_clk_src_x[internal_id];
+ }
+
+ /* Y */
+ internal_id -= PERIPHC_Y_FIRST;
+ return &clkrst->crc_clk_src_y[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id peripheral to start
+ * @param source PLL id of required parent clock
+ * @param mux_bits Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+ enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+ enum clock_type_id type;
+ enum periphc_internal_id internal_id;
+ int mux;
+
+ assert(clock_periph_id_isvalid(periph_id));
+
+ internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
+ assert(periphc_internal_id_isvalid(internal_id));
+
+ type = clock_periph_type[internal_id];
+ assert(clock_type_id_isvalid(type));
+
+ *mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+ if (type == CLOCK_TYPE_PC2CC3M_T16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+ if (clock_source[type][mux] == parent)
+ return mux;
+
+ /* if we get here, either us or the caller has made a mistake */
+ printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+ parent);
+ return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *clk;
+ u32 reg;
+
+ /* Enable/disable the clock to this peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+ clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+ else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
+ clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+ else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
+ clk = &clkrst->crc_clk_out_enb_x;
+ else
+ clk = &clkrst->crc_clk_out_enb_y;
+
+ reg = readl(clk);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *reset;
+ u32 reg;
+
+ /* Enable/disable reset to the peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if (periph_id < PERIPH_ID_VW_FIRST)
+ reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+ else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
+ reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+ else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
+ reset = &clkrst->crc_rst_devices_x;
+ else
+ reset = &clkrst->crc_rst_devices_y;
+
+ reg = readl(reset);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id Clock ID according to tegra210 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+ if (clk_id > PERIPH_ID_COUNT)
+ return PERIPH_ID_NONE;
+
+ switch (clk_id) {
+ case PERIPH_ID_RESERVED4:
+ case PERIPH_ID_RESERVED25:
+ case PERIPH_ID_RESERVED35:
+ case PERIPH_ID_RESERVED36:
+ case PERIPH_ID_RESERVED38:
+ case PERIPH_ID_RESERVED43:
+ case PERIPH_ID_RESERVED49:
+ case PERIPH_ID_RESERVED53:
+ case PERIPH_ID_RESERVED64:
+ case PERIPH_ID_RESERVED84:
+ case PERIPH_ID_RESERVED85:
+ case PERIPH_ID_RESERVED86:
+ case PERIPH_ID_RESERVED88:
+ case PERIPH_ID_RESERVED90:
+ case PERIPH_ID_RESERVED92:
+ case PERIPH_ID_RESERVED93:
+ case PERIPH_ID_RESERVED94:
+ case PERIPH_ID_V_RESERVED2:
+ case PERIPH_ID_V_RESERVED4:
+ case PERIPH_ID_V_RESERVED17:
+ case PERIPH_ID_V_RESERVED18:
+ case PERIPH_ID_V_RESERVED19:
+ case PERIPH_ID_V_RESERVED20:
+ case PERIPH_ID_V_RESERVED21:
+ case PERIPH_ID_V_RESERVED22:
+ case PERIPH_ID_W_RESERVED2:
+ case PERIPH_ID_W_RESERVED3:
+ case PERIPH_ID_W_RESERVED4:
+ case PERIPH_ID_W_RESERVED5:
+ case PERIPH_ID_W_RESERVED6:
+ case PERIPH_ID_W_RESERVED7:
+ case PERIPH_ID_W_RESERVED9:
+ case PERIPH_ID_W_RESERVED10:
+ case PERIPH_ID_W_RESERVED11:
+ case PERIPH_ID_W_RESERVED12:
+ case PERIPH_ID_W_RESERVED13:
+ case PERIPH_ID_W_RESERVED15:
+ case PERIPH_ID_W_RESERVED16:
+ case PERIPH_ID_W_RESERVED17:
+ case PERIPH_ID_W_RESERVED18:
+ case PERIPH_ID_W_RESERVED19:
+ case PERIPH_ID_W_RESERVED20:
+ case PERIPH_ID_W_RESERVED23:
+ case PERIPH_ID_W_RESERVED29:
+ case PERIPH_ID_W_RESERVED30:
+ case PERIPH_ID_W_RESERVED31:
+ return PERIPH_ID_NONE;
+ default:
+ return clk_id;
+ }
+}
+#endif /* CONFIG_OF_CONTROL */
+
+/*
+ * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
+ * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
+ */
+void tegra210_setup_pllp(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
+
+ /* OUT1 */
+ /* Assert RSTN before enable */
+ reg = PLLP_OUT1_RSTN_EN;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+ /* Set divisor and reenable */
+ reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
+ | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+
+ /* OUT3, 4 */
+ /* Assert RSTN before enable */
+ reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+ /* Set divisor and reenable */
+ reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
+ | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
+ | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
+ | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+
+ /*
+ * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
+ * you can change PLLP_BASE DIVP here. Currently defaults
+ * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
+ * See Table 13 in section 5.1.4 in T210 TRM for more info.
+ */
+}
+
+void clock_early_init(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 data;
+
+ tegra210_setup_pllp();
+
+ /*
+ * PLLC output frequency set to 600Mhz
+ * PLLD output frequency set to 925Mhz
+ */
+ switch (clock_get_osc_freq()) {
+ case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+ break;
+
+ case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+ break;
+
+ case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+ break;
+ case CLOCK_OSC_FREQ_19_2:
+ clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
+ clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
+ break;
+ default:
+ /*
+ * These are not supported. It is too early to print a
+ * message and the UART likely won't work anyway due to the
+ * oscillator being wrong.
+ */
+ break;
+ }
+
+ /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
+ clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << PLLC_IDDQ));
+ udelay(2);
+
+ /* PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps to pll_out[1] */
+ clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], (1 << PLLC_RESET));
+ udelay(2);
+
+ /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
+ data = (1 << PLLD_ENABLE_CLK) | (1 << PLLD_EN_LCKDET);
+ writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+ udelay(2);
+}
+
+void arch_timer_init(void)
+{
+ struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+ u32 freq, val;
+
+ freq = clock_get_rate(CLOCK_ID_OSC);
+ debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+ /* ARM CNTFRQ */
+#ifndef CONFIG_ARM64
+ asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+#endif
+
+ /* Only Tegra114+ has the System Counter regs */
+ debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+ writel(freq, &sysctr->cntfid0);
+
+ val = readl(&sysctr->cntcr);
+ val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+ writel(val, &sysctr->cntcr);
+ debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
+
+#define PLLE_SS_CNTL 0x68
+#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
+#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
+#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
+#define PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_BASE 0x0e8
+#define PLLE_BASE_ENABLE (1 << 30)
+#define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
+#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
+#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
+#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
+
+#define PLLE_MISC 0x0ec
+#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
+#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
+#define PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define PLLE_MISC_PTS (1 << 8)
+#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
+#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
+
+#define PLLE_AUX 0x48c
+#define PLLE_AUX_SEQ_ENABLE (1 << 24)
+#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
+
+int tegra_plle_enable(void)
+{
+ unsigned int m = 1, n = 200, cpcon = 13;
+ u32 value;
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value &= ~PLLE_BASE_LOCK_OVERRIDE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
+ value |= PLLE_AUX_ENABLE_SWCTL;
+ value &= ~PLLE_AUX_SEQ_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
+
+ udelay(1);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+ value |= PLLE_MISC_IDDQ_SWCTL;
+ value &= ~PLLE_MISC_IDDQ_OVERRIDE;
+ value |= PLLE_MISC_LOCK_ENABLE;
+ value |= PLLE_MISC_PTS;
+ value |= PLLE_MISC_VREG_BG_CTRL(3);
+ value |= PLLE_MISC_VREG_CTRL(2);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+ udelay(5);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
+ PLLE_SS_CNTL_BYPASS_SS;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value &= ~PLLE_BASE_PLDIV_CML(0xf);
+ value &= ~PLLE_BASE_NDIV(0xff);
+ value &= ~PLLE_BASE_MDIV(0xff);
+ value |= PLLE_BASE_PLDIV_CML(cpcon);
+ value |= PLLE_BASE_NDIV(n);
+ value |= PLLE_BASE_MDIV(m);
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ udelay(1);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+ value |= PLLE_BASE_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+ /* wait for lock */
+ udelay(300);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value &= ~PLLE_SS_CNTL_SSCINVERT;
+ value &= ~PLLE_SS_CNTL_SSCCENTER;
+
+ value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
+ value &= ~PLLE_SS_CNTL_SSCINC(0xff);
+ value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
+
+ value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
+ value |= PLLE_SS_CNTL_SSCINC(0x01);
+ value |= PLLE_SS_CNTL_SSCMAX(0x25);
+
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value &= ~PLLE_SS_CNTL_SSCBYP;
+ value &= ~PLLE_SS_CNTL_BYPASS_SS;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ udelay(1);
+
+ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+ value &= ~PLLE_SS_CNTL_INTERP_RESET;
+ writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+ udelay(1);
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra210/cpu.c b/arch/arm/mach-tegra/tegra210/cpu.c
new file mode 100644
index 0000000..e9483e4
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra210/cpu.c
@@ -0,0 +1,328 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ahb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/ap.h>
+#include "../cpu.h"
+
+static void power_partition(u32 partid);
+
+/* Tegra210-specific CPU init code */
+
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("%s entry\n", __func__);
+
+ /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PY3);
+ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PY4);
+
+ pmic_enable_cpu_vdd();
+
+ /*
+ * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+ * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
+ */
+ writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
+
+ /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+ clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+ setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+}
+
+static void enable_cpu_clocks(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("%s entry\n", __func__);
+
+ /* Wait for PLL-X to lock */
+ do {
+ reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+ debug("%s: PLLX base = 0x%08X\n", __func__, reg);
+ } while ((reg & PLL_LOCK_MASK) == 0);
+
+ debug("%s: PLLX locked, delay for stable clocks\n", __func__);
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
+ writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+ debug("%s: Enabling clock to all CPUs\n", __func__);
+ /* Enable the clock to all CPUs */
+ reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
+ CLR_CPU0_CLK_STP;
+ writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
+
+ debug("%s: Enabling main CPU complex clocks\n", __func__);
+ /* Always enable the main CPU complex clocks */
+ clock_enable(PERIPH_ID_CPU);
+ clock_enable(PERIPH_ID_CPULP);
+ clock_enable(PERIPH_ID_CPUG);
+
+ debug("%s: Done\n", __func__);
+}
+
+static void remove_cpu_resets(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("%s entry\n", __func__);
+
+ /* Take the slow and fast partitions out of reset */
+ reg = CLR_NONCPURESET;
+ writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+ writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+
+ /* Clear the SW-controlled reset of the slow cluster */
+ reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+ CLR_L2RESET | CLR_PRESETDBG;
+ writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+ /* Clear the SW-controlled reset of the fast cluster */
+ reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+ CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
+ CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
+ CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
+ CLR_L2RESET | CLR_PRESETDBG;
+ writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * Tegra210 requires some special clock initialization, including setting
+ * up the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void tegra210_init_clocks(void)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 val;
+
+ debug("%s entry\n", __func__);
+
+ /* Set active CPU cluster to G */
+ clrbits_le32(&flow->cluster_control, 1);
+
+ /* Change the oscillator drive strength */
+ val = readl(&clkrst->crc_osc_ctrl);
+ val &= ~OSC_XOFS_MASK;
+ val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
+ writel(val, &clkrst->crc_osc_ctrl);
+
+ /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
+ val = readl(&pmc->pmc_osc_edpd_over);
+ val &= ~PMC_XOFS_MASK;
+ val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
+ writel(val, &pmc->pmc_osc_edpd_over);
+
+ /* Set HOLD_CKE_LOW_EN to 1 */
+ setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
+
+ debug("Setting up PLLX\n");
+ init_pllx();
+
+ val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+ writel(val, &clkrst->crc_clk_sys_rate);
+#if defined(CONFIG_I2C6_SUPPORTED)
+ debug("%s: powering up SOR partition\n", __func__);
+ power_partition(SOR);
+#endif
+
+ /* Enable clocks to required peripherals. TBD - minimize this list */
+ debug("Enabling clocks\n");
+
+ clock_set_enable(PERIPH_ID_CACHE2, 1);
+ clock_set_enable(PERIPH_ID_GPIO, 1);
+ clock_set_enable(PERIPH_ID_TMR, 1);
+ clock_set_enable(PERIPH_ID_CPU, 1);
+ clock_set_enable(PERIPH_ID_EMC, 1);
+ clock_set_enable(PERIPH_ID_I2C5, 1);
+ clock_set_enable(PERIPH_ID_APBDMA, 1);
+ clock_set_enable(PERIPH_ID_MEM, 1);
+ clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+ clock_set_enable(PERIPH_ID_MSELECT, 1);
+ clock_set_enable(PERIPH_ID_DVFS, 1);
+#if defined(CONFIG_I2C6_SUPPORTED)
+ /* I2C6 is in the SOR/DPAUX domain, so enable these blocks, too */
+ clock_set_enable(PERIPH_ID_DPAUX, 1);
+ clock_set_enable(PERIPH_ID_HOST1X, 1);
+ clock_set_enable(PERIPH_ID_I2C6, 1);
+#endif
+
+ /*
+ * Set MSELECT clock source as PLLP (00), and ask for a clock
+ * divider that would set the MSELECT clock at 102MHz for a
+ * PLLP base of 408MHz.
+ */
+ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+ CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+ /* Give clock time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+
+ /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+ /* Give clock time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+
+#if defined(CONFIG_I2C6_SUPPORTED)
+ /* Remove SOR clamp */
+ val = readl(&pmc->pmc_remove_clamping);
+ val |= (1 << SOR);
+ writel(val, &pmc->pmc_remove_clamping);
+ udelay(IO_STABILIZATION_DELAY);
+ /* Wait for the clamp bit to clear */
+ val = readl(&pmc->pmc_remove_clamping);
+ debug("%s: remove_clamping reg = 0x%08X\n", __func__, val);
+ while (val & (1 << SOR)) {
+ debug("%s: SOR bit still set (0x%08X), waiting ..\n", __func__, val);
+ val = readl(&pmc->pmc_remove_clamping);
+ }
+#endif
+ /* Take required peripherals out of reset */
+ debug("Taking periphs out of reset\n");
+ reset_set_enable(PERIPH_ID_CACHE2, 0);
+ reset_set_enable(PERIPH_ID_GPIO, 0);
+ reset_set_enable(PERIPH_ID_TMR, 0);
+ reset_set_enable(PERIPH_ID_COP, 0);
+ reset_set_enable(PERIPH_ID_EMC, 0);
+ reset_set_enable(PERIPH_ID_I2C5, 0);
+ reset_set_enable(PERIPH_ID_APBDMA, 0);
+ reset_set_enable(PERIPH_ID_MEM, 0);
+ reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+ reset_set_enable(PERIPH_ID_MSELECT, 0);
+ reset_set_enable(PERIPH_ID_DVFS, 0);
+#if defined(CONFIG_I2C6_SUPPORTED)
+ /* I2C6 is in the SOR/DPAUX domain, so enable these blocks, too */
+ reset_set_enable(PERIPH_ID_DPAUX, 0);
+ reset_set_enable(PERIPH_ID_HOST1X, 0);
+ reset_set_enable(PERIPH_ID_I2C6, 0);
+
+ /* Set DPAUX_HYBRID_PADCTL for I2C6: I2C_SDA/SCL RCVs enabled, MODE=I2C */
+ writel(0xc001, 0x545C0124);
+ /* Reset DPAUX_HYBRID_SPARE_0 bit 0 to power up pads */
+ writel(0x0, 0x545C0134);
+#endif
+ debug("%s exit\n", __func__);
+}
+
+static bool is_partition_powered(u32 partid)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Get power gate status */
+ reg = readl(&pmc->pmc_pwrgate_status);
+ return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("%s: part ID = %08X\n", __func__, partid);
+ /* Is the partition already on? */
+ if (!is_partition_powered(partid)) {
+ /* No, toggle the partition power state (OFF -> ON) */
+ debug("power_partition, toggling state\n");
+ writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+ /* Wait for the power to come up */
+ while (!is_partition_powered(partid))
+ ;
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+ }
+}
+
+void powerup_cpus(void)
+{
+ /* We boot to the fast cluster */
+ debug("%s entry: G cluster\n", __func__);
+
+ /* Power up the fast cluster rail partition */
+ debug("%s: CRAIL\n", __func__);
+ power_partition(CRAIL);
+
+ /* Power up the fast cluster non-CPU partition */
+ debug("%s: C0NC\n", __func__);
+ power_partition(C0NC);
+
+ /* Power up the fast cluster CPU0 partition */
+ debug("%s: CE0\n", __func__);
+ power_partition(CE0);
+
+ debug("%s: done\n", __func__);
+}
+
+void start_cpu(u32 reset_vector)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
+
+ tegra210_init_clocks();
+
+ /* Set power-gating timer multiplier */
+ writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+ &pmc->pmc_pwrgate_timer_mult);
+
+ enable_cpu_power_rail();
+ enable_cpu_clocks();
+ clock_enable_coresight(1);
+ remove_cpu_resets();
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+ /*
+ * T210 TRM, section 12.4.4.2: "SB_AA64_RESET_LOW_0[0:0] is used to
+ * decide between CPU boot up in AARCH32 (=0) or AARCH64 (=1) mode.
+ * This bit .. is sampled only during 'cold reset of CPU'. Before the
+ * CPU is powered up, the CPU reset vector is loaded in EVP_CPU_REST_VECTOR_0
+ * for 32-bit boot mode .... However, the CPU decides to boot in
+ * 32-/64-bit mode based on SB_AA64_RESET_LOW_0[0:0]. If this bit is
+ * set (=1), the CPU boots in 64-bit mode using SB_AA64_RESET_* as the
+ * reset address. If this bit is clear (=0), CPU boots in 32-bit mode
+ * using EVP_CPU_RESET_VECTOR."
+ *
+ * reset_vector s/b the same as TEXT_BASE (0x8010E000), so bit 0 = 0.
+ */
+ writel(reset_vector, SB_AA64_RESET_LOW);
+ writel(0, SB_AA64_RESET_HIGH);
+ /*
+ * Special case here:
+ * To get a 64-bit CPU binary, we build w/ARM64 defined. But that doesn't
+ * build a SPL portion, since the AVP/BPMP is only 32-bit. So we need a
+ * hybrid 32-bit SPL/64-bit CPU binary, and to get that we need a special
+ * 32-bit build with CONFIG_BUILD_64BIT_LOADER defined to set bit 0 here
+ * to boot the A57 CPU in 64-bit mode. This special SPL build is then
+ * used with the 64-bit CPU binary from a 64-bit build to create a hybrid
+ * U-Boot than can boot T210 on a 64-bit CPU. Kludgy, but it works.
+ */
+#if defined(CONFIG_BUILD_64BIT_LOADER)
+ setbits_le32(SB_AA64_RESET_LOW, (1 << 0));
+#endif
+ powerup_cpus();
+ debug("%s exit, should continue @ reset_vector\n", __func__);
+}
diff --git a/arch/arm/mach-tegra/tegra210/funcmux.c b/arch/arm/mach-tegra/tegra210/funcmux.c
new file mode 100644
index 0000000..d5fc009
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra210/funcmux.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra210 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+ int bad_config = config != FUNCMUX_DEFAULT;
+
+ switch (id) {
+ case PERIPH_ID_UART4:
+ switch (config) {
+ case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
+ pinmux_set_func(PMUX_PINGRP_UART4_TX_PI4, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_UART4_RX_PI5, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_UART4_CTS_PI7, PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_UART4_RTS_PI6, PMUX_FUNC_UARTD);
+
+ pinmux_set_io(PMUX_PINGRP_UART4_TX_PI4, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_UART4_RX_PI5, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_UART4_CTS_PI7, PMUX_PIN_INPUT);
+ pinmux_set_io(PMUX_PINGRP_UART4_RTS_PI6, PMUX_PIN_OUTPUT);
+
+ pinmux_tristate_disable(PMUX_PINGRP_UART4_TX_PI4);
+ pinmux_tristate_disable(PMUX_PINGRP_UART4_RX_PI5);
+ pinmux_tristate_disable(PMUX_PINGRP_UART4_CTS_PI7);
+ pinmux_tristate_disable(PMUX_PINGRP_UART4_RTS_PI6);
+ break;
+ }
+ break;
+
+ case PERIPH_ID_UART1:
+ switch (config) {
+ case FUNCMUX_UART1_KBC:
+ pinmux_set_func(PMUX_PINGRP_UART1_TX_PU0,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_UART1_RX_PU1,
+ PMUX_FUNC_UARTA);
+
+ pinmux_set_io(PMUX_PINGRP_UART1_TX_PU0, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_UART1_RX_PU1, PMUX_PIN_INPUT);
+
+ pinmux_tristate_disable(PMUX_PINGRP_UART1_TX_PU0);
+ pinmux_tristate_disable(PMUX_PINGRP_UART1_RX_PU1);
+ break;
+ }
+ break;
+
+ /* Add other periph IDs here as needed */
+
+ default:
+ debug("%s: invalid periph_id %d", __func__, id);
+ return -1;
+ }
+
+ if (bad_config) {
+ debug("%s: invalid config %d for periph_id %d", __func__,
+ config, id);
+ return -1;
+ }
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
new file mode 100644
index 0000000..75ffdc7
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/xusb-padctl.h>
+
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+
+struct tegra_xusb_phy_ops {
+ int (*prepare)(struct tegra_xusb_phy *phy);
+ int (*enable)(struct tegra_xusb_phy *phy);
+ int (*disable)(struct tegra_xusb_phy *phy);
+ int (*unprepare)(struct tegra_xusb_phy *phy);
+};
+
+struct tegra_xusb_phy {
+ const struct tegra_xusb_phy_ops *ops;
+
+ struct tegra_xusb_padctl *padctl;
+};
+
+struct tegra_xusb_padctl {
+ struct fdt_resource regs;
+
+ unsigned int enable;
+
+ struct tegra_xusb_phy phys[2];
+};
+
+static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
+ unsigned long offset)
+{
+ u32 value = readl(padctl->regs.start + offset);
+ debug("padctl: %08lx > %08x\n", offset, value);
+ return value;
+}
+
+static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
+ u32 value, unsigned long offset)
+{
+ debug("padctl: %08lx < %08x\n", offset, value);
+ writel(value, padctl->regs.start + offset);
+}
+
+#define XUSB_PADCTL_ELPG_PROGRAM 0x024
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
+
+static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
+{
+ u32 value;
+
+ if (padctl->enable++ > 0)
+ return 0;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ udelay(100);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ udelay(100);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ return 0;
+}
+
+static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
+{
+ u32 value;
+
+ if (padctl->enable == 0) {
+ error("tegra-xusb-padctl: unbalanced enable/disable");
+ return 0;
+ }
+
+ if (--padctl->enable > 0)
+ return 0;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ udelay(100);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ udelay(100);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ return 0;
+}
+
+static int phy_prepare(struct tegra_xusb_phy *phy)
+{
+ int err;
+
+ err = tegra_xusb_padctl_enable(phy->padctl);
+ if (err < 0)
+ return err;
+
+ reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
+
+ return 0;
+}
+
+static int phy_unprepare(struct tegra_xusb_phy *phy)
+{
+ reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
+
+ return tegra_xusb_padctl_disable(phy->padctl);
+}
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
+
+#define CLK_RST_XUSBIO_PLL_CFG0 0x51c
+#define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
+#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
+#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
+#define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
+#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
+
+static int pcie_phy_enable(struct tegra_xusb_phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy->padctl;
+ unsigned long start;
+ u32 value;
+
+ debug("> %s(phy=%p)\n", __func__, phy);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+ udelay(1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+
+ debug(" waiting for calibration\n");
+
+ start = get_timer(0);
+
+ while (get_timer(start) < 250) {
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
+ break;
+ }
+
+ debug(" done\n");
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+
+ debug(" waiting for calibration to stop\n");
+
+ start = get_timer(0);
+
+ while (get_timer(start) < 250) {
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
+ break;
+ }
+
+ debug(" done\n");
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+ debug(" waiting for PLL to lock...\n");
+ start = get_timer(0);
+
+ while (get_timer(start) < 250) {
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
+ break;
+ }
+
+ debug(" done\n");
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+
+ debug(" waiting for register calibration...\n");
+ start = get_timer(0);
+
+ while (get_timer(start) < 250) {
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
+ break;
+ }
+
+ debug(" done\n");
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+
+ debug(" waiting for register calibration to stop...\n");
+ start = get_timer(0);
+
+ while (get_timer(start) < 250) {
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
+ break;
+ }
+
+ debug(" done\n");
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+
+ value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
+ value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
+ value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
+ value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
+ value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
+ writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
+ padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+
+ udelay(1);
+
+ value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
+ value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
+ writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
+
+ debug("< %s()\n", __func__);
+ return 0;
+}
+
+static int pcie_phy_disable(struct tegra_xusb_phy *phy)
+{
+ return 0;
+}
+
+static const struct tegra_xusb_phy_ops pcie_phy_ops = {
+ .prepare = phy_prepare,
+ .enable = pcie_phy_enable,
+ .disable = pcie_phy_disable,
+ .unprepare = phy_unprepare,
+};
+
+static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
+ .phys = {
+ [0] = {
+ .ops = &pcie_phy_ops,
+ },
+ },
+};
+
+static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
+ const void *fdt, int node)
+{
+ int err;
+
+ err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
+ if (err < 0) {
+ error("tegra-xusb-padctl: registers not found");
+ return err;
+ }
+
+ debug("tegra-xusb-padctl: regs: %pa-%pa\n", &padctl->regs.start,
+ &padctl->regs.end);
+
+ return 0;
+}
+
+static int process_nodes(const void *fdt, int nodes[], unsigned int count)
+{
+ unsigned int i;
+ int err;
+
+ debug("> %s(fdt=%p, nodes=%p, count=%u)\n", __func__, fdt, nodes, count);
+
+ for (i = 0; i < count; i++) {
+ enum fdt_compat_id id;
+
+ if (!fdtdec_get_is_enabled(fdt, nodes[i]))
+ continue;
+
+ id = fdtdec_lookup(fdt, nodes[i]);
+ switch (id) {
+ case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
+ case COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL:
+ break;
+
+ default:
+ error("tegra-xusb-padctl: unsupported compatible: %s",
+ fdtdec_get_compatible(id));
+ continue;
+ }
+
+ err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
+ if (err < 0) {
+ error("tegra-xusb-padctl: failed to parse DT: %d",
+ err);
+ continue;
+ }
+
+ /* deassert XUSB padctl reset */
+ reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
+
+ /* only a single instance is supported */
+ break;
+ }
+
+ debug("< %s()\n", __func__);
+ return 0;
+}
+
+struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
+{
+ struct tegra_xusb_phy *phy = NULL;
+
+ switch (type) {
+ case TEGRA_XUSB_PADCTL_PCIE:
+ phy = &padctl->phys[0];
+ phy->padctl = padctl;
+ break;
+ }
+
+ return phy;
+}
+
+int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
+{
+ if (phy && phy->ops && phy->ops->prepare)
+ return phy->ops->prepare(phy);
+
+ return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
+{
+ if (phy && phy->ops && phy->ops->enable)
+ return phy->ops->enable(phy);
+
+ return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
+{
+ if (phy && phy->ops && phy->ops->disable)
+ return phy->ops->disable(phy);
+
+ return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
+{
+ if (phy && phy->ops && phy->ops->unprepare)
+ return phy->ops->unprepare(phy);
+
+ return phy ? -ENOSYS : -EINVAL;
+}
+
+void tegra_xusb_padctl_init(const void *fdt)
+{
+ int count, nodes[1];
+
+ debug("> %s(fdt=%p)\n", __func__, fdt);
+
+ count = fdtdec_find_aliases_for_id(fdt, "padctl",
+ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+ nodes, ARRAY_SIZE(nodes));
+ if (process_nodes(fdt, nodes, count))
+ return;
+
+ count = fdtdec_find_aliases_for_id(fdt, "padctl",
+ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+ nodes, ARRAY_SIZE(nodes));
+ if (process_nodes(fdt, nodes, count))
+ return;
+
+ debug("< %s()\n", __func__);
+}
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
new file mode 100644
index 0000000..102a3ef
--- /dev/null
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -0,0 +1,342 @@
+/*
+ * This header provides constants for binding nvidia,tegra210-car.
+ *
+ * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 185 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+#define TEGRA210_CLK_ISPB 3
+#define TEGRA210_CLK_RTC 4
+#define TEGRA210_CLK_TIMER 5
+#define TEGRA210_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA210_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA210_CLK_I2S1 11
+#define TEGRA210_CLK_I2C1 12
+#define TEGRA210_CLK_NDFLASH 13
+#define TEGRA210_CLK_SDMMC1 14
+#define TEGRA210_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA210_CLK_PWM 17
+#define TEGRA210_CLK_I2S2 18
+/* 20 (register bit affects vi and vi_sensor) */
+/* 21 */
+#define TEGRA210_CLK_USBD 22
+#define TEGRA210_CLK_ISP 23
+/* 26 */
+/* 25 */
+#define TEGRA210_CLK_DISP2 26
+#define TEGRA210_CLK_DISP1 27
+#define TEGRA210_CLK_HOST1X 28
+#define TEGRA210_CLK_VCP 29
+#define TEGRA210_CLK_I2S0 30
+/* 31 */
+
+/* 32 */
+/* 33 */
+#define TEGRA210_CLK_APBDMA 34
+/* 35 */
+#define TEGRA210_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA210_CLK_KFUSE 40
+#define TEGRA210_CLK_SBC1 41
+#define TEGRA210_CLK_NOR 42
+/* 43 */
+#define TEGRA210_CLK_SBC2 44
+/* 45 */
+#define TEGRA210_CLK_SBC3 46
+#define TEGRA210_CLK_I2C5 47
+#define TEGRA210_CLK_DSIA 48
+/* 49 */
+#define TEGRA210_CLK_MIPI 50
+#define TEGRA210_CLK_HDMI 51
+#define TEGRA210_CLK_CSI 52
+/* 53 */
+#define TEGRA210_CLK_I2C2 54
+#define TEGRA210_CLK_UARTC 55
+#define TEGRA210_CLK_MIPI_CAL 56
+#define TEGRA210_CLK_EMC 57
+#define TEGRA210_CLK_USB2 58
+#define TEGRA210_CLK_USB3 59
+/* 60 */
+#define TEGRA210_CLK_VDE 61
+#define TEGRA210_CLK_BSEA 62
+#define TEGRA210_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA210_CLK_UARTD 65
+#define TEGRA210_CLK_UARTE 66
+#define TEGRA210_CLK_I2C3 67
+#define TEGRA210_CLK_SBC4 68
+#define TEGRA210_CLK_SDMMC3 69
+#define TEGRA210_CLK_PCIE 70
+#define TEGRA210_CLK_OWR 71
+#define TEGRA210_CLK_AFI 72
+#define TEGRA210_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA210_CLK_LA 76
+#define TEGRA210_CLK_TRACE 77
+#define TEGRA210_CLK_SOC_THERM 78
+#define TEGRA210_CLK_DTV 79
+#define TEGRA210_CLK_NDSPEED 80
+#define TEGRA210_CLK_I2CSLOW 81
+#define TEGRA210_CLK_DSIB 82
+#define TEGRA210_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA210_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA210_CLK_MSENC 91
+#define TEGRA210_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA210_CLK_MSELECT 99
+#define TEGRA210_CLK_TSENSOR 100
+#define TEGRA210_CLK_I2S3 101
+#define TEGRA210_CLK_I2S4 102
+#define TEGRA210_CLK_I2C4 103
+#define TEGRA210_CLK_SBC5 104
+#define TEGRA210_CLK_SBC6 105
+#define TEGRA210_CLK_D_AUDIO 106
+#define TEGRA210_CLK_APBIF 107
+#define TEGRA210_CLK_DAM0 108
+#define TEGRA210_CLK_DAM1 109
+#define TEGRA210_CLK_DAM2 110
+#define TEGRA210_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA210_CLK_AUDIO0_2X 113
+#define TEGRA210_CLK_AUDIO1_2X 114
+#define TEGRA210_CLK_AUDIO2_2X 115
+#define TEGRA210_CLK_AUDIO3_2X 116
+#define TEGRA210_CLK_AUDIO4_2X 117
+#define TEGRA210_CLK_SPDIF_2X 118
+#define TEGRA210_CLK_ACTMON 119
+#define TEGRA210_CLK_EXTERN1 120
+#define TEGRA210_CLK_EXTERN2 121
+#define TEGRA210_CLK_EXTERN3 122
+#define TEGRA210_CLK_SATA_OOB 123
+#define TEGRA210_CLK_SATA 124
+#define TEGRA210_CLK_HDA 125
+/* 126 */
+#define TEGRA210_CLK_SE 127
+
+#define TEGRA210_CLK_HDA2HDMI 128
+#define TEGRA210_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/* xusb_host_src and xusb_ss_src) */
+#define TEGRA210_CLK_CILAB 144
+#define TEGRA210_CLK_CILCD 145
+#define TEGRA210_CLK_CILE 146
+#define TEGRA210_CLK_DSIALP 147
+#define TEGRA210_CLK_DSIBLP 148
+#define TEGRA210_CLK_ENTROPY 149
+#define TEGRA210_CLK_DDS 150
+/* 151 */
+#define TEGRA210_CLK_DP2 152
+#define TEGRA210_CLK_AMX 153
+#define TEGRA210_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA210_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+#define TEGRA210_CLK_I2C6 166
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+#define TEGRA210_CLK_VIM2_CLK 171
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+#define TEGRA210_CLK_HDMI_AUDIO 176
+#define TEGRA210_CLK_CLK72MHZ 177
+#define TEGRA210_CLK_VIC03 178
+/* 179 */
+#define TEGRA210_CLK_ADX1 180
+#define TEGRA210_CLK_DPAUX 181
+#define TEGRA210_CLK_SOR0 182
+/* 183 */
+#define TEGRA210_CLK_GPU 184
+#define TEGRA210_CLK_AMX1 185
+#define TEGRA210_CLK_AFC0 186
+#define TEGRA210_CLK_AFC1 187
+#define TEGRA210_CLK_AFC2 188
+#define TEGRA210_CLK_AFC3 189
+#define TEGRA210_CLK_AFC4 190
+#define TEGRA210_CLK_AFC5 191
+#define TEGRA210_CLK_UARTB 192
+#define TEGRA210_CLK_VFIR 193
+#define TEGRA210_CLK_SPDIF_IN 194
+#define TEGRA210_CLK_SPDIF_OUT 195
+#define TEGRA210_CLK_VI 196
+#define TEGRA210_CLK_VI_SENSOR 197
+#define TEGRA210_CLK_FUSE 198
+#define TEGRA210_CLK_FUSE_BURN 199
+#define TEGRA210_CLK_CLK_32K 200
+#define TEGRA210_CLK_CLK_M 201
+#define TEGRA210_CLK_CLK_M_DIV2 202
+#define TEGRA210_CLK_CLK_M_DIV4 203
+#define TEGRA210_CLK_PLL_REF 204
+#define TEGRA210_CLK_PLL_C 205
+#define TEGRA210_CLK_PLL_C_OUT1 206
+#define TEGRA210_CLK_PLL_C2 207
+#define TEGRA210_CLK_PLL_C3 208
+#define TEGRA210_CLK_PLL_M 209
+#define TEGRA210_CLK_PLL_M_OUT1 210
+#define TEGRA210_CLK_PLL_P 211
+#define TEGRA210_CLK_PLL_P_OUT1 212
+#define TEGRA210_CLK_PLL_P_OUT2 213
+#define TEGRA210_CLK_PLL_P_OUT3 214
+#define TEGRA210_CLK_PLL_P_OUT4 215
+#define TEGRA210_CLK_PLL_A 216
+#define TEGRA210_CLK_PLL_A_OUT0 217
+#define TEGRA210_CLK_PLL_D 218
+#define TEGRA210_CLK_PLL_D_OUT0 219
+#define TEGRA210_CLK_PLL_D2 220
+#define TEGRA210_CLK_PLL_D2_OUT0 221
+#define TEGRA210_CLK_PLL_U 222
+#define TEGRA210_CLK_PLL_U_480M 223
+
+#define TEGRA210_CLK_PLL_U_60M 224
+#define TEGRA210_CLK_PLL_U_48M 225
+#define TEGRA210_CLK_PLL_U_12M 226
+#define TEGRA210_CLK_PLL_X 227
+#define TEGRA210_CLK_PLL_X_OUT0 228
+#define TEGRA210_CLK_PLL_RE_VCO 229
+#define TEGRA210_CLK_PLL_RE_OUT 230
+#define TEGRA210_CLK_PLL_E 231
+#define TEGRA210_CLK_SPDIF_IN_SYNC 232
+#define TEGRA210_CLK_I2S0_SYNC 233
+#define TEGRA210_CLK_I2S1_SYNC 234
+#define TEGRA210_CLK_I2S2_SYNC 235
+#define TEGRA210_CLK_I2S3_SYNC 236
+#define TEGRA210_CLK_I2S4_SYNC 237
+#define TEGRA210_CLK_VIMCLK_SYNC 238
+#define TEGRA210_CLK_AUDIO0 239
+#define TEGRA210_CLK_AUDIO1 240
+#define TEGRA210_CLK_AUDIO2 241
+#define TEGRA210_CLK_AUDIO3 242
+#define TEGRA210_CLK_AUDIO4 243
+#define TEGRA210_CLK_SPDIF 244
+#define TEGRA210_CLK_CLK_OUT_1 245
+#define TEGRA210_CLK_CLK_OUT_2 246
+#define TEGRA210_CLK_CLK_OUT_3 247
+#define TEGRA210_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA210_CLK_XUSB_HOST_SRC 252
+#define TEGRA210_CLK_XUSB_FALCON_SRC 253
+#define TEGRA210_CLK_XUSB_FS_SRC 254
+#define TEGRA210_CLK_XUSB_SS_SRC 255
+
+#define TEGRA210_CLK_XUSB_DEV_SRC 256
+#define TEGRA210_CLK_XUSB_DEV 257
+#define TEGRA210_CLK_XUSB_HS_SRC 258
+#define TEGRA210_CLK_SCLK 259
+#define TEGRA210_CLK_HCLK 260
+#define TEGRA210_CLK_PCLK 261
+#define TEGRA210_CLK_CCLK_G 262
+#define TEGRA210_CLK_CCLK_LP 263
+#define TEGRA210_CLK_DFLL_REF 264
+#define TEGRA210_CLK_DFLL_SOC 265
+#define TEGRA210_CLK_VI_SENSOR2 266
+#define TEGRA210_CLK_PLL_P_OUT5 267
+#define TEGRA210_CLK_CML0 268
+#define TEGRA210_CLK_CML1 269
+#define TEGRA210_CLK_PLL_C4 270
+#define TEGRA210_CLK_PLL_DP 271
+#define TEGRA210_CLK_PLL_E_MUX 272
+/* 273 */
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA210_CLK_AUDIO0_MUX 300
+#define TEGRA210_CLK_AUDIO1_MUX 301
+#define TEGRA210_CLK_AUDIO2_MUX 302
+#define TEGRA210_CLK_AUDIO3_MUX 303
+#define TEGRA210_CLK_AUDIO4_MUX 304
+#define TEGRA210_CLK_SPDIF_MUX 305
+#define TEGRA210_CLK_CLK_OUT_1_MUX 306
+#define TEGRA210_CLK_CLK_OUT_2_MUX 307
+#define TEGRA210_CLK_CLK_OUT_3_MUX 308
+#define TEGRA210_CLK_DSIA_MUX 309
+#define TEGRA210_CLK_DSIB_MUX 310
+#define TEGRA210_CLK_SOR0_LVDS 311
+#define TEGRA210_CLK_PLL_M_UD 311
+#define TEGRA210_CLK_CLK_MAX 312
+
+#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
--
1.8.2.1.610.g562af5b
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 2/4] ARM: Tegra210: Add support to common Tegra source/config files
2015-06-03 20:35 [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Tom Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210 Tom Warren
@ 2015-06-03 20:35 ` Tom Warren
2015-06-15 17:18 ` Stephen Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board Tom Warren
` (2 subsequent siblings)
4 siblings, 1 reply; 21+ messages in thread
From: Tom Warren @ 2015-06-03 20:35 UTC (permalink / raw)
To: u-boot
Derived from Tegra124, modify as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too.
Note that the 'empty' Kconfig for Tegra210 will cause
an innocuous build warning, but it'll go away when a
real T210 board is instantiated.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
arch/arm/include/asm/arch-tegra/ap.h | 6 +--
arch/arm/include/asm/arch-tegra/clk_rst.h | 28 +++++++++++---
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 3 +-
arch/arm/include/asm/arch-tegra/pmc.h | 7 ++--
arch/arm/include/asm/arch-tegra/tegra.h | 4 +-
arch/arm/mach-tegra/Kconfig | 4 ++
arch/arm/mach-tegra/Makefile | 4 +-
arch/arm/mach-tegra/ap.c | 9 ++++-
arch/arm/mach-tegra/clock.c | 3 +-
arch/arm/mach-tegra/cpu.c | 55 ++++++++++++++++++++--------
arch/arm/mach-tegra/cpu.h | 10 +++--
include/fdtdec.h | 4 ++
lib/fdtdec.c | 3 ++
13 files changed, 104 insertions(+), 36 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index ca40e4e..76773b7 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -24,8 +24,6 @@
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
-
/* AP base physical address of internal SRAM */
#define NV_PA_BASE_SRAM 0x40000000
@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
/* Do any chip-specific cache config */
void config_cache(void);
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
/* Do chip-specific vpr config */
void config_vpr(void);
#else
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index de50e08..43efa65 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -48,6 +48,7 @@ enum {
TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
+ TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
- uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */
+ uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
+ uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
+ uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
+
+ uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
+ uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
+ uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
+
+ uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
- /* Additional (T114) registers */
+ /* Additional (T114+) registers */
uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
u32 _rsv32_1[7]; /* 0x574-58c */
struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
- u32 _rsrv32_2[25];
- /* Tegra124 */
- uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+
+ /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+ uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
+ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+ /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+ uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
+ /*
+ * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+ * two later if PLLA1 is needed, but for now this is cleaner.
+ */
+ uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
index 7a86acb..695f3e6 100644
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2012
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -21,5 +21,6 @@
#define CHIPID_TEGRA30 0x30
#define CHIPID_TEGRA114 0x35
#define CHIPID_TEGRA124 0x40
+#define CHIPID_TEGRA210 0x21
#endif /* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index 1dd3154..66c0879 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011,2014
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -294,6 +294,7 @@ struct pmc_ctlr {
#define CRAIL 0
#define CE0 14
#define C0NC 15
+#define SOR 17
#define PMC_XOFS_SHIFT 1
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
@@ -303,7 +304,7 @@ struct pmc_ctlr {
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 2
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
-#elif defined(CONFIG_TEGRA124)
+#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 3
@@ -314,7 +315,7 @@ struct pmc_ctlr {
#define MULT_2 1
#define MULT_4 2
#define MULT_8 3
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define MULT_16 4
#endif
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index d63af0e..b6c7cab 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -74,6 +74,7 @@ enum {
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
+ SKU_ID_T210_ENG = 0x00, /* unfused value TBD */
};
/*
@@ -88,6 +89,7 @@ enum {
TEGRA_SOC_T30,
TEGRA_SOC_T114,
TEGRA_SOC_T124,
+ TEGRA_SOC_T210,
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index fce1c1d..02164ee 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -15,6 +15,9 @@ config TEGRA114
config TEGRA124
bool "Tegra124 family"
+config TEGRA210
+ bool "Tegra210 family"
+
endchoice
config SYS_MALLOC_F_LEN
@@ -48,5 +51,6 @@ source "arch/arm/mach-tegra/tegra20/Kconfig"
source "arch/arm/mach-tegra/tegra30/Kconfig"
source "arch/arm/mach-tegra/tegra114/Kconfig"
source "arch/arm/mach-tegra/tegra124/Kconfig"
+source "arch/arm/mach-tegra/tegra210/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 68eec5c..f000e1a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2010,2011 Nvidia Corporation.
+# (C) Copyright 2010-2015 Nvidia Corporation.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -25,8 +25,10 @@ obj-y += powergate.o
obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
obj-$(CONFIG_TEGRA124) += vpr.o
+obj-$(CONFIG_TEGRA210) += vpr.o
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA210) += tegra210/
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index a17dfd1..8d95069 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -1,5 +1,5 @@
/*
-* (C) Copyright 2010-2014
+* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -91,6 +91,13 @@ int tegra_get_chip_sku(void)
return TEGRA_SOC_T124;
}
break;
+ case CHIPID_TEGRA210:
+ switch (sku_id) {
+ case SKU_ID_T210_ENG:
+ default:
+ return TEGRA_SOC_T210;
+ }
+ break;
}
/* unknown chip/sku id */
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index cdd5438..2ef8ae2 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -629,6 +629,7 @@ static void set_avp_clock_source(u32 src)
/*
* This function is useful on Tegra30, and any later SoCs that have compatible
* PLLP configuration registers.
+ * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
*/
void tegra30_set_up_pllp(void)
{
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index c6f3b02..f7d45e8 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -29,6 +29,7 @@ int get_num_cpus(void)
{
struct apb_misc_gp_ctlr *gp;
uint rev;
+ debug("%s entry\n", __func__);
gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
@@ -39,6 +40,8 @@ int get_num_cpus(void)
break;
case CHIPID_TEGRA30:
case CHIPID_TEGRA114:
+ case CHIPID_TEGRA124:
+ case CHIPID_TEGRA210:
default:
return 4;
break;
@@ -128,13 +131,30 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
},
+
+ /*
+ * T210: 700 MHz
+ *
+ * Register Field Bits Width
+ * ------------------------------
+ * PLLX_BASE p 24:20 5
+ * PLLX_BASE n 15: 8 8
+ * PLLX_BASE m 7: 0 8
+ */
+ {
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
+ { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
+ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
+ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
+ },
};
static inline void pllx_set_iddq(void)
{
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
+ debug("%s entry\n", __func__);
/* Disable IDDQ */
reg = readl(&clkrst->crc_pllx_misc3);
@@ -151,15 +171,14 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
{
int chip = tegra_get_chip();
u32 reg;
+ debug("%s entry\n", __func__);
/* If PLLX is already enabled, just return */
if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
- debug("pllx_set_rate: PLLX already enabled, returning\n");
+ debug("%s: PLLX already enabled, returning\n", __func__);
return 0;
}
- debug(" pllx_set_rate entry\n");
-
pllx_set_iddq();
/* Set BYPASS, m, n and p to PLLX_BASE */
@@ -182,19 +201,19 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
reg = readl(&pll->pll_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
- debug("pllx_set_rate: base = 0x%08X\n", reg);
+ debug("%s: base = 0x%08X\n", __func__, reg);
/* Set lock_enable to PLLX_MISC */
reg = readl(&pll->pll_misc);
reg |= PLL_LOCK_ENABLE_MASK;
writel(reg, &pll->pll_misc);
- debug("pllx_set_rate: misc = 0x%08X\n", reg);
+ debug("%s: misc = 0x%08X\n", __func__, reg);
/* Enable PLLX last, once it's all configured */
reg = readl(&pll->pll_base);
reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
- debug("pllx_set_rate: base final = 0x%08X\n", reg);
+ debug("%s: base final = 0x%08X\n", __func__, reg);
return 0;
}
@@ -206,24 +225,23 @@ void init_pllx(void)
int soc_type, sku_info, chip_sku;
enum clock_osc_freq osc;
struct clk_pll_table *sel;
-
- debug("init_pllx entry\n");
+ debug("%s entry\n", __func__);
/* get SOC (chip) type */
soc_type = tegra_get_chip();
- debug(" init_pllx: SoC = 0x%02X\n", soc_type);
+ debug("%s: SoC = 0x%02X\n", __func__, soc_type);
/* get SKU info */
sku_info = tegra_get_sku_info();
- debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
+ debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
/* get chip SKU, combo of the above info */
chip_sku = tegra_get_chip_sku();
- debug(" init_pllx: Chip SKU = %d\n", chip_sku);
+ debug("%s: Chip SKU = %d\n", __func__, chip_sku);
/* get osc freq */
osc = clock_get_osc_freq();
- debug(" init_pllx: osc = %d\n", osc);
+ debug("%s: osc = %d\n", __func__, osc);
/* set pllx */
sel = &tegra_pll_x_table[chip_sku][osc];
@@ -234,6 +252,7 @@ void enable_cpu_clock(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 clk;
+ debug("%s entry\n", __func__);
/*
* NOTE:
@@ -282,6 +301,7 @@ static void remove_cpu_io_clamps(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
+ debug("%s entry\n", __func__);
/* Remove the clamps on the CPU I/O signals */
reg = readl(&pmc->pmc_remove_clamping);
@@ -297,6 +317,7 @@ void powerup_cpu(void)
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
+ debug("%s entry\n", __func__);
if (!is_cpu_powered()) {
/* Toggle the CPU power state (OFF -> ON) */
@@ -336,7 +357,7 @@ void reset_A9_cpu(int reset)
int num_cpus = get_num_cpus();
int cpu;
- debug("reset_a9_cpu entry\n");
+ debug("%s entry\n", __func__);
/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
for (cpu = 1; cpu < num_cpus; cpu++)
reset_cmplx_set_enable(cpu, mask, 1);
@@ -350,7 +371,7 @@ void clock_enable_coresight(int enable)
{
u32 rst, src = 2;
- debug("clock_enable_coresight entry\n");
+ debug("%s entry\n", __func__);
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
@@ -377,6 +398,8 @@ void clock_enable_coresight(int enable)
void halt_avp(void)
{
+ debug("%s entry\n", __func__);
+
for (;;) {
writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
FLOW_CTLR_HALT_COP_EVENTS);
diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h
index b4ca44f..3f38969 100644
--- a/arch/arm/mach-tegra/cpu.h
+++ b/arch/arm/mach-tegra/cpu.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2014
+ * (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -14,7 +14,7 @@
#define NVBL_PLLP_KHZ 216000
#define CSITE_KHZ 144000
#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
- defined(CONFIG_TEGRA124)
+ defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define NVBL_PLLP_KHZ 408000
#define CSITE_KHZ 204000
#else
@@ -35,7 +35,7 @@
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
+#define CORESIGHT_UNLOCK 0xC5ACCE55
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
@@ -53,6 +53,10 @@
#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
+#define SB_AA64_RESET_LOW 0x6000C230
+#define SB_AA64_RESET_HIGH 0x6000C234
+
struct clk_pll_table {
u16 n;
u16 m;
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 207035a..fc84258 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -115,6 +115,7 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */
COMPAT_NVIDIA_TEGRA30_USB, /* Tegra30 USB port */
COMPAT_NVIDIA_TEGRA114_USB, /* Tegra114 USB port */
+ COMPAT_NVIDIA_TEGRA210_USB, /* Tegra210 USB port */
COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
@@ -124,6 +125,7 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */
COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
@@ -132,6 +134,8 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
/* Tegra124 XUSB pad controller */
+ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+ /* Tegra210 XUSB pad controller */
COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 576b797..cf8c573 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -24,6 +24,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
COMPAT(NVIDIA_TEGRA30_USB, "nvidia,tegra30-ehci"),
COMPAT(NVIDIA_TEGRA114_USB, "nvidia,tegra114-ehci"),
+ COMPAT(NVIDIA_TEGRA210_USB, "nvidia,tegra210-ehci"),
COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
@@ -33,6 +34,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+ COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
@@ -40,6 +42,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"),
COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"),
COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
+ COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
--
1.8.2.1.610.g562af5b
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board
2015-06-03 20:35 [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Tom Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210 Tom Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 2/4] ARM: Tegra210: Add support to common Tegra source/config files Tom Warren
@ 2015-06-03 20:35 ` Tom Warren
2015-06-15 17:23 ` Stephen Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board Tom Warren
2015-06-17 20:07 ` [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Stephen Warren
4 siblings, 1 reply; 21+ messages in thread
From: Tom Warren @ 2015-06-03 20:35 UTC (permalink / raw)
To: u-boot
Based on T124 Venice2. SDMMC1 is SD-card slot.
Using tegra124 compat names for now to get everything
working. May need minor work to match the real board.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
arch/arm/dts/Makefile | 3 +-
.../{tegra124-venice2.dts => tegra210-p2571.dts} | 40 ++++--
arch/arm/dts/{tegra124.dtsi => tegra210.dtsi} | 153 ++++-----------------
3 files changed, 56 insertions(+), 140 deletions(-)
copy arch/arm/dts/{tegra124-venice2.dts => tegra210-p2571.dts} (65%)
copy arch/arm/dts/{tegra124.dtsi => tegra210.dtsi} (76%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f897e6d..3e09cb5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,7 +33,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
- tegra124-venice2.dtb
+ tegra124-venice2.dtb \
+ tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra210-p2571.dts
similarity index 65%
copy from arch/arm/dts/tegra124-venice2.dts
copy to arch/arm/dts/tegra210-p2571.dts
index 9e93cf9..ca41390 100644
--- a/arch/arm/dts/tegra124-venice2.dts
+++ b/arch/arm/dts/tegra210-p2571.dts
@@ -1,10 +1,10 @@
/dts-v1/;
-#include "tegra124.dtsi"
+#include "tegra210.dtsi"
/ {
- model = "NVIDIA Venice2";
- compatible = "nvidia,venice2", "nvidia,tegra124";
+ model = "NVIDIA P2571";
+ compatible = "nvidia,p2571", "nvidia,tegra210";
chosen {
stdout-path = &uarta;
@@ -18,16 +18,15 @@
i2c4 = "/i2c at 7000c700";
i2c5 = "/i2c at 7000d100";
sdhci0 = "/sdhci at 700b0600";
- sdhci1 = "/sdhci at 700b0400";
+ sdhci1 = "/sdhci at 700b0000";
spi0 = "/spi at 7000d400";
spi1 = "/spi at 7000da00";
+ spi2 = "/spi at 70410000";
usb0 = "/usb at 7d000000";
- usb1 = "/usb at 7d008000";
};
memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
+ reg = <0x0 0x80000000 0x0 0xc0000000>;
};
i2c at 7000c000 {
@@ -70,11 +69,15 @@
spi-max-frequency = <25000000>;
};
- sdhci at 700b0400 {
+ spi at 70410000 {
status = "okay";
- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
- power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
- wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <24000000>;
+ };
+
+ sdhci at 700b0000 {
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -86,11 +89,18 @@
usb at 7d000000 {
status = "okay";
dr_mode = "otg";
- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
- usb at 7d008000 {
- status = "okay";
- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock at 0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
};
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra210.dtsi
similarity index 76%
copy from arch/arm/dts/tegra124.dtsi
copy to arch/arm/dts/tegra210.dtsi
index 43b7f22..f09a1a7 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra210.dtsi
@@ -1,4 +1,4 @@
-#include <dt-bindings/clock/tegra124-car.h>
+#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -7,7 +7,7 @@
#include "skeleton.dtsi"
/ {
- compatible = "nvidia,tegra124";
+ compatible = "nvidia,tegra210";
interrupt-parent = <&gic>;
pcie-controller at 01003000 {
@@ -35,10 +35,10 @@
0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
- clocks = <&tegra_car TEGRA124_CLK_PCIE>,
- <&tegra_car TEGRA124_CLK_AFI>,
- <&tegra_car TEGRA124_CLK_PLL_E>,
- <&tegra_car TEGRA124_CLK_CML0>;
+ clocks = <&tegra_car TEGRA210_CLK_PCIE>,
+ <&tegra_car TEGRA210_CLK_AFI>,
+ <&tegra_car TEGRA210_CLK_PLL_E>,
+ <&tegra_car TEGRA210_CLK_CML0>;
clock-names = "pex", "afi", "pll_e", "cml";
resets = <&tegra_car 70>,
<&tegra_car 72>,
@@ -76,85 +76,6 @@
};
};
- host1x at 50000000 {
- compatible = "nvidia,tegra124-host1x", "simple-bus";
- reg = <0x50000000 0x00034000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
- <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
- clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
- resets = <&tegra_car 28>;
- reset-names = "host1x";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- ranges = <0x54000000 0x54000000 0x01000000>;
-
- dc at 54200000 {
- compatible = "nvidia,tegra124-dc";
- reg = <0x54200000 0x00040000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_DISP1>,
- <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "dc", "parent";
- resets = <&tegra_car 27>;
- reset-names = "dc";
-
- nvidia,head = <0>;
- };
-
- dc at 54240000 {
- compatible = "nvidia,tegra124-dc";
- reg = <0x54240000 0x00040000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_DISP2>,
- <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "dc", "parent";
- resets = <&tegra_car 26>;
- reset-names = "dc";
-
- nvidia,head = <1>;
- };
-
- hdmi at 54280000 {
- compatible = "nvidia,tegra124-hdmi";
- reg = <0x54280000 0x00040000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_HDMI>,
- <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
- clock-names = "hdmi", "parent";
- resets = <&tegra_car 51>;
- reset-names = "hdmi";
- status = "disabled";
- };
-
- sor at 54540000 {
- compatible = "nvidia,tegra124-sor";
- reg = <0x54540000 0x00040000>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_SOR0>,
- <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
- <&tegra_car TEGRA124_CLK_PLL_DP>,
- <&tegra_car TEGRA124_CLK_CLK_M>;
- clock-names = "sor", "parent", "dp", "safe";
- resets = <&tegra_car 182>;
- reset-names = "sor";
- status = "disabled";
- };
-
- dpaux: dpaux at 545c0000 {
- compatible = "nvidia,tegra124-dpaux";
- reg = <0x545c0000 0x00040000>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
- <&tegra_car TEGRA124_CLK_PLL_DP>;
- clock-names = "dpaux", "parent";
- resets = <&tegra_car 181>;
- reset-names = "dpaux";
- status = "disabled";
- };
- };
-
gic: interrupt-controller at 50041000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
@@ -292,7 +213,7 @@
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_UARTA>;
+ clocks = <&tegra_car TEGRA210_CLK_UARTA>;
resets = <&tegra_car 6>;
reset-names = "serial";
dmas = <&apbdma 8>, <&apbdma 8>;
@@ -305,7 +226,7 @@
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_UARTB>;
+ clocks = <&tegra_car TEGRA210_CLK_UARTB>;
resets = <&tegra_car 7>;
reset-names = "serial";
dmas = <&apbdma 9>, <&apbdma 9>;
@@ -318,7 +239,7 @@
reg = <0x70006200 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_UARTC>;
+ clocks = <&tegra_car TEGRA210_CLK_UARTC>;
resets = <&tegra_car 55>;
reset-names = "serial";
dmas = <&apbdma 10>, <&apbdma 10>;
@@ -331,7 +252,7 @@
reg = <0x70006300 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_UARTD>;
+ clocks = <&tegra_car TEGRA210_CLK_UARTD>;
resets = <&tegra_car 65>;
reset-names = "serial";
dmas = <&apbdma 19>, <&apbdma 19>;
@@ -339,24 +260,11 @@
status = "disabled";
};
- uarte: serial at 70006400 {
- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
- reg = <0x70006400 0x40>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_UARTE>;
- resets = <&tegra_car 66>;
- reset-names = "serial";
- dmas = <&apbdma 20>, <&apbdma 20>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
pwm: pwm at 7000a000 {
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
- clocks = <&tegra_car TEGRA124_CLK_PWM>;
+ clocks = <&tegra_car TEGRA210_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
status = "disabled";
@@ -428,9 +336,15 @@
clocks = <&tegra_car 105>;
};
- pmc at 7000e400 {
- compatible = "nvidia,tegra124-pmc";
- reg = <0x7000e400 0x400>;
+ spi at 70410000 {
+ compatible = "nvidia,tegra210-qspi";
+ reg = <0x70410000 0x200>;
+ interrupts = <0 10 0x04>;
+ nvidia,dma-request-selector = <&apbdma 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 211>;
};
padctl: padctl at 7009f000 {
@@ -480,8 +394,8 @@
<0x70300800 0x800>,
<0x70300200 0x600>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
- <&tegra_car TEGRA124_CLK_APBIF>;
+ clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>,
+ <&tegra_car TEGRA210_CLK_APBIF>;
clock-names = "d_audio", "apbif";
resets = <&tegra_car 106>, /* d_audio */
<&tegra_car 107>, /* apbif */
@@ -530,7 +444,7 @@
compatible = "nvidia,tegra124-i2s";
reg = <0x70301000 0x100>;
nvidia,ahub-cif-ids = <4 4>;
- clocks = <&tegra_car TEGRA124_CLK_I2S0>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S0>;
resets = <&tegra_car 30>;
reset-names = "i2s";
status = "disabled";
@@ -540,7 +454,7 @@
compatible = "nvidia,tegra124-i2s";
reg = <0x70301100 0x100>;
nvidia,ahub-cif-ids = <5 5>;
- clocks = <&tegra_car TEGRA124_CLK_I2S1>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S1>;
resets = <&tegra_car 11>;
reset-names = "i2s";
status = "disabled";
@@ -550,7 +464,7 @@
compatible = "nvidia,tegra124-i2s";
reg = <0x70301200 0x100>;
nvidia,ahub-cif-ids = <6 6>;
- clocks = <&tegra_car TEGRA124_CLK_I2S2>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S2>;
resets = <&tegra_car 18>;
reset-names = "i2s";
status = "disabled";
@@ -560,7 +474,7 @@
compatible = "nvidia,tegra124-i2s";
reg = <0x70301300 0x100>;
nvidia,ahub-cif-ids = <7 7>;
- clocks = <&tegra_car TEGRA124_CLK_I2S3>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S3>;
resets = <&tegra_car 101>;
reset-names = "i2s";
status = "disabled";
@@ -570,7 +484,7 @@
compatible = "nvidia,tegra124-i2s";
reg = <0x70301400 0x100>;
nvidia,ahub-cif-ids = <8 8>;
- clocks = <&tegra_car TEGRA124_CLK_I2S4>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S4>;
resets = <&tegra_car 102>;
reset-names = "i2s";
status = "disabled";
@@ -578,7 +492,7 @@
};
usb at 7d000000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ compatible = "nvidia,tegra210-ehci";
reg = <0x7d000000 0x4000>;
interrupts = < 52 >;
phy_type = "utmi";
@@ -587,20 +501,11 @@
};
usb at 7d004000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ compatible = "nvidia,tegra210-ehci";
reg = <0x7d004000 0x4000>;
interrupts = < 53 >;
phy_type = "hsic";
clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
status = "disabled";
};
-
- usb at 7d008000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
- reg = <0x7d008000 0x4000>;
- interrupts = < 129 >;
- phy_type = "utmi";
- clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
- status = "disabled";
- };
};
--
1.8.2.1.610.g562af5b
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board
2015-06-03 20:35 [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Tom Warren
` (2 preceding siblings ...)
2015-06-03 20:35 ` [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board Tom Warren
@ 2015-06-03 20:35 ` Tom Warren
2015-06-15 17:58 ` Stephen Warren
2015-06-17 20:07 ` [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Stephen Warren
4 siblings, 1 reply; 21+ messages in thread
From: Tom Warren @ 2015-06-03 20:35 UTC (permalink / raw)
To: u-boot
Based on Venice2, may change as P2571 board is fully
brought up. Incorporates Stephen Warren's P2571 pinmux table.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
arch/arm/mach-tegra/tegra210/Kconfig | 7 +
board/nvidia/{beaver => p2571}/Kconfig | 6 +-
board/nvidia/p2571/MAINTAINERS | 6 +
board/nvidia/{venice2 => p2571}/Makefile | 6 +-
board/nvidia/p2571/max77620_init.c | 47 +++++
board/nvidia/p2571/max77620_init.h | 14 ++
board/nvidia/p2571/p2571.c | 29 +++
board/nvidia/p2571/pinmux-config-p2571.h | 235 +++++++++++++++++++++
configs/p2571_defconfig | 5 +
include/configs/{venice2.h => p2571.h} | 17 +-
.../{tegra124-common.h => tegra210-common.h} | 8 +-
11 files changed, 363 insertions(+), 17 deletions(-)
copy board/nvidia/{beaver => p2571}/Kconfig (61%)
create mode 100644 board/nvidia/p2571/MAINTAINERS
copy board/nvidia/{venice2 => p2571}/Makefile (55%)
create mode 100644 board/nvidia/p2571/max77620_init.c
create mode 100644 board/nvidia/p2571/max77620_init.h
create mode 100644 board/nvidia/p2571/p2571.c
create mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
create mode 100644 configs/p2571_defconfig
copy include/configs/{venice2.h => p2571.h} (81%)
copy include/configs/{tegra124-common.h => tegra210-common.h} (95%)
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index f2a0059..147e6a8 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,9 +3,16 @@ if TEGRA210
choice
prompt "Tegra210 board select"
+config TARGET_P2571
+ bool "NVIDIA Tegra210 P2571 base board"
+ help
+ P2571 is a P2530 married to a P1963 I/O board
+
endchoice
config SYS_SOC
default "tegra210"
+source "board/nvidia/p2571/Kconfig"
+
endif
diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/p2571/Kconfig
similarity index 61%
copy from board/nvidia/beaver/Kconfig
copy to board/nvidia/p2571/Kconfig
index 23f7c94..7bc4874 100644
--- a/board/nvidia/beaver/Kconfig
+++ b/board/nvidia/p2571/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_BEAVER
+if TARGET_P2571
config SYS_BOARD
- default "beaver"
+ default "p2571"
config SYS_VENDOR
default "nvidia"
config SYS_CONFIG_NAME
- default "beaver"
+ default "p2571"
endif
diff --git a/board/nvidia/p2571/MAINTAINERS b/board/nvidia/p2571/MAINTAINERS
new file mode 100644
index 0000000..c165135
--- /dev/null
+++ b/board/nvidia/p2571/MAINTAINERS
@@ -0,0 +1,6 @@
+P2571 BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/p2571/
+F: include/configs/p2571.h
+F: configs/p2571_defconfig
diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/p2571/Makefile
similarity index 55%
copy from board/nvidia/venice2/Makefile
copy to board/nvidia/p2571/Makefile
index 5fac5ab..223062e 100644
--- a/board/nvidia/venice2/Makefile
+++ b/board/nvidia/p2571/Makefile
@@ -1,9 +1,9 @@
#
-# (C) Copyright 2013-2014
+# (C) Copyright 2013-2015
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += as3722_init.o
-obj-y += venice2.o
+obj-y += max77620_init.o
+obj-y += p2571.o
diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c
new file mode 100644
index 0000000..98c94af
--- /dev/null
+++ b/board/nvidia/p2571/max77620_init.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "max77620_init.h"
+
+/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, ®->cmd_addr0);
+ writel(config, ®->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, ®->cmd_data1);
+ writel(config, ®->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+ debug("%s entry\n", __func__);
+
+ //from TegraShell init script: Set GPIO5 to drive CPU_REG_EN
+ // then 1.0V on ???
+ debug("%s: Setting GPIO5 to push-pull out, logic high to enable CPU regulator\n", __func__);
+ tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(0x2040, I2C_SEND_2_BYTES); //data/reg
+ udelay(10*1000);
+
+ tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(0x093B, I2C_SEND_2_BYTES); //B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull
+ udelay(10 * 1000);
+
+ debug("%s: Set VDD_SDMMC to 3.3V via MAX77620 reg ???\n", __func__);
+}
diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h
new file mode 100644
index 0000000..2278386
--- /dev/null
+++ b/board/nvidia/p2571/max77620_init.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* MAX77620-PMIC-specific early init regs */
+
+#define MAX77620_I2C_ADDR 0x78 /* or 0x3C 7-bit */
+
+#define I2C_SEND_2_BYTES 0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
new file mode 100644
index 0000000..fc710c1
--- /dev/null
+++ b/board/nvidia/p2571/p2571.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-p2571.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_clear_tristate_input_clamping();
+
+ gpio_config_table(p2571_gpio_inits,
+ ARRAY_SIZE(p2571_gpio_inits));
+
+ pinmux_config_pingrp_table(p2571_pingrps,
+ ARRAY_SIZE(p2571_pingrps));
+
+ pinmux_config_drvgrp_table(p2571_drvgrps,
+ ARRAY_SIZE(p2571_drvgrps));
+}
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
new file mode 100644
index 0000000..d476d5c
--- /dev/null
+++ b/board/nvidia/p2571/pinmux-config-p2571.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_P2571_H_
+#define _PINMUX_CONFIG_P2571_H_
+
+#define GPIO_INIT(_gpio, _init) \
+ { \
+ .gpio = GPIO_P##_gpio, \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config p2571_gpio_inits[] = {
+ /* gpio, init_val */
+ GPIO_INIT(A0, IN),
+ GPIO_INIT(A5, IN),
+ GPIO_INIT(D4, IN),
+ GPIO_INIT(E4, OUT0),
+ GPIO_INIT(G0, IN),
+ GPIO_INIT(H0, OUT0),
+ GPIO_INIT(H2, IN),
+ GPIO_INIT(H3, OUT0),
+ GPIO_INIT(H4, OUT0),
+ GPIO_INIT(H5, IN),
+ GPIO_INIT(I0, OUT0),
+ GPIO_INIT(I1, IN),
+ GPIO_INIT(V1, OUT0),
+ GPIO_INIT(V6, OUT1),
+ GPIO_INIT(X4, IN),
+ GPIO_INIT(X6, IN),
+ GPIO_INIT(X7, IN),
+ GPIO_INIT(Y1, IN),
+ GPIO_INIT(Z0, IN),
+ GPIO_INIT(Z4, OUT0),
+ GPIO_INIT(BB2, OUT0),
+ GPIO_INIT(CC1, IN),
+ GPIO_INIT(CC3, IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config p2571_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
+ PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config p2571_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_P2571_H */
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
new file mode 100644
index 0000000..a91ff22
--- /dev/null
+++ b/configs/p2571_defconfig
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA210=y
+CONFIG_TARGET_P2571=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
diff --git a/include/configs/venice2.h b/include/configs/p2571.h
similarity index 81%
copy from include/configs/venice2.h
copy to include/configs/p2571.h
index 4594002..b015452 100644
--- a/include/configs/venice2.h
+++ b/include/configs/p2571.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2013-2014
+ * (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -10,11 +10,14 @@
#include <linux/sizes.h>
-#include "tegra124-common.h"
+/* enable PMIC */
+#define CONFIG_MAX77620_POWER
+
+#include "tegra210-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra124 (Venice2) # "
-#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2"
+#define V_PROMPT "Tegra210 (P2571) # "
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
@@ -42,11 +45,11 @@
#define CONFIG_TEGRA114_SPI_CTRLS 6
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
#define CONFIG_USB_EHCI
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra210-common.h
similarity index 95%
copy from include/configs/tegra124-common.h
copy to include/configs/tegra210-common.h
index 1aee5c8..cebe598 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra210-common.h
@@ -1,12 +1,12 @@
/*
- * (C) Copyright 2013
+ * (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _TEGRA124_COMMON_H_
-#define _TEGRA124_COMMON_H_
+#ifndef _TEGRA210_COMMON_H_
+#define _TEGRA210_COMMON_H_
#include "tegra-common.h"
@@ -70,4 +70,4 @@
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
-#endif /* _TEGRA124_COMMON_H_ */
+#endif /* _TEGRA210_COMMON_H_ */
--
1.8.2.1.610.g562af5b
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
2015-06-03 20:35 ` [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210 Tom Warren
@ 2015-06-15 17:11 ` Stephen Warren
2015-06-15 20:04 ` Tom Warren
2015-06-15 22:18 ` Tom Warren
0 siblings, 2 replies; 21+ messages in thread
From: Stephen Warren @ 2015-06-15 17:11 UTC (permalink / raw)
To: u-boot
On 06/03/2015 02:35 PM, Tom Warren wrote:
> All based off of Tegra124. As a Tegra210 board is brought
> up, these may change a bit to match the HW more closely,
> but probably 90% of this is identical to T124.
Rather than duplicating lots of headers and code, can we share the
content with other chips?
> diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h b/arch/arm/include/asm/arch-tegra210/funcmux.h
We should be able to drop funcmux support completely now that we're
programming entire board pinmux tables.
> diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h
> +enum gpio_pin {
> + GPIO_PA0 = 0, /* pin 0 */
> + GPIO_PA1,
Given the move to DT, are any of these GPIO_xxx values actually used? I
wonder how many other types/defines in the other files are actually
used, rather than simply left over from times gone by.
> diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h b/arch/arm/include/asm/arch-tegra210/hardware.h
Can we drop this file? I don't see a hardware.h in any of the other
arch-tegra*/ directories.
> diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h
> +#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */
> +
> +#undef NVBOOTINFOTABLE_BCTSIZE
> +#undef NVBOOTINFOTABLE_BCTPTR
> +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
> +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
Have you validated those? I'm pretty sure the BCT and perhaps BIT layout
changed in T210, and those values match T124.
Have all the clock tables and IDs been updated to match T210? If not, I
think we should do that before checking in the code, or it'll be misleading.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 2/4] ARM: Tegra210: Add support to common Tegra source/config files
2015-06-03 20:35 ` [U-Boot] [PATCH 2/4] ARM: Tegra210: Add support to common Tegra source/config files Tom Warren
@ 2015-06-15 17:18 ` Stephen Warren
0 siblings, 0 replies; 21+ messages in thread
From: Stephen Warren @ 2015-06-15 17:18 UTC (permalink / raw)
To: u-boot
On 06/03/2015 02:35 PM, Tom Warren wrote:
> Derived from Tegra124, modify as appropriate during T210
> board bringup. Cleaned up debug statements to conserve
> string space, too.
>
> Note that the 'empty' Kconfig for Tegra210 will cause
> an innocuous build warning, but it'll go away when a
> real T210 board is instantiated.
> diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
> index cdd5438..2ef8ae2 100644
> --- a/arch/arm/mach-tegra/clock.c
> +++ b/arch/arm/mach-tegra/clock.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
> + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -629,6 +629,7 @@ static void set_avp_clock_source(u32 src)
> /*
> * This function is useful on Tegra30, and any later SoCs that have compatible
> * PLLP configuration registers.
> + * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
I think we're only meant to update the copyright date for non-trivial
changes.
> diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
> @@ -39,6 +40,8 @@ int get_num_cpus(void)
> break;
> case CHIPID_TEGRA30:
> case CHIPID_TEGRA114:
> + case CHIPID_TEGRA124:
> + case CHIPID_TEGRA210:
It would be nice to break out the T124 change as a separate patch, since
it affects something other than T210.
> diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h
> -#define CORESIGHT_UNLOCK 0xC5ACCE55;
> +#define CORESIGHT_UNLOCK 0xC5ACCE55
Do we use that anywhere? If not, perhaps just delete it, probably as a
separate patch.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board
2015-06-03 20:35 ` [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board Tom Warren
@ 2015-06-15 17:23 ` Stephen Warren
2015-06-15 17:57 ` Tom Warren
0 siblings, 1 reply; 21+ messages in thread
From: Stephen Warren @ 2015-06-15 17:23 UTC (permalink / raw)
To: u-boot
On 06/03/2015 02:35 PM, Tom Warren wrote:
> Based on T124 Venice2. SDMMC1 is SD-card slot.
> Using tegra124 compat names for now to get everything
> working. May need minor work to match the real board.
This looks OK at a quick glance, although the "may need minor rework"
comment is worrying; can't we simply not add things into the DT until
they've been validated? Otherwise, we run the risk of the DT containing
incorrect misleading data.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board
2015-06-15 17:23 ` Stephen Warren
@ 2015-06-15 17:57 ` Tom Warren
0 siblings, 0 replies; 21+ messages in thread
From: Tom Warren @ 2015-06-15 17:57 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Monday, June 15, 2015 10:23 AM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
> Subject: Re: [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571
> board
>
> On 06/03/2015 02:35 PM, Tom Warren wrote:
> > Based on T124 Venice2. SDMMC1 is SD-card slot.
> > Using tegra124 compat names for now to get everything working. May
> > need minor work to match the real board.
>
> This looks OK at a quick glance, although the "may need minor rework"
> comment is worrying; can't we simply not add things into the DT until they've
> been validated? Otherwise, we run the risk of the DT containing incorrect
> misleading data.
That's a disclaimer I had in originally before working through all the bringup issues. Should be removed, the DT files match what I have in my 'fully-ported & working' branch.
--
nvpublic
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board
2015-06-03 20:35 ` [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board Tom Warren
@ 2015-06-15 17:58 ` Stephen Warren
2015-06-15 18:08 ` Tom Warren
2015-06-15 18:22 ` Stephen Warren
0 siblings, 2 replies; 21+ messages in thread
From: Stephen Warren @ 2015-06-15 17:58 UTC (permalink / raw)
To: u-boot
On 06/03/2015 02:35 PM, Tom Warren wrote:
> Based on Venice2, may change as P2571 board is fully
> brought up. Incorporates Stephen Warren's P2571 pinmux table.
> diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c
> +void tegra_i2c_ll_write_addr(uint addr, uint config)
> +{
> + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
> +
> + writel(addr, ®->cmd_addr0);
> + writel(config, ®->cnfg);
> +}
> +
> +void tegra_i2c_ll_write_data(uint data, uint config)
> +{
> + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
> +
> + writel(data, ®->cmd_data1);
> + writel(config, ®->cnfg);
> +}
> +
We really should put that into a lilbrary function, probably along with
the definition of things like I2C_SEND_2_BYTES (or make some more helper
functions to hide that too).
> +void pmic_enable_cpu_vdd(void)
> +{
> + debug("%s entry\n", __func__);
> +
> + //from TegraShell init script: Set GPIO5 to drive CPU_REG_EN
> + // then 1.0V on ???
I don't think we should mention internal tool names in upstream source.
> + debug("%s: Setting GPIO5 to push-pull out, logic high to enable CPU regulator\n", __func__);
> + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
> + tegra_i2c_ll_write_data(0x2040, I2C_SEND_2_BYTES); //data/reg
> + udelay(10*1000);
Need spaces around "*".
I'm not sure what "data/reg" means?
> +
> + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
> + tegra_i2c_ll_write_data(0x093B, I2C_SEND_2_BYTES); //B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull
> + udelay(10 * 1000);
Can we wrap that put that comment on a separate line, since it's rather
long. I don't think U-Boot likes // comments.
Does this patch pass checkpatch?
> diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
I think I generated this a long time ago. I'd like to get this into
tegra-pinmux-scripts, and make sure we're pulling in data from the
latest board spreadsheet, before we commit this. I'll look into that today.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board
2015-06-15 17:58 ` Stephen Warren
@ 2015-06-15 18:08 ` Tom Warren
2015-06-15 18:22 ` Stephen Warren
1 sibling, 0 replies; 21+ messages in thread
From: Tom Warren @ 2015-06-15 18:08 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Monday, June 15, 2015 10:59 AM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
> Subject: Re: [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571
> board
>
> On 06/03/2015 02:35 PM, Tom Warren wrote:
> > Based on Venice2, may change as P2571 board is fully brought up.
> > Incorporates Stephen Warren's P2571 pinmux table.
>
> > diff --git a/board/nvidia/p2571/max77620_init.c
> > b/board/nvidia/p2571/max77620_init.c
>
> > +void tegra_i2c_ll_write_addr(uint addr, uint config) {
> > + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
> > +
> > + writel(addr, ®->cmd_addr0);
> > + writel(config, ®->cnfg);
> > +}
> > +
> > +void tegra_i2c_ll_write_data(uint data, uint config) {
> > + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
> > +
> > + writel(data, ®->cmd_data1);
> > + writel(config, ®->cnfg);
> > +}
> > +
>
> We really should put that into a lilbrary function, probably along with the
> definition of things like I2C_SEND_2_BYTES (or make some more helper
> functions to hide that too).
Yep, we should make a PMIC driver for this part, but haven't yet. This is cut&paste from all the other Tegra boards.
I'll look into moving things around to make it cleaner, but that'll affect all boards and would be a separate effort.
>
> > +void pmic_enable_cpu_vdd(void)
> > +{
> > + debug("%s entry\n", __func__);
> > +
> > + //from TegraShell init script: Set GPIO5 to drive CPU_REG_EN
> > + // then 1.0V on ???
>
> I don't think we should mention internal tool names in upstream source.
Good catch, thanks. This has been addressed in a V2 patchset I did last week when I ran checkpatch.
>
> > + debug("%s: Setting GPIO5 to push-pull out, logic high to enable CPU
> regulator\n", __func__);
> > + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
> > + tegra_i2c_ll_write_data(0x2040, I2C_SEND_2_BYTES); //data/reg
> > + udelay(10*1000);
>
> Need spaces around "*".
>
> I'm not sure what "data/reg" means?
0x2040 is 0x20 data, 0x40 register. Just a note to myself during bringup. Removed.
>
> > +
> > + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
> > + tegra_i2c_ll_write_data(0x093B, I2C_SEND_2_BYTES); //B3=1=logic
> high,B2=dontcare,B1=0=output,B0=1=push-pull
> > + udelay(10 * 1000);
>
> Can we wrap that put that comment on a separate line, since it's rather long. I
> don't think U-Boot likes // comments.
>
> Does this patch pass checkpatch?
V2 does, all C99 // comments removed, 80-char+ lines fixed, etc. I'll post it when I address your other concerns.
>
> > diff --git a/board/nvidia/p2571/pinmux-config-p2571.h
> > b/board/nvidia/p2571/pinmux-config-p2571.h
>
> I think I generated this a long time ago. I'd like to get this into tegra-pinmux-
> scripts, and make sure we're pulling in data from the latest board spreadsheet,
> before we commit this. I'll look into that today.
Good idea. Thanks.
--
Nvpublic
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board
2015-06-15 17:58 ` Stephen Warren
2015-06-15 18:08 ` Tom Warren
@ 2015-06-15 18:22 ` Stephen Warren
2015-06-15 19:41 ` Tom Warren
1 sibling, 1 reply; 21+ messages in thread
From: Stephen Warren @ 2015-06-15 18:22 UTC (permalink / raw)
To: u-boot
On 06/15/2015 11:58 AM, Stephen Warren wrote:
> On 06/03/2015 02:35 PM, Tom Warren wrote:
>> Based on Venice2, may change as P2571 board is fully
>> brought up. Incorporates Stephen Warren's P2571 pinmux table.
...
>> diff --git a/board/nvidia/p2571/pinmux-config-p2571.h
>> b/board/nvidia/p2571/pinmux-config-p2571.h
>
> I think I generated this a long time ago. I'd like to get this into
> tegra-pinmux-scripts, and make sure we're pulling in data from the
> latest board spreadsheet, before we commit this. I'll look into that today.
I've validated that the pinmux data in this patch is up-to-date. There
are some whitespace differences in the definition of the PINCFG() macro,
so it might be nice to regenerate pinmux-config-p2571.h before any
future patch version to make sure it 100% matches what the scripts output.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board
2015-06-15 18:22 ` Stephen Warren
@ 2015-06-15 19:41 ` Tom Warren
0 siblings, 0 replies; 21+ messages in thread
From: Tom Warren @ 2015-06-15 19:41 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Monday, June 15, 2015 11:22 AM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
> Subject: Re: [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571
> board
>
> On 06/15/2015 11:58 AM, Stephen Warren wrote:
> > On 06/03/2015 02:35 PM, Tom Warren wrote:
> >> Based on Venice2, may change as P2571 board is fully brought up.
> >> Incorporates Stephen Warren's P2571 pinmux table.
> ...
> >> diff --git a/board/nvidia/p2571/pinmux-config-p2571.h
> >> b/board/nvidia/p2571/pinmux-config-p2571.h
> >
> > I think I generated this a long time ago. I'd like to get this into
> > tegra-pinmux-scripts, and make sure we're pulling in data from the
> > latest board spreadsheet, before we commit this. I'll look into that today.
>
> I've validated that the pinmux data in this patch is up-to-date. There are some
> whitespace differences in the definition of the PINCFG() macro, so it might be
> nice to regenerate pinmux-config-p2571.h before any future patch version to
> make sure it 100% matches what the scripts output.
I don't know how to generate the pinmux table header from the SS, so if you could do that and pass it to me for the next patchset, I'd appreciate it.
Tom
--
nvpublic
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
2015-06-15 17:11 ` Stephen Warren
@ 2015-06-15 20:04 ` Tom Warren
2015-06-16 20:26 ` Stephen Warren
2015-06-15 22:18 ` Tom Warren
1 sibling, 1 reply; 21+ messages in thread
From: Tom Warren @ 2015-06-15 20:04 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Monday, June 15, 2015 10:11 AM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
> Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files
> for T210
>
> On 06/03/2015 02:35 PM, Tom Warren wrote:
> > All based off of Tegra124. As a Tegra210 board is brought up, these
> > may change a bit to match the HW more closely, but probably 90% of
> > this is identical to T124.
>
> Rather than duplicating lots of headers and code, can we share the content
> with other chips?
Sure, but I wasn't looking at this patchset as a reworking of all Tegra common headers, but an inclusion of T210 support. We can then move to common/shared content after this is in, or someone (you?) can do it now before I add T210 support, but that'll delay it.
>
> > diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h
> > b/arch/arm/include/asm/arch-tegra210/funcmux.h
>
> We should be able to drop funcmux support completely now that we're
> programming entire board pinmux tables.
I'll look into it, but I believe funcmux is only used to get early UART muxes set, which is done before the pinmux table is parsed/written.
>
> > diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h
> > b/arch/arm/include/asm/arch-tegra210/gpio.h
>
> > +enum gpio_pin {
> > + GPIO_PA0 = 0, /* pin 0 */
> > + GPIO_PA1,
>
> Given the move to DT, are any of these GPIO_xxx values actually used? I
> wonder how many other types/defines in the other files are actually used,
> rather than simply left over from times gone by.
Again, that's more of a general Tegra cleanup phase then this patchset is intended for. I'll take a quick look, but I don't want to get delayed by doing a bunch of Tegra cleanup stuff right now.
>
> > diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h
> > b/arch/arm/include/asm/arch-tegra210/hardware.h
>
> Can we drop this file? I don't see a hardware.h in any of the other arch-tegra*/
> directories.
Sure. It's never been used AFAICT.
>
> > diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h
> > b/arch/arm/include/asm/arch-tegra210/tegra.h
>
> > +#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */
> > +
> > +#undef NVBOOTINFOTABLE_BCTSIZE
> > +#undef NVBOOTINFOTABLE_BCTPTR
> > +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in
> IRAM */
> > +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in
> IRAM */
>
> Have you validated those? I'm pretty sure the BCT and perhaps BIT layout
> changed in T210, and those values match T124.
Good point. They have changed, since the BCT structure has changed. I'll update them w/real T210 offsets.
>
> Have all the clock tables and IDs been updated to match T210? If not, I think we
> should do that before checking in the code, or it'll be misleading.
I believe so - I'm using the clock tables from my 'fully working' branch, so they should be accurate/jibe with the TRM, but I'll double-check.
--
nvpublic
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
2015-06-15 17:11 ` Stephen Warren
2015-06-15 20:04 ` Tom Warren
@ 2015-06-15 22:18 ` Tom Warren
2015-06-16 20:29 ` Stephen Warren
1 sibling, 1 reply; 21+ messages in thread
From: Tom Warren @ 2015-06-15 22:18 UTC (permalink / raw)
To: u-boot
Update WRT gpio.h and hardware.h, below.
> -----Original Message-----
> From: Tom Warren
> Sent: Monday, June 15, 2015 1:05 PM
> To: 'Stephen Warren'; Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren
> Subject: RE: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files
> for T210
>
>
>
> > -----Original Message-----
> > From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> > Sent: Monday, June 15, 2015 10:11 AM
> > To: Tom Warren
> > Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
> > Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include
> > files for T210
> >
> > On 06/03/2015 02:35 PM, Tom Warren wrote:
> > > All based off of Tegra124. As a Tegra210 board is brought up, these
> > > may change a bit to match the HW more closely, but probably 90% of
> > > this is identical to T124.
> >
> > Rather than duplicating lots of headers and code, can we share the
> > content with other chips?
> Sure, but I wasn't looking at this patchset as a reworking of all Tegra common
> headers, but an inclusion of T210 support. We can then move to
> common/shared content after this is in, or someone (you?) can do it now
> before I add T210 support, but that'll delay it.
>
> >
> > > diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h
> > > b/arch/arm/include/asm/arch-tegra210/funcmux.h
> >
> > We should be able to drop funcmux support completely now that we're
> > programming entire board pinmux tables.
> I'll look into it, but I believe funcmux is only used to get early UART muxes set,
> which is done before the pinmux table is parsed/written.
>
> >
> > > diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h
> > > b/arch/arm/include/asm/arch-tegra210/gpio.h
> >
> > > +enum gpio_pin {
> > > + GPIO_PA0 = 0, /* pin 0 */
> > > + GPIO_PA1,
> >
> > Given the move to DT, are any of these GPIO_xxx values actually used?
> > I wonder how many other types/defines in the other files are actually
> > used, rather than simply left over from times gone by.
> Again, that's more of a general Tegra cleanup phase then this patchset is
> intended for. I'll take a quick look, but I don't want to get delayed by doing a
> bunch of Tegra cleanup stuff right now.
They're used in the pinmux table (pinmux-config-venice2.h, for example) and some board files (nyan-big.c, cardhu.c, seaboard.c). Can't remove 'em.
>
> >
> > > diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h
> > > b/arch/arm/include/asm/arch-tegra210/hardware.h
> >
> > Can we drop this file? I don't see a hardware.h in any of the other
> > arch-tegra*/ directories.
> Sure. It's never been used AFAICT.
Can't drop hardware.h. It's expected to be in every build, included from arch/arm/include/asm/hardware.h, created by Wolfgang way back in 2003.
>
> >
> > > diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h
> > > b/arch/arm/include/asm/arch-tegra210/tegra.h
> >
> > > +#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */
> > > +
> > > +#undef NVBOOTINFOTABLE_BCTSIZE
> > > +#undef NVBOOTINFOTABLE_BCTPTR
> > > +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in
> > IRAM */
> > > +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in
> > IRAM */
> >
> > Have you validated those? I'm pretty sure the BCT and perhaps BIT
> > layout changed in T210, and those values match T124.
> Good point. They have changed, since the BCT structure has changed. I'll
> update them w/real T210 offsets.
>
> >
> > Have all the clock tables and IDs been updated to match T210? If not,
> > I think we should do that before checking in the code, or it'll be misleading.
> I believe so - I'm using the clock tables from my 'fully working' branch, so they
> should be accurate/jibe with the TRM, but I'll double-check.
>
> --
> nvpublic
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
2015-06-15 20:04 ` Tom Warren
@ 2015-06-16 20:26 ` Stephen Warren
0 siblings, 0 replies; 21+ messages in thread
From: Stephen Warren @ 2015-06-16 20:26 UTC (permalink / raw)
To: u-boot
On 06/15/2015 02:04 PM, Tom Warren wrote:
>
>
>> -----Original Message-----
>> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
>> Sent: Monday, June 15, 2015 10:11 AM
>> To: Tom Warren
>> Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
>> Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files
>> for T210
>>
>> On 06/03/2015 02:35 PM, Tom Warren wrote:
>>> All based off of Tegra124. As a Tegra210 board is brought up, these
>>> may change a bit to match the HW more closely, but probably 90% of
>>> this is identical to T124.
>>
>> Rather than duplicating lots of headers and code, can we share the content
>> with other chips?
>
> Sure, but I wasn't looking at this patchset as a reworking of all Tegra common headers, but an inclusion of T210 support. We can then move to common/shared content after this is in, or someone (you?) can do it now before I add T210 support, but that'll delay it.
The problem here is that the same excuse against cleanup is made every
time a new SoC comes along, and the cleanup never happens.
>>> diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h
>>> b/arch/arm/include/asm/arch-tegra210/funcmux.h
>>
>> We should be able to drop funcmux support completely now that we're
>> programming entire board pinmux tables.
>
> I'll look into it, but I believe funcmux is only used to get early UART muxes set, which is done before the pinmux table is parsed/written.
There's no guarantee funcmux will work in general for the UARTs. The
best solution would be to apply the pinmux table before doing anything.
That way, we wouldn't need anything custom to try and get the UART working.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
2015-06-15 22:18 ` Tom Warren
@ 2015-06-16 20:29 ` Stephen Warren
2015-06-16 21:30 ` Tom Warren
0 siblings, 1 reply; 21+ messages in thread
From: Stephen Warren @ 2015-06-16 20:29 UTC (permalink / raw)
To: u-boot
On 06/15/2015 04:18 PM, Tom Warren wrote:
> Update WRT gpio.h and hardware.h, below.
>
>Tom Warren wrote at Monday, June 15, 2015 1:05 PM:
>> Stephen Warren wrote at Monday, June 15, 2015 10:11 AM:
>>> On 06/03/2015 02:35 PM, Tom Warren wrote:
>>>> All based off of Tegra124. As a Tegra210 board is brought up, these
>>>> may change a bit to match the HW more closely, but probably 90% of
>>>> this is identical to T124.
...
>>>> diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h
>>>> b/arch/arm/include/asm/arch-tegra210/hardware.h
>>>
>>> Can we drop this file? I don't see a hardware.h in any of the other
>>> arch-tegra*/ directories.
>> Sure. It's never been used AFAICT.
> Can't drop hardware.h. It's expected to be in every build, included from arch/arm/include/asm/hardware.h, created by Wolfgang way back in 2003.
But there is no hardware.h in any of arch/arm/include/asm/arch-tegra*.h
in u-boot.git's master branch as of today.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
2015-06-16 20:29 ` Stephen Warren
@ 2015-06-16 21:30 ` Tom Warren
0 siblings, 0 replies; 21+ messages in thread
From: Tom Warren @ 2015-06-16 21:30 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Tuesday, June 16, 2015 1:29 PM
> To: Tom Warren; Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren
> Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files
> for T210
>
> On 06/15/2015 04:18 PM, Tom Warren wrote:
> > Update WRT gpio.h and hardware.h, below.
> >
> >Tom Warren wrote at Monday, June 15, 2015 1:05 PM:
> >> Stephen Warren wrote at Monday, June 15, 2015 10:11 AM:
> >>> On 06/03/2015 02:35 PM, Tom Warren wrote:
> >>>> All based off of Tegra124. As a Tegra210 board is brought up, these
> >>>> may change a bit to match the HW more closely, but probably 90% of
> >>>> this is identical to T124.
> ...
> >>>> diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h
> >>>> b/arch/arm/include/asm/arch-tegra210/hardware.h
> >>>
> >>> Can we drop this file? I don't see a hardware.h in any of the other
> >>> arch-tegra*/ directories.
> >> Sure. It's never been used AFAICT.
> > Can't drop hardware.h. It's expected to be in every build, included from
> arch/arm/include/asm/hardware.h, created by Wolfgang way back in 2003.
>
> But there is no hardware.h in any of arch/arm/include/asm/arch-tegra*.h
> in u-boot.git's master branch as of today.
Sorry, I must have been looking at my u-boot-tegra/next branch, which hasn't been sync'd w/master (u-boot or u-boot-tegra) in a while. I'll remove hardware.h in the next patchset.
Thanks
--
nvpublic
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 0/4] Tegra210 support for P2571
2015-06-03 20:35 [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Tom Warren
` (3 preceding siblings ...)
2015-06-03 20:35 ` [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board Tom Warren
@ 2015-06-17 20:07 ` Stephen Warren
2015-06-17 22:44 ` Tom Warren
4 siblings, 1 reply; 21+ messages in thread
From: Stephen Warren @ 2015-06-17 20:07 UTC (permalink / raw)
To: u-boot
On 06/03/2015 02:35 PM, Tom Warren wrote:
> Adds support for Tegra210 SoC and P2571 NVIDIA board.
> Largely based on T124/Venice2. This is a baseline
> patchset - more will follow to make things more T210-
> specific as P2571 peripherals/devices are brought up.
Does this add support for a 32-bit or a 64-bit U-Boot? Since T210 is a
64-bit CPU I would have expected a 64-bit U-Boot, yet:
a)
arch/arm/Kconfig contains:
config TEGRA
...
select CPU_V7
and this patch doesn't modify that.
b)
I can built an executable with these patches applied (after manually
fixing up some merge problems) with an ARMv7 compiler, but not with an
ARMv8 compiler.
I think that means this is a 32-bit port. We need a 64-bit port.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 0/4] Tegra210 support for P2571
2015-06-17 20:07 ` [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Stephen Warren
@ 2015-06-17 22:44 ` Tom Warren
2015-06-19 22:25 ` Simon Glass
0 siblings, 1 reply; 21+ messages in thread
From: Tom Warren @ 2015-06-17 22:44 UTC (permalink / raw)
To: u-boot
Yes, it's a 32-bit T210 U-Boot. T210 supports both AARCH32 and AARCH64.
A 64-bit build will follow, but I haven't figured out how to meld the 32-bit AVP SPL portion/build with the 64-bit CPU portion/build in one clean build command, so I'm building them separately and then fusing them together in a separate script. If anyone has ideas on how to generate a hybrid 32-bit (AVP)/64-bit (A57) U-Boot binary in one fell swoop, I'm all ears. :)
Tom
> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Wednesday, June 17, 2015 1:07 PM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
> Subject: Re: [U-Boot] [PATCH 0/4] Tegra210 support for P2571
>
> On 06/03/2015 02:35 PM, Tom Warren wrote:
> > Adds support for Tegra210 SoC and P2571 NVIDIA board.
> > Largely based on T124/Venice2. This is a baseline patchset - more will
> > follow to make things more T210- specific as P2571 peripherals/devices
> > are brought up.
>
> Does this add support for a 32-bit or a 64-bit U-Boot? Since T210 is a 64-bit CPU I
> would have expected a 64-bit U-Boot, yet:
>
> a)
>
> arch/arm/Kconfig contains:
>
> config TEGRA
> ...
> select CPU_V7
>
> and this patch doesn't modify that.
>
> b)
>
> I can built an executable with these patches applied (after manually fixing up
> some merge problems) with an ARMv7 compiler, but not with an
> ARMv8 compiler.
>
> I think that means this is a 32-bit port. We need a 64-bit port.
-----------------------------------------------------------------------------------
This email message is for the sole use of the intended recipient(s) and may contain
confidential information. Any unauthorized review, use, disclosure or distribution
is prohibited. If you are not the intended recipient, please contact the sender by
reply email and destroy all copies of the original message.
-----------------------------------------------------------------------------------
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 0/4] Tegra210 support for P2571
2015-06-17 22:44 ` Tom Warren
@ 2015-06-19 22:25 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2015-06-19 22:25 UTC (permalink / raw)
To: u-boot
Hi Tom,
I've got one of these shield things - it is a seriously cool piece of
hardware. I've have to read a bit about what is it for.
So, any idea where to find a UART and recovery button?
Regards,
Simon
On 17 June 2015 at 16:44, Tom Warren <TWarren@nvidia.com> wrote:
> Yes, it's a 32-bit T210 U-Boot. T210 supports both AARCH32 and AARCH64.
>
> A 64-bit build will follow, but I haven't figured out how to meld the 32-bit AVP SPL portion/build with the 64-bit CPU portion/build in one clean build command, so I'm building them separately and then fusing them together in a separate script. If anyone has ideas on how to generate a hybrid 32-bit (AVP)/64-bit (A57) U-Boot binary in one fell swoop, I'm all ears. :)
>
> Tom
>
>> -----Original Message-----
>> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
>> Sent: Wednesday, June 17, 2015 1:07 PM
>> To: Tom Warren
>> Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
>> Subject: Re: [U-Boot] [PATCH 0/4] Tegra210 support for P2571
>>
>> On 06/03/2015 02:35 PM, Tom Warren wrote:
>> > Adds support for Tegra210 SoC and P2571 NVIDIA board.
>> > Largely based on T124/Venice2. This is a baseline patchset - more will
>> > follow to make things more T210- specific as P2571 peripherals/devices
>> > are brought up.
>>
>> Does this add support for a 32-bit or a 64-bit U-Boot? Since T210 is a 64-bit CPU I
>> would have expected a 64-bit U-Boot, yet:
>>
>> a)
>>
>> arch/arm/Kconfig contains:
>>
>> config TEGRA
>> ...
>> select CPU_V7
>>
>> and this patch doesn't modify that.
>>
>> b)
>>
>> I can built an executable with these patches applied (after manually fixing up
>> some merge problems) with an ARMv7 compiler, but not with an
>> ARMv8 compiler.
>>
>> I think that means this is a 32-bit port. We need a 64-bit port.
> -----------------------------------------------------------------------------------
> This email message is for the sole use of the intended recipient(s) and may contain
> confidential information. Any unauthorized review, use, disclosure or distribution
> is prohibited. If you are not the intended recipient, please contact the sender by
> reply email and destroy all copies of the original message.
> -----------------------------------------------------------------------------------
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2015-06-19 22:25 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-03 20:35 [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Tom Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210 Tom Warren
2015-06-15 17:11 ` Stephen Warren
2015-06-15 20:04 ` Tom Warren
2015-06-16 20:26 ` Stephen Warren
2015-06-15 22:18 ` Tom Warren
2015-06-16 20:29 ` Stephen Warren
2015-06-16 21:30 ` Tom Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 2/4] ARM: Tegra210: Add support to common Tegra source/config files Tom Warren
2015-06-15 17:18 ` Stephen Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board Tom Warren
2015-06-15 17:23 ` Stephen Warren
2015-06-15 17:57 ` Tom Warren
2015-06-03 20:35 ` [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board Tom Warren
2015-06-15 17:58 ` Stephen Warren
2015-06-15 18:08 ` Tom Warren
2015-06-15 18:22 ` Stephen Warren
2015-06-15 19:41 ` Tom Warren
2015-06-17 20:07 ` [U-Boot] [PATCH 0/4] Tegra210 support for P2571 Stephen Warren
2015-06-17 22:44 ` Tom Warren
2015-06-19 22:25 ` Simon Glass
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.