[U-Boot] [PATCH 0/6] rk3328 pinctrl drvier and sdmmc power fix

[U-Boot] [PATCH 0/6] rk3328 pinctrl drvier and sdmmc power fix

[Kever Yang]

Move pinctrl registers definition in GRF header file,
clean code with prefix like other Rockchip SoCs.
Use Fixed regulator(gpio) for sdmmc-pwren instead of
signal controled by mmc controller.


Kever Yang (6):
  rockchip: pinctrl: move rk3328 grf reg definition in header file
  rockchip: pinctrl: rk3328: do not set io routing
  rockchip: evb-rk3328: set uart2 and sdmmc io routing
  rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwren
  rockchip: evb-rk3328: enable boot on regulator
  rockchip: dts: rk3328-evb: add sdmmc-pwren regulator

 arch/arm/dts/rk3328-evb.dts                     |   8 +
 arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 114 ++++++++++++
 board/rockchip/evb_rk3328/evb-rk3328.c          |  20 ++-
 drivers/pinctrl/rockchip/pinctrl_rk3328.c       | 226 +++++++-----------------
 4 files changed, 205 insertions(+), 163 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH 1/6] rockchip: pinctrl: move rk3328 grf reg definition in header file

[Kever Yang]

Move GRF register bit definition into GRF header file, remove
'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 114 +++++++++++++
 drivers/pinctrl/rockchip/pinctrl_rk3328.c       | 205 ++++++------------------
 2 files changed, 164 insertions(+), 155 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index 2776cef..40a4de0 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,4 +131,118 @@ struct rk3328_sgrf_regs {
 };
 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
 
+enum {
+	/* GPIO0A_IOMUX */
+	GPIO0A5_SEL_SHIFT	= 10,
+	GPIO0A5_SEL_MASK	= 3 << GPIO0A5_SEL_SHIFT,
+	GPIO0A5_I2C3_SCL	= 2,
+
+	GPIO0A6_SEL_SHIFT	= 12,
+	GPIO0A6_SEL_MASK	= 3 << GPIO0A6_SEL_SHIFT,
+	GPIO0A6_I2C3_SDA	= 2,
+
+	GPIO0A7_SEL_SHIFT	= 14,
+	GPIO0A7_SEL_MASK	= 3 << GPIO0A7_SEL_SHIFT,
+	GPIO0A7_EMMC_DATA0	= 2,
+
+	/* GPIO0D_IOMUX*/
+	GPIO0D6_SEL_SHIFT	= 12,
+	GPIO0D6_SEL_MASK	= 3 << GPIO0D6_SEL_SHIFT,
+	GPIO0D6_GPIO		= 0,
+	GPIO0D6_SDMMC0_PWRENM1	= 3,
+
+	/* GPIO1A_IOMUX */
+	GPIO1A0_SEL_SHIFT	= 0,
+	GPIO1A0_SEL_MASK	= 0x3fff << GPIO1A0_SEL_SHIFT,
+	GPIO1A0_CARD_DATA_CLK_CMD_DETN	= 0x1555,
+
+	/* GPIO2A_IOMUX */
+	GPIO2A0_SEL_SHIFT	= 0,
+	GPIO2A0_SEL_MASK	= 3 << GPIO2A0_SEL_SHIFT,
+	GPIO2A0_UART2_TX_M1	= 1,
+
+	GPIO2A1_SEL_SHIFT	= 2,
+	GPIO2A1_SEL_MASK	= 3 << GPIO2A1_SEL_SHIFT,
+	GPIO2A1_UART2_RX_M1	= 1,
+
+	GPIO2A2_SEL_SHIFT	= 4,
+	GPIO2A2_SEL_MASK	= 3 << GPIO2A2_SEL_SHIFT,
+	GPIO2A2_PWM_IR		= 1,
+
+	GPIO2A4_SEL_SHIFT	= 8,
+	GPIO2A4_SEL_MASK	= 3 << GPIO2A4_SEL_SHIFT,
+	GPIO2A4_PWM_0		= 1,
+	GPIO2A4_I2C1_SDA,
+
+	GPIO2A5_SEL_SHIFT	= 10,
+	GPIO2A5_SEL_MASK	= 3 << GPIO2A5_SEL_SHIFT,
+	GPIO2A5_PWM_1		= 1,
+	GPIO2A5_I2C1_SCL,
+
+	GPIO2A6_SEL_SHIFT	= 12,
+	GPIO2A6_SEL_MASK	= 3 << GPIO2A6_SEL_SHIFT,
+	GPIO2A6_PWM_2		= 1,
+
+	GPIO2A7_SEL_SHIFT	= 14,
+	GPIO2A7_SEL_MASK	= 3 << GPIO2A7_SEL_SHIFT,
+	GPIO2A7_GPIO		= 0,
+	GPIO2A7_SDMMC0_PWRENM0,
+
+	/* GPIO2BL_IOMUX */
+	GPIO2BL0_SEL_SHIFT	= 0,
+	GPIO2BL0_SEL_MASK	= 0x3f << GPIO2BL0_SEL_SHIFT,
+	GPIO2BL0_SPI_CLK_TX_RX_M0	= 0x15,
+
+	GPIO2BL3_SEL_SHIFT	= 6,
+	GPIO2BL3_SEL_MASK	= 3 << GPIO2BL3_SEL_SHIFT,
+	GPIO2BL3_SPI_CSN0_M0	= 1,
+
+	GPIO2BL4_SEL_SHIFT	= 8,
+	GPIO2BL4_SEL_MASK	= 3 << GPIO2BL4_SEL_SHIFT,
+	GPIO2BL4_SPI_CSN1_M0	= 1,
+
+	GPIO2BL5_SEL_SHIFT	= 10,
+	GPIO2BL5_SEL_MASK	= 3 << GPIO2BL5_SEL_SHIFT,
+	GPIO2BL5_I2C2_SDA	= 1,
+
+	GPIO2BL6_SEL_SHIFT	= 12,
+	GPIO2BL6_SEL_MASK	= 3 << GPIO2BL6_SEL_SHIFT,
+	GPIO2BL6_I2C2_SCL	= 1,
+
+	/* GPIO2D_IOMUX */
+	GPIO2D0_SEL_SHIFT	= 0,
+	GPIO2D0_SEL_MASK	= 3 << GPIO2D0_SEL_SHIFT,
+	GPIO2D0_I2C0_SCL	= 1,
+
+	GPIO2D1_SEL_SHIFT	= 2,
+	GPIO2D1_SEL_MASK	= 3 << GPIO2D1_SEL_SHIFT,
+	GPIO2D1_I2C0_SDA	= 1,
+
+	GPIO2D4_SEL_SHIFT	= 8,
+	GPIO2D4_SEL_MASK	= 0xff << GPIO2D4_SEL_SHIFT,
+	GPIO2D4_EMMC_DATA1234	= 0xaa,
+
+	/* GPIO3C_IOMUX */
+	GPIO3C0_SEL_SHIFT	= 0,
+	GPIO3C0_SEL_MASK	= 0x3fff << GPIO3C0_SEL_SHIFT,
+	GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD	= 0x2aaa,
+
+	/* COM_IOMUX */
+	UART2_IOMUX_SEL_SHIFT	= 0,
+	UART2_IOMUX_SEL_MASK	= 3 << UART2_IOMUX_SEL_SHIFT,
+	UART2_IOMUX_SEL_M0		= 0,
+	UART2_IOMUX_SEL_M1,
+
+	SPI_IOMUX_SEL_SHIFT = 4,
+	SPI_IOMUX_SEL_MASK	= 3 << SPI_IOMUX_SEL_SHIFT,
+	SPI_IOMUX_SEL_M0	= 0,
+	SPI_IOMUX_SEL_M1,
+	SPI_IOMUX_SEL_M2,
+
+	CARD_IOMUX_SEL_SHIFT	= 7,
+	CARD_IOMUX_SEL_MASK		= 1 << CARD_IOMUX_SEL_SHIFT,
+	CARD_IOMUX_SEL_M0		= 0,
+	CARD_IOMUX_SEL_M1,
+};
+
 #endif	/* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 5ca6782..63ce7a0 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -21,135 +21,28 @@ struct rk3328_pinctrl_priv {
 	struct rk3328_grf_regs *grf;
 };
 
-enum {
-	/* GRF_GPIO0A_IOMUX */
-	GRF_GPIO0A5_SEL_SHIFT	= 10,
-	GRF_GPIO0A5_SEL_MASK	= 3 << GRF_GPIO0A5_SEL_SHIFT,
-	GRF_I2C3_SCL		= 2,
-
-	GRF_GPIO0A6_SEL_SHIFT	= 12,
-	GRF_GPIO0A6_SEL_MASK	= 3 << GRF_GPIO0A6_SEL_SHIFT,
-	GRF_I2C3_SDA		= 2,
-
-	GRF_GPIO0A7_SEL_SHIFT	= 14,
-	GRF_GPIO0A7_SEL_MASK	= 3 << GRF_GPIO0A7_SEL_SHIFT,
-	GRF_EMMC_DATA0		= 2,
-
-	/* GRF_GPIO1A_IOMUX */
-	GRF_GPIO1A0_SEL_SHIFT	= 0,
-	GRF_GPIO1A0_SEL_MASK	= 0x3fff << GRF_GPIO1A0_SEL_SHIFT,
-	GRF_CARD_DATA_CLK_CMD_DETN	= 0x1555,
-
-	/* GRF_GPIO2A_IOMUX */
-	GRF_GPIO2A0_SEL_SHIFT	= 0,
-	GRF_GPIO2A0_SEL_MASK	= 3 << GRF_GPIO2A0_SEL_SHIFT,
-	GRF_UART2_TX_M1		= 1,
-
-	GRF_GPIO2A1_SEL_SHIFT	= 2,
-	GRF_GPIO2A1_SEL_MASK	= 3 << GRF_GPIO2A1_SEL_SHIFT,
-	GRF_UART2_RX_M1		= 1,
-
-	GRF_GPIO2A2_SEL_SHIFT	= 4,
-	GRF_GPIO2A2_SEL_MASK	= 3 << GRF_GPIO2A2_SEL_SHIFT,
-	GRF_PWM_IR		= 1,
-
-	GRF_GPIO2A4_SEL_SHIFT	= 8,
-	GRF_GPIO2A4_SEL_MASK	= 3 << GRF_GPIO2A4_SEL_SHIFT,
-	GRF_PWM_0		= 1,
-	GRF_I2C1_SDA,
-
-	GRF_GPIO2A5_SEL_SHIFT	= 10,
-	GRF_GPIO2A5_SEL_MASK	= 3 << GRF_GPIO2A5_SEL_SHIFT,
-	GRF_PWM_1		= 1,
-	GRF_I2C1_SCL,
-
-	GRF_GPIO2A6_SEL_SHIFT	= 12,
-	GRF_GPIO2A6_SEL_MASK	= 3 << GRF_GPIO2A6_SEL_SHIFT,
-	GRF_PWM_2		= 1,
-
-	GRF_GPIO2A7_SEL_SHIFT	= 14,
-	GRF_GPIO2A7_SEL_MASK	= 3 << GRF_GPIO2A7_SEL_SHIFT,
-	GRF_CARD_PWR_EN_M0	= 1,
-
-	/* GRF_GPIO2BL_IOMUX */
-	GRF_GPIO2BL0_SEL_SHIFT	= 0,
-	GRF_GPIO2BL0_SEL_MASK	= 0x3f << GRF_GPIO2BL0_SEL_SHIFT,
-	GRF_SPI_CLK_TX_RX_M0	= 0x15,
-
-	GRF_GPIO2BL3_SEL_SHIFT	= 6,
-	GRF_GPIO2BL3_SEL_MASK	= 3 << GRF_GPIO2BL3_SEL_SHIFT,
-	GRF_SPI_CSN0_M0		= 1,
-
-	GRF_GPIO2BL4_SEL_SHIFT	= 8,
-	GRF_GPIO2BL4_SEL_MASK	= 3 << GRF_GPIO2BL4_SEL_SHIFT,
-	GRF_SPI_CSN1_M0		= 1,
-
-	GRF_GPIO2BL5_SEL_SHIFT	= 10,
-	GRF_GPIO2BL5_SEL_MASK	= 3 << GRF_GPIO2BL5_SEL_SHIFT,
-	GRF_I2C2_SDA		= 1,
-
-	GRF_GPIO2BL6_SEL_SHIFT	= 12,
-	GRF_GPIO2BL6_SEL_MASK	= 3 << GRF_GPIO2BL6_SEL_SHIFT,
-	GRF_I2C2_SCL		= 1,
-
-	/* GRF_GPIO2D_IOMUX */
-	GRF_GPIO2D0_SEL_SHIFT	= 0,
-	GRF_GPIO2D0_SEL_MASK	= 3 << GRF_GPIO2D0_SEL_SHIFT,
-	GRF_I2C0_SCL		= 1,
-
-	GRF_GPIO2D1_SEL_SHIFT	= 2,
-	GRF_GPIO2D1_SEL_MASK	= 3 << GRF_GPIO2D1_SEL_SHIFT,
-	GRF_I2C0_SDA		= 1,
-
-	GRF_GPIO2D4_SEL_SHIFT	= 8,
-	GRF_GPIO2D4_SEL_MASK	= 0xff << GRF_GPIO2D4_SEL_SHIFT,
-	GRF_EMMC_DATA123	= 0xaa,
-
-	/* GRF_GPIO3C_IOMUX */
-	GRF_GPIO3C0_SEL_SHIFT	= 0,
-	GRF_GPIO3C0_SEL_MASK	= 0x3fff << GRF_GPIO3C0_SEL_SHIFT,
-	GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD	= 0x2aaa,
-
-	/* GRF_COM_IOMUX */
-	GRF_UART2_IOMUX_SEL_SHIFT	= 0,
-	GRF_UART2_IOMUX_SEL_MASK	= 3 << GRF_UART2_IOMUX_SEL_SHIFT,
-	GRF_UART2_IOMUX_SEL_M0		= 0,
-	GRF_UART2_IOMUX_SEL_M1,
-
-	GRF_SPI_IOMUX_SEL_SHIFT = 4,
-	GRF_SPI_IOMUX_SEL_MASK	= 3 << GRF_SPI_IOMUX_SEL_SHIFT,
-	GRF_SPI_IOMUX_SEL_M0	= 0,
-	GRF_SPI_IOMUX_SEL_M1,
-	GRF_SPI_IOMUX_SEL_M2,
-
-	GRF_CARD_IOMUX_SEL_SHIFT	= 7,
-	GRF_CARD_IOMUX_SEL_MASK		= 1 << GRF_CARD_IOMUX_SEL_SHIFT,
-	GRF_CARD_IOMUX_SEL_M0		= 0,
-	GRF_CARD_IOMUX_SEL_M1,
-};
-
 static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
 {
 	switch (pwm_id) {
 	case PERIPH_ID_PWM0:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A4_SEL_MASK,
-			     GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT);
+			     GPIO2A4_SEL_MASK,
+			     GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT);
 		break;
 	case PERIPH_ID_PWM1:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A5_SEL_MASK,
-			     GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT);
+			     GPIO2A5_SEL_MASK,
+			     GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT);
 		break;
 	case PERIPH_ID_PWM2:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A6_SEL_MASK,
-			     GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT);
+			     GPIO2A6_SEL_MASK,
+			     GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT);
 		break;
 	case PERIPH_ID_PWM3:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A2_SEL_MASK,
-			     GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT);
+			     GPIO2A2_SEL_MASK,
+			     GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT);
 		break;
 	default:
 		debug("pwm id = %d iomux error!\n", pwm_id);
@@ -162,27 +55,27 @@ static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
 	switch (i2c_id) {
 	case PERIPH_ID_I2C0:
 		rk_clrsetreg(&grf->gpio2d_iomux,
-			     GRF_GPIO2D0_SEL_MASK | GRF_GPIO2D1_SEL_MASK,
-			     GRF_I2C0_SCL << GRF_GPIO2D0_SEL_SHIFT
-			     | GRF_I2C0_SDA << GRF_GPIO2D1_SEL_SHIFT);
+			     GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK,
+			     GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT |
+			     GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT);
 		break;
 	case PERIPH_ID_I2C1:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A4_SEL_MASK | GRF_GPIO2A5_SEL_MASK,
-			     GRF_I2C1_SCL << GRF_GPIO2A5_SEL_SHIFT
-			     | GRF_I2C1_SDA << GRF_GPIO2A4_SEL_SHIFT);
+			     GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK,
+			     GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT |
+			     GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT);
 		break;
 	case PERIPH_ID_I2C2:
 		rk_clrsetreg(&grf->gpio2bl_iomux,
-			     GRF_GPIO2BL5_SEL_MASK | GRF_GPIO2BL6_SEL_MASK,
-			     GRF_I2C2_SCL << GRF_GPIO2BL6_SEL_SHIFT
-			     | GRF_I2C2_SDA << GRF_GPIO2BL6_SEL_SHIFT);
+			     GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK,
+			     GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT |
+			     GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT);
 		break;
 	case PERIPH_ID_I2C3:
 		rk_clrsetreg(&grf->gpio0a_iomux,
-			     GRF_GPIO0A5_SEL_MASK | GRF_GPIO0A6_SEL_MASK,
-			     GRF_I2C3_SCL << GRF_GPIO0A5_SEL_SHIFT
-			     | GRF_I2C3_SDA << GRF_GPIO0A6_SEL_SHIFT);
+			     GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK,
+			     GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT |
+			     GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT);
 		break;
 	default:
 		debug("i2c id = %d iomux error!\n", i2c_id);
@@ -205,28 +98,30 @@ static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
 				     enum periph_id spi_id, int cs)
 {
 	rk_clrsetreg(&grf->com_iomux,
-		     GRF_SPI_IOMUX_SEL_MASK,
-		     GRF_SPI_IOMUX_SEL_M0 << GRF_SPI_IOMUX_SEL_SHIFT);
+		     SPI_IOMUX_SEL_MASK,
+		     SPI_IOMUX_SEL_M0 << SPI_IOMUX_SEL_SHIFT);
 
 	switch (spi_id) {
 	case PERIPH_ID_SPI0:
 		switch (cs) {
 		case 0:
 			rk_clrsetreg(&grf->gpio2bl_iomux,
-				     GRF_GPIO2BL3_SEL_MASK,
-				     GRF_SPI_CSN0_M0 << GRF_GPIO2BL3_SEL_SHIFT);
+				     GPIO2BL3_SEL_MASK,
+				     GPIO2BL3_SPI_CSN0_M0
+				     << GPIO2BL3_SEL_SHIFT);
 			break;
 		case 1:
 			rk_clrsetreg(&grf->gpio2bl_iomux,
-				     GRF_GPIO2BL4_SEL_MASK,
-				     GRF_SPI_CSN1_M0 << GRF_GPIO2BL4_SEL_SHIFT);
+				     GPIO2BL4_SEL_MASK,
+				     GPIO2BL4_SPI_CSN1_M0
+				     << GPIO2BL4_SEL_SHIFT);
 			break;
 		default:
 			goto err;
 		}
 		rk_clrsetreg(&grf->gpio2bl_iomux,
-			     GRF_GPIO2BL0_SEL_MASK,
-			     GRF_SPI_CLK_TX_RX_M0 << GRF_GPIO2BL0_SEL_SHIFT);
+			     GPIO2BL0_SEL_MASK,
+			     GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT);
 		break;
 	default:
 		goto err;
@@ -245,13 +140,13 @@ static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
 		break;
 		/* uart2 iomux select m1 */
 		rk_clrsetreg(&grf->com_iomux,
-			     GRF_UART2_IOMUX_SEL_MASK,
-			     GRF_UART2_IOMUX_SEL_M1
-			     << GRF_UART2_IOMUX_SEL_SHIFT);
+			     UART2_IOMUX_SEL_MASK,
+			     UART2_IOMUX_SEL_M1
+			     << UART2_IOMUX_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A0_SEL_MASK | GRF_GPIO2A1_SEL_MASK,
-			     GRF_UART2_TX_M1 << GRF_GPIO2A0_SEL_SHIFT |
-			     GRF_UART2_RX_M1 << GRF_GPIO2A1_SEL_SHIFT);
+			     GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
+			     GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
+			     GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
 		break;
 	case PERIPH_ID_UART0:
 	case PERIPH_ID_UART1:
@@ -269,28 +164,28 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 	switch (mmc_id) {
 	case PERIPH_ID_EMMC:
 		rk_clrsetreg(&grf->gpio0a_iomux,
-			     GRF_GPIO0A7_SEL_MASK,
-			     GRF_EMMC_DATA0 << GRF_GPIO0A7_SEL_SHIFT);
+			     GPIO0A7_SEL_MASK,
+			     GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio2d_iomux,
-			     GRF_GPIO2D4_SEL_MASK,
-			     GRF_EMMC_DATA123 << GRF_GPIO2D4_SEL_SHIFT);
+			     GPIO2D4_SEL_MASK,
+			     GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio3c_iomux,
-			     GRF_GPIO3C0_SEL_MASK,
-			     GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD
-			     << GRF_GPIO3C0_SEL_SHIFT);
+			     GPIO3C0_SEL_MASK,
+			     GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD
+			     << GPIO3C0_SEL_SHIFT);
 		break;
 	case PERIPH_ID_SDCARD:
 		/* sdcard iomux select m0 */
 		rk_clrsetreg(&grf->com_iomux,
-			     GRF_CARD_IOMUX_SEL_MASK,
-			     GRF_CARD_IOMUX_SEL_M0 << GRF_CARD_IOMUX_SEL_SHIFT);
+			     CARD_IOMUX_SEL_MASK,
+			     CARD_IOMUX_SEL_M0 << CARD_IOMUX_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A7_SEL_MASK,
-			     GRF_CARD_PWR_EN_M0 << GRF_GPIO2A7_SEL_SHIFT);
+			     GPIO2A7_SEL_MASK,
+			     GPIO2A7_SDMMC0_PWRENM0 << GPIO2A7_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio1a_iomux,
-			     GRF_GPIO1A0_SEL_MASK,
-			     GRF_CARD_DATA_CLK_CMD_DETN
-			     << GRF_GPIO1A0_SEL_SHIFT);
+			     GPIO1A0_SEL_MASK,
+			     GPIO1A0_CARD_DATA_CLK_CMD_DETN
+			     << GPIO1A0_SEL_SHIFT);
 		break;
 	default:
 		debug("mmc id = %d iomux error!\n", mmc_id);
-- 
1.9.1

[U-Boot] [PATCH 2/6] rockchip: pinctrl: rk3328: do not set io routing

[Kever Yang]

In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.

We should not decide which group to use in pinctrl driver,
for it may be different in different board, it should goes to board
file, and the pinctrl file should setting correct iomux depends on
the com_iomux value.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 30 ++++++++--------
 drivers/pinctrl/rockchip/pinctrl_rk3328.c       | 47 +++++++++++++++----------
 2 files changed, 43 insertions(+), 34 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index 40a4de0..f0a0781 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -228,21 +228,21 @@ enum {
 	GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD	= 0x2aaa,
 
 	/* COM_IOMUX */
-	UART2_IOMUX_SEL_SHIFT	= 0,
-	UART2_IOMUX_SEL_MASK	= 3 << UART2_IOMUX_SEL_SHIFT,
-	UART2_IOMUX_SEL_M0		= 0,
-	UART2_IOMUX_SEL_M1,
-
-	SPI_IOMUX_SEL_SHIFT = 4,
-	SPI_IOMUX_SEL_MASK	= 3 << SPI_IOMUX_SEL_SHIFT,
-	SPI_IOMUX_SEL_M0	= 0,
-	SPI_IOMUX_SEL_M1,
-	SPI_IOMUX_SEL_M2,
-
-	CARD_IOMUX_SEL_SHIFT	= 7,
-	CARD_IOMUX_SEL_MASK		= 1 << CARD_IOMUX_SEL_SHIFT,
-	CARD_IOMUX_SEL_M0		= 0,
-	CARD_IOMUX_SEL_M1,
+	IOMUX_SEL_UART2_SHIFT	= 0,
+	IOMUX_SEL_UART2_MASK	= 3 << IOMUX_SEL_UART2_SHIFT,
+	IOMUX_SEL_UART2_M0	= 0,
+	IOMUX_SEL_UART2_M1,
+
+	IOMUX_SEL_SPI_SHIFT	= 4,
+	IOMUX_SEL_SPI_MASK	= 3 << IOMUX_SEL_SPI_SHIFT,
+	IOMUX_SEL_SPI_M0	= 0,
+	IOMUX_SEL_SPI_M1,
+	IOMUX_SEL_SPI_M2,
+
+	IOMUX_SEL_SDMMC_SHIFT	= 7,
+	IOMUX_SEL_SDMMC_MASK	= 1 << IOMUX_SEL_SDMMC_SHIFT,
+	IOMUX_SEL_SDMMC_M0	= 0,
+	IOMUX_SEL_SDMMC_M1,
 };
 
 #endif	/* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 63ce7a0..716d02a 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -97,9 +97,13 @@ static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
 static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
 				     enum periph_id spi_id, int cs)
 {
-	rk_clrsetreg(&grf->com_iomux,
-		     SPI_IOMUX_SEL_MASK,
-		     SPI_IOMUX_SEL_M0 << SPI_IOMUX_SEL_SHIFT);
+	u32 com_iomux = readl(&grf->com_iomux);
+
+	if ((com_iomux & IOMUX_SEL_SPI_MASK) !=
+		IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) {
+		debug("driver do not support iomux other than m0\n");
+		goto err;
+	}
 
 	switch (spi_id) {
 	case PERIPH_ID_SPI0:
@@ -135,18 +139,17 @@ err:
 
 static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
 {
+	u32 com_iomux = readl(&grf->com_iomux);
+
 	switch (uart_id) {
 	case PERIPH_ID_UART2:
 		break;
-		/* uart2 iomux select m1 */
-		rk_clrsetreg(&grf->com_iomux,
-			     UART2_IOMUX_SEL_MASK,
-			     UART2_IOMUX_SEL_M1
-			     << UART2_IOMUX_SEL_SHIFT);
-		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
-			     GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
-			     GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
+		if (com_iomux & IOMUX_SEL_UART2_MASK)
+			rk_clrsetreg(&grf->gpio2a_iomux,
+				     GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
+				     GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
+				     GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
+
 		break;
 	case PERIPH_ID_UART0:
 	case PERIPH_ID_UART1:
@@ -161,6 +164,8 @@ static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
 static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 					int mmc_id)
 {
+	u32 com_iomux = readl(&grf->com_iomux);
+
 	switch (mmc_id) {
 	case PERIPH_ID_EMMC:
 		rk_clrsetreg(&grf->gpio0a_iomux,
@@ -175,13 +180,17 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 			     << GPIO3C0_SEL_SHIFT);
 		break;
 	case PERIPH_ID_SDCARD:
-		/* sdcard iomux select m0 */
-		rk_clrsetreg(&grf->com_iomux,
-			     CARD_IOMUX_SEL_MASK,
-			     CARD_IOMUX_SEL_M0 << CARD_IOMUX_SEL_SHIFT);
-		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GPIO2A7_SEL_MASK,
-			     GPIO2A7_SDMMC0_PWRENM0 << GPIO2A7_SEL_SHIFT);
+		/* SDMMC_PWREN use GPIO and init as regulator-fiexed  */
+		if (com_iomux & IOMUX_SEL_SDMMC_MASK)
+			rk_clrsetreg(&grf->gpio0d_iomux,
+				     GPIO0D6_SEL_MASK,
+				     GPIO0D6_SDMMC0_PWRENM1
+				     << GPIO0D6_SEL_SHIFT);
+		else
+			rk_clrsetreg(&grf->gpio2a_iomux,
+				     GPIO2A7_SEL_MASK,
+				     GPIO2A7_SDMMC0_PWRENM0
+				     << GPIO2A7_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio1a_iomux,
 			     GPIO1A0_SEL_MASK,
 			     GPIO1A0_CARD_DATA_CLK_CMD_DETN
-- 
1.9.1

[U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Kever Yang]

In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.

We should set these IO routing in board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 board/rockchip/evb_rk3328/evb-rk3328.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
index a7895cb..d9dc782 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -5,7 +5,10 @@
  */
 
 #include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3328.h>
 #include <asm/armv8/mmu.h>
+#include <asm/io.h>
 #include <dwc3-uboot.h>
 #include <usb.h>
 
@@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
+#define GRF_BASE	0xff100000
+	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+
+	/* uart2 select m1, sdcard select m1*/
+	rk_clrsetreg(&grf->com_iomux,
+		     IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
+		     IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
+		     IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
+
 	return 0;
 }
 
-- 
1.9.1

[U-Boot] [PATCH 4/6] rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwren

[Kever Yang]

SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may
be high active or low active, the dwmmc driver always assume
the sdmmc-pwren as high active.

Kernel treat this pin as fixed regulator instead of a pin from
controller, and then it can set in dts file upon board schematic,
that's a good solution, we can also do this in u-boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/pinctrl/rockchip/pinctrl_rk3328.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 716d02a..0995d9f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -184,13 +184,11 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 		if (com_iomux & IOMUX_SEL_SDMMC_MASK)
 			rk_clrsetreg(&grf->gpio0d_iomux,
 				     GPIO0D6_SEL_MASK,
-				     GPIO0D6_SDMMC0_PWRENM1
-				     << GPIO0D6_SEL_SHIFT);
+				     GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
 		else
 			rk_clrsetreg(&grf->gpio2a_iomux,
 				     GPIO2A7_SEL_MASK,
-				     GPIO2A7_SDMMC0_PWRENM0
-				     << GPIO2A7_SEL_SHIFT);
+				     GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio1a_iomux,
 			     GPIO1A0_SEL_MASK,
 			     GPIO1A0_CARD_DATA_CLK_CMD_DETN
-- 
1.9.1

[U-Boot] [PATCH 5/6] rockchip: evb-rk3328: enable boot on regulator

[Kever Yang]

Enable all the boot-on regulator in default.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 board/rockchip/evb_rk3328/evb-rk3328.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
index d9dc782..eb15cee 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -10,12 +10,14 @@
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
 #include <dwc3-uboot.h>
+#include <power/regulator.h>
 #include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
+	int ret;
 #define GRF_BASE	0xff100000
 	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
 
@@ -25,7 +27,11 @@ int board_init(void)
 		     IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
 		     IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
 
-	return 0;
+	ret = regulators_enable_boot_on(false);
+	if (ret)
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+
+	return ret;
 }
 
 int dram_init(void)
-- 
1.9.1

[U-Boot] [PATCH 6/6] rockchip: dts: rk3328-evb: add sdmmc-pwren regulator

[Kever Yang]

Use fixed regulator for sdmmc-pwren for sdmmc power.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/dts/rk3328-evb.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 01794ed..7b14982 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -14,6 +14,14 @@
 	chosen {
 		stdout-path = &uart2;
 	};
+
+	vcc3v3_sdmmc: sdmmc-pwren {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &uart2 {
-- 
1.9.1

[U-Boot] [PATCH 1/6] rockchip: pinctrl: move rk3328 grf reg definition in header file

[Simon Glass]

On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Move GRF register bit definition into GRF header file, remove
> 'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 114 +++++++++++++
>  drivers/pinctrl/rockchip/pinctrl_rk3328.c       | 205 ++++++------------------
>  2 files changed, 164 insertions(+), 155 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 2/6] rockchip: pinctrl: rk3328: do not set io routing

[Simon Glass]

On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
> In rk3328, some function pin may have more than one choice, and muxed
> with more than one IO, for example, the UART2 controller IO,
> TX and RX, have 3 choice(setting in com_iomux):
> - M0 which mux with GPIO1A0/GPIO1A1
> - M1 which mux with GPIO2A0/GPIO2A1
> - usb2phy which mux with USB2.0 DP/DM pin.
>
> We should not decide which group to use in pinctrl driver,
> for it may be different in different board, it should goes to board
> file, and the pinctrl file should setting correct iomux depends on
> the com_iomux value.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 30 ++++++++--------
>  drivers/pinctrl/rockchip/pinctrl_rk3328.c       | 47 +++++++++++++++----------
>  2 files changed, 43 insertions(+), 34 deletions(-)
>

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Simon Glass]

Hi Kever,

On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
> In rk3328, some function pin may have more than one choice, and muxed
> with more than one IO, for example, the UART2 controller IO,
> TX and RX, have 3 choice(setting in com_iomux):
> - M0 which mux with GPIO1A0/GPIO1A1
> - M1 which mux with GPIO2A0/GPIO2A1
> - usb2phy which mux with USB2.0 DP/DM pin.
>
> We should set these IO routing in board file.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  board/rockchip/evb_rk3328/evb-rk3328.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
> index a7895cb..d9dc782 100644
> --- a/board/rockchip/evb_rk3328/evb-rk3328.c
> +++ b/board/rockchip/evb_rk3328/evb-rk3328.c
> @@ -5,7 +5,10 @@
>   */
>
>  #include <common.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/grf_rk3328.h>
>  #include <asm/armv8/mmu.h>
> +#include <asm/io.h>
>  #include <dwc3-uboot.h>
>  #include <usb.h>
>
> @@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  int board_init(void)
>  {
> +#define GRF_BASE       0xff100000
> +       struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
> +
> +       /* uart2 select m1, sdcard select m1*/
> +       rk_clrsetreg(&grf->com_iomux,
> +                    IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
> +                    IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
> +                    IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
> +
>         return 0;
>  }

This needs to be done via a call to some sort of driver. The above
hack is OK in SPL but not in U-Boot proper.

See my comments elsewhere about using a misc driver with an IOCTL
interface to do this sort of thing. Although here I wonder why you
cannot use pinctrl?

Regards,
Simon

[U-Boot] [PATCH 4/6] rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwren

[Simon Glass]

On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
> SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may
> be high active or low active, the dwmmc driver always assume
> the sdmmc-pwren as high active.
>
> Kernel treat this pin as fixed regulator instead of a pin from
> controller, and then it can set in dts file upon board schematic,
> that's a good solution, we can also do this in u-boot.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  drivers/pinctrl/rockchip/pinctrl_rk3328.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 5/6] rockchip: evb-rk3328: enable boot on regulator

[Simon Glass]

On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
> Enable all the boot-on regulator in default.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  board/rockchip/evb_rk3328/evb-rk3328.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 6/6] rockchip: dts: rk3328-evb: add sdmmc-pwren regulator

[Simon Glass]

On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
> Use fixed regulator for sdmmc-pwren for sdmmc power.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/dts/rk3328-evb.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Kever Yang]

Hi Simon,


On 05/20/2017 10:29 AM, Simon Glass wrote:
> Hi Kever,
>
> On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
>> In rk3328, some function pin may have more than one choice, and muxed
>> with more than one IO, for example, the UART2 controller IO,
>> TX and RX, have 3 choice(setting in com_iomux):
>> - M0 which mux with GPIO1A0/GPIO1A1
>> - M1 which mux with GPIO2A0/GPIO2A1
>> - usb2phy which mux with USB2.0 DP/DM pin.
>>
>> We should set these IO routing in board file.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>   board/rockchip/evb_rk3328/evb-rk3328.c | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
>> index a7895cb..d9dc782 100644
>> --- a/board/rockchip/evb_rk3328/evb-rk3328.c
>> +++ b/board/rockchip/evb_rk3328/evb-rk3328.c
>> @@ -5,7 +5,10 @@
>>    */
>>
>>   #include <common.h>
>> +#include <asm/arch/hardware.h>
>> +#include <asm/arch/grf_rk3328.h>
>>   #include <asm/armv8/mmu.h>
>> +#include <asm/io.h>
>>   #include <dwc3-uboot.h>
>>   #include <usb.h>
>>
>> @@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;
>>
>>   int board_init(void)
>>   {
>> +#define GRF_BASE       0xff100000
>> +       struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
>> +
>> +       /* uart2 select m1, sdcard select m1*/
>> +       rk_clrsetreg(&grf->com_iomux,
>> +                    IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
>> +                    IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
>> +                    IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
>> +
>>          return 0;
>>   }
> This needs to be done via a call to some sort of driver. The above
> hack is OK in SPL but not in U-Boot proper.

Yes, SPL also needs this. I thinks here should be the right place
before there is a SPL for rk3328.
>
> See my comments elsewhere about using a misc driver with an IOCTL
> interface to do this sort of thing. Although here I wonder why you
> cannot use pinctrl?

This is different from traditional pinctrl, kernel also still not have
final solution on this, see [0], and some people think it should be
done in boot loader.


Thanks,
- Kever
[0] 
http://lists.infradead.org/pipermail/linux-rockchip/2016-August/011209.html
>
> Regards,
> Simon
>

[U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Heiko Stuebner]

Hi Kever,

Am Mittwoch, 24. Mai 2017, 10:35:04 CEST schrieb Kever Yang:
> On 05/20/2017 10:29 AM, Simon Glass wrote:
> > On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
> >> In rk3328, some function pin may have more than one choice, and muxed
> >> with more than one IO, for example, the UART2 controller IO,
> >> TX and RX, have 3 choice(setting in com_iomux):
> >> - M0 which mux with GPIO1A0/GPIO1A1
> >> - M1 which mux with GPIO2A0/GPIO2A1
> >> - usb2phy which mux with USB2.0 DP/DM pin.
> >>
> >> We should set these IO routing in board file.
> >>
> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> >> ---
> >>
> >>   board/rockchip/evb_rk3328/evb-rk3328.c | 12 ++++++++++++
> >>   1 file changed, 12 insertions(+)
> >>
> >> diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
> >> index a7895cb..d9dc782 100644
> >> --- a/board/rockchip/evb_rk3328/evb-rk3328.c
> >> +++ b/board/rockchip/evb_rk3328/evb-rk3328.c
> >> @@ -5,7 +5,10 @@
> >>    */
> >>
> >>   #include <common.h>
> >> +#include <asm/arch/hardware.h>
> >> +#include <asm/arch/grf_rk3328.h>
> >>   #include <asm/armv8/mmu.h>
> >> +#include <asm/io.h>
> >>   #include <dwc3-uboot.h>
> >>   #include <usb.h>
> >>
> >> @@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;
> >>
> >>   int board_init(void)
> >>   {
> >> +#define GRF_BASE       0xff100000
> >> +       struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
> >> +
> >> +       /* uart2 select m1, sdcard select m1*/
> >> +       rk_clrsetreg(&grf->com_iomux,
> >> +                    IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
> >> +                    IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
> >> +                    IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
> >> +
> >>          return 0;
> >>   }
> > This needs to be done via a call to some sort of driver. The above
> > hack is OK in SPL but not in U-Boot proper.
> 
> Yes, SPL also needs this. I thinks here should be the right place
> before there is a SPL for rk3328.
> >
> > See my comments elsewhere about using a misc driver with an IOCTL
> > interface to do this sort of thing. Although here I wonder why you
> > cannot use pinctrl?
> 
> This is different from traditional pinctrl, kernel also still not have
> final solution on this, see [0], and some people think it should be
> done in boot loader.

Just to point out that thanks to David Wu we now have a solution [1]
on the kernel side I'm pretty happy with - as part of the pinctrl driver.


Heiko


> [0] 
> http://lists.infradead.org/pipermail/linux-rockchip/2016-August/011209.html

[1] https://www.spinics.net/lists/kernel/msg2517794.html

[U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Simon Glass]

Hi Kever,

On 23 May 2017 at 20:35, Kever Yang <kever.yang@rock-chips.com> wrote:
> Hi Simon,
>
>
>
> On 05/20/2017 10:29 AM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
>>>
>>> In rk3328, some function pin may have more than one choice, and muxed
>>> with more than one IO, for example, the UART2 controller IO,
>>> TX and RX, have 3 choice(setting in com_iomux):
>>> - M0 which mux with GPIO1A0/GPIO1A1
>>> - M1 which mux with GPIO2A0/GPIO2A1
>>> - usb2phy which mux with USB2.0 DP/DM pin.
>>>
>>> We should set these IO routing in board file.
>>>
>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>> ---
>>>
>>>   board/rockchip/evb_rk3328/evb-rk3328.c | 12 ++++++++++++
>>>   1 file changed, 12 insertions(+)
>>>
>>> diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c
>>> b/board/rockchip/evb_rk3328/evb-rk3328.c
>>> index a7895cb..d9dc782 100644
>>> --- a/board/rockchip/evb_rk3328/evb-rk3328.c
>>> +++ b/board/rockchip/evb_rk3328/evb-rk3328.c
>>> @@ -5,7 +5,10 @@
>>>    */
>>>
>>>   #include <common.h>
>>> +#include <asm/arch/hardware.h>
>>> +#include <asm/arch/grf_rk3328.h>
>>>   #include <asm/armv8/mmu.h>
>>> +#include <asm/io.h>
>>>   #include <dwc3-uboot.h>
>>>   #include <usb.h>
>>>
>>> @@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;
>>>
>>>   int board_init(void)
>>>   {
>>> +#define GRF_BASE       0xff100000
>>> +       struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
>>> +
>>> +       /* uart2 select m1, sdcard select m1*/
>>> +       rk_clrsetreg(&grf->com_iomux,
>>> +                    IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
>>> +                    IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
>>> +                    IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
>>> +
>>>          return 0;
>>>   }
>>
>> This needs to be done via a call to some sort of driver. The above
>> hack is OK in SPL but not in U-Boot proper.
>
>
> Yes, SPL also needs this. I thinks here should be the right place
> before there is a SPL for rk3328.

But if you are booting from an SD card, how can you need a mux to
select it? Surely the boot ROM must set it up or you would not be able
to boot from MMC?

When will there be SPL for rk3328?

>>
>>
>> See my comments elsewhere about using a misc driver with an IOCTL
>> interface to do this sort of thing. Although here I wonder why you
>> cannot use pinctrl?
>
>
> This is different from traditional pinctrl, kernel also still not have
> final solution on this, see [0], and some people think it should be
> done in boot loader.

How about putting it in grf syscon driver?

>
>
> Thanks,
> - Kever
> [0]
> http://lists.infradead.org/pipermail/linux-rockchip/2016-August/011209.html
>>
>>
>> Regards,
>> Simon
>>
>
>

[U-Boot] [PATCH 4/6] rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwren

[Simon Glass]

Hi Kever,

On 19 May 2017 at 20:29, Simon Glass <sjg@chromium.org> wrote:
> On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
>> SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may
>> be high active or low active, the dwmmc driver always assume
>> the sdmmc-pwren as high active.
>>
>> Kernel treat this pin as fixed regulator instead of a pin from
>> controller, and then it can set in dts file upon board schematic,
>> that's a good solution, we can also do this in u-boot.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>  drivers/pinctrl/rockchip/pinctrl_rk3328.c | 6 ++----
>>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Can you please rebase this patch and the following ones? I have marked
them as 'changes requested' in patchwork.

Regards,
Simon

[U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Kever Yang]

Simon,


On 06/01/2017 11:10 AM, Simon Glass wrote:
> Hi Kever,
>
> On 23 May 2017 at 20:35, Kever Yang <kever.yang@rock-chips.com> wrote:
>> Hi Simon,
>>
>>
>>
>> On 05/20/2017 10:29 AM, Simon Glass wrote:
>>> Hi Kever,
>>>
>>> On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
>>>> In rk3328, some function pin may have more than one choice, and muxed
>>>> with more than one IO, for example, the UART2 controller IO,
>>>> TX and RX, have 3 choice(setting in com_iomux):
>>>> - M0 which mux with GPIO1A0/GPIO1A1
>>>> - M1 which mux with GPIO2A0/GPIO2A1
>>>> - usb2phy which mux with USB2.0 DP/DM pin.
>>>>
>>>> We should set these IO routing in board file.
>>>>
>>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>>> ---
>>>>
>>>>    board/rockchip/evb_rk3328/evb-rk3328.c | 12 ++++++++++++
>>>>    1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c
>>>> b/board/rockchip/evb_rk3328/evb-rk3328.c
>>>> index a7895cb..d9dc782 100644
>>>> --- a/board/rockchip/evb_rk3328/evb-rk3328.c
>>>> +++ b/board/rockchip/evb_rk3328/evb-rk3328.c
>>>> @@ -5,7 +5,10 @@
>>>>     */
>>>>
>>>>    #include <common.h>
>>>> +#include <asm/arch/hardware.h>
>>>> +#include <asm/arch/grf_rk3328.h>
>>>>    #include <asm/armv8/mmu.h>
>>>> +#include <asm/io.h>
>>>>    #include <dwc3-uboot.h>
>>>>    #include <usb.h>
>>>>
>>>> @@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;
>>>>
>>>>    int board_init(void)
>>>>    {
>>>> +#define GRF_BASE       0xff100000
>>>> +       struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
>>>> +
>>>> +       /* uart2 select m1, sdcard select m1*/
>>>> +       rk_clrsetreg(&grf->com_iomux,
>>>> +                    IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
>>>> +                    IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
>>>> +                    IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
>>>> +
>>>>           return 0;
>>>>    }
>>> This needs to be done via a call to some sort of driver. The above
>>> hack is OK in SPL but not in U-Boot proper.
>>
>> Yes, SPL also needs this. I thinks here should be the right place
>> before there is a SPL for rk3328.
> But if you are booting from an SD card, how can you need a mux to
> select it? Surely the boot ROM must set it up or you would not be able
> to boot from MMC?

If we need to boot from SD card, then we need to follow the boot ROM 
setting,
and hardware also need to follow it.
There is another case, the default SD card pin is used for other 
function in hardware,
then we use the alternative pin mux, we can't boot from SD card in bootrom,
but we still can use SD card in later stage like U-Boot and kernel.

Thanks,
- Kever
>
> When will there be SPL for rk3328?
>
>>>
>>> See my comments elsewhere about using a misc driver with an IOCTL
>>> interface to do this sort of thing. Although here I wonder why you
>>> cannot use pinctrl?
>>
>> This is different from traditional pinctrl, kernel also still not have
>> final solution on this, see [0], and some people think it should be
>> done in boot loader.
> How about putting it in grf syscon driver?
>
>>
>> Thanks,
>> - Kever
>> [0]
>> http://lists.infradead.org/pipermail/linux-rockchip/2016-August/011209.html
>>>
>>> Regards,
>>> Simon
>>>
>>

[U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Simon Glass]

Hi Kever,

On 6 June 2017 at 21:28, Kever Yang <kever.yang@rock-chips.com> wrote:
> Simon,
>
>
>
> On 06/01/2017 11:10 AM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 23 May 2017 at 20:35, Kever Yang <kever.yang@rock-chips.com> wrote:
>>>
>>> Hi Simon,
>>>
>>>
>>>
>>> On 05/20/2017 10:29 AM, Simon Glass wrote:
>>>>
>>>> Hi Kever,
>>>>
>>>> On 16 May 2017 at 21:44, Kever Yang <kever.yang@rock-chips.com> wrote:
>>>>>
>>>>> In rk3328, some function pin may have more than one choice, and muxed
>>>>> with more than one IO, for example, the UART2 controller IO,
>>>>> TX and RX, have 3 choice(setting in com_iomux):
>>>>> - M0 which mux with GPIO1A0/GPIO1A1
>>>>> - M1 which mux with GPIO2A0/GPIO2A1
>>>>> - usb2phy which mux with USB2.0 DP/DM pin.
>>>>>
>>>>> We should set these IO routing in board file.
>>>>>
>>>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>>>> ---
>>>>>
>>>>>    board/rockchip/evb_rk3328/evb-rk3328.c | 12 ++++++++++++
>>>>>    1 file changed, 12 insertions(+)
>>>>>
>>>>> diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c
>>>>> b/board/rockchip/evb_rk3328/evb-rk3328.c
>>>>> index a7895cb..d9dc782 100644
>>>>> --- a/board/rockchip/evb_rk3328/evb-rk3328.c
>>>>> +++ b/board/rockchip/evb_rk3328/evb-rk3328.c
>>>>> @@ -5,7 +5,10 @@
>>>>>     */
>>>>>
>>>>>    #include <common.h>
>>>>> +#include <asm/arch/hardware.h>
>>>>> +#include <asm/arch/grf_rk3328.h>
>>>>>    #include <asm/armv8/mmu.h>
>>>>> +#include <asm/io.h>
>>>>>    #include <dwc3-uboot.h>
>>>>>    #include <usb.h>
>>>>>
>>>>> @@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;
>>>>>
>>>>>    int board_init(void)
>>>>>    {
>>>>> +#define GRF_BASE       0xff100000
>>>>> +       struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
>>>>> +
>>>>> +       /* uart2 select m1, sdcard select m1*/
>>>>> +       rk_clrsetreg(&grf->com_iomux,
>>>>> +                    IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
>>>>> +                    IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
>>>>> +                    IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
>>>>> +
>>>>>           return 0;
>>>>>    }
>>>>
>>>> This needs to be done via a call to some sort of driver. The above
>>>> hack is OK in SPL but not in U-Boot proper.
>>>
>>>
>>> Yes, SPL also needs this. I thinks here should be the right place
>>> before there is a SPL for rk3328.
>>
>> But if you are booting from an SD card, how can you need a mux to
>> select it? Surely the boot ROM must set it up or you would not be able
>> to boot from MMC?
>
>
> If we need to boot from SD card, then we need to follow the boot ROM
> setting,
> and hardware also need to follow it.
> There is another case, the default SD card pin is used for other function in
> hardware,
> then we use the alternative pin mux, we can't boot from SD card in bootrom,
> but we still can use SD card in later stage like U-Boot and kernel.
>

OK, understood, thanks. Can you put it in the pinctrl driver?

- Simon

> Thanks,
> - Kever
>
>>
>> When will there be SPL for rk3328?
>>
>>>>
>>>> See my comments elsewhere about using a misc driver with an IOCTL
>>>> interface to do this sort of thing. Although here I wonder why you
>>>> cannot use pinctrl?
>>>
>>>
>>> This is different from traditional pinctrl, kernel also still not have
>>> final solution on this, see [0], and some people think it should be
>>> done in boot loader.
>>
>> How about putting it in grf syscon driver?
>>
>>>
>>> Thanks,
>>> - Kever
>>> [0]
>>>
>>> http://lists.infradead.org/pipermail/linux-rockchip/2016-August/011209.html
>>>>
>>>>
>>>> Regards,
>>>> Simon
>>>>
>>>
>
>