[U-Boot] [PATCH 0/8] sunxi: video: Add support for HDMI output on A64/H3/H5

[U-Boot] [PATCH 0/8] sunxi: video: Add support for HDMI output on A64/H3/H5

[Jernej Skrabec]

This series implements support for HDMI output. This is done using
DM video framework and sharing the HDMI controller code with RK3288.

First and second patch fix audio clock issue and remove unneeded CSC
initialization in RK3288 HDMI driver. I think audio initialization is
also not really needed, but I left it as it is for now.

Third patch splits out RK3288 HDMI code in a way that it is appropriate
for sharing with Allwinner SoCs.

Fourth patch splits out TCON code which is completely reusable on
all Allwinner SoCs.

Fifth patch adds all necessary clocks which are needed for Display
Engine 2, TCON and HDMI.

Finally, sixth patch implement actual DE2 and HDMI driver and
seventh enable HDMI on all boards which actually have it.

Code was tested on OrangePi 2 & OrangePi Plus 2E (both H3),
OrangePi PC 2 (H5) and Pine64 (A64). However, it was only compile
tested for A10, A20 and RK3288 targets because I don't have them.

This series was developed on u-boot-sunxi repository with additional
patch: https://patchwork.ozlabs.org/patch/735617/

Last patch here is included only for testing HDMI output on A64 due
to missing power regulator support (AXP803). Another option is to
use ATF which powers on HDMI. Such ATF can be found on Andre
Przywara's github.

Best regards,
Jernej Skrabec


Icenowy Zheng (1):
  [DO NOT MERGE] sunxi: power: add AXP803 support

Jernej Skrabec (7):
  rockchip: video: Fix HDMI audio clocks
  rockchip: video: Remove CSC initialization (HDMI)
  rockchip: video: Split out HDMI controller code
  sunxi: video: Split out TCON code
  sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs
  sunxi: video: Add A64/H3/H5 HDMI driver
  sunxi: Enable A64/H3/H5 video driver in defconfigs

 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 -------------
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h    |  54 ++
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h      |   8 +
 arch/arm/include/asm/arch-sunxi/display.h        | 103 ---
 arch/arm/include/asm/arch-sunxi/display2.h       | 124 ++++
 arch/arm/include/asm/arch-sunxi/lcdc.h           | 128 ++++
 arch/arm/mach-sunxi/Makefile                     |   3 +
 arch/arm/mach-sunxi/clock_sun6i.c                |  40 +-
 arch/arm/mach-sunxi/pmic_bus.c                   |   6 +-
 arch/arm/mach-sunxi/rsb.c                        |   2 +-
 board/sunxi/Kconfig                              |  10 +
 board/sunxi/board.c                              |  31 +-
 configs/orangepi_2_defconfig                     |   1 +
 configs/orangepi_lite_defconfig                  |   1 +
 configs/orangepi_one_defconfig                   |   1 +
 configs/orangepi_pc2_defconfig                   |   1 +
 configs/orangepi_pc_defconfig                    |   1 +
 configs/orangepi_pc_plus_defconfig               |   1 +
 configs/orangepi_plus2e_defconfig                |   1 +
 configs/orangepi_plus_defconfig                  |   1 +
 configs/pine64_plus_defconfig                    |   1 +
 drivers/power/Kconfig                            |  87 ++-
 drivers/power/Makefile                           |   1 +
 drivers/power/axp803.c                           | 256 ++++++++
 drivers/power/axp818.c                           |   2 +-
 drivers/video/Makefile                           |   2 +-
 drivers/video/dw_hdmi.c                          | 764 ++++++++++++++++++++++
 drivers/video/rockchip/Makefile                  |   2 +-
 drivers/video/rockchip/rk_hdmi.c                 | 796 +----------------------
 drivers/video/rockchip/rk_vop.c                  |   1 -
 drivers/video/sunxi/Makefile                     |   9 +
 drivers/video/sunxi/lcdc.c                       | 209 ++++++
 drivers/video/sunxi/sunxi_de2.c                  | 258 ++++++++
 drivers/video/{ => sunxi}/sunxi_display.c        | 224 ++-----
 drivers/video/sunxi/sunxi_dw_hdmi.c              | 389 +++++++++++
 include/axp803.h                                 |  73 +++
 include/axp_pmic.h                               |   3 +
 include/configs/sun50i.h                         |   2 +
 include/configs/sun8i.h                          |   4 +
 include/configs/sunxi-common.h                   |   5 +
 include/dw_hdmi.h                                | 486 ++++++++++++++
 scripts/config_whitelist.txt                     |   1 +
 42 files changed, 2984 insertions(+), 1564 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/display2.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/lcdc.h
 create mode 100644 drivers/power/axp803.c
 create mode 100644 drivers/video/dw_hdmi.c
 create mode 100644 drivers/video/sunxi/Makefile
 create mode 100644 drivers/video/sunxi/lcdc.c
 create mode 100644 drivers/video/sunxi/sunxi_de2.c
 rename drivers/video/{ => sunxi}/sunxi_display.c (86%)
 create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi.c
 create mode 100644 include/axp803.h
 create mode 100644 include/dw_hdmi.h

-- 
2.12.0

[U-Boot] [PATCH 1/8] rockchip: video: Fix HDMI audio clocks

[Jernej Skrabec]

Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets
compared with clocks in kHz. Fix that by converting all clocks to Hz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---

 drivers/video/rockchip/rk_hdmi.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 7b0c43b858..274d108851 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -32,37 +32,37 @@ struct rk_hdmi_priv {
 
 static const struct tmds_n_cts n_cts_table[] = {
 	{
-		.tmds = 25175, .n = 6144, .cts = 25175,
+		.tmds = 25175000, .n = 6144, .cts = 25175,
 	}, {
-		.tmds = 25200, .n = 6144, .cts = 25200,
+		.tmds = 25200000, .n = 6144, .cts = 25200,
 	}, {
-		.tmds = 27000, .n = 6144, .cts = 27000,
+		.tmds = 27000000, .n = 6144, .cts = 27000,
 	}, {
-		.tmds = 27027, .n = 6144, .cts = 27027,
+		.tmds = 27027000, .n = 6144, .cts = 27027,
 	}, {
-		.tmds = 40000, .n = 6144, .cts = 40000,
+		.tmds = 40000000, .n = 6144, .cts = 40000,
 	}, {
-		.tmds = 54000, .n = 6144, .cts = 54000,
+		.tmds = 54000000, .n = 6144, .cts = 54000,
 	}, {
-		.tmds = 54054, .n = 6144, .cts = 54054,
+		.tmds = 54054000, .n = 6144, .cts = 54054,
 	}, {
-		.tmds = 65000, .n = 6144, .cts = 65000,
+		.tmds = 65000000, .n = 6144, .cts = 65000,
 	}, {
-		.tmds = 74176, .n = 11648, .cts = 140625,
+		.tmds = 74176000, .n = 11648, .cts = 140625,
 	}, {
-		.tmds = 74250, .n = 6144, .cts = 74250,
+		.tmds = 74250000, .n = 6144, .cts = 74250,
 	}, {
-		.tmds = 83500, .n = 6144, .cts = 83500,
+		.tmds = 83500000, .n = 6144, .cts = 83500,
 	}, {
-		.tmds = 106500, .n = 6144, .cts = 106500,
+		.tmds = 106500000, .n = 6144, .cts = 106500,
 	}, {
-		.tmds = 108000, .n = 6144, .cts = 108000,
+		.tmds = 108000000, .n = 6144, .cts = 108000,
 	}, {
-		.tmds = 148352, .n = 5824, .cts = 140625,
+		.tmds = 148352000, .n = 5824, .cts = 140625,
 	}, {
-		.tmds = 148500, .n = 6144, .cts = 148500,
+		.tmds = 148500000, .n = 6144, .cts = 148500,
 	}, {
-		.tmds = 297000, .n = 5120, .cts = 247500,
+		.tmds = 297000000, .n = 5120, .cts = 247500,
 	}
 };
 
-- 
2.12.0

[U-Boot] [PATCH 1/8] rockchip: video: Fix HDMI audio clocks

[Simon Glass]

On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
> Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets
> compared with clocks in kHz. Fix that by converting all clocks to Hz.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
>
>  drivers/video/rockchip/rk_hdmi.c | 32 ++++++++++++++++----------------
>  1 file changed, 16 insertions(+), 16 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 1/8] rockchip: video: Fix HDMI audio clocks

[Simon Glass]

On 13 March 2017 at 06:33, Simon Glass <sjg@chromium.org> wrote:
> On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
>> Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets
>> compared with clocks in kHz. Fix that by converting all clocks to Hz.
>>
>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> ---
>>
>>  drivers/video/rockchip/rk_hdmi.c | 32 ++++++++++++++++----------------
>>  1 file changed, 16 insertions(+), 16 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip, thanks!

[U-Boot] [PATCH 2/8] rockchip: video: Remove CSC initialization (HDMI)

[Jernej Skrabec]

Despite the comment in the code, CSC unit is never used. According to
the only public description of DW HDMI controller (i.MX6 manual), CSC
unit is bypassed in MC_FLOWCTRL register and then actually powered
down in MC_CLKDIS register.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---

 drivers/video/rockchip/rk_hdmi.c | 39 ---------------------------------------
 1 file changed, 39 deletions(-)

diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 274d108851..c8608db23c 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -124,12 +124,6 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
 	}
 };
 
-static const u32 csc_coeff_default[3][4] = {
-	{ 0x2000, 0x0000, 0x0000, 0x0000 },
-	{ 0x0000, 0x2000, 0x0000, 0x0000 },
-	{ 0x0000, 0x0000, 0x2000, 0x0000 }
-};
-
 static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts)
 {
 	uint cts3;
@@ -220,37 +214,6 @@ static void hdmi_video_sample(struct rk3288_hdmi *regs)
 	writel(0x0, &regs->tx_bcbdata1);
 }
 
-static void hdmi_update_csc_coeffs(struct rk3288_hdmi *regs)
-{
-	u32 i, j;
-	u32 csc_scale = 1;
-
-	/* the csc registers are sequential, alternating msb then lsb */
-	for (i = 0; i < ARRAY_SIZE(csc_coeff_default); i++) {
-		for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) {
-			u32 coeff = csc_coeff_default[i][j];
-			writel(coeff >> 8, &regs->csc_coef[i][j].msb);
-			writel(coeff && 0xff, &regs->csc_coef[i][j].lsb);
-		}
-	}
-
-	clrsetbits_le32(&regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
-			csc_scale);
-}
-
-static void hdmi_video_csc(struct rk3288_hdmi *regs)
-{
-	u32 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
-	u32 interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
-
-	/* configure the csc registers */
-	writel(interpolation, &regs->csc_cfg);
-	clrsetbits_le32(&regs->csc_scale,
-			HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth);
-
-	hdmi_update_csc_coeffs(regs);
-}
-
 static void hdmi_video_packetize(struct rk3288_hdmi *regs)
 {
 	u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
@@ -467,7 +430,6 @@ static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock)
 		hdmi_phy_enable_tmds(regs, 0);
 		hdmi_phy_enable_power(regs, 0);
 
-		/* enable csc */
 		ret = hdmi_phy_configure(regs, mpixelclock);
 		if (ret) {
 			debug("hdmi phy config failure %d\n", ret);
@@ -837,7 +799,6 @@ static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
 	hdmi_audio_set_samplerate(regs, edid->pixelclock.typ);
 
 	hdmi_video_packetize(regs);
-	hdmi_video_csc(regs);
 	hdmi_video_sample(regs);
 
 	hdmi_clear_overflow(regs);
-- 
2.12.0

[U-Boot] [PATCH 2/8] rockchip: video: Remove CSC initialization (HDMI)

[Simon Glass]

On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
> Despite the comment in the code, CSC unit is never used. According to
> the only public description of DW HDMI controller (i.MX6 manual), CSC
> unit is bypassed in MC_FLOWCTRL register and then actually powered
> down in MC_CLKDIS register.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
>
>  drivers/video/rockchip/rk_hdmi.c | 39 ---------------------------------------
>  1 file changed, 39 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 2/8] rockchip: video: Remove CSC initialization (HDMI)

[Simon Glass]

On 13 March 2017 at 06:33, Simon Glass <sjg@chromium.org> wrote:
> On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
>> Despite the comment in the code, CSC unit is never used. According to
>> the only public description of DW HDMI controller (i.MX6 manual), CSC
>> unit is bypassed in MC_FLOWCTRL register and then actually powered
>> down in MC_CLKDIS register.
>>
>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> ---
>>
>>  drivers/video/rockchip/rk_hdmi.c | 39 ---------------------------------------
>>  1 file changed, 39 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip, thanks!

[U-Boot] [PATCH 3/8] rockchip: video: Split out HDMI controller code

[Jernej Skrabec]

Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.

DW HDMI has 8 bit registers but they can be represented as 32 bit
registers as well. Add support to select access mode.

EDID reading code use reading by blocks which is not supported by other
SoCs in general. Make it more general using byte by byte approach, which
is also used in Linux driver.

Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
Support custom phys by making controller code independent from phy code.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---

 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 --------------
 drivers/video/dw_hdmi.c                          | 764 +++++++++++++++++++++++
 drivers/video/rockchip/Makefile                  |   2 +-
 drivers/video/rockchip/rk_hdmi.c                 | 757 +---------------------
 drivers/video/rockchip/rk_vop.c                  |   1 -
 include/dw_hdmi.h                                | 486 ++++++++++++++
 6 files changed, 1275 insertions(+), 1191 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
 create mode 100644 drivers/video/dw_hdmi.c
 create mode 100644 include/dw_hdmi.h

diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
deleted file mode 100644
index 0b51d40882..0000000000
--- a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Copyright 2014 Rockchip Inc.
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_HDMI_H
-#define _ASM_ARCH_HDMI_H
-
-
-#define HDMI_EDID_BLOCK_SIZE            128
-
-struct rk3288_hdmi {
-	u32 reserved0[0x100];
-	u32 ih_fc_stat0;
-	u32 ih_fc_stat1;
-	u32 ih_fc_stat2;
-	u32 ih_as_stat0;
-	u32 ih_phy_stat0;
-	u32 ih_i2cm_stat0;
-	u32 ih_cec_stat0;
-	u32 ih_vp_stat0;
-	u32 ih_i2cmphy_stat0;
-	u32 ih_ahbdmaaud_stat0;
-	u32 reserved1[0x17f-0x109];
-	u32 ih_mute_fc_stat0;
-	u32 ih_mute_fc_stat1;
-	u32 ih_mute_fc_stat2;
-	u32 ih_mute_as_stat0;
-	u32 ih_mute_phy_stat0;
-	u32 ih_mute_i2cm_stat0;
-	u32 ih_mute_cec_stat0;
-	u32 ih_mute_vp_stat0;
-	u32 ih_mute_i2cmphy_stat0;
-	u32 ih_mute_ahbdmaaud_stat0;
-	u32 reserved2[0x1fe - 0x189];
-	u32 ih_mute;
-	u32 tx_invid0;
-	u32 tx_instuffing;
-	u32 tx_gydata0;
-	u32 tx_gydata1;
-	u32 tx_rcrdata0;
-	u32 tx_rcrdata1;
-	u32 tx_bcbdata0;
-	u32 tx_bcbdata1;
-	u32 reserved3[0x7ff-0x207];
-	u32 vp_status;
-	u32 vp_pr_cd;
-	u32 vp_stuff;
-	u32 vp_remap;
-	u32 vp_conf;
-	u32 vp_stat;
-	u32 vp_int;
-	u32 vp_mask;
-	u32 vp_pol;
-	u32 reserved4[0xfff-0x808];
-	u32 fc_invidconf;
-	u32 fc_inhactv0;
-	u32 fc_inhactv1;
-	u32 fc_inhblank0;
-	u32 fc_inhblank1;
-	u32 fc_invactv0;
-	u32 fc_invactv1;
-	u32 fc_invblank;
-	u32 fc_hsyncindelay0;
-	u32 fc_hsyncindelay1;
-	u32 fc_hsyncinwidth0;
-	u32 fc_hsyncinwidth1;
-	u32 fc_vsyncindelay;
-	u32 fc_vsyncinwidth;
-	u32 fc_infreq0;
-	u32 fc_infreq1;
-	u32 fc_infreq2;
-	u32 fc_ctrldur;
-	u32 fc_exctrldur;
-	u32 fc_exctrlspac;
-	u32 fc_ch0pream;
-	u32 fc_ch1pream;
-	u32 fc_ch2pream;
-	u32 fc_aviconf3;
-	u32 fc_gcp;
-	u32 fc_aviconf0;
-	u32 fc_aviconf1;
-	u32 fc_aviconf2;
-	u32 fc_avivid;
-	u32 fc_avietb0;
-	u32 fc_avietb1;
-	u32 fc_avisbb0;
-	u32 fc_avisbb1;
-	u32 fc_avielb0;
-	u32 fc_avielb1;
-	u32 fc_avisrb0;
-	u32 fc_avisrb1;
-	u32 fc_audiconf0;
-	u32 fc_audiconf1;
-	u32 fc_audiconf2;
-	u32 fc_audiconf3;
-	u32 fc_vsdieeeid0;
-	u32 fc_vsdsize;
-	u32 reserved7[0x2fff-0x102a];
-	u32 phy_conf0;
-	u32 phy_tst0;
-	u32 phy_tst1;
-	u32 phy_tst2;
-	u32 phy_stat0;
-	u32 phy_int0;
-	u32 phy_mask0;
-	u32 phy_pol0;
-	u32 reserved8[0x301f-0x3007];
-	u32 phy_i2cm_slave_addr;
-	u32 phy_i2cm_address_addr;
-	u32 phy_i2cm_datao_1_addr;
-	u32 phy_i2cm_datao_0_addr;
-	u32 phy_i2cm_datai_1_addr;
-	u32 phy_i2cm_datai_0_addr;
-	u32 phy_i2cm_operation_addr;
-	u32 phy_i2cm_int_addr;
-	u32 phy_i2cm_ctlint_addr;
-	u32 phy_i2cm_div_addr;
-	u32 phy_i2cm_softrstz_addr;
-	u32 phy_i2cm_ss_scl_hcnt_1_addr;
-	u32 phy_i2cm_ss_scl_hcnt_0_addr;
-	u32 phy_i2cm_ss_scl_lcnt_1_addr;
-	u32 phy_i2cm_ss_scl_lcnt_0_addr;
-	u32 phy_i2cm_fs_scl_hcnt_1_addr;
-	u32 phy_i2cm_fs_scl_hcnt_0_addr;
-	u32 phy_i2cm_fs_scl_lcnt_1_addr;
-	u32 phy_i2cm_fs_scl_lcnt_0_addr;
-	u32 reserved9[0x30ff-0x3032];
-	u32 aud_conf0;
-	u32 aud_conf1;
-	u32 aud_int;
-	u32 aud_conf2;
-	u32 aud_int1;
-	u32 reserved32[0x31ff-0x3104];
-	u32 aud_n1;
-	u32 aud_n2;
-	u32 aud_n3;
-	u32 aud_cts1;
-	u32 aud_cts2;
-	u32 aud_cts3;
-	u32 aud_inputclkfs;
-	u32 reserved12[0x3fff-0x3206];
-	u32 mc_sfrdiv;
-	u32 mc_clkdis;
-	u32 mc_swrstz;
-	u32 mc_opctrl;
-	u32 mc_flowctrl;
-	u32 mc_phyrstz;
-	u32 mc_lockonclock;
-	u32 mc_heacphy_rst;
-	u32 reserved13[0x40ff-0x4007];
-	u32 csc_cfg;
-	u32 csc_scale;
-	struct {
-		u32 msb;
-		u32 lsb;
-	} csc_coef[3][4];
-	u32 reserved17[0x7dff-0x4119];
-	u32 i2cm_slave;
-	u32 i2c_address;
-	u32 i2cm_datao;
-	u32 i2cm_datai;
-	u32 i2cm_operation;
-	u32 i2cm_int;
-	u32 i2cm_ctlint;
-	u32 i2cm_div;
-	u32 i2cm_segaddr;
-	u32 i2cm_softrstz;
-	u32 i2cm_segptr;
-	u32 i2cm_ss_scl_hcnt_1_addr;
-	u32 i2cm_ss_scl_hcnt_0_addr;
-	u32 i2cm_ss_scl_lcnt_1_addr;
-	u32 i2cm_ss_scl_lcnt_0_addr;
-	u32 i2cm_fs_scl_hcnt_1_addr;
-	u32 i2cm_fs_scl_hcnt_0_addr;
-	u32 i2cm_fs_scl_lcnt_1_addr;
-	u32 i2cm_fs_scl_lcnt_0_addr;
-	u32 reserved18[0x7e1f-0x7e12];
-	u32 i2cm_buf0;
-};
-check_member(rk3288_hdmi, i2cm_buf0, 0x1f880);
-
-enum {
-	/* HDMI PHY registers define */
-	PHY_OPMODE_PLLCFG = 0x06,
-	PHY_CKCALCTRL = 0x05,
-	PHY_CKSYMTXCTRL = 0x09,
-	PHY_VLEVCTRL = 0x0e,
-	PHY_PLLCURRCTRL = 0x10,
-	PHY_PLLPHBYCTRL = 0x13,
-	PHY_PLLGMPCTRL = 0x15,
-	PHY_PLLCLKBISTPHASE = 0x17,
-	PHY_TXTERM = 0x19,
-
-	/* ih_phy_stat0 field values */
-	HDMI_IH_PHY_STAT0_HPD = 0x1,
-
-	/* ih_mute field values */
-	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
-	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
-
-	/* tx_invid0 field values */
-	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
-	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
-	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
-
-	/* tx_instuffing field values */
-	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
-	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
-	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
-
-	/* vp_pr_cd field values */
-	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
-	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
-	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
-	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
-
-	/* vp_stuff field values */
-	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
-	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
-	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
-	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
-	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
-	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
-	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
-	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
-
-	/* vp_conf field values */
-	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
-	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
-	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
-	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
-	HDMI_VP_CONF_PR_EN_MASK = 0x10,
-	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
-	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
-	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
-	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
-	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
-	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
-	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
-
-	/* vp_remap field values */
-	HDMI_VP_REMAP_YCC422_16BIT = 0x0,
-
-	/* fc_invidconf field values */
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
-	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
-	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
-	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
-
-
-	/* fc_aviconf0-fc_aviconf3 field values */
-	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
-	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
-	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
-	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
-	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
-	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
-	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
-	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
-	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
-	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
-	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
-	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
-	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
-
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
-	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
-	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
-	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
-	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
-	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
-
-	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
-	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
-	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
-	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
-	HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
-	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
-	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
-	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
-	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
-	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
-	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
-	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
-
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
-	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
-	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
-	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
-
-	/* fc_gcp field values*/
-	HDMI_FC_GCP_SET_AVMUTE = 0x02,
-	HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
-
-	/* phy_conf0 field values */
-	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
-	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
-	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
-	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
-	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
-	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
-	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
-	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
-	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
-	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
-	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
-	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
-	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
-	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
-
-	/* phy_tst0 field values */
-	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
-	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
-
-	/* phy_stat0 field values */
-	HDMI_PHY_HPD = 0x02,
-	HDMI_PHY_TX_PHY_LOCK = 0x01,
-
-	/* phy_i2cm_slave_addr field values */
-	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
-
-	/* phy_i2cm_operation_addr field values */
-	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
-
-	/* hdmi_phy_i2cm_int_addr */
-	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
-
-	/* hdmi_phy_i2cm_ctlint_addr */
-	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
-	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
-
-	/* aud_conf0 field values */
-	HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
-	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
-	HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
-	HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
-	HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
-	HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
-
-	/* aud_conf0 field values */
-	HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
-	HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
-
-	/* aud_n3 field values */
-	HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
-	HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
-
-	/* aud_cts3 field values */
-	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
-	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
-	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
-	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
-	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
-	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
-	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
-	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
-	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
-	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
-
-	/* aud_inputclkfs filed values */
-	HDMI_AUD_INPUTCLKFS_128 = 0x0,
-
-	/* mc_clkdis field values */
-	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
-	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
-	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
-
-	/* mc_swrstz field values */
-	HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
-	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
-
-	/* mc_flowctrl field values */
-	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
-	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
-
-	/* mc_phyrstz field values */
-	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
-	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
-
-	/* mc_heacphy_rst field values */
-	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
-
-	/* csc_cfg field values */
-	HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
-
-	/* csc_scale field values */
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
-	HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
-
-	/* i2cm filed values */
-	HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
-	HDMI_I2CM_SEGADDR_DDC = 0x30,
-	HDMI_I2CM_OPT_RD8_EXT = 0x8,
-	HDMI_I2CM_OPT_RD8 = 0x4,
-	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
-	HDMI_I2CM_DIV_FAST_MODE = 0x8,
-	HDMI_I2CM_DIV_STD_MODE = 0x0,
-	HDMI_I2CM_SOFTRSTZ = 0x1,
-};
-
-/*
-struct display_timing;
-struct rk3288_grf;
-
-int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id);
-int rk_hdmi_enable(const struct display_timing *edid);
-int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing *edid);
-*/
-
-#endif
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
new file mode 100644
index 0000000000..8a53109823
--- /dev/null
+++ b/drivers/video/dw_hdmi.c
@@ -0,0 +1,764 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ * Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include "dw_hdmi.h"
+
+struct tmds_n_cts {
+	u32 tmds;
+	u32 cts;
+	u32 n;
+};
+
+static const struct tmds_n_cts n_cts_table[] = {
+	{
+		.tmds = 25175000, .n = 6144, .cts = 25175,
+	}, {
+		.tmds = 25200000, .n = 6144, .cts = 25200,
+	}, {
+		.tmds = 27000000, .n = 6144, .cts = 27000,
+	}, {
+		.tmds = 27027000, .n = 6144, .cts = 27027,
+	}, {
+		.tmds = 40000000, .n = 6144, .cts = 40000,
+	}, {
+		.tmds = 54000000, .n = 6144, .cts = 54000,
+	}, {
+		.tmds = 54054000, .n = 6144, .cts = 54054,
+	}, {
+		.tmds = 65000000, .n = 6144, .cts = 65000,
+	}, {
+		.tmds = 74176000, .n = 11648, .cts = 140625,
+	}, {
+		.tmds = 74250000, .n = 6144, .cts = 74250,
+	}, {
+		.tmds = 83500000, .n = 6144, .cts = 83500,
+	}, {
+		.tmds = 106500000, .n = 6144, .cts = 106500,
+	}, {
+		.tmds = 108000000, .n = 6144, .cts = 108000,
+	}, {
+		.tmds = 148352000, .n = 5824, .cts = 140625,
+	}, {
+		.tmds = 148500000, .n = 6144, .cts = 148500,
+	}, {
+		.tmds = 297000000, .n = 5120, .cts = 247500,
+	}
+};
+
+static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset)
+{
+	switch (hdmi->reg_io_width) {
+	case 1:
+		writeb(val, hdmi->ioaddr + offset);
+		break;
+	case 4:
+		writel(val, hdmi->ioaddr + (offset << 2));
+		break;
+	default:
+		debug("reg_io_width has unsupported width!\n");
+		break;
+	}
+}
+
+static u8 hdmi_read(struct dw_hdmi *hdmi, int offset)
+{
+	switch (hdmi->reg_io_width) {
+	case 1:
+		return readb(hdmi->ioaddr + offset);
+	case 4:
+		return readl(hdmi->ioaddr + (offset << 2));
+	default:
+		debug("reg_io_width has unsupported width!\n");
+		break;
+	}
+
+	return 0;
+}
+
+static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data)
+{
+	u8 val = hdmi_read(hdmi, reg) & ~mask;
+
+	val |= data & mask;
+	hdmi_write(hdmi, val, reg);
+}
+
+static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 cts)
+{
+	uint cts3;
+	uint n3;
+
+	/* first set ncts_atomic_write (if present) */
+	n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
+	hdmi_write(hdmi, n3, HDMI_AUD_N3);
+
+	/* set cts_manual (if present) */
+	cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
+
+	cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
+	cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
+
+	/* write cts values; cts3 must be written first */
+	hdmi_write(hdmi, cts3, HDMI_AUD_CTS3);
+	hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
+	hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1);
+
+	/* write n values; n1 must be written last */
+	n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
+	hdmi_write(hdmi, n3, HDMI_AUD_N3);
+	hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
+	hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3);
+
+	hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS);
+}
+
+static int hdmi_lookup_n_cts(u32 pixel_clk)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
+		if (pixel_clk <= n_cts_table[i].tmds)
+			break;
+
+	if (i >= ARRAY_SIZE(n_cts_table))
+		return -1;
+
+	return i;
+}
+
+static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk)
+{
+	u32 clk_n, clk_cts;
+	int index;
+
+	index = hdmi_lookup_n_cts(pixel_clk);
+	if (index == -1) {
+		debug("audio not supported for pixel clk %d\n", pixel_clk);
+		return;
+	}
+
+	clk_n = n_cts_table[index].n;
+	clk_cts = n_cts_table[index].cts;
+	hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts);
+}
+
+/*
+ * this submodule is responsible for the video data synchronization.
+ * for example, for rgb 4:4:4 input, the data map is defined as
+ *			pin{47~40} <==> r[7:0]
+ *			pin{31~24} <==> g[7:0]
+ *			pin{15~8}  <==> b[7:0]
+ */
+static void hdmi_video_sample(struct dw_hdmi *hdmi)
+{
+	u32 color_format = 0x01;
+	uint val;
+
+	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
+	      ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
+	      HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
+
+	hdmi_write(hdmi, val, HDMI_TX_INVID0);
+
+	/* enable tx stuffing: when de is inactive, fix the output data to 0 */
+	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
+	      HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
+	      HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
+	hdmi_write(hdmi, val, HDMI_TX_INSTUFFING);
+	hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0);
+	hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1);
+	hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0);
+	hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1);
+	hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0);
+	hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1);
+}
+
+static void hdmi_video_packetize(struct dw_hdmi *hdmi)
+{
+	u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+	u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
+	u32 color_depth = 0;
+	uint val, vp_conf;
+
+	/* set the packetizer registers */
+	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
+		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
+		((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
+		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
+	hdmi_write(hdmi, val, HDMI_VP_PR_CD);
+
+	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK,
+		 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
+
+	/* data from pixel repeater block */
+	vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
+		  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
+
+	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK |
+		 HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
+
+	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
+		 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
+
+	hdmi_write(hdmi, remap_size, HDMI_VP_REMAP);
+
+	vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
+		  HDMI_VP_CONF_PP_EN_DISABLE |
+		  HDMI_VP_CONF_YCC422_EN_DISABLE;
+
+	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK |
+		 HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
+		 vp_conf);
+
+	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK |
+		 HDMI_VP_STUFF_YCC422_STUFFING_MASK,
+		 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
+		 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
+
+	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
+		 output_select);
+}
+
+static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit)
+{
+	hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK,
+		 bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
+}
+
+static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec)
+{
+	ulong start;
+	u32 val;
+
+	start = get_timer(0);
+	do {
+		val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0);
+		if (val & 0x3) {
+			hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
+			return 0;
+		}
+
+		udelay(100);
+	} while (get_timer(start) < msec);
+
+	return 1;
+}
+
+static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint addr)
+{
+	hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0);
+	hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
+	hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR);
+	hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR);
+	hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
+		   HDMI_PHY_I2CM_OPERATION_ADDR);
+
+	hdmi_phy_wait_i2c_done(hdmi, 1000);
+}
+
+static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK,
+		 enable << HDMI_PHY_CONF0_PDZ_OFFSET);
+}
+
+static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK,
+		 enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
+}
+
+static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK,
+		 enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
+}
+
+static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
+		 enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
+}
+
+static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0,
+		 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
+		 enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
+}
+
+static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0,
+		 HDMI_PHY_CONF0_SELDATAENPOL_MASK,
+		 enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
+}
+
+static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi,
+					   uint enable)
+{
+	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK,
+		 enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
+}
+
+static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock)
+{
+	ulong start;
+	uint i, val;
+
+	if (!hdmi->mpll_cfg || !hdmi->phy_cfg)
+		return -1;
+
+	/* gen2 tx power off */
+	hdmi_phy_gen2_txpwron(hdmi, 0);
+
+	/* gen2 pddq */
+	hdmi_phy_gen2_pddq(hdmi, 1);
+
+	/* phy reset */
+	hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
+	hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
+	hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
+
+	hdmi_phy_test_clear(hdmi, 1);
+	hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
+		   HDMI_PHY_I2CM_SLAVE_ADDR);
+	hdmi_phy_test_clear(hdmi, 0);
+
+	/* pll/mpll cfg - always match on final entry */
+	for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++)
+		if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock)
+			break;
+
+	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
+	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
+	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL);
+
+	hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL);
+	hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE);
+
+	for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++)
+		if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock)
+			break;
+
+	/*
+	 * resistance term 133ohm cfg
+	 * preemp cgf 0.00
+	 * tx/ck lvl 10
+	 */
+	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM);
+	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL);
+	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL);
+
+	/* remove clk term */
+	hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL);
+
+	hdmi_phy_enable_power(hdmi, 1);
+
+	/* toggle tmds enable */
+	hdmi_phy_enable_tmds(hdmi, 0);
+	hdmi_phy_enable_tmds(hdmi, 1);
+
+	/* gen2 tx power on */
+	hdmi_phy_gen2_txpwron(hdmi, 1);
+	hdmi_phy_gen2_pddq(hdmi, 0);
+
+	hdmi_phy_enable_spare(hdmi, 1);
+
+	/* wait for phy pll lock */
+	start = get_timer(0);
+	do {
+		val = hdmi_read(hdmi, HDMI_PHY_STAT0);
+		if (!(val & HDMI_PHY_TX_PHY_LOCK))
+			return 0;
+
+		udelay(100);
+	} while (get_timer(start) < 5);
+
+	return -1;
+}
+
+static void hdmi_av_composer(struct dw_hdmi *hdmi,
+			     const struct display_timing *edid)
+{
+	bool mdataenablepolarity = true;
+	uint inv_val;
+	uint hbl;
+	uint vbl;
+
+	hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
+			edid->hsync_len.typ;
+	vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
+			edid->vsync_len.typ;
+
+	/* set up hdmi_fc_invidconf */
+	inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
+
+	inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
+		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
+		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
+
+	inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
+		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
+		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
+
+	inv_val |= (mdataenablepolarity ?
+		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
+		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
+
+	/*
+	 * TODO(sjg at chromium.org>: Need to check for HDMI / DVI
+	 * inv_val |= (edid->hdmi_monitor_detected ?
+	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
+	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
+	 */
+	inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
+
+	inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
+
+	inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
+
+	hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF);
+
+	/* set up horizontal active pixel width */
+	hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1);
+	hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0);
+
+	/* set up vertical active lines */
+	hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1);
+	hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0);
+
+	/* set up horizontal blanking pixel region width */
+	hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1);
+	hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0);
+
+	/* set up vertical blanking pixel region width */
+	hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK);
+
+	/* set up hsync active edge delay width (in pixel clks) */
+	hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1);
+	hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0);
+
+	/* set up vsync active edge delay (in lines) */
+	hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY);
+
+	/* set up hsync active pulse width (in pixel clks) */
+	hdmi_write(hdmi, edid->hsync_len.typ >> 8, HDMI_FC_HSYNCINWIDTH1);
+	hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0);
+
+	/* set up vsync active edge delay (in lines) */
+	hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH);
+}
+
+/* hdmi initialization step b.4 */
+static void hdmi_enable_video_path(struct dw_hdmi *hdmi)
+{
+	uint clkdis;
+
+	/* control period minimum duration */
+	hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR);
+	hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR);
+	hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC);
+
+	/* set to fill tmds data channels */
+	hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM);
+	hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM);
+	hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM);
+
+	hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
+		   HDMI_MC_FLOWCTRL);
+
+	/* enable pixel clock and tmds data path */
+	clkdis = 0x7f;
+	clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
+	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
+
+	clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
+	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
+
+	clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
+	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
+}
+
+/* workaround to clear the overflow condition */
+static void hdmi_clear_overflow(struct dw_hdmi *hdmi)
+{
+	uint val, count;
+
+	/* tmds software reset */
+	hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
+
+	val = hdmi_read(hdmi, HDMI_FC_INVIDCONF);
+
+	for (count = 0; count < 4; count++)
+		hdmi_write(hdmi, val, HDMI_FC_INVIDCONF);
+}
+
+static void hdmi_audio_set_format(struct dw_hdmi *hdmi)
+{
+	hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
+		   HDMI_AUD_CONF0);
+
+
+	hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
+		   HDMI_AUD_CONF1_I2S_WIDTH_16BIT, HDMI_AUD_CONF1);
+
+	hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2);
+}
+
+static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi)
+{
+	hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, HDMI_MC_SWRSTZ);
+	hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, HDMI_AUD_CONF0);
+
+	hdmi_write(hdmi, 0x00, HDMI_AUD_INT);
+	hdmi_write(hdmi, 0x00, HDMI_AUD_INT1);
+}
+
+static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi)
+{
+	uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD;
+
+	return !!val;
+}
+
+static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
+{
+	u32 val;
+	ulong start;
+
+	start = get_timer(0);
+	do {
+		val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0);
+		if (val & 0x2) {
+			hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0);
+			return 0;
+		}
+
+		udelay(100);
+	} while (get_timer(start) < msec);
+
+	return 1;
+}
+
+static void hdmi_ddc_reset(struct dw_hdmi *hdmi)
+{
+	hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0);
+}
+
+static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff)
+{
+	int shift = (block % 2) * 0x80;
+	int edid_read_err = 0;
+	u32 trytime = 5;
+	u32 n;
+
+	/* set ddc i2c clk which devided from ddc_clk to 100khz */
+	hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
+	hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
+	hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE,
+		 HDMI_I2CM_DIV_STD_MODE);
+
+	hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE);
+	hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR);
+	hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR);
+
+	while (trytime--) {
+		edid_read_err = 0;
+
+		for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) {
+			hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS);
+
+			if (block == 0)
+				hdmi_write(hdmi, HDMI_I2CM_OP_RD8,
+					   HDMI_I2CM_OPERATION);
+			else
+				hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT,
+					   HDMI_I2CM_OPERATION);
+
+			if (hdmi_ddc_wait_i2c_done(hdmi, 10)) {
+				hdmi_ddc_reset(hdmi);
+				edid_read_err = 1;
+				break;
+			}
+
+			buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI);
+		}
+
+		if (!edid_read_err)
+			break;
+	}
+
+	return edid_read_err;
+}
+
+static const u8 pre_buf[] = {
+	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
+	0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
+	0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
+	0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
+	0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
+	0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
+	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
+	0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
+	0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
+	0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
+	0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
+	0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
+	0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
+	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
+	0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
+	0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
+	0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
+	0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
+	0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
+	0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
+	0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
+	0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
+	0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
+	0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
+	0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
+	0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
+	0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
+	0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
+	0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
+	0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
+};
+
+int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
+{
+	int i, ret;
+
+	/* hdmi phy spec says to do the phy initialization sequence twice */
+	for (i = 0; i < 2; i++) {
+		hdmi_phy_sel_data_en_pol(hdmi, 1);
+		hdmi_phy_sel_interface_control(hdmi, 0);
+		hdmi_phy_enable_tmds(hdmi, 0);
+		hdmi_phy_enable_power(hdmi, 0);
+
+		ret = hdmi_phy_configure(hdmi, mpixelclock);
+		if (ret) {
+			debug("hdmi phy config failure %d\n", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
+{
+	ulong start;
+
+	start = get_timer(0);
+	do {
+		if (hdmi_get_plug_in_status(hdmi))
+			return 0;
+		udelay(100);
+	} while (get_timer(start) < 300);
+
+	return -1;
+}
+
+void dw_hdmi_phy_init(struct dw_hdmi *hdmi)
+{
+	/* enable phy i2cm done irq */
+	hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
+		   HDMI_PHY_I2CM_INT_ADDR);
+
+	/* enable phy i2cm nack & arbitration error irq */
+	hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
+		   HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
+		   HDMI_PHY_I2CM_CTLINT_ADDR);
+
+	/* enable cable hot plug irq */
+	hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
+
+	/* clear hotplug interrupts */
+	hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+}
+
+int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size)
+{
+	u32 edid_size = HDMI_EDID_BLOCK_SIZE;
+	int ret;
+
+	if (0) {
+		edid_size = sizeof(pre_buf);
+		memcpy(buf, pre_buf, edid_size);
+	} else {
+		ret = hdmi_read_edid(hdmi, 0, buf);
+		if (ret) {
+			debug("failed to read edid.\n");
+			return -1;
+		}
+
+		if (buf[0x7e] != 0) {
+			hdmi_read_edid(hdmi, 1, buf + HDMI_EDID_BLOCK_SIZE);
+			edid_size += HDMI_EDID_BLOCK_SIZE;
+		}
+	}
+
+	return edid_size;
+}
+
+int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
+{
+	int ret;
+
+	debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
+	      edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
+
+	hdmi_av_composer(hdmi, edid);
+
+	ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
+	if (ret)
+		return ret;
+
+	hdmi_enable_video_path(hdmi);
+
+	hdmi_audio_fifo_reset(hdmi);
+	hdmi_audio_set_format(hdmi);
+	hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ);
+
+	hdmi_video_packetize(hdmi);
+	hdmi_video_sample(hdmi);
+
+	hdmi_clear_overflow(hdmi);
+
+	return 0;
+}
+
+void dw_hdmi_init(struct dw_hdmi *hdmi)
+{
+	uint ih_mute;
+
+	/*
+	 * boot up defaults are:
+	 * hdmi_ih_mute   = 0x03 (disabled)
+	 * hdmi_ih_mute_* = 0x00 (enabled)
+	 *
+	 * disable top level interrupt bits in hdmi block
+	 */
+	ih_mute = /*hdmi_read(hdmi, HDMI_IH_MUTE) |*/
+		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
+		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
+
+	hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE);
+
+	/* enable i2c master done irq */
+	hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT);
+
+	/* enable i2c client nack % arbitration error irq */
+	hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT);
+}
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 7962f8611e..755350b934 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o
+obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index c8608db23c..db07588302 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -9,6 +9,7 @@
 #include <clk.h>
 #include <display.h>
 #include <dm.h>
+#include <dw_hdmi.h>
 #include <edid.h>
 #include <regmap.h>
 #include <syscon.h>
@@ -16,73 +17,13 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/grf_rk3288.h>
-#include <asm/arch/hdmi_rk3288.h>
 #include <power/regulator.h>
 
-struct tmds_n_cts {
-	u32 tmds;
-	u32 cts;
-	u32 n;
-};
-
 struct rk_hdmi_priv {
-	struct rk3288_hdmi *regs;
+	struct dw_hdmi hdmi;
 	struct rk3288_grf *grf;
 };
 
-static const struct tmds_n_cts n_cts_table[] = {
-	{
-		.tmds = 25175000, .n = 6144, .cts = 25175,
-	}, {
-		.tmds = 25200000, .n = 6144, .cts = 25200,
-	}, {
-		.tmds = 27000000, .n = 6144, .cts = 27000,
-	}, {
-		.tmds = 27027000, .n = 6144, .cts = 27027,
-	}, {
-		.tmds = 40000000, .n = 6144, .cts = 40000,
-	}, {
-		.tmds = 54000000, .n = 6144, .cts = 54000,
-	}, {
-		.tmds = 54054000, .n = 6144, .cts = 54054,
-	}, {
-		.tmds = 65000000, .n = 6144, .cts = 65000,
-	}, {
-		.tmds = 74176000, .n = 11648, .cts = 140625,
-	}, {
-		.tmds = 74250000, .n = 6144, .cts = 74250,
-	}, {
-		.tmds = 83500000, .n = 6144, .cts = 83500,
-	}, {
-		.tmds = 106500000, .n = 6144, .cts = 106500,
-	}, {
-		.tmds = 108000000, .n = 6144, .cts = 108000,
-	}, {
-		.tmds = 148352000, .n = 5824, .cts = 140625,
-	}, {
-		.tmds = 148500000, .n = 6144, .cts = 148500,
-	}, {
-		.tmds = 297000000, .n = 5120, .cts = 247500,
-	}
-};
-
-struct hdmi_mpll_config {
-	u64 mpixelclock;
-	/* Mode of Operation and PLL Dividers Control Register */
-	u32 cpce;
-	/* PLL Gmp Control Register */
-	u32 gmp;
-	/* PLL Current COntrol Register */
-	u32 curr;
-};
-
-struct hdmi_phy_config {
-	u64 mpixelclock;
-	u32 sym_ctr;    /* clock symbol and transmitter control */
-	u32 term;       /* transmission termination value */
-	u32 vlev_ctr;   /* voltage level control */
-};
-
 static const struct hdmi_phy_config rockchip_phy_config[] = {
 	{
 		.mpixelclock = 74250000,
@@ -124,693 +65,41 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
 	}
 };
 
-static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts)
-{
-	uint cts3;
-	uint n3;
-
-	/* first set ncts_atomic_write (if present) */
-	n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
-	writel(n3, &regs->aud_n3);
-
-	/* set cts_manual (if present) */
-	cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
-
-	cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
-	cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
-
-	/* write cts values; cts3 must be written first */
-	writel(cts3, &regs->aud_cts3);
-	writel((cts >> 8) & 0xff, &regs->aud_cts2);
-	writel(cts & 0xff, &regs->aud_cts1);
-
-	/* write n values; n1 must be written last */
-	n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
-	writel(n3, &regs->aud_n3);
-	writel((n >> 8) & 0xff, &regs->aud_n2);
-	writel(n & 0xff, &regs->aud_n1);
-
-	writel(HDMI_AUD_INPUTCLKFS_128, &regs->aud_inputclkfs);
-}
-
-static int hdmi_lookup_n_cts(u32 pixel_clk)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
-		if (pixel_clk <= n_cts_table[i].tmds)
-			break;
-
-	if (i >= ARRAY_SIZE(n_cts_table))
-		return -1;
-
-	return i;
-}
-
-static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 pixel_clk)
-{
-	u32 clk_n, clk_cts;
-	int index;
-
-	index = hdmi_lookup_n_cts(pixel_clk);
-	if (index == -1) {
-		debug("audio not supported for pixel clk %d\n", pixel_clk);
-		return;
-	}
-
-	clk_n = n_cts_table[index].n;
-	clk_cts = n_cts_table[index].cts;
-	hdmi_set_clock_regenerator(regs, clk_n, clk_cts);
-}
-
-/*
- * this submodule is responsible for the video data synchronization.
- * for example, for rgb 4:4:4 input, the data map is defined as
- *			pin{47~40} <==> r[7:0]
- *			pin{31~24} <==> g[7:0]
- *			pin{15~8}  <==> b[7:0]
- */
-static void hdmi_video_sample(struct rk3288_hdmi *regs)
-{
-	u32 color_format = 0x01;
-	uint val;
-
-	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
-	      ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
-	      HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
-
-	writel(val, &regs->tx_invid0);
-
-	/* enable tx stuffing: when de is inactive, fix the output data to 0 */
-	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
-	      HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
-	      HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
-	writel(val, &regs->tx_instuffing);
-	writel(0x0, &regs->tx_gydata0);
-	writel(0x0, &regs->tx_gydata1);
-	writel(0x0, &regs->tx_rcrdata0);
-	writel(0x0, &regs->tx_rcrdata1);
-	writel(0x0, &regs->tx_bcbdata0);
-	writel(0x0, &regs->tx_bcbdata1);
-}
-
-static void hdmi_video_packetize(struct rk3288_hdmi *regs)
-{
-	u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
-	u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
-	u32 color_depth = 0;
-	uint val, vp_conf;
-
-	/* set the packetizer registers */
-	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
-		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
-		((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
-		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
-	writel(val, &regs->vp_pr_cd);
-
-	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK,
-			HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
-
-	/* data from pixel repeater block */
-	vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
-		  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
-
-	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK |
-			HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
-
-	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
-			1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
-
-	writel(remap_size, &regs->vp_remap);
-
-	vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
-		  HDMI_VP_CONF_PP_EN_DISABLE |
-		  HDMI_VP_CONF_YCC422_EN_DISABLE;
-
-	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK |
-			HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
-			vp_conf);
-
-	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK |
-			HDMI_VP_STUFF_YCC422_STUFFING_MASK,
-			HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
-			HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
-
-	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
-			output_select);
-}
-
-static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit)
-{
-	clrsetbits_le32(&regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
-			bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
-}
-
-static int hdmi_phy_wait_i2c_done(struct rk3288_hdmi *regs, u32 msec)
-{
-	ulong start;
-	u32 val;
-
-	start = get_timer(0);
-	do {
-		val = readl(&regs->ih_i2cmphy_stat0);
-		if (val & 0x3) {
-			writel(val, &regs->ih_i2cmphy_stat0);
-			return 0;
-		}
-
-		udelay(100);
-	} while (get_timer(start) < msec);
-
-	return 1;
-}
-
-static void hdmi_phy_i2c_write(struct rk3288_hdmi *regs, uint data, uint addr)
-{
-	writel(0xff, &regs->ih_i2cmphy_stat0);
-	writel(addr, &regs->phy_i2cm_address_addr);
-	writel((u8)(data >> 8), &regs->phy_i2cm_datao_1_addr);
-	writel((u8)(data >> 0), &regs->phy_i2cm_datao_0_addr);
-	writel(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
-	       &regs->phy_i2cm_operation_addr);
-
-	hdmi_phy_wait_i2c_done(regs, 1000);
-}
-
-static void hdmi_phy_enable_power(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK,
-			enable << HDMI_PHY_CONF0_PDZ_OFFSET);
-}
-
-static void hdmi_phy_enable_tmds(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK,
-			enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
-}
-
-static void hdmi_phy_enable_spare(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK,
-			enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
-}
-
-static void hdmi_phy_gen2_pddq(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
-			enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
-}
-
-static void hdmi_phy_gen2_txpwron(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0,
-			HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
-			enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
-}
-
-static void hdmi_phy_sel_data_en_pol(struct rk3288_hdmi *regs, uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0,
-			HDMI_PHY_CONF0_SELDATAENPOL_MASK,
-			enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
-}
-
-static void hdmi_phy_sel_interface_control(struct rk3288_hdmi *regs,
-					   uint enable)
-{
-	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK,
-			enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
-}
-
-static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock)
-{
-	ulong start;
-	uint i, val;
-
-	writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
-	       &regs->mc_flowctrl);
-
-	/* gen2 tx power off */
-	hdmi_phy_gen2_txpwron(regs, 0);
-
-	/* gen2 pddq */
-	hdmi_phy_gen2_pddq(regs, 1);
-
-	/* phy reset */
-	writel(HDMI_MC_PHYRSTZ_DEASSERT, &regs->mc_phyrstz);
-	writel(HDMI_MC_PHYRSTZ_ASSERT, &regs->mc_phyrstz);
-	writel(HDMI_MC_HEACPHY_RST_ASSERT, &regs->mc_heacphy_rst);
-
-	hdmi_phy_test_clear(regs, 1);
-	writel(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, &regs->phy_i2cm_slave_addr);
-	hdmi_phy_test_clear(regs, 0);
-
-	/* pll/mpll cfg - always match on final entry */
-	for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++)
-		if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock)
-			break;
-
-	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
-	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
-	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL);
-
-	hdmi_phy_i2c_write(regs, 0x0000, PHY_PLLPHBYCTRL);
-	hdmi_phy_i2c_write(regs, 0x0006, PHY_PLLCLKBISTPHASE);
-
-	for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++)
-		if (mpixelclock <= rockchip_phy_config[i].mpixelclock)
-			break;
-
-	/*
-	 * resistance term 133ohm cfg
-	 * preemp cgf 0.00
-	 * tx/ck lvl 10
-	 */
-	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].term, PHY_TXTERM);
-	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].sym_ctr,
-			   PHY_CKSYMTXCTRL);
-	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL);
-
-	/* remove clk term */
-	hdmi_phy_i2c_write(regs, 0x8000, PHY_CKCALCTRL);
-
-	hdmi_phy_enable_power(regs, 1);
-
-	/* toggle tmds enable */
-	hdmi_phy_enable_tmds(regs, 0);
-	hdmi_phy_enable_tmds(regs, 1);
-
-	/* gen2 tx power on */
-	hdmi_phy_gen2_txpwron(regs, 1);
-	hdmi_phy_gen2_pddq(regs, 0);
-
-	hdmi_phy_enable_spare(regs, 1);
-
-	/* wait for phy pll lock */
-	start = get_timer(0);
-	do {
-		val = readl(&regs->phy_stat0);
-		if (!(val & HDMI_PHY_TX_PHY_LOCK))
-			return 0;
-
-		udelay(100);
-	} while (get_timer(start) < 5);
-
-	return -1;
-}
-
-static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock)
-{
-	int i, ret;
-
-	/* hdmi phy spec says to do the phy initialization sequence twice */
-	for (i = 0; i < 2; i++) {
-		hdmi_phy_sel_data_en_pol(regs, 1);
-		hdmi_phy_sel_interface_control(regs, 0);
-		hdmi_phy_enable_tmds(regs, 0);
-		hdmi_phy_enable_power(regs, 0);
-
-		ret = hdmi_phy_configure(regs, mpixelclock);
-		if (ret) {
-			debug("hdmi phy config failure %d\n", ret);
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-static void hdmi_av_composer(struct rk3288_hdmi *regs,
-			     const struct display_timing *edid)
-{
-	bool mdataenablepolarity = true;
-	uint inv_val;
-	uint hbl;
-	uint vbl;
-
-	hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
-			edid->hsync_len.typ;
-	vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
-			edid->vsync_len.typ;
-
-	/* set up hdmi_fc_invidconf */
-	inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
-
-	inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
-		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
-		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
-
-	inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
-		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
-		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
-
-	inv_val |= (mdataenablepolarity ?
-		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
-		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
-
-	/*
-	 * TODO(sjg at chromium.org>: Need to check for HDMI / DVI
-	 * inv_val |= (edid->hdmi_monitor_detected ?
-	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
-	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
-	 */
-	inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
-
-	inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
-
-	inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
-
-	writel(inv_val, &regs->fc_invidconf);
-
-	/* set up horizontal active pixel width */
-	writel(edid->hactive.typ >> 8, &regs->fc_inhactv1);
-	writel(edid->hactive.typ, &regs->fc_inhactv0);
-
-	/* set up vertical active lines */
-	writel(edid->vactive.typ >> 8, &regs->fc_invactv1);
-	writel(edid->vactive.typ, &regs->fc_invactv0);
-
-	/* set up horizontal blanking pixel region width */
-	writel(hbl >> 8, &regs->fc_inhblank1);
-	writel(hbl, &regs->fc_inhblank0);
-
-	/* set up vertical blanking pixel region width */
-	writel(vbl, &regs->fc_invblank);
-
-	/* set up hsync active edge delay width (in pixel clks) */
-	writel(edid->hfront_porch.typ >> 8, &regs->fc_hsyncindelay1);
-	writel(edid->hfront_porch.typ, &regs->fc_hsyncindelay0);
-
-	/* set up vsync active edge delay (in lines) */
-	writel(edid->vfront_porch.typ, &regs->fc_vsyncindelay);
-
-	/* set up hsync active pulse width (in pixel clks) */
-	writel(edid->hsync_len.typ >> 8, &regs->fc_hsyncinwidth1);
-	writel(edid->hsync_len.typ, &regs->fc_hsyncinwidth0);
-
-	/* set up vsync active edge delay (in lines) */
-	writel(edid->vsync_len.typ, &regs->fc_vsyncinwidth);
-}
-
-/* hdmi initialization step b.4 */
-static void hdmi_enable_video_path(struct rk3288_hdmi *regs)
-{
-	uint clkdis;
-
-	/* control period minimum duration */
-	writel(12, &regs->fc_ctrldur);
-	writel(32, &regs->fc_exctrldur);
-	writel(1, &regs->fc_exctrlspac);
-
-	/* set to fill tmds data channels */
-	writel(0x0b, &regs->fc_ch0pream);
-	writel(0x16, &regs->fc_ch1pream);
-	writel(0x21, &regs->fc_ch2pream);
-
-	/* enable pixel clock and tmds data path */
-	clkdis = 0x7f;
-	clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
-	writel(clkdis, &regs->mc_clkdis);
-
-	clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
-	writel(clkdis, &regs->mc_clkdis);
-
-	clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
-	writel(clkdis, &regs->mc_clkdis);
-}
-
-/* workaround to clear the overflow condition */
-static void hdmi_clear_overflow(struct rk3288_hdmi *regs)
-{
-	uint val, count;
-
-	/* tmds software reset */
-	writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &regs->mc_swrstz);
-
-	val = readl(&regs->fc_invidconf);
-
-	for (count = 0; count < 4; count++)
-		writel(val, &regs->fc_invidconf);
-}
-
-static void hdmi_audio_set_format(struct rk3288_hdmi *regs)
-{
-	writel(HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
-	       &regs->aud_conf0);
-
-
-	writel(HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
-	       HDMI_AUD_CONF1_I2S_WIDTH_16BIT, &regs->aud_conf1);
-
-	writel(0x00, &regs->aud_conf2);
-}
-
-static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs)
-{
-	writel((u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, &regs->mc_swrstz);
-	writel(HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, &regs->aud_conf0);
-
-	writel(0x00, &regs->aud_int);
-	writel(0x00, &regs->aud_int1);
-}
-
-static void hdmi_init_interrupt(struct rk3288_hdmi *regs)
-{
-	uint ih_mute;
-
-	/*
-	 * boot up defaults are:
-	 * hdmi_ih_mute   = 0x03 (disabled)
-	 * hdmi_ih_mute_* = 0x00 (enabled)
-	 *
-	 * disable top level interrupt bits in hdmi block
-	 */
-	ih_mute = readl(&regs->ih_mute) |
-		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
-		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
-
-	writel(ih_mute, &regs->ih_mute);
-
-	/* enable i2c master done irq */
-	writel(~0x04, &regs->i2cm_int);
-
-	/* enable i2c client nack % arbitration error irq */
-	writel(~0x44, &regs->i2cm_ctlint);
-
-	/* enable phy i2cm done irq */
-	writel(HDMI_PHY_I2CM_INT_ADDR_DONE_POL, &regs->phy_i2cm_int_addr);
-
-	/* enable phy i2cm nack & arbitration error irq */
-	writel(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
-		HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
-		&regs->phy_i2cm_ctlint_addr);
-
-	/* enable cable hot plug irq */
-	writel((u8)~HDMI_PHY_HPD, &regs->phy_mask0);
-
-	/* clear hotplug interrupts */
-	writel(HDMI_IH_PHY_STAT0_HPD, &regs->ih_phy_stat0);
-}
-
-static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
-{
-	uint val = readl(&regs->phy_stat0) & HDMI_PHY_HPD;
-
-	return !!val;
-}
-
-static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
-{
-	ulong start;
-
-	start = get_timer(0);
-	do {
-		if (hdmi_get_plug_in_status(regs))
-			return 0;
-		udelay(100);
-	} while (get_timer(start) < 300);
-
-	return -1;
-}
-
-static int hdmi_ddc_wait_i2c_done(struct rk3288_hdmi *regs, int msec)
-{
-	u32 val;
-	ulong start;
-
-	start = get_timer(0);
-	do {
-		val = readl(&regs->ih_i2cm_stat0);
-		if (val & 0x2) {
-			writel(val, &regs->ih_i2cm_stat0);
-			return 0;
-		}
-
-		udelay(100);
-	} while (get_timer(start) < msec);
-
-	return 1;
-}
-
-static void hdmi_ddc_reset(struct rk3288_hdmi *regs)
-{
-	clrbits_le32(&regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ);
-}
-
-static int hdmi_read_edid(struct rk3288_hdmi *regs, int block, u8 *buff)
-{
-	int shift = (block % 2) * 0x80;
-	int edid_read_err = 0;
-	u32 trytime = 5;
-	u32 n, j, val;
-
-	/* set ddc i2c clk which devided from ddc_clk to 100khz */
-	writel(0x7a, &regs->i2cm_ss_scl_hcnt_0_addr);
-	writel(0x8d, &regs->i2cm_ss_scl_lcnt_0_addr);
-
-	/*
-	 * TODO(sjg at chromium.org): The above values don't work - these ones
-	 * work better, but generate lots of errors in the data.
-	 */
-	writel(0x0d, &regs->i2cm_ss_scl_hcnt_0_addr);
-	writel(0x0d, &regs->i2cm_ss_scl_lcnt_0_addr);
-	clrsetbits_le32(&regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
-			HDMI_I2CM_DIV_STD_MODE);
-
-	writel(HDMI_I2CM_SLAVE_DDC_ADDR, &regs->i2cm_slave);
-	writel(HDMI_I2CM_SEGADDR_DDC, &regs->i2cm_segaddr);
-	writel(block >> 1, &regs->i2cm_segptr);
-
-	while (trytime--) {
-		edid_read_err = 0;
-
-		for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
-			writel(shift + 8 * n, &regs->i2c_address);
-
-			if (block == 0)
-				clrsetbits_le32(&regs->i2cm_operation,
-						HDMI_I2CM_OPT_RD8,
-						HDMI_I2CM_OPT_RD8);
-			else
-				clrsetbits_le32(&regs->i2cm_operation,
-						HDMI_I2CM_OPT_RD8_EXT,
-						HDMI_I2CM_OPT_RD8_EXT);
-
-			if (hdmi_ddc_wait_i2c_done(regs, 10)) {
-				hdmi_ddc_reset(regs);
-				edid_read_err = 1;
-				break;
-			}
-
-			for (j = 0; j < 8; j++) {
-				val = readl(&regs->i2cm_buf0 + j);
-				buff[8 * n + j] = val;
-			}
-		}
-
-		if (!edid_read_err)
-			break;
-	}
-
-	return edid_read_err;
-}
-
-static const u8 pre_buf[] = {
-	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
-	0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
-	0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
-	0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
-	0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
-	0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
-	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
-	0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
-	0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
-	0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
-	0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
-	0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
-	0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
-	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
-	0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
-	0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
-	0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
-	0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
-	0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
-	0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
-	0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
-	0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
-	0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
-	0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
-	0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
-	0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
-	0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
-	0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
-	0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
-	0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
-};
-
 static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 {
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
-	u32 edid_size = HDMI_EDID_BLOCK_SIZE;
-	int ret;
-
-	if (0) {
-		edid_size = sizeof(pre_buf);
-		memcpy(buf, pre_buf, edid_size);
-	} else {
-		ret = hdmi_read_edid(priv->regs, 0, buf);
-		if (ret) {
-			debug("failed to read edid.\n");
-			return -1;
-		}
 
-		if (buf[0x7e] != 0) {
-			hdmi_read_edid(priv->regs, 1,
-				       buf + HDMI_EDID_BLOCK_SIZE);
-			edid_size += HDMI_EDID_BLOCK_SIZE;
-		}
-	}
-
-	return edid_size;
+	return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
 }
 
 static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
 			  const struct display_timing *edid)
 {
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
-	struct rk3288_hdmi *regs = priv->regs;
-	int ret;
-
-	debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
-	      edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
 
-	hdmi_av_composer(regs, edid);
-
-	ret = hdmi_phy_init(regs, edid->pixelclock.typ);
-	if (ret)
-		return ret;
-
-	hdmi_enable_video_path(regs);
-
-	hdmi_audio_fifo_reset(regs);
-	hdmi_audio_set_format(regs);
-	hdmi_audio_set_samplerate(regs, edid->pixelclock.typ);
-
-	hdmi_video_packetize(regs);
-	hdmi_video_sample(regs);
-
-	hdmi_clear_overflow(regs);
-
-	return 0;
+	return dw_hdmi_enable(&priv->hdmi, edid);
 }
 
 static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
 {
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
+	struct dw_hdmi *hdmi = &priv->hdmi;
+
+	hdmi->ioaddr = (ulong)dev_get_addr(dev);
+	hdmi->mpll_cfg = rockchip_mpll_cfg;
+	hdmi->phy_cfg = rockchip_phy_config;
+	hdmi->i2c_clk_high = 0x7a;
+	hdmi->i2c_clk_low = 0x8d;
+
+	/*
+	 * TODO(sjg at chromium.org): The above values don't work - these ones
+	 * work better, but generate lots of errors in the data.
+	 */
+	hdmi->i2c_clk_high = 0x0d;
+	hdmi->i2c_clk_low = 0x0d;
+	hdmi->reg_io_width = 4;
+	hdmi->phy_set = dw_hdmi_phy_cfg;
 
-	priv->regs = (struct rk3288_hdmi *)dev_get_addr(dev);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 
 	return 0;
@@ -820,6 +109,7 @@ static int rk_hdmi_probe(struct udevice *dev)
 {
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
+	struct dw_hdmi *hdmi = &priv->hdmi;
 	struct udevice *reg;
 	struct clk clk;
 	int ret;
@@ -863,13 +153,14 @@ static int rk_hdmi_probe(struct udevice *dev)
 	rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
 		     (vop_id == 1) ? (1 << 4) : 0);
 
-	ret = hdmi_wait_for_hpd(priv->regs);
+	ret = dw_hdmi_phy_wait_for_hpd(hdmi);
 	if (ret < 0) {
 		debug("hdmi can not get hpd signal\n");
 		return -1;
 	}
 
-	hdmi_init_interrupt(priv->regs);
+	dw_hdmi_init(hdmi);
+	dw_hdmi_phy_init(hdmi);
 
 	return 0;
 }
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index aeecb5815b..bc02f800dc 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -20,7 +20,6 @@
 #include <asm/arch/cru_rk3288.h>
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/edp_rk3288.h>
-#include <asm/arch/hdmi_rk3288.h>
 #include <asm/arch/vop_rk3288.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
new file mode 100644
index 0000000000..902abd4d44
--- /dev/null
+++ b/include/dw_hdmi.h
@@ -0,0 +1,486 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DW_HDMI_H
+#define _DW_HDMI_H
+
+#include <edid.h>
+
+#define HDMI_EDID_BLOCK_SIZE            128
+
+/* Identification Registers */
+#define HDMI_DESIGN_ID                          0x0000
+#define HDMI_REVISION_ID                        0x0001
+#define HDMI_PRODUCT_ID0                        0x0002
+#define HDMI_PRODUCT_ID1                        0x0003
+#define HDMI_CONFIG0_ID                         0x0004
+#define HDMI_CONFIG1_ID                         0x0005
+#define HDMI_CONFIG2_ID                         0x0006
+#define HDMI_CONFIG3_ID                         0x0007
+
+/* Interrupt Registers */
+#define HDMI_IH_FC_STAT0                        0x0100
+#define HDMI_IH_FC_STAT1                        0x0101
+#define HDMI_IH_FC_STAT2                        0x0102
+#define HDMI_IH_AS_STAT0                        0x0103
+#define HDMI_IH_PHY_STAT0                       0x0104
+#define HDMI_IH_I2CM_STAT0                      0x0105
+#define HDMI_IH_CEC_STAT0                       0x0106
+#define HDMI_IH_VP_STAT0                        0x0107
+#define HDMI_IH_I2CMPHY_STAT0                   0x0108
+#define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
+
+#define HDMI_IH_MUTE_FC_STAT0                   0x0180
+#define HDMI_IH_MUTE_FC_STAT1                   0x0181
+#define HDMI_IH_MUTE_FC_STAT2                   0x0182
+#define HDMI_IH_MUTE_AS_STAT0                   0x0183
+#define HDMI_IH_MUTE_PHY_STAT0                  0x0184
+#define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
+#define HDMI_IH_MUTE_CEC_STAT0                  0x0186
+#define HDMI_IH_MUTE_VP_STAT0                   0x0187
+#define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
+#define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
+#define HDMI_IH_MUTE                            0x01FF
+
+/* Video Sample Registers */
+#define HDMI_TX_INVID0                          0x0200
+#define HDMI_TX_INSTUFFING                      0x0201
+#define HDMI_TX_GYDATA0                         0x0202
+#define HDMI_TX_GYDATA1                         0x0203
+#define HDMI_TX_RCRDATA0                        0x0204
+#define HDMI_TX_RCRDATA1                        0x0205
+#define HDMI_TX_BCBDATA0                        0x0206
+#define HDMI_TX_BCBDATA1                        0x0207
+
+/* Video Packetizer Registers */
+#define HDMI_VP_STATUS                          0x0800
+#define HDMI_VP_PR_CD                           0x0801
+#define HDMI_VP_STUFF                           0x0802
+#define HDMI_VP_REMAP                           0x0803
+#define HDMI_VP_CONF                            0x0804
+#define HDMI_VP_STAT                            0x0805
+#define HDMI_VP_INT                             0x0806
+#define HDMI_VP_MASK                            0x0807
+#define HDMI_VP_POL                             0x0808
+
+/* Frame Composer Registers */
+#define HDMI_FC_INVIDCONF                       0x1000
+#define HDMI_FC_INHACTV0                        0x1001
+#define HDMI_FC_INHACTV1                        0x1002
+#define HDMI_FC_INHBLANK0                       0x1003
+#define HDMI_FC_INHBLANK1                       0x1004
+#define HDMI_FC_INVACTV0                        0x1005
+#define HDMI_FC_INVACTV1                        0x1006
+#define HDMI_FC_INVBLANK                        0x1007
+#define HDMI_FC_HSYNCINDELAY0                   0x1008
+#define HDMI_FC_HSYNCINDELAY1                   0x1009
+#define HDMI_FC_HSYNCINWIDTH0                   0x100A
+#define HDMI_FC_HSYNCINWIDTH1                   0x100B
+#define HDMI_FC_VSYNCINDELAY                    0x100C
+#define HDMI_FC_VSYNCINWIDTH                    0x100D
+#define HDMI_FC_INFREQ0                         0x100E
+#define HDMI_FC_INFREQ1                         0x100F
+#define HDMI_FC_INFREQ2                         0x1010
+#define HDMI_FC_CTRLDUR                         0x1011
+#define HDMI_FC_EXCTRLDUR                       0x1012
+#define HDMI_FC_EXCTRLSPAC                      0x1013
+#define HDMI_FC_CH0PREAM                        0x1014
+#define HDMI_FC_CH1PREAM                        0x1015
+#define HDMI_FC_CH2PREAM                        0x1016
+#define HDMI_FC_AVICONF3                        0x1017
+#define HDMI_FC_GCP                             0x1018
+#define HDMI_FC_AVICONF0                        0x1019
+#define HDMI_FC_AVICONF1                        0x101A
+#define HDMI_FC_AVICONF2                        0x101B
+#define HDMI_FC_AVIVID                          0x101C
+#define HDMI_FC_AVIETB0                         0x101D
+#define HDMI_FC_AVIETB1                         0x101E
+#define HDMI_FC_AVISBB0                         0x101F
+#define HDMI_FC_AVISBB1                         0x1020
+#define HDMI_FC_AVIELB0                         0x1021
+#define HDMI_FC_AVIELB1                         0x1022
+#define HDMI_FC_AVISRB0                         0x1023
+#define HDMI_FC_AVISRB1                         0x1024
+#define HDMI_FC_AUDICONF0                       0x1025
+#define HDMI_FC_AUDICONF1                       0x1026
+#define HDMI_FC_AUDICONF2                       0x1027
+#define HDMI_FC_AUDICONF3                       0x1028
+#define HDMI_FC_VSDIEEEID0                      0x1029
+#define HDMI_FC_VSDSIZE                         0x102A
+
+/* HDMI Source PHY Registers */
+#define HDMI_PHY_CONF0                          0x3000
+#define HDMI_PHY_TST0                           0x3001
+#define HDMI_PHY_TST1                           0x3002
+#define HDMI_PHY_TST2                           0x3003
+#define HDMI_PHY_STAT0                          0x3004
+#define HDMI_PHY_INT0                           0x3005
+#define HDMI_PHY_MASK0                          0x3006
+#define HDMI_PHY_POL0                           0x3007
+
+/* HDMI Master PHY Registers */
+#define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
+#define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
+#define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
+#define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
+#define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
+#define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
+#define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
+#define HDMI_PHY_I2CM_INT_ADDR                  0x3027
+#define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
+#define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
+#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
+
+/* Audio Sampler Registers */
+#define HDMI_AUD_CONF0                          0x3100
+#define HDMI_AUD_CONF1                          0x3101
+#define HDMI_AUD_INT                            0x3102
+#define HDMI_AUD_CONF2                          0x3103
+#define HDMI_AUD_INT1                           0x3104
+#define HDMI_AUD_N1                             0x3200
+#define HDMI_AUD_N2                             0x3201
+#define HDMI_AUD_N3                             0x3202
+#define HDMI_AUD_CTS1                           0x3203
+#define HDMI_AUD_CTS2                           0x3204
+#define HDMI_AUD_CTS3                           0x3205
+#define HDMI_AUD_INPUTCLKFS                     0x3206
+#define HDMI_AUD_SPDIFINT			0x3302
+#define HDMI_AUD_CONF0_HBR                      0x3400
+#define HDMI_AUD_HBR_STATUS                     0x3401
+#define HDMI_AUD_HBR_INT                        0x3402
+#define HDMI_AUD_HBR_POL                        0x3403
+#define HDMI_AUD_HBR_MASK                       0x3404
+
+/* Main Controller Registers */
+#define HDMI_MC_SFRDIV                          0x4000
+#define HDMI_MC_CLKDIS                          0x4001
+#define HDMI_MC_SWRSTZ                          0x4002
+#define HDMI_MC_OPCTRL                          0x4003
+#define HDMI_MC_FLOWCTRL                        0x4004
+#define HDMI_MC_PHYRSTZ                         0x4005
+#define HDMI_MC_LOCKONCLOCK                     0x4006
+#define HDMI_MC_HEACPHY_RST                     0x4007
+
+/* I2C Master Registers (E-DDC) */
+#define HDMI_I2CM_SLAVE                         0x7E00
+#define HDMI_I2CM_ADDRESS                       0x7E01
+#define HDMI_I2CM_DATAO                         0x7E02
+#define HDMI_I2CM_DATAI                         0x7E03
+#define HDMI_I2CM_OPERATION                     0x7E04
+#define HDMI_I2CM_INT                           0x7E05
+#define HDMI_I2CM_CTLINT                        0x7E06
+#define HDMI_I2CM_DIV                           0x7E07
+#define HDMI_I2CM_SEGADDR                       0x7E08
+#define HDMI_I2CM_SOFTRSTZ                      0x7E09
+#define HDMI_I2CM_SEGPTR                        0x7E0A
+#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
+#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
+#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
+#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
+#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
+#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
+#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
+#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
+#define HDMI_I2CM_BUF0                          0x7E20
+
+enum {
+	/* HDMI PHY registers define */
+	PHY_OPMODE_PLLCFG = 0x06,
+	PHY_CKCALCTRL = 0x05,
+	PHY_CKSYMTXCTRL = 0x09,
+	PHY_VLEVCTRL = 0x0e,
+	PHY_PLLCURRCTRL = 0x10,
+	PHY_PLLPHBYCTRL = 0x13,
+	PHY_PLLGMPCTRL = 0x15,
+	PHY_PLLCLKBISTPHASE = 0x17,
+	PHY_TXTERM = 0x19,
+
+	/* ih_phy_stat0 field values */
+	HDMI_IH_PHY_STAT0_HPD = 0x1,
+
+	/* ih_mute field values */
+	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
+	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
+
+	/* tx_invid0 field values */
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
+	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
+	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
+
+	/* tx_instuffing field values */
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
+
+	/* vp_pr_cd field values */
+	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
+	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
+
+	/* vp_stuff field values */
+	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
+	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
+	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
+	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
+	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
+
+	/* vp_conf field values */
+	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
+	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
+	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PR_EN_MASK = 0x10,
+	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
+	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
+	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
+
+	/* vp_remap field values */
+	HDMI_VP_REMAP_YCC422_16BIT = 0x0,
+
+	/* fc_invidconf field values */
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
+	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
+
+
+	/* fc_aviconf0-fc_aviconf3 field values */
+	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
+	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
+	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
+	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
+	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
+	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
+	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
+	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
+
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
+	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
+	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
+	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
+	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
+
+	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
+	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
+	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
+	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
+	HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
+	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
+	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
+	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
+	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
+	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
+	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
+	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
+
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
+	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
+	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+
+	/* fc_gcp field values*/
+	HDMI_FC_GCP_SET_AVMUTE = 0x02,
+	HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
+
+	/* phy_conf0 field values */
+	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
+	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
+	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
+	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
+	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
+	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
+	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
+	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
+	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
+	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
+	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
+	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
+
+	/* phy_tst0 field values */
+	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
+	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
+
+	/* phy_stat0 field values */
+	HDMI_PHY_HPD = 0x02,
+	HDMI_PHY_TX_PHY_LOCK = 0x01,
+
+	/* phy_i2cm_slave_addr field values */
+	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
+
+	/* phy_i2cm_operation_addr field values */
+	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
+
+	/* hdmi_phy_i2cm_int_addr */
+	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
+
+	/* hdmi_phy_i2cm_ctlint_addr */
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
+
+	/* aud_conf0 field values */
+	HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
+	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
+	HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
+	HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
+	HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
+	HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
+
+	/* aud_conf0 field values */
+	HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
+	HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
+
+	/* aud_n3 field values */
+	HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
+	HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
+
+	/* aud_cts3 field values */
+	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
+	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
+	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
+	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
+	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
+	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
+	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
+	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
+
+	/* aud_inputclkfs filed values */
+	HDMI_AUD_INPUTCLKFS_128 = 0x0,
+
+	/* mc_clkdis field values */
+	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
+	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
+	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
+
+	/* mc_swrstz field values */
+	HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
+	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
+
+	/* mc_flowctrl field values */
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
+
+	/* mc_phyrstz field values */
+	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
+	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
+
+	/* mc_heacphy_rst field values */
+	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
+
+	/* i2cm filed values */
+	HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
+	HDMI_I2CM_SEGADDR_DDC = 0x30,
+	HDMI_I2CM_OP_RD8_EXT = 0x2,
+	HDMI_I2CM_OP_RD8 = 0x1,
+	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
+	HDMI_I2CM_DIV_FAST_MODE = 0x8,
+	HDMI_I2CM_DIV_STD_MODE = 0x0,
+	HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
+};
+
+struct hdmi_mpll_config {
+	u64 mpixelclock;
+	/* Mode of Operation and PLL Dividers Control Register */
+	u32 cpce;
+	/* PLL Gmp Control Register */
+	u32 gmp;
+	/* PLL Current Control Register */
+	u32 curr;
+};
+
+struct hdmi_phy_config {
+	u64 mpixelclock;
+	u32 sym_ctr;    /* clock symbol and transmitter control */
+	u32 term;       /* transmission termination value */
+	u32 vlev_ctr;   /* voltage level control */
+};
+
+struct dw_hdmi {
+	ulong ioaddr;
+	const struct hdmi_mpll_config *mpll_cfg;
+	const struct hdmi_phy_config *phy_cfg;
+	u8 i2c_clk_high;
+	u8 i2c_clk_low;
+	u8 reg_io_width;
+
+	int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
+};
+
+int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
+int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
+void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
+
+int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
+int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
+void dw_hdmi_init(struct dw_hdmi *hdmi);
+
+#endif
-- 
2.12.0

[U-Boot] [PATCH 3/8] rockchip: video: Split out HDMI controller code

[Nickey.Yang]

Hi Jernej,


在 2017年03月09日 07:34, Jernej Skrabec 写道:
> Designware HDMI controller and phy are used in other SoCs as well. Split
> out platform independent code.
>
> DW HDMI has 8 bit registers but they can be represented as 32 bit
> registers as well. Add support to select access mode.
>
> EDID reading code use reading by blocks which is not supported by other
> SoCs in general. Make it more general using byte by byte approach, which
> is also used in Linux driver.
>
> Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
> Support custom phys by making controller code independent from phy code.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
I have tested this series of patches in rockchip rk3288 tinker boards.

Tested-by: Nickey Yang <nickey.yang@rock-chips.com>
>   arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 --------------
>   drivers/video/dw_hdmi.c                          | 764 +++++++++++++++++++++++
>   drivers/video/rockchip/Makefile                  |   2 +-
>   drivers/video/rockchip/rk_hdmi.c                 | 757 +---------------------
>   drivers/video/rockchip/rk_vop.c                  |   1 -
>   include/dw_hdmi.h                                | 486 ++++++++++++++
>   6 files changed, 1275 insertions(+), 1191 deletions(-)
>   delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
>   create mode 100644 drivers/video/dw_hdmi.c
>   create mode 100644 include/dw_hdmi.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> deleted file mode 100644
> index 0b51d40882..0000000000
> --- a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> +++ /dev/null
> @@ -1,456 +0,0 @@
> -/*
> - * Copyright (c) 2015 Google, Inc
> - * Copyright 2014 Rockchip Inc.
> - * Copyright (C) 2011 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier:	GPL-2.0+
> - */
> -
> -#ifndef _ASM_ARCH_HDMI_H
> -#define _ASM_ARCH_HDMI_H
> -
> -
> -#define HDMI_EDID_BLOCK_SIZE            128
> -
> -struct rk3288_hdmi {
> -	u32 reserved0[0x100];
> -	u32 ih_fc_stat0;
> -	u32 ih_fc_stat1;
> -	u32 ih_fc_stat2;
> -	u32 ih_as_stat0;
> -	u32 ih_phy_stat0;
> -	u32 ih_i2cm_stat0;
> -	u32 ih_cec_stat0;
> -	u32 ih_vp_stat0;
> -	u32 ih_i2cmphy_stat0;
> -	u32 ih_ahbdmaaud_stat0;
> -	u32 reserved1[0x17f-0x109];
> -	u32 ih_mute_fc_stat0;
> -	u32 ih_mute_fc_stat1;
> -	u32 ih_mute_fc_stat2;
> -	u32 ih_mute_as_stat0;
> -	u32 ih_mute_phy_stat0;
> -	u32 ih_mute_i2cm_stat0;
> -	u32 ih_mute_cec_stat0;
> -	u32 ih_mute_vp_stat0;
> -	u32 ih_mute_i2cmphy_stat0;
> -	u32 ih_mute_ahbdmaaud_stat0;
> -	u32 reserved2[0x1fe - 0x189];
> -	u32 ih_mute;
> -	u32 tx_invid0;
> -	u32 tx_instuffing;
> -	u32 tx_gydata0;
> -	u32 tx_gydata1;
> -	u32 tx_rcrdata0;
> -	u32 tx_rcrdata1;
> -	u32 tx_bcbdata0;
> -	u32 tx_bcbdata1;
> -	u32 reserved3[0x7ff-0x207];
> -	u32 vp_status;
> -	u32 vp_pr_cd;
> -	u32 vp_stuff;
> -	u32 vp_remap;
> -	u32 vp_conf;
> -	u32 vp_stat;
> -	u32 vp_int;
> -	u32 vp_mask;
> -	u32 vp_pol;
> -	u32 reserved4[0xfff-0x808];
> -	u32 fc_invidconf;
> -	u32 fc_inhactv0;
> -	u32 fc_inhactv1;
> -	u32 fc_inhblank0;
> -	u32 fc_inhblank1;
> -	u32 fc_invactv0;
> -	u32 fc_invactv1;
> -	u32 fc_invblank;
> -	u32 fc_hsyncindelay0;
> -	u32 fc_hsyncindelay1;
> -	u32 fc_hsyncinwidth0;
> -	u32 fc_hsyncinwidth1;
> -	u32 fc_vsyncindelay;
> -	u32 fc_vsyncinwidth;
> -	u32 fc_infreq0;
> -	u32 fc_infreq1;
> -	u32 fc_infreq2;
> -	u32 fc_ctrldur;
> -	u32 fc_exctrldur;
> -	u32 fc_exctrlspac;
> -	u32 fc_ch0pream;
> -	u32 fc_ch1pream;
> -	u32 fc_ch2pream;
> -	u32 fc_aviconf3;
> -	u32 fc_gcp;
> -	u32 fc_aviconf0;
> -	u32 fc_aviconf1;
> -	u32 fc_aviconf2;
> -	u32 fc_avivid;
> -	u32 fc_avietb0;
> -	u32 fc_avietb1;
> -	u32 fc_avisbb0;
> -	u32 fc_avisbb1;
> -	u32 fc_avielb0;
> -	u32 fc_avielb1;
> -	u32 fc_avisrb0;
> -	u32 fc_avisrb1;
> -	u32 fc_audiconf0;
> -	u32 fc_audiconf1;
> -	u32 fc_audiconf2;
> -	u32 fc_audiconf3;
> -	u32 fc_vsdieeeid0;
> -	u32 fc_vsdsize;
> -	u32 reserved7[0x2fff-0x102a];
> -	u32 phy_conf0;
> -	u32 phy_tst0;
> -	u32 phy_tst1;
> -	u32 phy_tst2;
> -	u32 phy_stat0;
> -	u32 phy_int0;
> -	u32 phy_mask0;
> -	u32 phy_pol0;
> -	u32 reserved8[0x301f-0x3007];
> -	u32 phy_i2cm_slave_addr;
> -	u32 phy_i2cm_address_addr;
> -	u32 phy_i2cm_datao_1_addr;
> -	u32 phy_i2cm_datao_0_addr;
> -	u32 phy_i2cm_datai_1_addr;
> -	u32 phy_i2cm_datai_0_addr;
> -	u32 phy_i2cm_operation_addr;
> -	u32 phy_i2cm_int_addr;
> -	u32 phy_i2cm_ctlint_addr;
> -	u32 phy_i2cm_div_addr;
> -	u32 phy_i2cm_softrstz_addr;
> -	u32 phy_i2cm_ss_scl_hcnt_1_addr;
> -	u32 phy_i2cm_ss_scl_hcnt_0_addr;
> -	u32 phy_i2cm_ss_scl_lcnt_1_addr;
> -	u32 phy_i2cm_ss_scl_lcnt_0_addr;
> -	u32 phy_i2cm_fs_scl_hcnt_1_addr;
> -	u32 phy_i2cm_fs_scl_hcnt_0_addr;
> -	u32 phy_i2cm_fs_scl_lcnt_1_addr;
> -	u32 phy_i2cm_fs_scl_lcnt_0_addr;
> -	u32 reserved9[0x30ff-0x3032];
> -	u32 aud_conf0;
> -	u32 aud_conf1;
> -	u32 aud_int;
> -	u32 aud_conf2;
> -	u32 aud_int1;
> -	u32 reserved32[0x31ff-0x3104];
> -	u32 aud_n1;
> -	u32 aud_n2;
> -	u32 aud_n3;
> -	u32 aud_cts1;
> -	u32 aud_cts2;
> -	u32 aud_cts3;
> -	u32 aud_inputclkfs;
> -	u32 reserved12[0x3fff-0x3206];
> -	u32 mc_sfrdiv;
> -	u32 mc_clkdis;
> -	u32 mc_swrstz;
> -	u32 mc_opctrl;
> -	u32 mc_flowctrl;
> -	u32 mc_phyrstz;
> -	u32 mc_lockonclock;
> -	u32 mc_heacphy_rst;
> -	u32 reserved13[0x40ff-0x4007];
> -	u32 csc_cfg;
> -	u32 csc_scale;
> -	struct {
> -		u32 msb;
> -		u32 lsb;
> -	} csc_coef[3][4];
> -	u32 reserved17[0x7dff-0x4119];
> -	u32 i2cm_slave;
> -	u32 i2c_address;
> -	u32 i2cm_datao;
> -	u32 i2cm_datai;
> -	u32 i2cm_operation;
> -	u32 i2cm_int;
> -	u32 i2cm_ctlint;
> -	u32 i2cm_div;
> -	u32 i2cm_segaddr;
> -	u32 i2cm_softrstz;
> -	u32 i2cm_segptr;
> -	u32 i2cm_ss_scl_hcnt_1_addr;
> -	u32 i2cm_ss_scl_hcnt_0_addr;
> -	u32 i2cm_ss_scl_lcnt_1_addr;
> -	u32 i2cm_ss_scl_lcnt_0_addr;
> -	u32 i2cm_fs_scl_hcnt_1_addr;
> -	u32 i2cm_fs_scl_hcnt_0_addr;
> -	u32 i2cm_fs_scl_lcnt_1_addr;
> -	u32 i2cm_fs_scl_lcnt_0_addr;
> -	u32 reserved18[0x7e1f-0x7e12];
> -	u32 i2cm_buf0;
> -};
> -check_member(rk3288_hdmi, i2cm_buf0, 0x1f880);
> -
> -enum {
> -	/* HDMI PHY registers define */
> -	PHY_OPMODE_PLLCFG = 0x06,
> -	PHY_CKCALCTRL = 0x05,
> -	PHY_CKSYMTXCTRL = 0x09,
> -	PHY_VLEVCTRL = 0x0e,
> -	PHY_PLLCURRCTRL = 0x10,
> -	PHY_PLLPHBYCTRL = 0x13,
> -	PHY_PLLGMPCTRL = 0x15,
> -	PHY_PLLCLKBISTPHASE = 0x17,
> -	PHY_TXTERM = 0x19,
> -
> -	/* ih_phy_stat0 field values */
> -	HDMI_IH_PHY_STAT0_HPD = 0x1,
> -
> -	/* ih_mute field values */
> -	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
> -	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
> -
> -	/* tx_invid0 field values */
> -	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
> -	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
> -	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
> -
> -	/* tx_instuffing field values */
> -	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
> -	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
> -	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
> -
> -	/* vp_pr_cd field values */
> -	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
> -	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
> -	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
> -	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
> -
> -	/* vp_stuff field values */
> -	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
> -	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
> -	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
> -	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
> -	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
> -	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
> -	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
> -	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
> -
> -	/* vp_conf field values */
> -	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
> -	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
> -	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
> -	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
> -	HDMI_VP_CONF_PR_EN_MASK = 0x10,
> -	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
> -	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
> -	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
> -	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
> -	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
> -	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
> -	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
> -
> -	/* vp_remap field values */
> -	HDMI_VP_REMAP_YCC422_16BIT = 0x0,
> -
> -	/* fc_invidconf field values */
> -	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
> -	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
> -	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
> -	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
> -	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
> -	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
> -	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
> -	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
> -	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
> -	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
> -	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
> -	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
> -	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
> -	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
> -	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
> -	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
> -	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
> -	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
> -	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
> -	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
> -	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
> -
> -
> -	/* fc_aviconf0-fc_aviconf3 field values */
> -	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
> -	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
> -	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
> -	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
> -	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
> -	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
> -	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
> -	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
> -	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
> -	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
> -	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
> -	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
> -	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
> -	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
> -	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
> -	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
> -
> -	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
> -	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
> -	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
> -	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
> -	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
> -	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
> -	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
> -	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
> -	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
> -	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
> -	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
> -	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
> -	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
> -	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
> -
> -	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
> -	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
> -	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
> -	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
> -	HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
> -	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
> -	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
> -	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
> -	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
> -	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
> -	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
> -	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
> -	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
> -	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
> -	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
> -	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
> -	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
> -	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
> -
> -	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
> -	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
> -	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
> -	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
> -	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
> -	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
> -	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
> -	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
> -
> -	/* fc_gcp field values*/
> -	HDMI_FC_GCP_SET_AVMUTE = 0x02,
> -	HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
> -
> -	/* phy_conf0 field values */
> -	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
> -	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
> -	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
> -	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
> -	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
> -	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
> -	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
> -	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
> -	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
> -	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
> -	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
> -	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
> -	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
> -	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
> -
> -	/* phy_tst0 field values */
> -	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
> -	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
> -
> -	/* phy_stat0 field values */
> -	HDMI_PHY_HPD = 0x02,
> -	HDMI_PHY_TX_PHY_LOCK = 0x01,
> -
> -	/* phy_i2cm_slave_addr field values */
> -	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
> -
> -	/* phy_i2cm_operation_addr field values */
> -	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
> -
> -	/* hdmi_phy_i2cm_int_addr */
> -	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
> -
> -	/* hdmi_phy_i2cm_ctlint_addr */
> -	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
> -	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
> -
> -	/* aud_conf0 field values */
> -	HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
> -	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
> -	HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
> -	HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
> -	HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
> -	HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
> -
> -	/* aud_conf0 field values */
> -	HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
> -	HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
> -
> -	/* aud_n3 field values */
> -	HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
> -	HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
> -
> -	/* aud_cts3 field values */
> -	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
> -	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
> -	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
> -	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
> -	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
> -	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
> -	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
> -	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
> -	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
> -	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
> -
> -	/* aud_inputclkfs filed values */
> -	HDMI_AUD_INPUTCLKFS_128 = 0x0,
> -
> -	/* mc_clkdis field values */
> -	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
> -	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
> -	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
> -
> -	/* mc_swrstz field values */
> -	HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
> -	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
> -
> -	/* mc_flowctrl field values */
> -	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
> -	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
> -
> -	/* mc_phyrstz field values */
> -	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
> -	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
> -
> -	/* mc_heacphy_rst field values */
> -	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
> -
> -	/* csc_cfg field values */
> -	HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
> -
> -	/* csc_scale field values */
> -	HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0,
> -	HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
> -	HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
> -	HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
> -	HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
> -	HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
> -
> -	/* i2cm filed values */
> -	HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
> -	HDMI_I2CM_SEGADDR_DDC = 0x30,
> -	HDMI_I2CM_OPT_RD8_EXT = 0x8,
> -	HDMI_I2CM_OPT_RD8 = 0x4,
> -	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
> -	HDMI_I2CM_DIV_FAST_MODE = 0x8,
> -	HDMI_I2CM_DIV_STD_MODE = 0x0,
> -	HDMI_I2CM_SOFTRSTZ = 0x1,
> -};
> -
> -/*
> -struct display_timing;
> -struct rk3288_grf;
> -
> -int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id);
> -int rk_hdmi_enable(const struct display_timing *edid);
> -int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing *edid);
> -*/
> -
> -#endif
> diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
> new file mode 100644
> index 0000000000..8a53109823
> --- /dev/null
> +++ b/drivers/video/dw_hdmi.c
> @@ -0,0 +1,764 @@
> +/*
> + * Copyright (c) 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + * Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <asm/io.h>
> +#include "dw_hdmi.h"
> +
> +struct tmds_n_cts {
> +	u32 tmds;
> +	u32 cts;
> +	u32 n;
> +};
> +
> +static const struct tmds_n_cts n_cts_table[] = {
> +	{
> +		.tmds = 25175000, .n = 6144, .cts = 25175,
> +	}, {
> +		.tmds = 25200000, .n = 6144, .cts = 25200,
> +	}, {
> +		.tmds = 27000000, .n = 6144, .cts = 27000,
> +	}, {
> +		.tmds = 27027000, .n = 6144, .cts = 27027,
> +	}, {
> +		.tmds = 40000000, .n = 6144, .cts = 40000,
> +	}, {
> +		.tmds = 54000000, .n = 6144, .cts = 54000,
> +	}, {
> +		.tmds = 54054000, .n = 6144, .cts = 54054,
> +	}, {
> +		.tmds = 65000000, .n = 6144, .cts = 65000,
> +	}, {
> +		.tmds = 74176000, .n = 11648, .cts = 140625,
> +	}, {
> +		.tmds = 74250000, .n = 6144, .cts = 74250,
> +	}, {
> +		.tmds = 83500000, .n = 6144, .cts = 83500,
> +	}, {
> +		.tmds = 106500000, .n = 6144, .cts = 106500,
> +	}, {
> +		.tmds = 108000000, .n = 6144, .cts = 108000,
> +	}, {
> +		.tmds = 148352000, .n = 5824, .cts = 140625,
> +	}, {
> +		.tmds = 148500000, .n = 6144, .cts = 148500,
> +	}, {
> +		.tmds = 297000000, .n = 5120, .cts = 247500,
> +	}
> +};
> +
> +static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset)
> +{
> +	switch (hdmi->reg_io_width) {
> +	case 1:
> +		writeb(val, hdmi->ioaddr + offset);
> +		break;
> +	case 4:
> +		writel(val, hdmi->ioaddr + (offset << 2));
> +		break;
> +	default:
> +		debug("reg_io_width has unsupported width!\n");
> +		break;
> +	}
> +}
> +
> +static u8 hdmi_read(struct dw_hdmi *hdmi, int offset)
> +{
> +	switch (hdmi->reg_io_width) {
> +	case 1:
> +		return readb(hdmi->ioaddr + offset);
> +	case 4:
> +		return readl(hdmi->ioaddr + (offset << 2));
> +	default:
> +		debug("reg_io_width has unsupported width!\n");
> +		break;
> +	}
> +
> +	return 0;
> +}
> +
> +static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data)
> +{
> +	u8 val = hdmi_read(hdmi, reg) & ~mask;
> +
> +	val |= data & mask;
> +	hdmi_write(hdmi, val, reg);
> +}
> +
> +static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 cts)
> +{
> +	uint cts3;
> +	uint n3;
> +
> +	/* first set ncts_atomic_write (if present) */
> +	n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
> +	hdmi_write(hdmi, n3, HDMI_AUD_N3);
> +
> +	/* set cts_manual (if present) */
> +	cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
> +
> +	cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
> +	cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
> +
> +	/* write cts values; cts3 must be written first */
> +	hdmi_write(hdmi, cts3, HDMI_AUD_CTS3);
> +	hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
> +	hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1);
> +
> +	/* write n values; n1 must be written last */
> +	n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
> +	hdmi_write(hdmi, n3, HDMI_AUD_N3);
> +	hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
> +	hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3);
> +
> +	hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS);
> +}
> +
> +static int hdmi_lookup_n_cts(u32 pixel_clk)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
> +		if (pixel_clk <= n_cts_table[i].tmds)
> +			break;
> +
> +	if (i >= ARRAY_SIZE(n_cts_table))
> +		return -1;
> +
> +	return i;
> +}
> +
> +static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk)
> +{
> +	u32 clk_n, clk_cts;
> +	int index;
> +
> +	index = hdmi_lookup_n_cts(pixel_clk);
> +	if (index == -1) {
> +		debug("audio not supported for pixel clk %d\n", pixel_clk);
> +		return;
> +	}
> +
> +	clk_n = n_cts_table[index].n;
> +	clk_cts = n_cts_table[index].cts;
> +	hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts);
> +}
> +
> +/*
> + * this submodule is responsible for the video data synchronization.
> + * for example, for rgb 4:4:4 input, the data map is defined as
> + *			pin{47~40} <==> r[7:0]
> + *			pin{31~24} <==> g[7:0]
> + *			pin{15~8}  <==> b[7:0]
> + */
> +static void hdmi_video_sample(struct dw_hdmi *hdmi)
> +{
> +	u32 color_format = 0x01;
> +	uint val;
> +
> +	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
> +	      ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
> +	      HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
> +
> +	hdmi_write(hdmi, val, HDMI_TX_INVID0);
> +
> +	/* enable tx stuffing: when de is inactive, fix the output data to 0 */
> +	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
> +	      HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
> +	      HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
> +	hdmi_write(hdmi, val, HDMI_TX_INSTUFFING);
> +	hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0);
> +	hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1);
> +	hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0);
> +	hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1);
> +	hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0);
> +	hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1);
> +}
> +
> +static void hdmi_video_packetize(struct dw_hdmi *hdmi)
> +{
> +	u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
> +	u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
> +	u32 color_depth = 0;
> +	uint val, vp_conf;
> +
> +	/* set the packetizer registers */
> +	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
> +		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
> +		((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
> +		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
> +	hdmi_write(hdmi, val, HDMI_VP_PR_CD);
> +
> +	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK,
> +		 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
> +
> +	/* data from pixel repeater block */
> +	vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
> +		  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
> +
> +	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK |
> +		 HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
> +
> +	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
> +		 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
> +
> +	hdmi_write(hdmi, remap_size, HDMI_VP_REMAP);
> +
> +	vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
> +		  HDMI_VP_CONF_PP_EN_DISABLE |
> +		  HDMI_VP_CONF_YCC422_EN_DISABLE;
> +
> +	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK |
> +		 HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
> +		 vp_conf);
> +
> +	hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK |
> +		 HDMI_VP_STUFF_YCC422_STUFFING_MASK,
> +		 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
> +		 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
> +
> +	hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
> +		 output_select);
> +}
> +
> +static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit)
> +{
> +	hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK,
> +		 bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
> +}
> +
> +static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec)
> +{
> +	ulong start;
> +	u32 val;
> +
> +	start = get_timer(0);
> +	do {
> +		val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0);
> +		if (val & 0x3) {
> +			hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
> +			return 0;
> +		}
> +
> +		udelay(100);
> +	} while (get_timer(start) < msec);
> +
> +	return 1;
> +}
> +
> +static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint addr)
> +{
> +	hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0);
> +	hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
> +	hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR);
> +	hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR);
> +	hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
> +		   HDMI_PHY_I2CM_OPERATION_ADDR);
> +
> +	hdmi_phy_wait_i2c_done(hdmi, 1000);
> +}
> +
> +static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable)
> +{
> +	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK,
> +		 enable << HDMI_PHY_CONF0_PDZ_OFFSET);
> +}
> +
> +static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable)
> +{
> +	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK,
> +		 enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
> +}
> +
> +static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable)
> +{
> +	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK,
> +		 enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
> +}
> +
> +static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable)
> +{
> +	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
> +		 enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
> +}
> +
> +static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable)
> +{
> +	hdmi_mod(hdmi, HDMI_PHY_CONF0,
> +		 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
> +		 enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
> +}
> +
> +static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable)
> +{
> +	hdmi_mod(hdmi, HDMI_PHY_CONF0,
> +		 HDMI_PHY_CONF0_SELDATAENPOL_MASK,
> +		 enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
> +}
> +
> +static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi,
> +					   uint enable)
> +{
> +	hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK,
> +		 enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
> +}
> +
> +static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock)
> +{
> +	ulong start;
> +	uint i, val;
> +
> +	if (!hdmi->mpll_cfg || !hdmi->phy_cfg)
> +		return -1;
> +
> +	/* gen2 tx power off */
> +	hdmi_phy_gen2_txpwron(hdmi, 0);
> +
> +	/* gen2 pddq */
> +	hdmi_phy_gen2_pddq(hdmi, 1);
> +
> +	/* phy reset */
> +	hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
> +	hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
> +	hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
> +
> +	hdmi_phy_test_clear(hdmi, 1);
> +	hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
> +		   HDMI_PHY_I2CM_SLAVE_ADDR);
> +	hdmi_phy_test_clear(hdmi, 0);
> +
> +	/* pll/mpll cfg - always match on final entry */
> +	for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++)
> +		if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock)
> +			break;
> +
> +	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
> +	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
> +	hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL);
> +
> +	hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL);
> +	hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE);
> +
> +	for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++)
> +		if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock)
> +			break;
> +
> +	/*
> +	 * resistance term 133ohm cfg
> +	 * preemp cgf 0.00
> +	 * tx/ck lvl 10
> +	 */
> +	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM);
> +	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL);
> +	hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL);
> +
> +	/* remove clk term */
> +	hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL);
> +
> +	hdmi_phy_enable_power(hdmi, 1);
> +
> +	/* toggle tmds enable */
> +	hdmi_phy_enable_tmds(hdmi, 0);
> +	hdmi_phy_enable_tmds(hdmi, 1);
> +
> +	/* gen2 tx power on */
> +	hdmi_phy_gen2_txpwron(hdmi, 1);
> +	hdmi_phy_gen2_pddq(hdmi, 0);
> +
> +	hdmi_phy_enable_spare(hdmi, 1);
> +
> +	/* wait for phy pll lock */
> +	start = get_timer(0);
> +	do {
> +		val = hdmi_read(hdmi, HDMI_PHY_STAT0);
> +		if (!(val & HDMI_PHY_TX_PHY_LOCK))
> +			return 0;
> +
> +		udelay(100);
> +	} while (get_timer(start) < 5);
> +
> +	return -1;
> +}
> +
> +static void hdmi_av_composer(struct dw_hdmi *hdmi,
> +			     const struct display_timing *edid)
> +{
> +	bool mdataenablepolarity = true;
> +	uint inv_val;
> +	uint hbl;
> +	uint vbl;
> +
> +	hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
> +			edid->hsync_len.typ;
> +	vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
> +			edid->vsync_len.typ;
> +
> +	/* set up hdmi_fc_invidconf */
> +	inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
> +
> +	inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
> +		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
> +		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
> +
> +	inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
> +		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
> +		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
> +
> +	inv_val |= (mdataenablepolarity ?
> +		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
> +		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
> +
> +	/*
> +	 * TODO(sjg at chromium.org>: Need to check for HDMI / DVI
> +	 * inv_val |= (edid->hdmi_monitor_detected ?
> +	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
> +	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
> +	 */
> +	inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
> +
> +	inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
> +
> +	inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
> +
> +	hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF);
> +
> +	/* set up horizontal active pixel width */
> +	hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1);
> +	hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0);
> +
> +	/* set up vertical active lines */
> +	hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1);
> +	hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0);
> +
> +	/* set up horizontal blanking pixel region width */
> +	hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1);
> +	hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0);
> +
> +	/* set up vertical blanking pixel region width */
> +	hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK);
> +
> +	/* set up hsync active edge delay width (in pixel clks) */
> +	hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1);
> +	hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0);
> +
> +	/* set up vsync active edge delay (in lines) */
> +	hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY);
> +
> +	/* set up hsync active pulse width (in pixel clks) */
> +	hdmi_write(hdmi, edid->hsync_len.typ >> 8, HDMI_FC_HSYNCINWIDTH1);
> +	hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0);
> +
> +	/* set up vsync active edge delay (in lines) */
> +	hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH);
> +}
> +
> +/* hdmi initialization step b.4 */
> +static void hdmi_enable_video_path(struct dw_hdmi *hdmi)
> +{
> +	uint clkdis;
> +
> +	/* control period minimum duration */
> +	hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR);
> +	hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR);
> +	hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC);
> +
> +	/* set to fill tmds data channels */
> +	hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM);
> +	hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM);
> +	hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM);
> +
> +	hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
> +		   HDMI_MC_FLOWCTRL);
> +
> +	/* enable pixel clock and tmds data path */
> +	clkdis = 0x7f;
> +	clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
> +	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
> +
> +	clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
> +	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
> +
> +	clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
> +	hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
> +}
> +
> +/* workaround to clear the overflow condition */
> +static void hdmi_clear_overflow(struct dw_hdmi *hdmi)
> +{
> +	uint val, count;
> +
> +	/* tmds software reset */
> +	hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
> +
> +	val = hdmi_read(hdmi, HDMI_FC_INVIDCONF);
> +
> +	for (count = 0; count < 4; count++)
> +		hdmi_write(hdmi, val, HDMI_FC_INVIDCONF);
> +}
> +
> +static void hdmi_audio_set_format(struct dw_hdmi *hdmi)
> +{
> +	hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
> +		   HDMI_AUD_CONF0);
> +
> +
> +	hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
> +		   HDMI_AUD_CONF1_I2S_WIDTH_16BIT, HDMI_AUD_CONF1);
> +
> +	hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2);
> +}
> +
> +static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi)
> +{
> +	hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, HDMI_MC_SWRSTZ);
> +	hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, HDMI_AUD_CONF0);
> +
> +	hdmi_write(hdmi, 0x00, HDMI_AUD_INT);
> +	hdmi_write(hdmi, 0x00, HDMI_AUD_INT1);
> +}
> +
> +static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi)
> +{
> +	uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD;
> +
> +	return !!val;
> +}
> +
> +static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
> +{
> +	u32 val;
> +	ulong start;
> +
> +	start = get_timer(0);
> +	do {
> +		val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0);
> +		if (val & 0x2) {
> +			hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0);
> +			return 0;
> +		}
> +
> +		udelay(100);
> +	} while (get_timer(start) < msec);
> +
> +	return 1;
> +}
> +
> +static void hdmi_ddc_reset(struct dw_hdmi *hdmi)
> +{
> +	hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0);
> +}
> +
> +static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff)
> +{
> +	int shift = (block % 2) * 0x80;
> +	int edid_read_err = 0;
> +	u32 trytime = 5;
> +	u32 n;
> +
> +	/* set ddc i2c clk which devided from ddc_clk to 100khz */
> +	hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
> +	hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
> +	hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE,
> +		 HDMI_I2CM_DIV_STD_MODE);
> +
> +	hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE);
> +	hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR);
> +	hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR);
> +
> +	while (trytime--) {
> +		edid_read_err = 0;
> +
> +		for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) {
> +			hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS);
> +
> +			if (block == 0)
> +				hdmi_write(hdmi, HDMI_I2CM_OP_RD8,
> +					   HDMI_I2CM_OPERATION);
> +			else
> +				hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT,
> +					   HDMI_I2CM_OPERATION);
> +
> +			if (hdmi_ddc_wait_i2c_done(hdmi, 10)) {
> +				hdmi_ddc_reset(hdmi);
> +				edid_read_err = 1;
> +				break;
> +			}
> +
> +			buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI);
> +		}
> +
> +		if (!edid_read_err)
> +			break;
> +	}
> +
> +	return edid_read_err;
> +}
> +
> +static const u8 pre_buf[] = {
> +	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
> +	0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
> +	0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
> +	0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
> +	0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
> +	0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
> +	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
> +	0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
> +	0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
> +	0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
> +	0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
> +	0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
> +	0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
> +	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
> +	0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
> +	0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
> +	0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
> +	0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
> +	0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
> +	0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
> +	0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
> +	0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
> +	0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
> +	0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
> +	0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
> +	0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
> +	0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
> +	0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
> +	0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
> +	0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
> +};
> +
> +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
> +{
> +	int i, ret;
> +
> +	/* hdmi phy spec says to do the phy initialization sequence twice */
> +	for (i = 0; i < 2; i++) {
> +		hdmi_phy_sel_data_en_pol(hdmi, 1);
> +		hdmi_phy_sel_interface_control(hdmi, 0);
> +		hdmi_phy_enable_tmds(hdmi, 0);
> +		hdmi_phy_enable_power(hdmi, 0);
> +
> +		ret = hdmi_phy_configure(hdmi, mpixelclock);
> +		if (ret) {
> +			debug("hdmi phy config failure %d\n", ret);
> +			return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
> +{
> +	ulong start;
> +
> +	start = get_timer(0);
> +	do {
> +		if (hdmi_get_plug_in_status(hdmi))
> +			return 0;
> +		udelay(100);
> +	} while (get_timer(start) < 300);
> +
> +	return -1;
> +}
> +
> +void dw_hdmi_phy_init(struct dw_hdmi *hdmi)
> +{
> +	/* enable phy i2cm done irq */
> +	hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
> +		   HDMI_PHY_I2CM_INT_ADDR);
> +
> +	/* enable phy i2cm nack & arbitration error irq */
> +	hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
> +		   HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
> +		   HDMI_PHY_I2CM_CTLINT_ADDR);
> +
> +	/* enable cable hot plug irq */
> +	hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
> +
> +	/* clear hotplug interrupts */
> +	hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
> +}
> +
> +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size)
> +{
> +	u32 edid_size = HDMI_EDID_BLOCK_SIZE;
> +	int ret;
> +
> +	if (0) {
> +		edid_size = sizeof(pre_buf);
> +		memcpy(buf, pre_buf, edid_size);
> +	} else {
> +		ret = hdmi_read_edid(hdmi, 0, buf);
> +		if (ret) {
> +			debug("failed to read edid.\n");
> +			return -1;
> +		}
> +
> +		if (buf[0x7e] != 0) {
> +			hdmi_read_edid(hdmi, 1, buf + HDMI_EDID_BLOCK_SIZE);
> +			edid_size += HDMI_EDID_BLOCK_SIZE;
> +		}
> +	}
> +
> +	return edid_size;
> +}
> +
> +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
> +{
> +	int ret;
> +
> +	debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
> +	      edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
> +
> +	hdmi_av_composer(hdmi, edid);
> +
> +	ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
> +	if (ret)
> +		return ret;
> +
> +	hdmi_enable_video_path(hdmi);
> +
> +	hdmi_audio_fifo_reset(hdmi);
> +	hdmi_audio_set_format(hdmi);
> +	hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ);
> +
> +	hdmi_video_packetize(hdmi);
> +	hdmi_video_sample(hdmi);
> +
> +	hdmi_clear_overflow(hdmi);
> +
> +	return 0;
> +}
> +
> +void dw_hdmi_init(struct dw_hdmi *hdmi)
> +{
> +	uint ih_mute;
> +
> +	/*
> +	 * boot up defaults are:
> +	 * hdmi_ih_mute   = 0x03 (disabled)
> +	 * hdmi_ih_mute_* = 0x00 (enabled)
> +	 *
> +	 * disable top level interrupt bits in hdmi block
> +	 */
> +	ih_mute = /*hdmi_read(hdmi, HDMI_IH_MUTE) |*/
> +		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
> +		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
> +
> +	hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE);
> +
> +	/* enable i2c master done irq */
> +	hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT);
> +
> +	/* enable i2c client nack % arbitration error irq */
> +	hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT);
> +}
> diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
> index 7962f8611e..755350b934 100644
> --- a/drivers/video/rockchip/Makefile
> +++ b/drivers/video/rockchip/Makefile
> @@ -5,4 +5,4 @@
>   # SPDX-License-Identifier:	GPL-2.0+
>   #
>   
> -obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o
> +obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o
> diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
> index c8608db23c..db07588302 100644
> --- a/drivers/video/rockchip/rk_hdmi.c
> +++ b/drivers/video/rockchip/rk_hdmi.c
> @@ -9,6 +9,7 @@
>   #include <clk.h>
>   #include <display.h>
>   #include <dm.h>
> +#include <dw_hdmi.h>
>   #include <edid.h>
>   #include <regmap.h>
>   #include <syscon.h>
> @@ -16,73 +17,13 @@
>   #include <asm/io.h>
>   #include <asm/arch/clock.h>
>   #include <asm/arch/grf_rk3288.h>
> -#include <asm/arch/hdmi_rk3288.h>
>   #include <power/regulator.h>
>   
> -struct tmds_n_cts {
> -	u32 tmds;
> -	u32 cts;
> -	u32 n;
> -};
> -
>   struct rk_hdmi_priv {
> -	struct rk3288_hdmi *regs;
> +	struct dw_hdmi hdmi;
>   	struct rk3288_grf *grf;
>   };
>   
> -static const struct tmds_n_cts n_cts_table[] = {
> -	{
> -		.tmds = 25175000, .n = 6144, .cts = 25175,
> -	}, {
> -		.tmds = 25200000, .n = 6144, .cts = 25200,
> -	}, {
> -		.tmds = 27000000, .n = 6144, .cts = 27000,
> -	}, {
> -		.tmds = 27027000, .n = 6144, .cts = 27027,
> -	}, {
> -		.tmds = 40000000, .n = 6144, .cts = 40000,
> -	}, {
> -		.tmds = 54000000, .n = 6144, .cts = 54000,
> -	}, {
> -		.tmds = 54054000, .n = 6144, .cts = 54054,
> -	}, {
> -		.tmds = 65000000, .n = 6144, .cts = 65000,
> -	}, {
> -		.tmds = 74176000, .n = 11648, .cts = 140625,
> -	}, {
> -		.tmds = 74250000, .n = 6144, .cts = 74250,
> -	}, {
> -		.tmds = 83500000, .n = 6144, .cts = 83500,
> -	}, {
> -		.tmds = 106500000, .n = 6144, .cts = 106500,
> -	}, {
> -		.tmds = 108000000, .n = 6144, .cts = 108000,
> -	}, {
> -		.tmds = 148352000, .n = 5824, .cts = 140625,
> -	}, {
> -		.tmds = 148500000, .n = 6144, .cts = 148500,
> -	}, {
> -		.tmds = 297000000, .n = 5120, .cts = 247500,
> -	}
> -};
> -
> -struct hdmi_mpll_config {
> -	u64 mpixelclock;
> -	/* Mode of Operation and PLL Dividers Control Register */
> -	u32 cpce;
> -	/* PLL Gmp Control Register */
> -	u32 gmp;
> -	/* PLL Current COntrol Register */
> -	u32 curr;
> -};
> -
> -struct hdmi_phy_config {
> -	u64 mpixelclock;
> -	u32 sym_ctr;    /* clock symbol and transmitter control */
> -	u32 term;       /* transmission termination value */
> -	u32 vlev_ctr;   /* voltage level control */
> -};
> -
>   static const struct hdmi_phy_config rockchip_phy_config[] = {
>   	{
>   		.mpixelclock = 74250000,
> @@ -124,693 +65,41 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
>   	}
>   };
>   
> -static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts)
> -{
> -	uint cts3;
> -	uint n3;
> -
> -	/* first set ncts_atomic_write (if present) */
> -	n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
> -	writel(n3, &regs->aud_n3);
> -
> -	/* set cts_manual (if present) */
> -	cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
> -
> -	cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
> -	cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
> -
> -	/* write cts values; cts3 must be written first */
> -	writel(cts3, &regs->aud_cts3);
> -	writel((cts >> 8) & 0xff, &regs->aud_cts2);
> -	writel(cts & 0xff, &regs->aud_cts1);
> -
> -	/* write n values; n1 must be written last */
> -	n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
> -	writel(n3, &regs->aud_n3);
> -	writel((n >> 8) & 0xff, &regs->aud_n2);
> -	writel(n & 0xff, &regs->aud_n1);
> -
> -	writel(HDMI_AUD_INPUTCLKFS_128, &regs->aud_inputclkfs);
> -}
> -
> -static int hdmi_lookup_n_cts(u32 pixel_clk)
> -{
> -	int i;
> -
> -	for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
> -		if (pixel_clk <= n_cts_table[i].tmds)
> -			break;
> -
> -	if (i >= ARRAY_SIZE(n_cts_table))
> -		return -1;
> -
> -	return i;
> -}
> -
> -static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 pixel_clk)
> -{
> -	u32 clk_n, clk_cts;
> -	int index;
> -
> -	index = hdmi_lookup_n_cts(pixel_clk);
> -	if (index == -1) {
> -		debug("audio not supported for pixel clk %d\n", pixel_clk);
> -		return;
> -	}
> -
> -	clk_n = n_cts_table[index].n;
> -	clk_cts = n_cts_table[index].cts;
> -	hdmi_set_clock_regenerator(regs, clk_n, clk_cts);
> -}
> -
> -/*
> - * this submodule is responsible for the video data synchronization.
> - * for example, for rgb 4:4:4 input, the data map is defined as
> - *			pin{47~40} <==> r[7:0]
> - *			pin{31~24} <==> g[7:0]
> - *			pin{15~8}  <==> b[7:0]
> - */
> -static void hdmi_video_sample(struct rk3288_hdmi *regs)
> -{
> -	u32 color_format = 0x01;
> -	uint val;
> -
> -	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
> -	      ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
> -	      HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
> -
> -	writel(val, &regs->tx_invid0);
> -
> -	/* enable tx stuffing: when de is inactive, fix the output data to 0 */
> -	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
> -	      HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
> -	      HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
> -	writel(val, &regs->tx_instuffing);
> -	writel(0x0, &regs->tx_gydata0);
> -	writel(0x0, &regs->tx_gydata1);
> -	writel(0x0, &regs->tx_rcrdata0);
> -	writel(0x0, &regs->tx_rcrdata1);
> -	writel(0x0, &regs->tx_bcbdata0);
> -	writel(0x0, &regs->tx_bcbdata1);
> -}
> -
> -static void hdmi_video_packetize(struct rk3288_hdmi *regs)
> -{
> -	u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
> -	u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
> -	u32 color_depth = 0;
> -	uint val, vp_conf;
> -
> -	/* set the packetizer registers */
> -	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
> -		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
> -		((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
> -		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
> -	writel(val, &regs->vp_pr_cd);
> -
> -	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK,
> -			HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
> -
> -	/* data from pixel repeater block */
> -	vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
> -		  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
> -
> -	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK |
> -			HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
> -
> -	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
> -			1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
> -
> -	writel(remap_size, &regs->vp_remap);
> -
> -	vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
> -		  HDMI_VP_CONF_PP_EN_DISABLE |
> -		  HDMI_VP_CONF_YCC422_EN_DISABLE;
> -
> -	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK |
> -			HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
> -			vp_conf);
> -
> -	clrsetbits_le32(&regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK |
> -			HDMI_VP_STUFF_YCC422_STUFFING_MASK,
> -			HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
> -			HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
> -
> -	clrsetbits_le32(&regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
> -			output_select);
> -}
> -
> -static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit)
> -{
> -	clrsetbits_le32(&regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
> -			bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
> -}
> -
> -static int hdmi_phy_wait_i2c_done(struct rk3288_hdmi *regs, u32 msec)
> -{
> -	ulong start;
> -	u32 val;
> -
> -	start = get_timer(0);
> -	do {
> -		val = readl(&regs->ih_i2cmphy_stat0);
> -		if (val & 0x3) {
> -			writel(val, &regs->ih_i2cmphy_stat0);
> -			return 0;
> -		}
> -
> -		udelay(100);
> -	} while (get_timer(start) < msec);
> -
> -	return 1;
> -}
> -
> -static void hdmi_phy_i2c_write(struct rk3288_hdmi *regs, uint data, uint addr)
> -{
> -	writel(0xff, &regs->ih_i2cmphy_stat0);
> -	writel(addr, &regs->phy_i2cm_address_addr);
> -	writel((u8)(data >> 8), &regs->phy_i2cm_datao_1_addr);
> -	writel((u8)(data >> 0), &regs->phy_i2cm_datao_0_addr);
> -	writel(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
> -	       &regs->phy_i2cm_operation_addr);
> -
> -	hdmi_phy_wait_i2c_done(regs, 1000);
> -}
> -
> -static void hdmi_phy_enable_power(struct rk3288_hdmi *regs, uint enable)
> -{
> -	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK,
> -			enable << HDMI_PHY_CONF0_PDZ_OFFSET);
> -}
> -
> -static void hdmi_phy_enable_tmds(struct rk3288_hdmi *regs, uint enable)
> -{
> -	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK,
> -			enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
> -}
> -
> -static void hdmi_phy_enable_spare(struct rk3288_hdmi *regs, uint enable)
> -{
> -	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK,
> -			enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
> -}
> -
> -static void hdmi_phy_gen2_pddq(struct rk3288_hdmi *regs, uint enable)
> -{
> -	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
> -			enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
> -}
> -
> -static void hdmi_phy_gen2_txpwron(struct rk3288_hdmi *regs, uint enable)
> -{
> -	clrsetbits_le32(&regs->phy_conf0,
> -			HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
> -			enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
> -}
> -
> -static void hdmi_phy_sel_data_en_pol(struct rk3288_hdmi *regs, uint enable)
> -{
> -	clrsetbits_le32(&regs->phy_conf0,
> -			HDMI_PHY_CONF0_SELDATAENPOL_MASK,
> -			enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
> -}
> -
> -static void hdmi_phy_sel_interface_control(struct rk3288_hdmi *regs,
> -					   uint enable)
> -{
> -	clrsetbits_le32(&regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK,
> -			enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
> -}
> -
> -static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock)
> -{
> -	ulong start;
> -	uint i, val;
> -
> -	writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
> -	       &regs->mc_flowctrl);
> -
> -	/* gen2 tx power off */
> -	hdmi_phy_gen2_txpwron(regs, 0);
> -
> -	/* gen2 pddq */
> -	hdmi_phy_gen2_pddq(regs, 1);
> -
> -	/* phy reset */
> -	writel(HDMI_MC_PHYRSTZ_DEASSERT, &regs->mc_phyrstz);
> -	writel(HDMI_MC_PHYRSTZ_ASSERT, &regs->mc_phyrstz);
> -	writel(HDMI_MC_HEACPHY_RST_ASSERT, &regs->mc_heacphy_rst);
> -
> -	hdmi_phy_test_clear(regs, 1);
> -	writel(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, &regs->phy_i2cm_slave_addr);
> -	hdmi_phy_test_clear(regs, 0);
> -
> -	/* pll/mpll cfg - always match on final entry */
> -	for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++)
> -		if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock)
> -			break;
> -
> -	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
> -	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
> -	hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL);
> -
> -	hdmi_phy_i2c_write(regs, 0x0000, PHY_PLLPHBYCTRL);
> -	hdmi_phy_i2c_write(regs, 0x0006, PHY_PLLCLKBISTPHASE);
> -
> -	for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++)
> -		if (mpixelclock <= rockchip_phy_config[i].mpixelclock)
> -			break;
> -
> -	/*
> -	 * resistance term 133ohm cfg
> -	 * preemp cgf 0.00
> -	 * tx/ck lvl 10
> -	 */
> -	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].term, PHY_TXTERM);
> -	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].sym_ctr,
> -			   PHY_CKSYMTXCTRL);
> -	hdmi_phy_i2c_write(regs, rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL);
> -
> -	/* remove clk term */
> -	hdmi_phy_i2c_write(regs, 0x8000, PHY_CKCALCTRL);
> -
> -	hdmi_phy_enable_power(regs, 1);
> -
> -	/* toggle tmds enable */
> -	hdmi_phy_enable_tmds(regs, 0);
> -	hdmi_phy_enable_tmds(regs, 1);
> -
> -	/* gen2 tx power on */
> -	hdmi_phy_gen2_txpwron(regs, 1);
> -	hdmi_phy_gen2_pddq(regs, 0);
> -
> -	hdmi_phy_enable_spare(regs, 1);
> -
> -	/* wait for phy pll lock */
> -	start = get_timer(0);
> -	do {
> -		val = readl(&regs->phy_stat0);
> -		if (!(val & HDMI_PHY_TX_PHY_LOCK))
> -			return 0;
> -
> -		udelay(100);
> -	} while (get_timer(start) < 5);
> -
> -	return -1;
> -}
> -
> -static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock)
> -{
> -	int i, ret;
> -
> -	/* hdmi phy spec says to do the phy initialization sequence twice */
> -	for (i = 0; i < 2; i++) {
> -		hdmi_phy_sel_data_en_pol(regs, 1);
> -		hdmi_phy_sel_interface_control(regs, 0);
> -		hdmi_phy_enable_tmds(regs, 0);
> -		hdmi_phy_enable_power(regs, 0);
> -
> -		ret = hdmi_phy_configure(regs, mpixelclock);
> -		if (ret) {
> -			debug("hdmi phy config failure %d\n", ret);
> -			return ret;
> -		}
> -	}
> -
> -	return 0;
> -}
> -
> -static void hdmi_av_composer(struct rk3288_hdmi *regs,
> -			     const struct display_timing *edid)
> -{
> -	bool mdataenablepolarity = true;
> -	uint inv_val;
> -	uint hbl;
> -	uint vbl;
> -
> -	hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
> -			edid->hsync_len.typ;
> -	vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
> -			edid->vsync_len.typ;
> -
> -	/* set up hdmi_fc_invidconf */
> -	inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
> -
> -	inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
> -		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
> -		   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
> -
> -	inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
> -		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
> -		   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
> -
> -	inv_val |= (mdataenablepolarity ?
> -		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
> -		   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
> -
> -	/*
> -	 * TODO(sjg at chromium.org>: Need to check for HDMI / DVI
> -	 * inv_val |= (edid->hdmi_monitor_detected ?
> -	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
> -	 *	   HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
> -	 */
> -	inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
> -
> -	inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
> -
> -	inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
> -
> -	writel(inv_val, &regs->fc_invidconf);
> -
> -	/* set up horizontal active pixel width */
> -	writel(edid->hactive.typ >> 8, &regs->fc_inhactv1);
> -	writel(edid->hactive.typ, &regs->fc_inhactv0);
> -
> -	/* set up vertical active lines */
> -	writel(edid->vactive.typ >> 8, &regs->fc_invactv1);
> -	writel(edid->vactive.typ, &regs->fc_invactv0);
> -
> -	/* set up horizontal blanking pixel region width */
> -	writel(hbl >> 8, &regs->fc_inhblank1);
> -	writel(hbl, &regs->fc_inhblank0);
> -
> -	/* set up vertical blanking pixel region width */
> -	writel(vbl, &regs->fc_invblank);
> -
> -	/* set up hsync active edge delay width (in pixel clks) */
> -	writel(edid->hfront_porch.typ >> 8, &regs->fc_hsyncindelay1);
> -	writel(edid->hfront_porch.typ, &regs->fc_hsyncindelay0);
> -
> -	/* set up vsync active edge delay (in lines) */
> -	writel(edid->vfront_porch.typ, &regs->fc_vsyncindelay);
> -
> -	/* set up hsync active pulse width (in pixel clks) */
> -	writel(edid->hsync_len.typ >> 8, &regs->fc_hsyncinwidth1);
> -	writel(edid->hsync_len.typ, &regs->fc_hsyncinwidth0);
> -
> -	/* set up vsync active edge delay (in lines) */
> -	writel(edid->vsync_len.typ, &regs->fc_vsyncinwidth);
> -}
> -
> -/* hdmi initialization step b.4 */
> -static void hdmi_enable_video_path(struct rk3288_hdmi *regs)
> -{
> -	uint clkdis;
> -
> -	/* control period minimum duration */
> -	writel(12, &regs->fc_ctrldur);
> -	writel(32, &regs->fc_exctrldur);
> -	writel(1, &regs->fc_exctrlspac);
> -
> -	/* set to fill tmds data channels */
> -	writel(0x0b, &regs->fc_ch0pream);
> -	writel(0x16, &regs->fc_ch1pream);
> -	writel(0x21, &regs->fc_ch2pream);
> -
> -	/* enable pixel clock and tmds data path */
> -	clkdis = 0x7f;
> -	clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
> -	writel(clkdis, &regs->mc_clkdis);
> -
> -	clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
> -	writel(clkdis, &regs->mc_clkdis);
> -
> -	clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
> -	writel(clkdis, &regs->mc_clkdis);
> -}
> -
> -/* workaround to clear the overflow condition */
> -static void hdmi_clear_overflow(struct rk3288_hdmi *regs)
> -{
> -	uint val, count;
> -
> -	/* tmds software reset */
> -	writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &regs->mc_swrstz);
> -
> -	val = readl(&regs->fc_invidconf);
> -
> -	for (count = 0; count < 4; count++)
> -		writel(val, &regs->fc_invidconf);
> -}
> -
> -static void hdmi_audio_set_format(struct rk3288_hdmi *regs)
> -{
> -	writel(HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
> -	       &regs->aud_conf0);
> -
> -
> -	writel(HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
> -	       HDMI_AUD_CONF1_I2S_WIDTH_16BIT, &regs->aud_conf1);
> -
> -	writel(0x00, &regs->aud_conf2);
> -}
> -
> -static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs)
> -{
> -	writel((u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, &regs->mc_swrstz);
> -	writel(HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, &regs->aud_conf0);
> -
> -	writel(0x00, &regs->aud_int);
> -	writel(0x00, &regs->aud_int1);
> -}
> -
> -static void hdmi_init_interrupt(struct rk3288_hdmi *regs)
> -{
> -	uint ih_mute;
> -
> -	/*
> -	 * boot up defaults are:
> -	 * hdmi_ih_mute   = 0x03 (disabled)
> -	 * hdmi_ih_mute_* = 0x00 (enabled)
> -	 *
> -	 * disable top level interrupt bits in hdmi block
> -	 */
> -	ih_mute = readl(&regs->ih_mute) |
> -		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
> -		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
> -
> -	writel(ih_mute, &regs->ih_mute);
> -
> -	/* enable i2c master done irq */
> -	writel(~0x04, &regs->i2cm_int);
> -
> -	/* enable i2c client nack % arbitration error irq */
> -	writel(~0x44, &regs->i2cm_ctlint);
> -
> -	/* enable phy i2cm done irq */
> -	writel(HDMI_PHY_I2CM_INT_ADDR_DONE_POL, &regs->phy_i2cm_int_addr);
> -
> -	/* enable phy i2cm nack & arbitration error irq */
> -	writel(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
> -		HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
> -		&regs->phy_i2cm_ctlint_addr);
> -
> -	/* enable cable hot plug irq */
> -	writel((u8)~HDMI_PHY_HPD, &regs->phy_mask0);
> -
> -	/* clear hotplug interrupts */
> -	writel(HDMI_IH_PHY_STAT0_HPD, &regs->ih_phy_stat0);
> -}
> -
> -static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
> -{
> -	uint val = readl(&regs->phy_stat0) & HDMI_PHY_HPD;
> -
> -	return !!val;
> -}
> -
> -static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
> -{
> -	ulong start;
> -
> -	start = get_timer(0);
> -	do {
> -		if (hdmi_get_plug_in_status(regs))
> -			return 0;
> -		udelay(100);
> -	} while (get_timer(start) < 300);
> -
> -	return -1;
> -}
> -
> -static int hdmi_ddc_wait_i2c_done(struct rk3288_hdmi *regs, int msec)
> -{
> -	u32 val;
> -	ulong start;
> -
> -	start = get_timer(0);
> -	do {
> -		val = readl(&regs->ih_i2cm_stat0);
> -		if (val & 0x2) {
> -			writel(val, &regs->ih_i2cm_stat0);
> -			return 0;
> -		}
> -
> -		udelay(100);
> -	} while (get_timer(start) < msec);
> -
> -	return 1;
> -}
> -
> -static void hdmi_ddc_reset(struct rk3288_hdmi *regs)
> -{
> -	clrbits_le32(&regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ);
> -}
> -
> -static int hdmi_read_edid(struct rk3288_hdmi *regs, int block, u8 *buff)
> -{
> -	int shift = (block % 2) * 0x80;
> -	int edid_read_err = 0;
> -	u32 trytime = 5;
> -	u32 n, j, val;
> -
> -	/* set ddc i2c clk which devided from ddc_clk to 100khz */
> -	writel(0x7a, &regs->i2cm_ss_scl_hcnt_0_addr);
> -	writel(0x8d, &regs->i2cm_ss_scl_lcnt_0_addr);
> -
> -	/*
> -	 * TODO(sjg at chromium.org): The above values don't work - these ones
> -	 * work better, but generate lots of errors in the data.
> -	 */
> -	writel(0x0d, &regs->i2cm_ss_scl_hcnt_0_addr);
> -	writel(0x0d, &regs->i2cm_ss_scl_lcnt_0_addr);
> -	clrsetbits_le32(&regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
> -			HDMI_I2CM_DIV_STD_MODE);
> -
> -	writel(HDMI_I2CM_SLAVE_DDC_ADDR, &regs->i2cm_slave);
> -	writel(HDMI_I2CM_SEGADDR_DDC, &regs->i2cm_segaddr);
> -	writel(block >> 1, &regs->i2cm_segptr);
> -
> -	while (trytime--) {
> -		edid_read_err = 0;
> -
> -		for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
> -			writel(shift + 8 * n, &regs->i2c_address);
> -
> -			if (block == 0)
> -				clrsetbits_le32(&regs->i2cm_operation,
> -						HDMI_I2CM_OPT_RD8,
> -						HDMI_I2CM_OPT_RD8);
> -			else
> -				clrsetbits_le32(&regs->i2cm_operation,
> -						HDMI_I2CM_OPT_RD8_EXT,
> -						HDMI_I2CM_OPT_RD8_EXT);
> -
> -			if (hdmi_ddc_wait_i2c_done(regs, 10)) {
> -				hdmi_ddc_reset(regs);
> -				edid_read_err = 1;
> -				break;
> -			}
> -
> -			for (j = 0; j < 8; j++) {
> -				val = readl(&regs->i2cm_buf0 + j);
> -				buff[8 * n + j] = val;
> -			}
> -		}
> -
> -		if (!edid_read_err)
> -			break;
> -	}
> -
> -	return edid_read_err;
> -}
> -
> -static const u8 pre_buf[] = {
> -	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
> -	0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
> -	0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
> -	0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
> -	0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
> -	0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
> -	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
> -	0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
> -	0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
> -	0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
> -	0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
> -	0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
> -	0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
> -	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
> -	0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
> -	0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
> -	0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
> -	0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
> -	0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
> -	0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
> -	0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
> -	0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
> -	0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
> -	0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
> -	0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
> -	0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
> -	0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
> -	0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
> -	0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
> -	0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> -	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> -	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
> -};
> -
>   static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
>   {
>   	struct rk_hdmi_priv *priv = dev_get_priv(dev);
> -	u32 edid_size = HDMI_EDID_BLOCK_SIZE;
> -	int ret;
> -
> -	if (0) {
> -		edid_size = sizeof(pre_buf);
> -		memcpy(buf, pre_buf, edid_size);
> -	} else {
> -		ret = hdmi_read_edid(priv->regs, 0, buf);
> -		if (ret) {
> -			debug("failed to read edid.\n");
> -			return -1;
> -		}
>   
> -		if (buf[0x7e] != 0) {
> -			hdmi_read_edid(priv->regs, 1,
> -				       buf + HDMI_EDID_BLOCK_SIZE);
> -			edid_size += HDMI_EDID_BLOCK_SIZE;
> -		}
> -	}
> -
> -	return edid_size;
> +	return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
>   }
>   
>   static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
>   			  const struct display_timing *edid)
>   {
>   	struct rk_hdmi_priv *priv = dev_get_priv(dev);
> -	struct rk3288_hdmi *regs = priv->regs;
> -	int ret;
> -
> -	debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
> -	      edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
>   
> -	hdmi_av_composer(regs, edid);
> -
> -	ret = hdmi_phy_init(regs, edid->pixelclock.typ);
> -	if (ret)
> -		return ret;
> -
> -	hdmi_enable_video_path(regs);
> -
> -	hdmi_audio_fifo_reset(regs);
> -	hdmi_audio_set_format(regs);
> -	hdmi_audio_set_samplerate(regs, edid->pixelclock.typ);
> -
> -	hdmi_video_packetize(regs);
> -	hdmi_video_sample(regs);
> -
> -	hdmi_clear_overflow(regs);
> -
> -	return 0;
> +	return dw_hdmi_enable(&priv->hdmi, edid);
>   }
>   
>   static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
>   {
>   	struct rk_hdmi_priv *priv = dev_get_priv(dev);
> +	struct dw_hdmi *hdmi = &priv->hdmi;
> +
> +	hdmi->ioaddr = (ulong)dev_get_addr(dev);
> +	hdmi->mpll_cfg = rockchip_mpll_cfg;
> +	hdmi->phy_cfg = rockchip_phy_config;
> +	hdmi->i2c_clk_high = 0x7a;
> +	hdmi->i2c_clk_low = 0x8d;
> +
> +	/*
> +	 * TODO(sjg at chromium.org): The above values don't work - these ones
> +	 * work better, but generate lots of errors in the data.
> +	 */
> +	hdmi->i2c_clk_high = 0x0d;
> +	hdmi->i2c_clk_low = 0x0d;
> +	hdmi->reg_io_width = 4;
> +	hdmi->phy_set = dw_hdmi_phy_cfg;
>   
> -	priv->regs = (struct rk3288_hdmi *)dev_get_addr(dev);
>   	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>   
>   	return 0;
> @@ -820,6 +109,7 @@ static int rk_hdmi_probe(struct udevice *dev)
>   {
>   	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
>   	struct rk_hdmi_priv *priv = dev_get_priv(dev);
> +	struct dw_hdmi *hdmi = &priv->hdmi;
>   	struct udevice *reg;
>   	struct clk clk;
>   	int ret;
> @@ -863,13 +153,14 @@ static int rk_hdmi_probe(struct udevice *dev)
>   	rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
>   		     (vop_id == 1) ? (1 << 4) : 0);
>   
> -	ret = hdmi_wait_for_hpd(priv->regs);
> +	ret = dw_hdmi_phy_wait_for_hpd(hdmi);
>   	if (ret < 0) {
>   		debug("hdmi can not get hpd signal\n");
>   		return -1;
>   	}
>   
> -	hdmi_init_interrupt(priv->regs);
> +	dw_hdmi_init(hdmi);
> +	dw_hdmi_phy_init(hdmi);
>   
>   	return 0;
>   }
> diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
> index aeecb5815b..bc02f800dc 100644
> --- a/drivers/video/rockchip/rk_vop.c
> +++ b/drivers/video/rockchip/rk_vop.c
> @@ -20,7 +20,6 @@
>   #include <asm/arch/cru_rk3288.h>
>   #include <asm/arch/grf_rk3288.h>
>   #include <asm/arch/edp_rk3288.h>
> -#include <asm/arch/hdmi_rk3288.h>
>   #include <asm/arch/vop_rk3288.h>
>   #include <dm/device-internal.h>
>   #include <dm/uclass-internal.h>
> diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
> new file mode 100644
> index 0000000000..902abd4d44
> --- /dev/null
> +++ b/include/dw_hdmi.h
> @@ -0,0 +1,486 @@
> +/*
> + * Copyright (c) 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef _DW_HDMI_H
> +#define _DW_HDMI_H
> +
> +#include <edid.h>
> +
> +#define HDMI_EDID_BLOCK_SIZE            128
> +
> +/* Identification Registers */
> +#define HDMI_DESIGN_ID                          0x0000
> +#define HDMI_REVISION_ID                        0x0001
> +#define HDMI_PRODUCT_ID0                        0x0002
> +#define HDMI_PRODUCT_ID1                        0x0003
> +#define HDMI_CONFIG0_ID                         0x0004
> +#define HDMI_CONFIG1_ID                         0x0005
> +#define HDMI_CONFIG2_ID                         0x0006
> +#define HDMI_CONFIG3_ID                         0x0007
> +
> +/* Interrupt Registers */
> +#define HDMI_IH_FC_STAT0                        0x0100
> +#define HDMI_IH_FC_STAT1                        0x0101
> +#define HDMI_IH_FC_STAT2                        0x0102
> +#define HDMI_IH_AS_STAT0                        0x0103
> +#define HDMI_IH_PHY_STAT0                       0x0104
> +#define HDMI_IH_I2CM_STAT0                      0x0105
> +#define HDMI_IH_CEC_STAT0                       0x0106
> +#define HDMI_IH_VP_STAT0                        0x0107
> +#define HDMI_IH_I2CMPHY_STAT0                   0x0108
> +#define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
> +
> +#define HDMI_IH_MUTE_FC_STAT0                   0x0180
> +#define HDMI_IH_MUTE_FC_STAT1                   0x0181
> +#define HDMI_IH_MUTE_FC_STAT2                   0x0182
> +#define HDMI_IH_MUTE_AS_STAT0                   0x0183
> +#define HDMI_IH_MUTE_PHY_STAT0                  0x0184
> +#define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
> +#define HDMI_IH_MUTE_CEC_STAT0                  0x0186
> +#define HDMI_IH_MUTE_VP_STAT0                   0x0187
> +#define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
> +#define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
> +#define HDMI_IH_MUTE                            0x01FF
> +
> +/* Video Sample Registers */
> +#define HDMI_TX_INVID0                          0x0200
> +#define HDMI_TX_INSTUFFING                      0x0201
> +#define HDMI_TX_GYDATA0                         0x0202
> +#define HDMI_TX_GYDATA1                         0x0203
> +#define HDMI_TX_RCRDATA0                        0x0204
> +#define HDMI_TX_RCRDATA1                        0x0205
> +#define HDMI_TX_BCBDATA0                        0x0206
> +#define HDMI_TX_BCBDATA1                        0x0207
> +
> +/* Video Packetizer Registers */
> +#define HDMI_VP_STATUS                          0x0800
> +#define HDMI_VP_PR_CD                           0x0801
> +#define HDMI_VP_STUFF                           0x0802
> +#define HDMI_VP_REMAP                           0x0803
> +#define HDMI_VP_CONF                            0x0804
> +#define HDMI_VP_STAT                            0x0805
> +#define HDMI_VP_INT                             0x0806
> +#define HDMI_VP_MASK                            0x0807
> +#define HDMI_VP_POL                             0x0808
> +
> +/* Frame Composer Registers */
> +#define HDMI_FC_INVIDCONF                       0x1000
> +#define HDMI_FC_INHACTV0                        0x1001
> +#define HDMI_FC_INHACTV1                        0x1002
> +#define HDMI_FC_INHBLANK0                       0x1003
> +#define HDMI_FC_INHBLANK1                       0x1004
> +#define HDMI_FC_INVACTV0                        0x1005
> +#define HDMI_FC_INVACTV1                        0x1006
> +#define HDMI_FC_INVBLANK                        0x1007
> +#define HDMI_FC_HSYNCINDELAY0                   0x1008
> +#define HDMI_FC_HSYNCINDELAY1                   0x1009
> +#define HDMI_FC_HSYNCINWIDTH0                   0x100A
> +#define HDMI_FC_HSYNCINWIDTH1                   0x100B
> +#define HDMI_FC_VSYNCINDELAY                    0x100C
> +#define HDMI_FC_VSYNCINWIDTH                    0x100D
> +#define HDMI_FC_INFREQ0                         0x100E
> +#define HDMI_FC_INFREQ1                         0x100F
> +#define HDMI_FC_INFREQ2                         0x1010
> +#define HDMI_FC_CTRLDUR                         0x1011
> +#define HDMI_FC_EXCTRLDUR                       0x1012
> +#define HDMI_FC_EXCTRLSPAC                      0x1013
> +#define HDMI_FC_CH0PREAM                        0x1014
> +#define HDMI_FC_CH1PREAM                        0x1015
> +#define HDMI_FC_CH2PREAM                        0x1016
> +#define HDMI_FC_AVICONF3                        0x1017
> +#define HDMI_FC_GCP                             0x1018
> +#define HDMI_FC_AVICONF0                        0x1019
> +#define HDMI_FC_AVICONF1                        0x101A
> +#define HDMI_FC_AVICONF2                        0x101B
> +#define HDMI_FC_AVIVID                          0x101C
> +#define HDMI_FC_AVIETB0                         0x101D
> +#define HDMI_FC_AVIETB1                         0x101E
> +#define HDMI_FC_AVISBB0                         0x101F
> +#define HDMI_FC_AVISBB1                         0x1020
> +#define HDMI_FC_AVIELB0                         0x1021
> +#define HDMI_FC_AVIELB1                         0x1022
> +#define HDMI_FC_AVISRB0                         0x1023
> +#define HDMI_FC_AVISRB1                         0x1024
> +#define HDMI_FC_AUDICONF0                       0x1025
> +#define HDMI_FC_AUDICONF1                       0x1026
> +#define HDMI_FC_AUDICONF2                       0x1027
> +#define HDMI_FC_AUDICONF3                       0x1028
> +#define HDMI_FC_VSDIEEEID0                      0x1029
> +#define HDMI_FC_VSDSIZE                         0x102A
> +
> +/* HDMI Source PHY Registers */
> +#define HDMI_PHY_CONF0                          0x3000
> +#define HDMI_PHY_TST0                           0x3001
> +#define HDMI_PHY_TST1                           0x3002
> +#define HDMI_PHY_TST2                           0x3003
> +#define HDMI_PHY_STAT0                          0x3004
> +#define HDMI_PHY_INT0                           0x3005
> +#define HDMI_PHY_MASK0                          0x3006
> +#define HDMI_PHY_POL0                           0x3007
> +
> +/* HDMI Master PHY Registers */
> +#define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
> +#define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
> +#define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
> +#define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
> +#define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
> +#define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
> +#define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
> +#define HDMI_PHY_I2CM_INT_ADDR                  0x3027
> +#define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
> +#define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
> +#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
> +#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
> +#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
> +#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
> +#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
> +#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
> +#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
> +#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
> +#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
> +
> +/* Audio Sampler Registers */
> +#define HDMI_AUD_CONF0                          0x3100
> +#define HDMI_AUD_CONF1                          0x3101
> +#define HDMI_AUD_INT                            0x3102
> +#define HDMI_AUD_CONF2                          0x3103
> +#define HDMI_AUD_INT1                           0x3104
> +#define HDMI_AUD_N1                             0x3200
> +#define HDMI_AUD_N2                             0x3201
> +#define HDMI_AUD_N3                             0x3202
> +#define HDMI_AUD_CTS1                           0x3203
> +#define HDMI_AUD_CTS2                           0x3204
> +#define HDMI_AUD_CTS3                           0x3205
> +#define HDMI_AUD_INPUTCLKFS                     0x3206
> +#define HDMI_AUD_SPDIFINT			0x3302
> +#define HDMI_AUD_CONF0_HBR                      0x3400
> +#define HDMI_AUD_HBR_STATUS                     0x3401
> +#define HDMI_AUD_HBR_INT                        0x3402
> +#define HDMI_AUD_HBR_POL                        0x3403
> +#define HDMI_AUD_HBR_MASK                       0x3404
> +
> +/* Main Controller Registers */
> +#define HDMI_MC_SFRDIV                          0x4000
> +#define HDMI_MC_CLKDIS                          0x4001
> +#define HDMI_MC_SWRSTZ                          0x4002
> +#define HDMI_MC_OPCTRL                          0x4003
> +#define HDMI_MC_FLOWCTRL                        0x4004
> +#define HDMI_MC_PHYRSTZ                         0x4005
> +#define HDMI_MC_LOCKONCLOCK                     0x4006
> +#define HDMI_MC_HEACPHY_RST                     0x4007
> +
> +/* I2C Master Registers (E-DDC) */
> +#define HDMI_I2CM_SLAVE                         0x7E00
> +#define HDMI_I2CM_ADDRESS                       0x7E01
> +#define HDMI_I2CM_DATAO                         0x7E02
> +#define HDMI_I2CM_DATAI                         0x7E03
> +#define HDMI_I2CM_OPERATION                     0x7E04
> +#define HDMI_I2CM_INT                           0x7E05
> +#define HDMI_I2CM_CTLINT                        0x7E06
> +#define HDMI_I2CM_DIV                           0x7E07
> +#define HDMI_I2CM_SEGADDR                       0x7E08
> +#define HDMI_I2CM_SOFTRSTZ                      0x7E09
> +#define HDMI_I2CM_SEGPTR                        0x7E0A
> +#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
> +#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
> +#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
> +#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
> +#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
> +#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
> +#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
> +#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
> +#define HDMI_I2CM_BUF0                          0x7E20
> +
> +enum {
> +	/* HDMI PHY registers define */
> +	PHY_OPMODE_PLLCFG = 0x06,
> +	PHY_CKCALCTRL = 0x05,
> +	PHY_CKSYMTXCTRL = 0x09,
> +	PHY_VLEVCTRL = 0x0e,
> +	PHY_PLLCURRCTRL = 0x10,
> +	PHY_PLLPHBYCTRL = 0x13,
> +	PHY_PLLGMPCTRL = 0x15,
> +	PHY_PLLCLKBISTPHASE = 0x17,
> +	PHY_TXTERM = 0x19,
> +
> +	/* ih_phy_stat0 field values */
> +	HDMI_IH_PHY_STAT0_HPD = 0x1,
> +
> +	/* ih_mute field values */
> +	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
> +	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
> +
> +	/* tx_invid0 field values */
> +	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
> +	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
> +	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
> +
> +	/* tx_instuffing field values */
> +	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
> +	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
> +	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
> +
> +	/* vp_pr_cd field values */
> +	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
> +	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
> +	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
> +	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
> +
> +	/* vp_stuff field values */
> +	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
> +	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
> +	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
> +	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
> +	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
> +	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
> +	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
> +	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
> +
> +	/* vp_conf field values */
> +	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
> +	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
> +	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
> +	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
> +	HDMI_VP_CONF_PR_EN_MASK = 0x10,
> +	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
> +	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
> +	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
> +	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
> +	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
> +	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
> +	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
> +
> +	/* vp_remap field values */
> +	HDMI_VP_REMAP_YCC422_16BIT = 0x0,
> +
> +	/* fc_invidconf field values */
> +	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
> +	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
> +	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
> +	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
> +	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
> +	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
> +	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
> +	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
> +	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
> +	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
> +	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
> +	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
> +	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
> +	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
> +	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
> +	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
> +	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
> +	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
> +	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
> +	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
> +	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
> +
> +
> +	/* fc_aviconf0-fc_aviconf3 field values */
> +	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
> +	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
> +	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
> +	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
> +	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
> +	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
> +	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
> +	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
> +	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
> +	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
> +	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
> +	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
> +	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
> +	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
> +	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
> +	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
> +
> +	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
> +	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
> +	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
> +	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
> +	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
> +	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
> +	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
> +	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
> +	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
> +	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
> +	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
> +	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
> +	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
> +	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
> +
> +	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
> +	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
> +	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
> +	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
> +	HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
> +	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
> +	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
> +	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
> +	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
> +	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
> +	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
> +	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
> +	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
> +	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
> +	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
> +	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
> +	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
> +	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
> +
> +	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
> +	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
> +	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
> +	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
> +	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
> +	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
> +	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
> +	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
> +
> +	/* fc_gcp field values*/
> +	HDMI_FC_GCP_SET_AVMUTE = 0x02,
> +	HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
> +
> +	/* phy_conf0 field values */
> +	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
> +	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
> +	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
> +	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
> +	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
> +	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
> +	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
> +	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
> +	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
> +	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
> +	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
> +	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
> +	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
> +	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
> +
> +	/* phy_tst0 field values */
> +	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
> +	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
> +
> +	/* phy_stat0 field values */
> +	HDMI_PHY_HPD = 0x02,
> +	HDMI_PHY_TX_PHY_LOCK = 0x01,
> +
> +	/* phy_i2cm_slave_addr field values */
> +	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
> +
> +	/* phy_i2cm_operation_addr field values */
> +	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
> +
> +	/* hdmi_phy_i2cm_int_addr */
> +	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
> +
> +	/* hdmi_phy_i2cm_ctlint_addr */
> +	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
> +	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
> +
> +	/* aud_conf0 field values */
> +	HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
> +	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
> +	HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
> +	HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
> +	HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
> +	HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
> +
> +	/* aud_conf0 field values */
> +	HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
> +	HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
> +
> +	/* aud_n3 field values */
> +	HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
> +	HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
> +
> +	/* aud_cts3 field values */
> +	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
> +	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
> +	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
> +	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
> +	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
> +	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
> +	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
> +	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
> +	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
> +	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
> +
> +	/* aud_inputclkfs filed values */
> +	HDMI_AUD_INPUTCLKFS_128 = 0x0,
> +
> +	/* mc_clkdis field values */
> +	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
> +	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
> +	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
> +
> +	/* mc_swrstz field values */
> +	HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
> +	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
> +
> +	/* mc_flowctrl field values */
> +	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
> +	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
> +
> +	/* mc_phyrstz field values */
> +	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
> +	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
> +
> +	/* mc_heacphy_rst field values */
> +	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
> +
> +	/* i2cm filed values */
> +	HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
> +	HDMI_I2CM_SEGADDR_DDC = 0x30,
> +	HDMI_I2CM_OP_RD8_EXT = 0x2,
> +	HDMI_I2CM_OP_RD8 = 0x1,
> +	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
> +	HDMI_I2CM_DIV_FAST_MODE = 0x8,
> +	HDMI_I2CM_DIV_STD_MODE = 0x0,
> +	HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
> +};
> +
> +struct hdmi_mpll_config {
> +	u64 mpixelclock;
> +	/* Mode of Operation and PLL Dividers Control Register */
> +	u32 cpce;
> +	/* PLL Gmp Control Register */
> +	u32 gmp;
> +	/* PLL Current Control Register */
> +	u32 curr;
> +};
> +
> +struct hdmi_phy_config {
> +	u64 mpixelclock;
> +	u32 sym_ctr;    /* clock symbol and transmitter control */
> +	u32 term;       /* transmission termination value */
> +	u32 vlev_ctr;   /* voltage level control */
> +};
> +
> +struct dw_hdmi {
> +	ulong ioaddr;
> +	const struct hdmi_mpll_config *mpll_cfg;
> +	const struct hdmi_phy_config *phy_cfg;
> +	u8 i2c_clk_high;
> +	u8 i2c_clk_low;
> +	u8 reg_io_width;
> +
> +	int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
> +};
> +
> +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
> +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
> +void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
> +
> +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
> +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
> +void dw_hdmi_init(struct dw_hdmi *hdmi);
> +
> +#endif

[U-Boot] [PATCH 3/8] rockchip: video: Split out HDMI controller code

[Jernej Škrabec]

Hi Nickey,

Dne petek, 10. marec 2017 ob 03:19:44 CET je Nickey.Yang napisal(a):
> Hi Jernej,
> 
> 在 2017年03月09日 07:34, Jernej Skrabec 写道:
> > Designware HDMI controller and phy are used in other SoCs as well. Split
> > out platform independent code.
> > 
> > DW HDMI has 8 bit registers but they can be represented as 32 bit
> > registers as well. Add support to select access mode.
> > 
> > EDID reading code use reading by blocks which is not supported by other
> > SoCs in general. Make it more general using byte by byte approach, which
> > is also used in Linux driver.
> > 
> > Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
> > Support custom phys by making controller code independent from phy code.
> > 
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > ---
> 
> I have tested this series of patches in rockchip rk3288 tinker boards.
> 
> Tested-by: Nickey Yang <nickey.yang@rock-chips.com>

Great, thanks!

Best regards,
Jernej

[U-Boot] [PATCH 3/8] rockchip: video: Split out HDMI controller code

[Simon Glass]

On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
> Designware HDMI controller and phy are used in other SoCs as well. Split
> out platform independent code.
>
> DW HDMI has 8 bit registers but they can be represented as 32 bit
> registers as well. Add support to select access mode.
>
> EDID reading code use reading by blocks which is not supported by other
> SoCs in general. Make it more general using byte by byte approach, which
> is also used in Linux driver.
>
> Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
> Support custom phys by making controller code independent from phy code.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
>
>  arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 --------------
>  drivers/video/dw_hdmi.c                          | 764 +++++++++++++++++++++++
>  drivers/video/rockchip/Makefile                  |   2 +-
>  drivers/video/rockchip/rk_hdmi.c                 | 757 +---------------------
>  drivers/video/rockchip/rk_vop.c                  |   1 -
>  include/dw_hdmi.h                                | 486 ++++++++++++++
>  6 files changed, 1275 insertions(+), 1191 deletions(-)
>  delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
>  create mode 100644 drivers/video/dw_hdmi.c
>  create mode 100644 include/dw_hdmi.h

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/8] rockchip: video: Split out HDMI controller code

[Mike Valk]

On Thursday, March 9, 2017 at 12:36:31 AM UTC+1, Jernej Å krabec wrote:
>
> Designware HDMI controller and phy are used in other SoCs as well. Split 
> out platform independent code. 
>
> DW HDMI has 8 bit registers but they can be represented as 32 bit 
> registers as well. Add support to select access mode. 
>
> EDID reading code use reading by blocks which is not supported by other 
> SoCs in general. Make it more general using byte by byte approach, which 
> is also used in Linux driver. 
>
> Finally, not all DW HDMI controllers are accompanied with DW HDMI phy. 
> Support custom phys by making controller code independent from phy code. 
>
> Signed-off-by: Jernej Skrabec <jernej....@siol.net <javascript:>> 
> --- 
>
>  arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 -------------- 
>  drivers/video/dw_hdmi.c                          | 764 
> +++++++++++++++++++++++ 
>  drivers/video/rockchip/Makefile                  |   2 +- 
>  drivers/video/rockchip/rk_hdmi.c                 | 757 
> +--------------------- 
>  drivers/video/rockchip/rk_vop.c                  |   1 - 
>  include/dw_hdmi.h                                | 486 ++++++++++++++ 
>  6 files changed, 1275 insertions(+), 1191 deletions(-) 
>  delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h 
>  create mode 100644 drivers/video/dw_hdmi.c 
>  create mode 100644 include/dw_hdmi.h 
>
> diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h 
> b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h 
> deleted file mode 100644 
> index 0b51d40882..0000000000 
> --- a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h 
> +++ /dev/null 
> @@ -1,456 +0,0 @@ 
> -/* 
> - * Copyright (c) 2015 Google, Inc 
> - * Copyright 2014 Rockchip Inc. 
> - * Copyright (C) 2011 Freescale Semiconductor, Inc. 
> - * 
> - * SPDX-License-Identifier:        GPL-2.0+ 
> - */ 
> - 
> -#ifndef _ASM_ARCH_HDMI_H 
> -#define _ASM_ARCH_HDMI_H 
> - 
> - 
> -#define HDMI_EDID_BLOCK_SIZE            128 
> - 
> -struct rk3288_hdmi { 
> -        u32 reserved0[0x100]; 
> -        u32 ih_fc_stat0; 
> -        u32 ih_fc_stat1; 
> -        u32 ih_fc_stat2; 
> -        u32 ih_as_stat0; 
> -        u32 ih_phy_stat0; 
> -        u32 ih_i2cm_stat0; 
> -        u32 ih_cec_stat0; 
> -        u32 ih_vp_stat0; 
> -        u32 ih_i2cmphy_stat0; 
> -        u32 ih_ahbdmaaud_stat0; 
> -        u32 reserved1[0x17f-0x109]; 
> -        u32 ih_mute_fc_stat0; 
> -        u32 ih_mute_fc_stat1; 
> -        u32 ih_mute_fc_stat2; 
> -        u32 ih_mute_as_stat0; 
> -        u32 ih_mute_phy_stat0; 
> -        u32 ih_mute_i2cm_stat0; 
> -        u32 ih_mute_cec_stat0; 
> -        u32 ih_mute_vp_stat0; 
> -        u32 ih_mute_i2cmphy_stat0; 
> -        u32 ih_mute_ahbdmaaud_stat0; 
> -        u32 reserved2[0x1fe - 0x189]; 
> -        u32 ih_mute; 
> -        u32 tx_invid0; 
> -        u32 tx_instuffing; 
> -        u32 tx_gydata0; 
> -        u32 tx_gydata1; 
> -        u32 tx_rcrdata0; 
> -        u32 tx_rcrdata1; 
> -        u32 tx_bcbdata0; 
> -        u32 tx_bcbdata1; 
> -        u32 reserved3[0x7ff-0x207]; 
> -        u32 vp_status; 
> -        u32 vp_pr_cd; 
> -        u32 vp_stuff; 
> -        u32 vp_remap; 
> -        u32 vp_conf; 
> -        u32 vp_stat; 
> -        u32 vp_int; 
> -        u32 vp_mask; 
> -        u32 vp_pol; 
> -        u32 reserved4[0xfff-0x808]; 
> -        u32 fc_invidconf; 
> -        u32 fc_inhactv0; 
> -        u32 fc_inhactv1; 
> -        u32 fc_inhblank0; 
> -        u32 fc_inhblank1; 
> -        u32 fc_invactv0; 
> -        u32 fc_invactv1; 
> -        u32 fc_invblank; 
> -        u32 fc_hsyncindelay0; 
> -        u32 fc_hsyncindelay1; 
> -        u32 fc_hsyncinwidth0; 
> -        u32 fc_hsyncinwidth1; 
> -        u32 fc_vsyncindelay; 
> -        u32 fc_vsyncinwidth; 
> -        u32 fc_infreq0; 
> -        u32 fc_infreq1; 
> -        u32 fc_infreq2; 
> -        u32 fc_ctrldur; 
> -        u32 fc_exctrldur; 
> -        u32 fc_exctrlspac; 
> -        u32 fc_ch0pream; 
> -        u32 fc_ch1pream; 
> -        u32 fc_ch2pream; 
> -        u32 fc_aviconf3; 
> -        u32 fc_gcp; 
> -        u32 fc_aviconf0; 
> -        u32 fc_aviconf1; 
> -        u32 fc_aviconf2; 
> -        u32 fc_avivid; 
> -        u32 fc_avietb0; 
> -        u32 fc_avietb1; 
> -        u32 fc_avisbb0; 
> -        u32 fc_avisbb1; 
> -        u32 fc_avielb0; 
> -        u32 fc_avielb1; 
> -        u32 fc_avisrb0; 
> -        u32 fc_avisrb1; 
> -        u32 fc_audiconf0; 
> -        u32 fc_audiconf1; 
> -        u32 fc_audiconf2; 
> -        u32 fc_audiconf3; 
> -        u32 fc_vsdieeeid0; 
> -        u32 fc_vsdsize; 
> -        u32 reserved7[0x2fff-0x102a]; 
> -        u32 phy_conf0; 
> -        u32 phy_tst0; 
> -        u32 phy_tst1; 
> -        u32 phy_tst2; 
> -        u32 phy_stat0; 
> -        u32 phy_int0; 
> -        u32 phy_mask0; 
> -        u32 phy_pol0; 
> -        u32 reserved8[0x301f-0x3007]; 
> -        u32 phy_i2cm_slave_addr; 
> -        u32 phy_i2cm_address_addr; 
> -        u32 phy_i2cm_datao_1_addr; 
> -        u32 phy_i2cm_datao_0_addr; 
> -        u32 phy_i2cm_datai_1_addr; 
> -        u32 phy_i2cm_datai_0_addr; 
> -        u32 phy_i2cm_operation_addr; 
> -        u32 phy_i2cm_int_addr; 
> -        u32 phy_i2cm_ctlint_addr; 
> -        u32 phy_i2cm_div_addr; 
> -        u32 phy_i2cm_softrstz_addr; 
> -        u32 phy_i2cm_ss_scl_hcnt_1_addr; 
> -        u32 phy_i2cm_ss_scl_hcnt_0_addr; 
> -        u32 phy_i2cm_ss_scl_lcnt_1_addr; 
> -        u32 phy_i2cm_ss_scl_lcnt_0_addr; 
> -        u32 phy_i2cm_fs_scl_hcnt_1_addr; 
> -        u32 phy_i2cm_fs_scl_hcnt_0_addr; 
> -        u32 phy_i2cm_fs_scl_lcnt_1_addr; 
> -        u32 phy_i2cm_fs_scl_lcnt_0_addr; 
> -        u32 reserved9[0x30ff-0x3032]; 
> -        u32 aud_conf0; 
> -        u32 aud_conf1; 
> -        u32 aud_int; 
> -        u32 aud_conf2; 
> -        u32 aud_int1; 
> -        u32 reserved32[0x31ff-0x3104]; 
> -        u32 aud_n1; 
> -        u32 aud_n2; 
> -        u32 aud_n3; 
> -        u32 aud_cts1; 
> -        u32 aud_cts2; 
> -        u32 aud_cts3; 
> -        u32 aud_inputclkfs; 
> -        u32 reserved12[0x3fff-0x3206]; 
> -        u32 mc_sfrdiv; 
> -        u32 mc_clkdis; 
> -        u32 mc_swrstz; 
> -        u32 mc_opctrl; 
> -        u32 mc_flowctrl; 
> -        u32 mc_phyrstz; 
> -        u32 mc_lockonclock; 
> -        u32 mc_heacphy_rst; 
> -        u32 reserved13[0x40ff-0x4007]; 
> -        u32 csc_cfg; 
> -        u32 csc_scale; 
> -        struct { 
> -                u32 msb; 
> -                u32 lsb; 
> -        } csc_coef[3][4]; 
> -        u32 reserved17[0x7dff-0x4119]; 
> -        u32 i2cm_slave; 
> -        u32 i2c_address; 
> -        u32 i2cm_datao; 
> -        u32 i2cm_datai; 
> -        u32 i2cm_operation; 
> -        u32 i2cm_int; 
> -        u32 i2cm_ctlint; 
> -        u32 i2cm_div; 
> -        u32 i2cm_segaddr; 
> -        u32 i2cm_softrstz; 
> -        u32 i2cm_segptr; 
> -        u32 i2cm_ss_scl_hcnt_1_addr; 
> -        u32 i2cm_ss_scl_hcnt_0_addr; 
> -        u32 i2cm_ss_scl_lcnt_1_addr; 
> -        u32 i2cm_ss_scl_lcnt_0_addr; 
> -        u32 i2cm_fs_scl_hcnt_1_addr; 
> -        u32 i2cm_fs_scl_hcnt_0_addr; 
> -        u32 i2cm_fs_scl_lcnt_1_addr; 
> -        u32 i2cm_fs_scl_lcnt_0_addr; 
> -        u32 reserved18[0x7e1f-0x7e12]; 
> -        u32 i2cm_buf0; 
> -}; 
> -check_member(rk3288_hdmi, i2cm_buf0, 0x1f880); 
> - 
> -enum { 
> -        /* HDMI PHY registers define */ 
> -        PHY_OPMODE_PLLCFG = 0x06, 
> -        PHY_CKCALCTRL = 0x05, 
> -        PHY_CKSYMTXCTRL = 0x09, 
> -        PHY_VLEVCTRL = 0x0e, 
> -        PHY_PLLCURRCTRL = 0x10, 
> -        PHY_PLLPHBYCTRL = 0x13, 
> -        PHY_PLLGMPCTRL = 0x15, 
> -        PHY_PLLCLKBISTPHASE = 0x17, 
> -        PHY_TXTERM = 0x19, 
> - 
> -        /* ih_phy_stat0 field values */ 
> -        HDMI_IH_PHY_STAT0_HPD = 0x1, 
> - 
> -        /* ih_mute field values */ 
> -        HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, 
> -        HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, 
> - 
> -        /* tx_invid0 field values */ 
> -        HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, 
> -        HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, 
> -        HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, 
> - 
> -        /* tx_instuffing field values */ 
> -        HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, 
> -        HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, 
> -        HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, 
> - 
> -        /* vp_pr_cd field values */ 
> -        HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, 
> -        HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, 
> -        HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, 
> -        HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, 
> - 
> -        /* vp_stuff field values */ 
> -        HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, 
> -        HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, 
> -        HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, 
> -        HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, 
> -        HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, 
> -        HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, 
> -        HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, 
> -        HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, 
> - 
> -        /* vp_conf field values */ 
> -        HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, 
> -        HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, 
> -        HDMI_VP_CONF_PP_EN_ENMASK = 0x20, 
> -        HDMI_VP_CONF_PP_EN_DISABLE = 0x00, 
> -        HDMI_VP_CONF_PR_EN_MASK = 0x10, 
> -        HDMI_VP_CONF_PR_EN_DISABLE = 0x00, 
> -        HDMI_VP_CONF_YCC422_EN_MASK = 0x8, 
> -        HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, 
> -        HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, 
> -        HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, 
> -        HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, 
> -        HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, 
> - 
> -        /* vp_remap field values */ 
> -        HDMI_VP_REMAP_YCC422_16BIT = 0x0, 
> - 
> -        /* fc_invidconf field values */ 
> -        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, 
> -        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, 
> -        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, 
> -        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, 
> -        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, 
> -        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 
> -        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, 
> -        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, 
> -        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 
> -        HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, 
> -        HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, 
> -        HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, 
> -        HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, 
> -        HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, 
> -        HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, 
> -        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, 
> -        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, 
> -        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, 
> -        HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, 
> -        HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, 
> -        HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, 
> - 
> - 
> -        /* fc_aviconf0-fc_aviconf3 field values */ 
> -        HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, 
> -        HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, 
> -        HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, 
> -        HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, 
> -        HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, 
> -        HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, 
> -        HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, 
> -        HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, 
> -        HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, 
> -        HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, 
> -        HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, 
> -        HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, 
> -        HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, 
> -        HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, 
> -        HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, 
> -        HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, 
> - 
> -        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, 
> -        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, 
> -        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, 
> -        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, 
> -        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, 
> -        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, 
> -        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, 
> -        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, 
> -        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, 
> -        HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, 
> -        HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, 
> -        HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, 
> -        HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, 
> -        HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, 
> - 
> -        HDMI_FC_AVICONF2_SCALING_MASK = 0x03, 
> -        HDMI_FC_AVICONF2_SCALING_NONE = 0x00, 
> -        HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, 
> -        HDMI_FC_AVICONF2_SCALING_VERT = 0x02, 
> -        HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, 
> -        HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, 
> -        HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, 
> -        HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, 
> -        HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, 
> -        HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, 
> -        HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, 
> -        HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, 
> -        HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, 
> -        HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, 
> -        HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, 
> -        HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, 
> -        HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, 
> -        HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, 
> - 
> -        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, 
> -        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, 
> -        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, 
> -        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, 
> -        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, 
> -        HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, 
> -        HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, 
> -        HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, 
> - 
> -        /* fc_gcp field values*/ 
> -        HDMI_FC_GCP_SET_AVMUTE = 0x02, 
> -        HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, 
> - 
> -        /* phy_conf0 field values */ 
> -        HDMI_PHY_CONF0_PDZ_MASK = 0x80, 
> -        HDMI_PHY_CONF0_PDZ_OFFSET = 7, 
> -        HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, 
> -        HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, 
> -        HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, 
> -        HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, 
> -        HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, 
> -        HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, 
> -        HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, 
> -        HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, 
> -        HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, 
> -        HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, 
> -        HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, 
> -        HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, 
> - 
> -        /* phy_tst0 field values */ 
> -        HDMI_PHY_TST0_TSTCLR_MASK = 0x20, 
> -        HDMI_PHY_TST0_TSTCLR_OFFSET = 5, 
> - 
> -        /* phy_stat0 field values */ 
> -        HDMI_PHY_HPD = 0x02, 
> -        HDMI_PHY_TX_PHY_LOCK = 0x01, 
> - 
> -        /* phy_i2cm_slave_addr field values */ 
> -        HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, 
> - 
> -        /* phy_i2cm_operation_addr field values */ 
> -        HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, 
> - 
> -        /* hdmi_phy_i2cm_int_addr */ 
> -        HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, 
> - 
> -        /* hdmi_phy_i2cm_ctlint_addr */ 
> -        HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, 
> -        HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, 
> - 
> -        /* aud_conf0 field values */ 
> -        HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, 
> -        HDMI_AUD_CONF0_I2S_SELECT = 0x20, 
> -        HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, 
> -        HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, 
> -        HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, 
> -        HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, 
> - 
> -        /* aud_conf0 field values */ 
> -        HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, 
> -        HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, 
> - 
> -        /* aud_n3 field values */ 
> -        HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, 
> -        HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, 
> - 
> -        /* aud_cts3 field values */ 
> -        HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, 
> -        HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, 
> -        HDMI_AUD_CTS3_N_SHIFT_1 = 0, 
> -        HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, 
> -        HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, 
> -        HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, 
> -        HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, 
> -        HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, 
> -        HDMI_AUD_CTS3_CTS_MANUAL = 0x10, 
> -        HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, 
> - 
> -        /* aud_inputclkfs filed values */ 
> -        HDMI_AUD_INPUTCLKFS_128 = 0x0, 
> - 
> -        /* mc_clkdis field values */ 
> -        HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, 
> -        HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, 
> -        HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, 
> - 
> -        /* mc_swrstz field values */ 
> -        HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, 
> -        HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, 
> - 
> -        /* mc_flowctrl field values */ 
> -        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, 
> -        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, 
> - 
> -        /* mc_phyrstz field values */ 
> -        HDMI_MC_PHYRSTZ_ASSERT = 0x0, 
> -        HDMI_MC_PHYRSTZ_DEASSERT = 0x1, 
> - 
> -        /* mc_heacphy_rst field values */ 
> -        HDMI_MC_HEACPHY_RST_ASSERT = 0x1, 
> - 
> -        /* csc_cfg field values */ 
> -        HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, 
> - 
> -        /* csc_scale field values */ 
> -        HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0, 
> -        HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, 
> -        HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, 
> -        HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, 
> -        HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, 
> -        HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, 
> - 
> -        /* i2cm filed values */ 
> -        HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, 
> -        HDMI_I2CM_SEGADDR_DDC = 0x30, 
> -        HDMI_I2CM_OPT_RD8_EXT = 0x8, 
> -        HDMI_I2CM_OPT_RD8 = 0x4, 
> -        HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, 
> -        HDMI_I2CM_DIV_FAST_MODE = 0x8, 
> -        HDMI_I2CM_DIV_STD_MODE = 0x0, 
> -        HDMI_I2CM_SOFTRSTZ = 0x1, 
> -}; 
> - 
> -/* 
> -struct display_timing; 
> -struct rk3288_grf; 
> - 
> -int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id); 
> -int rk_hdmi_enable(const struct display_timing *edid); 
> -int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing 
> *edid); 
> -*/ 
> - 
> -#endif 
> diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c 
> new file mode 100644 
> index 0000000000..8a53109823 
> --- /dev/null 
> +++ b/drivers/video/dw_hdmi.c 
> @@ -0,0 +1,764 @@ 
> +/* 
> + * Copyright (c) 2015 Google, Inc 
> + * Copyright 2014 Rockchip Inc. 
> + * Copyright 2017 Jernej Skrabec <jernej....@siol.net <javascript:>> 
>
You're removing Freescale from the copyright list and shouldn't you be on 
top?

Thanks for your effort!

+ * 
> + * SPDX-License-Identifier:        GPL-2.0+ 
> + */ 
> + 
> +#include <common.h> 
> +#include <fdtdec.h> 
> +#include <asm/io.h> 
> +#include "dw_hdmi.h" 
> + 
> +struct tmds_n_cts { 
> +        u32 tmds; 
> +        u32 cts; 
> +        u32 n; 
> +}; 
> + 
> +static const struct tmds_n_cts n_cts_table[] = { 
> +        { 
> +                .tmds = 25175000, .n = 6144, .cts = 25175, 
> +        }, { 
> +                .tmds = 25200000, .n = 6144, .cts = 25200, 
> +        }, { 
> +                .tmds = 27000000, .n = 6144, .cts = 27000, 
> +        }, { 
> +                .tmds = 27027000, .n = 6144, .cts = 27027, 
> +        }, { 
> +                .tmds = 40000000, .n = 6144, .cts = 40000, 
> +        }, { 
> +                .tmds = 54000000, .n = 6144, .cts = 54000, 
> +        }, { 
> +                .tmds = 54054000, .n = 6144, .cts = 54054, 
> +        }, { 
> +                .tmds = 65000000, .n = 6144, .cts = 65000, 
> +        }, { 
> +                .tmds = 74176000, .n = 11648, .cts = 140625, 
> +        }, { 
> +                .tmds = 74250000, .n = 6144, .cts = 74250, 
> +        }, { 
> +                .tmds = 83500000, .n = 6144, .cts = 83500, 
> +        }, { 
> +                .tmds = 106500000, .n = 6144, .cts = 106500, 
> +        }, { 
> +                .tmds = 108000000, .n = 6144, .cts = 108000, 
> +        }, { 
> +                .tmds = 148352000, .n = 5824, .cts = 140625, 
> +        }, { 
> +                .tmds = 148500000, .n = 6144, .cts = 148500, 
> +        }, { 
> +                .tmds = 297000000, .n = 5120, .cts = 247500, 
> +        } 
> +}; 
> + 
> +static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset) 
> +{ 
> +        switch (hdmi->reg_io_width) { 
> +        case 1: 
> +                writeb(val, hdmi->ioaddr + offset); 
> +                break; 
> +        case 4: 
> +                writel(val, hdmi->ioaddr + (offset << 2)); 
> +                break; 
> +        default: 
> +                debug("reg_io_width has unsupported width!\n"); 
> +                break; 
> +        } 
> +} 
> + 
> +static u8 hdmi_read(struct dw_hdmi *hdmi, int offset) 
> +{ 
> +        switch (hdmi->reg_io_width) { 
> +        case 1: 
> +                return readb(hdmi->ioaddr + offset); 
> +        case 4: 
> +                return readl(hdmi->ioaddr + (offset << 2)); 
> +        default: 
> +                debug("reg_io_width has unsupported width!\n"); 
> +                break; 
> +        } 
> + 
> +        return 0; 
> +} 
> + 
> +static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 
> data) 
> +{ 
> +        u8 val = hdmi_read(hdmi, reg) & ~mask; 
> + 
> +        val |= data & mask; 
> +        hdmi_write(hdmi, val, reg); 
> +} 
> + 
> +static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 
> cts) 
> +{ 
> +        uint cts3; 
> +        uint n3; 
> + 
> +        /* first set ncts_atomic_write (if present) */ 
> +        n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE; 
> +        hdmi_write(hdmi, n3, HDMI_AUD_N3); 
> + 
> +        /* set cts_manual (if present) */ 
> +        cts3 = HDMI_AUD_CTS3_CTS_MANUAL; 
> + 
> +        cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET; 
> +        cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK; 
> + 
> +        /* write cts values; cts3 must be written first */ 
> +        hdmi_write(hdmi, cts3, HDMI_AUD_CTS3); 
> +        hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 
> +        hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1); 
> + 
> +        /* write n values; n1 must be written last */ 
> +        n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK; 
> +        hdmi_write(hdmi, n3, HDMI_AUD_N3); 
> +        hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 
> +        hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3); 
> + 
> +        hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS); 
> +} 
> + 
> +static int hdmi_lookup_n_cts(u32 pixel_clk) 
> +{ 
> +        int i; 
> + 
> +        for (i = 0; i < ARRAY_SIZE(n_cts_table); i++) 
> +                if (pixel_clk <= n_cts_table[i].tmds) 
> +                        break; 
> + 
> +        if (i >= ARRAY_SIZE(n_cts_table)) 
> +                return -1; 
> + 
> +        return i; 
> +} 
> + 
> +static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 
> pixel_clk) 
> +{ 
> +        u32 clk_n, clk_cts; 
> +        int index; 
> + 
> +        index = hdmi_lookup_n_cts(pixel_clk); 
> +        if (index == -1) { 
> +                debug("audio not supported for pixel clk %d\n", 
> pixel_clk); 
> +                return; 
> +        } 
> + 
> +        clk_n = n_cts_table[index].n; 
> +        clk_cts = n_cts_table[index].cts; 
> +        hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts); 
> +} 
> + 
> +/* 
> + * this submodule is responsible for the video data synchronization. 
> + * for example, for rgb 4:4:4 input, the data map is defined as 
> + *                        pin{47~40} <==> r[7:0] 
> + *                        pin{31~24} <==> g[7:0] 
> + *                        pin{15~8}  <==> b[7:0] 
> + */ 
> +static void hdmi_video_sample(struct dw_hdmi *hdmi) 
> +{ 
> +        u32 color_format = 0x01; 
> +        uint val; 
> + 
> +        val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 
> +              ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 
> +              HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 
> + 
> +        hdmi_write(hdmi, val, HDMI_TX_INVID0); 
> + 
> +        /* enable tx stuffing: when de is inactive, fix the output data 
> to 0 */ 
> +        val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 
> +              HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 
> +              HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 
> +        hdmi_write(hdmi, val, HDMI_TX_INSTUFFING); 
> +        hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0); 
> +        hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1); 
> +        hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0); 
> +        hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1); 
> +        hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0); 
> +        hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1); 
> +} 
> + 
> +static void hdmi_video_packetize(struct dw_hdmi *hdmi) 
> +{ 
> +        u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 
> +        u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT; 
> +        u32 color_depth = 0; 
> +        uint val, vp_conf; 
> + 
> +        /* set the packetizer registers */ 
> +        val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 
> +                HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 
> +                ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 
> +                HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 
> +        hdmi_write(hdmi, val, HDMI_VP_PR_CD); 
> + 
> +        hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK, 
> +                 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); 
> + 
> +        /* data from pixel repeater block */ 
> +        vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 
> +                  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 
> + 
> +        hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK | 
> +                 HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); 
> + 
> +        hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 
> +                 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); 
> + 
> +        hdmi_write(hdmi, remap_size, HDMI_VP_REMAP); 
> + 
> +        vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 
> +                  HDMI_VP_CONF_PP_EN_DISABLE | 
> +                  HDMI_VP_CONF_YCC422_EN_DISABLE; 
> + 
> +        hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK | 
> +                 HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, 
> +                 vp_conf); 
> + 
> +        hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK | 
> +                 HDMI_VP_STUFF_YCC422_STUFFING_MASK, 
> +                 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 
> +                 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); 
> + 
> +        hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 
> +                 output_select); 
> +} 
> + 
> +static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK, 
> +                 bit << HDMI_PHY_TST0_TSTCLR_OFFSET); 
> +} 
> + 
> +static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec) 
> +{ 
> +        ulong start; 
> +        u32 val; 
> + 
> +        start = get_timer(0); 
> +        do { 
> +                val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0); 
> +                if (val & 0x3) { 
> +                        hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 
> +                        return 0; 
> +                } 
> + 
> +                udelay(100); 
> +        } while (get_timer(start) < msec); 
> + 
> +        return 1; 
> +} 
> + 
> +static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint 
> addr) 
> +{ 
> +        hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0); 
> +        hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 
> +        hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR); 
> +        hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR); 
> +        hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 
> +                   HDMI_PHY_I2CM_OPERATION_ADDR); 
> + 
> +        hdmi_phy_wait_i2c_done(hdmi, 1000); 
> +} 
> + 
> +static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK, 
> +                 enable << HDMI_PHY_CONF0_PDZ_OFFSET); 
> +} 
> + 
> +static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK, 
> +                 enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); 
> +} 
> + 
> +static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK, 
> +                 enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); 
> +} 
> + 
> +static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, 
> +                 enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); 
> +} 
> + 
> +static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_PHY_CONF0, 
> +                 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, 
> +                 enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); 
> +} 
> + 
> +static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_PHY_CONF0, 
> +                 HDMI_PHY_CONF0_SELDATAENPOL_MASK, 
> +                 enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); 
> +} 
> + 
> +static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, 
> +                                           uint enable) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK, 
> +                 enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); 
> +} 
> + 
> +static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock) 
> +{ 
> +        ulong start; 
> +        uint i, val; 
> + 
> +        if (!hdmi->mpll_cfg || !hdmi->phy_cfg) 
> +                return -1; 
> + 
> +        /* gen2 tx power off */ 
> +        hdmi_phy_gen2_txpwron(hdmi, 0); 
> + 
> +        /* gen2 pddq */ 
> +        hdmi_phy_gen2_pddq(hdmi, 1); 
> + 
> +        /* phy reset */ 
> +        hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ); 
> +        hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ); 
> +        hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, 
> HDMI_MC_HEACPHY_RST); 
> + 
> +        hdmi_phy_test_clear(hdmi, 1); 
> +        hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 
> +                   HDMI_PHY_I2CM_SLAVE_ADDR); 
> +        hdmi_phy_test_clear(hdmi, 0); 
> + 
> +        /* pll/mpll cfg - always match on final entry */ 
> +        for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++) 
> +                if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock) 
> +                        break; 
> + 
> +        hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, 
> PHY_OPMODE_PLLCFG); 
> +        hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL); 
> +        hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, 
> PHY_PLLCURRCTRL); 
> + 
> +        hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL); 
> +        hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE); 
> + 
> +        for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++) 
> +                if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock) 
> +                        break; 
> + 
> +        /* 
> +         * resistance term 133ohm cfg 
> +         * preemp cgf 0.00 
> +         * tx/ck lvl 10 
> +         */ 
> +        hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM); 
> +        hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, 
> PHY_CKSYMTXCTRL); 
> +        hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, 
> PHY_VLEVCTRL); 
> + 
> +        /* remove clk term */ 
> +        hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL); 
> + 
> +        hdmi_phy_enable_power(hdmi, 1); 
> + 
> +        /* toggle tmds enable */ 
> +        hdmi_phy_enable_tmds(hdmi, 0); 
> +        hdmi_phy_enable_tmds(hdmi, 1); 
> + 
> +        /* gen2 tx power on */ 
> +        hdmi_phy_gen2_txpwron(hdmi, 1); 
> +        hdmi_phy_gen2_pddq(hdmi, 0); 
> + 
> +        hdmi_phy_enable_spare(hdmi, 1); 
> + 
> +        /* wait for phy pll lock */ 
> +        start = get_timer(0); 
> +        do { 
> +                val = hdmi_read(hdmi, HDMI_PHY_STAT0); 
> +                if (!(val & HDMI_PHY_TX_PHY_LOCK)) 
> +                        return 0; 
> + 
> +                udelay(100); 
> +        } while (get_timer(start) < 5); 
> + 
> +        return -1; 
> +} 
> + 
> +static void hdmi_av_composer(struct dw_hdmi *hdmi, 
> +                             const struct display_timing *edid) 
> +{ 
> +        bool mdataenablepolarity = true; 
> +        uint inv_val; 
> +        uint hbl; 
> +        uint vbl; 
> + 
> +        hbl = edid->hback_porch.typ + edid->hfront_porch.typ + 
> +                        edid->hsync_len.typ; 
> +        vbl = edid->vback_porch.typ + edid->vfront_porch.typ + 
> +                        edid->vsync_len.typ; 
> + 
> +        /* set up hdmi_fc_invidconf */ 
> +        inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE; 
> + 
> +        inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ? 
> +                   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 
> +                   HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); 
> + 
> +        inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ? 
> +                   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 
> +                   HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); 
> + 
> +        inv_val |= (mdataenablepolarity ? 
> +                   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 
> +                   HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 
> + 
> +        /* 
> +         * TODO(s... at chromium.org <javascript:>>: Need to check for HDMI 
> / DVI 
> +         * inv_val |= (edid->hdmi_monitor_detected ? 
> +         *           HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 
> +         *           HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE); 
> +         */ 
> +        inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE; 
> + 
> +        inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 
> + 
> +        inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 
> + 
> +        hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF); 
> + 
> +        /* set up horizontal active pixel width */ 
> +        hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1); 
> +        hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0); 
> + 
> +        /* set up vertical active lines */ 
> +        hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1); 
> +        hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0); 
> + 
> +        /* set up horizontal blanking pixel region width */ 
> +        hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1); 
> +        hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0); 
> + 
> +        /* set up vertical blanking pixel region width */ 
> +        hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK); 
> + 
> +        /* set up hsync active edge delay width (in pixel clks) */ 
> +        hdmi_write(hdmi, edid->hfront_porch.typ >> 8, 
> HDMI_FC_HSYNCINDELAY1); 
> +        hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0); 
> + 
> +        /* set up vsync active edge delay (in lines) */ 
> +        hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY); 
> + 
> +        /* set up hsync active pulse width (in pixel clks) */ 
> +        hdmi_write(hdmi, edid->hsync_len.typ >> 8, 
> HDMI_FC_HSYNCINWIDTH1); 
> +        hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0); 
> + 
> +        /* set up vsync active edge delay (in lines) */ 
> +        hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH); 
> +} 
> + 
> +/* hdmi initialization step b.4 */ 
> +static void hdmi_enable_video_path(struct dw_hdmi *hdmi) 
> +{ 
> +        uint clkdis; 
> + 
> +        /* control period minimum duration */ 
> +        hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR); 
> +        hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR); 
> +        hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC); 
> + 
> +        /* set to fill tmds data channels */ 
> +        hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM); 
> +        hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM); 
> +        hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM); 
> + 
> +        hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 
> +                   HDMI_MC_FLOWCTRL); 
> + 
> +        /* enable pixel clock and tmds data path */ 
> +        clkdis = 0x7f; 
> +        clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 
> +        hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); 
> + 
> +        clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 
> +        hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); 
> + 
> +        clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 
> +        hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); 
> +} 
> + 
> +/* workaround to clear the overflow condition */ 
> +static void hdmi_clear_overflow(struct dw_hdmi *hdmi) 
> +{ 
> +        uint val, count; 
> + 
> +        /* tmds software reset */ 
> +        hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 
> HDMI_MC_SWRSTZ); 
> + 
> +        val = hdmi_read(hdmi, HDMI_FC_INVIDCONF); 
> + 
> +        for (count = 0; count < 4; count++) 
> +                hdmi_write(hdmi, val, HDMI_FC_INVIDCONF); 
> +} 
> + 
> +static void hdmi_audio_set_format(struct dw_hdmi *hdmi) 
> +{ 
> +        hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | 
> HDMI_AUD_CONF0_I2S_IN_EN_0, 
> +                   HDMI_AUD_CONF0); 
> + 
> + 
> +        hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE | 
> +                   HDMI_AUD_CONF1_I2S_WIDTH_16BIT, HDMI_AUD_CONF1); 
> + 
> +        hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2); 
> +} 
> + 
> +static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi) 
> +{ 
> +        hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, 
> HDMI_MC_SWRSTZ); 
> +        hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, 
> HDMI_AUD_CONF0); 
> + 
> +        hdmi_write(hdmi, 0x00, HDMI_AUD_INT); 
> +        hdmi_write(hdmi, 0x00, HDMI_AUD_INT1); 
> +} 
> + 
> +static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi) 
> +{ 
> +        uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD; 
> + 
> +        return !!val; 
> +} 
> + 
> +static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 
> +{ 
> +        u32 val; 
> +        ulong start; 
> + 
> +        start = get_timer(0); 
> +        do { 
> +                val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0); 
> +                if (val & 0x2) { 
> +                        hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0); 
> +                        return 0; 
> +                } 
> + 
> +                udelay(100); 
> +        } while (get_timer(start) < msec); 
> + 
> +        return 1; 
> +} 
> + 
> +static void hdmi_ddc_reset(struct dw_hdmi *hdmi) 
> +{ 
> +        hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0); 
> +} 
> + 
> +static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff) 
> +{ 
> +        int shift = (block % 2) * 0x80; 
> +        int edid_read_err = 0; 
> +        u32 trytime = 5; 
> +        u32 n; 
> + 
> +        /* set ddc i2c clk which devided from ddc_clk to 100khz */ 
> +        hdmi_write(hdmi, hdmi->i2c_clk_high, 
> HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 
> +        hdmi_write(hdmi, hdmi->i2c_clk_low, 
> HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 
> +        hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE, 
> +                 HDMI_I2CM_DIV_STD_MODE); 
> + 
> +        hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE); 
> +        hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR); 
> +        hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR); 
> + 
> +        while (trytime--) { 
> +                edid_read_err = 0; 
> + 
> +                for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) { 
> +                        hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS); 
> + 
> +                        if (block == 0) 
> +                                hdmi_write(hdmi, HDMI_I2CM_OP_RD8, 
> +                                           HDMI_I2CM_OPERATION); 
> +                        else 
> +                                hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT, 
> +                                           HDMI_I2CM_OPERATION); 
> + 
> +                        if (hdmi_ddc_wait_i2c_done(hdmi, 10)) { 
> +                                hdmi_ddc_reset(hdmi); 
> +                                edid_read_err = 1; 
> +                                break; 
> +                        } 
> + 
> +                        buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI); 
> +                } 
> + 
> +                if (!edid_read_err) 
> +                        break; 
> +        } 
> + 
> +        return edid_read_err; 
> +} 
> + 
> +static const u8 pre_buf[] = { 
> +        0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 
> +        0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00, 
> +        0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78, 
> +        0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27, 
> +        0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f, 
> +        0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00, 
> +        0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a, 
> +        0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c, 
> +        0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 
> +        0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c, 
> +        0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37, 
> +        0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32, 
> +        0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20, 
> +        0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, 
> +        0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53, 
> +        0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0, 
> +        0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03, 
> +        0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f, 
> +        0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07, 
> +        0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00, 
> +        0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0, 
> +        0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e, 
> +        0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72, 
> +        0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00, 
> +        0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d, 
> +        0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28, 
> +        0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 
> +        0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20, 
> +        0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00, 
> +        0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
> +        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
> +        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9, 
> +}; 
> + 
> +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) 
> +{ 
> +        int i, ret; 
> + 
> +        /* hdmi phy spec says to do the phy initialization sequence twice 
> */ 
> +        for (i = 0; i < 2; i++) { 
> +                hdmi_phy_sel_data_en_pol(hdmi, 1); 
> +                hdmi_phy_sel_interface_control(hdmi, 0); 
> +                hdmi_phy_enable_tmds(hdmi, 0); 
> +                hdmi_phy_enable_power(hdmi, 0); 
> + 
> +                ret = hdmi_phy_configure(hdmi, mpixelclock); 
> +                if (ret) { 
> +                        debug("hdmi phy config failure %d\n", ret); 
> +                        return ret; 
> +                } 
> +        } 
> + 
> +        return 0; 
> +} 
> + 
> +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi) 
> +{ 
> +        ulong start; 
> + 
> +        start = get_timer(0); 
> +        do { 
> +                if (hdmi_get_plug_in_status(hdmi)) 
> +                        return 0; 
> +                udelay(100); 
> +        } while (get_timer(start) < 300); 
> + 
> +        return -1; 
> +} 
> + 
> +void dw_hdmi_phy_init(struct dw_hdmi *hdmi) 
> +{ 
> +        /* enable phy i2cm done irq */ 
> +        hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 
> +                   HDMI_PHY_I2CM_INT_ADDR); 
> + 
> +        /* enable phy i2cm nack & arbitration error irq */ 
> +        hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 
> +                   HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 
> +                   HDMI_PHY_I2CM_CTLINT_ADDR); 
> + 
> +        /* enable cable hot plug irq */ 
> +        hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0); 
> + 
> +        /* clear hotplug interrupts */ 
> +        hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); 
> +} 
> + 
> +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size) 
> +{ 
> +        u32 edid_size = HDMI_EDID_BLOCK_SIZE; 
> +        int ret; 
> + 
> +        if (0) { 
> +                edid_size = sizeof(pre_buf); 
> +                memcpy(buf, pre_buf, edid_size); 
> +        } else { 
> +                ret = hdmi_read_edid(hdmi, 0, buf); 
> +                if (ret) { 
> +                        debug("failed to read edid.\n"); 
> +                        return -1; 
> +                } 
> + 
> +                if (buf[0x7e] != 0) { 
> +                        hdmi_read_edid(hdmi, 1, buf + 
> HDMI_EDID_BLOCK_SIZE); 
> +                        edid_size += HDMI_EDID_BLOCK_SIZE; 
> +                } 
> +        } 
> + 
> +        return edid_size; 
> +} 
> + 
> +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing 
> *edid) 
> +{ 
> +        int ret; 
> + 
> +        debug("hdmi, mode info : clock %d hdis %d vdis %d\n", 
> +              edid->pixelclock.typ, edid->hactive.typ, 
> edid->vactive.typ); 
> + 
> +        hdmi_av_composer(hdmi, edid); 
> + 
> +        ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); 
> +        if (ret) 
> +                return ret; 
> + 
> +        hdmi_enable_video_path(hdmi); 
> + 
> +        hdmi_audio_fifo_reset(hdmi); 
> +        hdmi_audio_set_format(hdmi); 
> +        hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ); 
> + 
> +        hdmi_video_packetize(hdmi); 
> +        hdmi_video_sample(hdmi); 
> + 
> +        hdmi_clear_overflow(hdmi); 
> + 
> +        return 0; 
> +} 
> + 
> +void dw_hdmi_init(struct dw_hdmi *hdmi) 
> +{ 
> +        uint ih_mute; 
> + 
> +        /* 
> +         * boot up defaults are: 
> +         * hdmi_ih_mute   = 0x03 (disabled) 
> +         * hdmi_ih_mute_* = 0x00 (enabled) 
> +         * 
> +         * disable top level interrupt bits in hdmi block 
> +         */ 
> +        ih_mute = /*hdmi_read(hdmi, HDMI_IH_MUTE) |*/ 
> +                  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 
> +                  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 
> + 
> +        hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE); 
> + 
> +        /* enable i2c master done irq */ 
> +        hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT); 
> + 
> +        /* enable i2c client nack % arbitration error irq */ 
> +        hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT); 
> +} 
> diff --git a/drivers/video/rockchip/Makefile 
> b/drivers/video/rockchip/Makefile 
> index 7962f8611e..755350b934 100644 
> --- a/drivers/video/rockchip/Makefile 
> +++ b/drivers/video/rockchip/Makefile 
> @@ -5,4 +5,4 @@ 
>  # SPDX-License-Identifier:        GPL-2.0+ 
>  # 
>   
> -obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o 
> +obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o 
> diff --git a/drivers/video/rockchip/rk_hdmi.c 
> b/drivers/video/rockchip/rk_hdmi.c 
> index c8608db23c..db07588302 100644 
> --- a/drivers/video/rockchip/rk_hdmi.c 
> +++ b/drivers/video/rockchip/rk_hdmi.c 
> @@ -9,6 +9,7 @@ 
>  #include <clk.h> 
>  #include <display.h> 
>  #include <dm.h> 
> +#include <dw_hdmi.h> 
>  #include <edid.h> 
>  #include <regmap.h> 
>  #include <syscon.h> 
> @@ -16,73 +17,13 @@ 
>  #include <asm/io.h> 
>  #include <asm/arch/clock.h> 
>  #include <asm/arch/grf_rk3288.h> 
> -#include <asm/arch/hdmi_rk3288.h> 
>  #include <power/regulator.h> 
>   
> -struct tmds_n_cts { 
> -        u32 tmds; 
> -        u32 cts; 
> -        u32 n; 
> -}; 
> - 
>  struct rk_hdmi_priv { 
> -        struct rk3288_hdmi *regs; 
> +        struct dw_hdmi hdmi; 
>          struct rk3288_grf *grf; 
>  }; 
>   
> -static const struct tmds_n_cts n_cts_table[] = { 
> -        { 
> -                .tmds = 25175000, .n = 6144, .cts = 25175, 
> -        }, { 
> -                .tmds = 25200000, .n = 6144, .cts = 25200, 
> -        }, { 
> -                .tmds = 27000000, .n = 6144, .cts = 27000, 
> -        }, { 
> -                .tmds = 27027000, .n = 6144, .cts = 27027, 
> -        }, { 
> -                .tmds = 40000000, .n = 6144, .cts = 40000, 
> -        }, { 
> -                .tmds = 54000000, .n = 6144, .cts = 54000, 
> -        }, { 
> -                .tmds = 54054000, .n = 6144, .cts = 54054, 
> -        }, { 
> -                .tmds = 65000000, .n = 6144, .cts = 65000, 
> -        }, { 
> -                .tmds = 74176000, .n = 11648, .cts = 140625, 
> -        }, { 
> -                .tmds = 74250000, .n = 6144, .cts = 74250, 
> -        }, { 
> -                .tmds = 83500000, .n = 6144, .cts = 83500, 
> -        }, { 
> -                .tmds = 106500000, .n = 6144, .cts = 106500, 
> -        }, { 
> -                .tmds = 108000000, .n = 6144, .cts = 108000, 
> -        }, { 
> -                .tmds = 148352000, .n = 5824, .cts = 140625, 
> -        }, { 
> -                .tmds = 148500000, .n = 6144, .cts = 148500, 
> -        }, { 
> -                .tmds = 297000000, .n = 5120, .cts = 247500, 
> -        } 
> -}; 
> - 
> -struct hdmi_mpll_config { 
> -        u64 mpixelclock; 
> -        /* Mode of Operation and PLL Dividers Control Register */ 
> -        u32 cpce; 
> -        /* PLL Gmp Control Register */ 
> -        u32 gmp; 
> -        /* PLL Current COntrol Register */ 
> -        u32 curr; 
> -}; 
> - 
> -struct hdmi_phy_config { 
> -        u64 mpixelclock; 
> -        u32 sym_ctr;    /* clock symbol and transmitter control */ 
> -        u32 term;       /* transmission termination value */ 
> -        u32 vlev_ctr;   /* voltage level control */ 
> -}; 
> - 
>  static const struct hdmi_phy_config rockchip_phy_config[] = { 
>          { 
>                  .mpixelclock = 74250000, 
> @@ -124,693 +65,41 @@ static const struct hdmi_mpll_config 
> rockchip_mpll_cfg[] = { 
>          } 
>  }; 
>   
> -static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, 
> u32 cts) 
> -{ 
> -        uint cts3; 
> -        uint n3; 
> - 
> -        /* first set ncts_atomic_write (if present) */ 
> -        n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE; 
> -        writel(n3, &regs->aud_n3); 
> - 
> -        /* set cts_manual (if present) */ 
> -        cts3 = HDMI_AUD_CTS3_CTS_MANUAL; 
> - 
> -        cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET; 
> -        cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK; 
> - 
> -        /* write cts values; cts3 must be written first */ 
> -        writel(cts3, &regs->aud_cts3); 
> -        writel((cts >> 8) & 0xff, &regs->aud_cts2); 
> -        writel(cts & 0xff, &regs->aud_cts1); 
> - 
> -        /* write n values; n1 must be written last */ 
> -        n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK; 
> -        writel(n3, &regs->aud_n3); 
> -        writel((n >> 8) & 0xff, &regs->aud_n2); 
> -        writel(n & 0xff, &regs->aud_n1); 
> - 
> -        writel(HDMI_AUD_INPUTCLKFS_128, &regs->aud_inputclkfs); 
> -} 
> - 
> -static int hdmi_lookup_n_cts(u32 pixel_clk) 
> -{ 
> -        int i; 
> - 
> -        for (i = 0; i < ARRAY_SIZE(n_cts_table); i++) 
> -                if (pixel_clk <= n_cts_table[i].tmds) 
> -                        break; 
> - 
> -        if (i >= ARRAY_SIZE(n_cts_table)) 
> -                return -1; 
> - 
> -        return i; 
> -} 
> - 
> -static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 
> pixel_clk) 
> -{ 
> -        u32 clk_n, clk_cts; 
> -        int index; 
> - 
> -        index = hdmi_lookup_n_cts(pixel_clk); 
> -        if (index == -1) { 
> -                debug("audio not supported for pixel clk %d\n", 
> pixel_clk); 
> -                return; 
> -        } 
> - 
> -        clk_n = n_cts_table[index].n; 
> -        clk_cts = n_cts_table[index].cts; 
> -        hdmi_set_clock_regenerator(regs, clk_n, clk_cts); 
> -} 
> - 
> -/* 
> - * this submodule is responsible for the video data synchronization. 
> - * for example, for rgb 4:4:4 input, the data map is defined as 
> - *                        pin{47~40} <==> r[7:0] 
> - *                        pin{31~24} <==> g[7:0] 
> - *                        pin{15~8}  <==> b[7:0] 
> - */ 
> -static void hdmi_video_sample(struct rk3288_hdmi *regs) 
> -{ 
> -        u32 color_format = 0x01; 
> -        uint val; 
> - 
> -        val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 
> -              ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 
> -              HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 
> - 
> -        writel(val, &regs->tx_invid0); 
> - 
> -        /* enable tx stuffing: when de is inactive, fix the output data 
> to 0 */ 
> -        val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 
> -              HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 
> -              HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 
> -        writel(val, &regs->tx_instuffing); 
> -        writel(0x0, &regs->tx_gydata0); 
> -        writel(0x0, &regs->tx_gydata1); 
> -        writel(0x0, &regs->tx_rcrdata0); 
> -        writel(0x0, &regs->tx_rcrdata1); 
> -        writel(0x0, &regs->tx_bcbdata0); 
> -        writel(0x0, &regs->tx_bcbdata1); 
> -} 
> - 
> -static void hdmi_video_packetize(struct rk3288_hdmi *regs) 
> -{ 
> -        u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 
> -        u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT; 
> -        u32 color_depth = 0; 
> -        uint val, vp_conf; 
> - 
> -        /* set the...

[U-Boot] [PATCH 4/8] sunxi: video: Split out TCON code

[Jernej Skrabec]

TCON unit has similar layout and functionality also on newer SoCs. This
commit splits out TCON code for easier reuse later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---

 arch/arm/include/asm/arch-sunxi/display.h | 103 --------------
 arch/arm/include/asm/arch-sunxi/lcdc.h    | 128 +++++++++++++++++
 drivers/video/Makefile                    |   2 +-
 drivers/video/sunxi/Makefile              |   8 ++
 drivers/video/sunxi/lcdc.c                | 205 +++++++++++++++++++++++++++
 drivers/video/{ => sunxi}/sunxi_display.c | 224 ++++++------------------------
 6 files changed, 387 insertions(+), 283 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/lcdc.h
 create mode 100644 drivers/video/sunxi/Makefile
 create mode 100644 drivers/video/sunxi/lcdc.c
 rename drivers/video/{ => sunxi}/sunxi_display.c (86%)

diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
index b64f310b8b..93803addfb 100644
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -157,52 +157,6 @@ struct sunxi_de_be_reg {
 	u32 output_color_coef[12];	/* 0x9d0 */
 };
 
-struct sunxi_lcdc_reg {
-	u32 ctrl;			/* 0x00 */
-	u32 int0;			/* 0x04 */
-	u32 int1;			/* 0x08 */
-	u8 res0[0x04];			/* 0x0c */
-	u32 tcon0_frm_ctrl;		/* 0x10 */
-	u32 tcon0_frm_seed[6];		/* 0x14 */
-	u32 tcon0_frm_table[4];		/* 0x2c */
-	u8 res1[4];			/* 0x3c */
-	u32 tcon0_ctrl;			/* 0x40 */
-	u32 tcon0_dclk;			/* 0x44 */
-	u32 tcon0_timing_active;	/* 0x48 */
-	u32 tcon0_timing_h;		/* 0x4c */
-	u32 tcon0_timing_v;		/* 0x50 */
-	u32 tcon0_timing_sync;		/* 0x54 */
-	u32 tcon0_hv_intf;		/* 0x58 */
-	u8 res2[0x04];			/* 0x5c */
-	u32 tcon0_cpu_intf;		/* 0x60 */
-	u32 tcon0_cpu_wr_dat;		/* 0x64 */
-	u32 tcon0_cpu_rd_dat0;		/* 0x68 */
-	u32 tcon0_cpu_rd_dat1;		/* 0x6c */
-	u32 tcon0_ttl_timing0;		/* 0x70 */
-	u32 tcon0_ttl_timing1;		/* 0x74 */
-	u32 tcon0_ttl_timing2;		/* 0x78 */
-	u32 tcon0_ttl_timing3;		/* 0x7c */
-	u32 tcon0_ttl_timing4;		/* 0x80 */
-	u32 tcon0_lvds_intf;		/* 0x84 */
-	u32 tcon0_io_polarity;		/* 0x88 */
-	u32 tcon0_io_tristate;		/* 0x8c */
-	u32 tcon1_ctrl;			/* 0x90 */
-	u32 tcon1_timing_source;	/* 0x94 */
-	u32 tcon1_timing_scale;		/* 0x98 */
-	u32 tcon1_timing_out;		/* 0x9c */
-	u32 tcon1_timing_h;		/* 0xa0 */
-	u32 tcon1_timing_v;		/* 0xa4 */
-	u32 tcon1_timing_sync;		/* 0xa8 */
-	u8 res3[0x44];			/* 0xac */
-	u32 tcon1_io_polarity;		/* 0xf0 */
-	u32 tcon1_io_tristate;		/* 0xf4 */
-	u8 res4[0x108];			/* 0xf8 */
-	u32 mux_ctrl;			/* 0x200 */
-	u8 res5[0x1c];			/* 0x204 */
-	u32 lvds_ana0;			/* 0x220 */
-	u32 lvds_ana1;			/* 0x224 */
-};
-
 struct sunxi_hdmi_reg {
 	u32 version_id;			/* 0x000 */
 	u32 ctrl;			/* 0x004 */
@@ -347,63 +301,6 @@ struct sunxi_tve_reg {
 #define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE	1
 
 /*
- * LCDC register constants.
- */
-#define SUNXI_LCDC_X(x)				(((x) - 1) << 16)
-#define SUNXI_LCDC_Y(y)				(((y) - 1) << 0)
-#define SUNXI_LCDC_TCON_VSYNC_MASK		(1 << 24)
-#define SUNXI_LCDC_TCON_HSYNC_MASK		(1 << 25)
-#define SUNXI_LCDC_CTRL_IO_MAP_MASK		(1 << 0)
-#define SUNXI_LCDC_CTRL_IO_MAP_TCON0		(0 << 0)
-#define SUNXI_LCDC_CTRL_IO_MAP_TCON1		(1 << 0)
-#define SUNXI_LCDC_CTRL_TCON_ENABLE		(1 << 31)
-#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666	((1 << 31) | (0 << 4))
-#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565	((1 << 31) | (5 << 4))
-#define SUNXI_LCDC_TCON0_FRM_SEED		0x11111111
-#define SUNXI_LCDC_TCON0_FRM_TAB0		0x01010000
-#define SUNXI_LCDC_TCON0_FRM_TAB1		0x15151111
-#define SUNXI_LCDC_TCON0_FRM_TAB2		0x57575555
-#define SUNXI_LCDC_TCON0_FRM_TAB3		0x7f7f7777
-#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
-#define SUNXI_LCDC_TCON0_CTRL_ENABLE		(1 << 31)
-#define SUNXI_LCDC_TCON0_DCLK_DIV(n)		((n) << 0)
-#define SUNXI_LCDC_TCON0_DCLK_ENABLE		(0xf << 28)
-#define SUNXI_LCDC_TCON0_TIMING_H_BP(n)		(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
-#define SUNXI_LCDC_TCON0_TIMING_V_BP(n)		(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n)	(((n) * 2) << 16)
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	(1 << 20)
-#else
-#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	0 /* NA */
-#endif
-#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n)	((n) << 26)
-#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE	(1 << 31)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x)	((x) << 28)
-#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
-#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE	(1 << 20)
-#define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
-#define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
-#define SUNXI_LCDC_TCON1_TIMING_V_BP(n)		(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)	((n) << 16)
-#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK		(0xf << 0)
-#define SUNXI_LCDC_MUX_CTRL_SRC0(x)		((x) << 0)
-#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK		(0xf << 4)
-#define SUNXI_LCDC_MUX_CTRL_SRC1(x)		((x) << 4)
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-#define SUNXI_LCDC_LVDS_ANA0			0x40040320
-#define SUNXI_LCDC_LVDS_ANA0_EN_MB		(1 << 31)
-#define SUNXI_LCDC_LVDS_ANA0_DRVC		(1 << 24)
-#define SUNXI_LCDC_LVDS_ANA0_DRVD(x)		((x) << 20)
-#else
-#define SUNXI_LCDC_LVDS_ANA0			0x3f310000
-#define SUNXI_LCDC_LVDS_ANA0_UPDATE		(1 << 22)
-#endif
-#define SUNXI_LCDC_LVDS_ANA1_INIT1		(0x1f << 26 | 0x1f << 10)
-#define SUNXI_LCDC_LVDS_ANA1_INIT2		(0x1f << 16 | 0x1f << 00)
-
-/*
  * HDMI register constants.
  */
 #define SUNXI_HDMI_X(x)				(((x) - 1) << 0)
diff --git a/arch/arm/include/asm/arch-sunxi/lcdc.h b/arch/arm/include/asm/arch-sunxi/lcdc.h
new file mode 100644
index 0000000000..a751698b4f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/lcdc.h
@@ -0,0 +1,128 @@
+/*
+ * Sunxi platform timing controller register and constant defines
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LCDC_H
+#define _LCDC_H
+
+#include <fdtdec.h>
+
+struct sunxi_lcdc_reg {
+	u32 ctrl;			/* 0x00 */
+	u32 int0;			/* 0x04 */
+	u32 int1;			/* 0x08 */
+	u8 res0[0x04];			/* 0x0c */
+	u32 tcon0_frm_ctrl;		/* 0x10 */
+	u32 tcon0_frm_seed[6];		/* 0x14 */
+	u32 tcon0_frm_table[4];		/* 0x2c */
+	u8 res1[4];			/* 0x3c */
+	u32 tcon0_ctrl;			/* 0x40 */
+	u32 tcon0_dclk;			/* 0x44 */
+	u32 tcon0_timing_active;	/* 0x48 */
+	u32 tcon0_timing_h;		/* 0x4c */
+	u32 tcon0_timing_v;		/* 0x50 */
+	u32 tcon0_timing_sync;		/* 0x54 */
+	u32 tcon0_hv_intf;		/* 0x58 */
+	u8 res2[0x04];			/* 0x5c */
+	u32 tcon0_cpu_intf;		/* 0x60 */
+	u32 tcon0_cpu_wr_dat;		/* 0x64 */
+	u32 tcon0_cpu_rd_dat0;		/* 0x68 */
+	u32 tcon0_cpu_rd_dat1;		/* 0x6c */
+	u32 tcon0_ttl_timing0;		/* 0x70 */
+	u32 tcon0_ttl_timing1;		/* 0x74 */
+	u32 tcon0_ttl_timing2;		/* 0x78 */
+	u32 tcon0_ttl_timing3;		/* 0x7c */
+	u32 tcon0_ttl_timing4;		/* 0x80 */
+	u32 tcon0_lvds_intf;		/* 0x84 */
+	u32 tcon0_io_polarity;		/* 0x88 */
+	u32 tcon0_io_tristate;		/* 0x8c */
+	u32 tcon1_ctrl;			/* 0x90 */
+	u32 tcon1_timing_source;	/* 0x94 */
+	u32 tcon1_timing_scale;		/* 0x98 */
+	u32 tcon1_timing_out;		/* 0x9c */
+	u32 tcon1_timing_h;		/* 0xa0 */
+	u32 tcon1_timing_v;		/* 0xa4 */
+	u32 tcon1_timing_sync;		/* 0xa8 */
+	u8 res3[0x44];			/* 0xac */
+	u32 tcon1_io_polarity;		/* 0xf0 */
+	u32 tcon1_io_tristate;		/* 0xf4 */
+	u8 res4[0x108];			/* 0xf8 */
+	u32 mux_ctrl;			/* 0x200 */
+	u8 res5[0x1c];			/* 0x204 */
+	u32 lvds_ana0;			/* 0x220 */
+	u32 lvds_ana1;			/* 0x224 */
+};
+
+/*
+ * LCDC register constants.
+ */
+#define SUNXI_LCDC_X(x)				(((x) - 1) << 16)
+#define SUNXI_LCDC_Y(y)				(((y) - 1) << 0)
+#define SUNXI_LCDC_TCON_VSYNC_MASK		(1 << 24)
+#define SUNXI_LCDC_TCON_HSYNC_MASK		(1 << 25)
+#define SUNXI_LCDC_CTRL_IO_MAP_MASK		(1 << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_TCON0		(0 << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_TCON1		(1 << 0)
+#define SUNXI_LCDC_CTRL_TCON_ENABLE		(1 << 31)
+#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666	((1 << 31) | (0 << 4))
+#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565	((1 << 31) | (5 << 4))
+#define SUNXI_LCDC_TCON0_FRM_SEED		0x11111111
+#define SUNXI_LCDC_TCON0_FRM_TAB0		0x01010000
+#define SUNXI_LCDC_TCON0_FRM_TAB1		0x15151111
+#define SUNXI_LCDC_TCON0_FRM_TAB2		0x57575555
+#define SUNXI_LCDC_TCON0_FRM_TAB3		0x7f7f7777
+#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
+#define SUNXI_LCDC_TCON0_CTRL_ENABLE		(1 << 31)
+#define SUNXI_LCDC_TCON0_DCLK_DIV(n)		((n) << 0)
+#define SUNXI_LCDC_TCON0_DCLK_ENABLE		(0xf << 28)
+#define SUNXI_LCDC_TCON0_TIMING_H_BP(n)		(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
+#define SUNXI_LCDC_TCON0_TIMING_V_BP(n)		(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n)	(((n) * 2) << 16)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	(1 << 20)
+#else
+#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	0 /* NA */
+#endif
+#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n)	((n) << 26)
+#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE	(1 << 31)
+#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x)	((x) << 28)
+#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
+#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE	(1 << 20)
+#define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
+#define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
+#define SUNXI_LCDC_TCON1_TIMING_V_BP(n)		(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)	((n) << 16)
+#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK		(0xf << 0)
+#define SUNXI_LCDC_MUX_CTRL_SRC0(x)		((x) << 0)
+#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK		(0xf << 4)
+#define SUNXI_LCDC_MUX_CTRL_SRC1(x)		((x) << 4)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+#define SUNXI_LCDC_LVDS_ANA0			0x40040320
+#define SUNXI_LCDC_LVDS_ANA0_EN_MB		(1 << 31)
+#define SUNXI_LCDC_LVDS_ANA0_DRVC		(1 << 24)
+#define SUNXI_LCDC_LVDS_ANA0_DRVD(x)		((x) << 20)
+#else
+#define SUNXI_LCDC_LVDS_ANA0			0x3f310000
+#define SUNXI_LCDC_LVDS_ANA0_UPDATE		(1 << 22)
+#endif
+#define SUNXI_LCDC_LVDS_ANA1_INIT1		(0x1f << 26 | 0x1f << 10)
+#define SUNXI_LCDC_LVDS_ANA1_INIT2		(0x1f << 16 | 0x1f << 00)
+
+void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
+void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
+void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
+			 const struct display_timing *mode,
+			 int clk_div, bool for_ext_vga_dac,
+			 int depth, int dclk_phase);
+void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
+			 const struct display_timing *mode,
+			 bool ext_hvsync, bool is_composite);
+
+#endif /* _LCDC_H */
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index db34904a9a..7230fd9570 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -51,7 +51,6 @@ obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
 obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
 obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
 obj-$(CONFIG_VIDEO_SM501) += sm501.o
-obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
 obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
@@ -64,3 +63,4 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
 obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
 
 obj-y += bridge/
+obj-y += sunxi/
diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile
new file mode 100644
index 0000000000..dfc9b47a1f
--- /dev/null
+++ b/drivers/video/sunxi/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o ../videomodes.o
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
new file mode 100644
index 0000000000..8c8fb2e4ee
--- /dev/null
+++ b/drivers/video/sunxi/lcdc.c
@@ -0,0 +1,205 @@
+/*
+ * Timing controller driver for Allwinner SoCs.
+ *
+ * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/arch/lcdc.h>
+#include <asm/io.h>
+
+static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon)
+{
+	int delay;
+
+	delay = mode->vfront_porch.typ + mode->vsync_len.typ +
+		mode->vback_porch.typ;
+	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
+		delay /= 2;
+	if (tcon == 1)
+		delay -= 2;
+
+	return (delay > 30) ? 30 : delay;
+}
+
+void lcdc_init(struct sunxi_lcdc_reg * const lcdc)
+{
+	/* Init lcdc */
+	writel(0, &lcdc->ctrl); /* Disable tcon */
+	writel(0, &lcdc->int0); /* Disable all interrupts */
+
+	/* Disable tcon0 dot clock */
+	clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
+
+	/* Set all io lines to tristate */
+	writel(0xffffffff, &lcdc->tcon0_io_tristate);
+	writel(0xffffffff, &lcdc->tcon1_io_tristate);
+}
+
+void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth)
+{
+	setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
+#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+	setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
+	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+	udelay(2); /* delay at least 1200 ns */
+	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
+	udelay(2); /* delay at least 1200 ns */
+	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
+	if (depth == 18)
+		setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
+	else
+		setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
+#else
+	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
+	udelay(2); /* delay at least 1200 ns */
+	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
+	udelay(1); /* delay at least 120 ns */
+	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
+	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
+#endif
+#endif
+}
+
+void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
+			 const struct display_timing *mode,
+			 int clk_div, bool for_ext_vga_dac,
+			 int depth, int dclk_phase)
+{
+	int bp, clk_delay, total, val;
+
+	/* Use tcon0 */
+	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
+			SUNXI_LCDC_CTRL_IO_MAP_TCON0);
+
+	clk_delay = lcdc_get_clk_delay(mode, 0);
+	writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
+	       SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
+
+	writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
+	       SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
+
+	writel(SUNXI_LCDC_X(mode->hactive.typ) |
+	       SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active);
+
+	bp = mode->hsync_len.typ + mode->hback_porch.typ;
+	total = mode->hactive.typ + mode->hfront_porch.typ + bp;
+	writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
+	       SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
+
+	bp = mode->vsync_len.typ + mode->vback_porch.typ;
+	total = mode->vactive.typ + mode->vfront_porch.typ + bp;
+	writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
+	       SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
+
+#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
+	writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
+	       SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);
+
+	writel(0, &lcdc->tcon0_hv_intf);
+	writel(0, &lcdc->tcon0_cpu_intf);
+#endif
+#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+	val = (depth == 18) ? 1 : 0;
+	writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
+	       SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
+#endif
+
+	if (depth == 18 || depth == 16) {
+		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
+		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
+		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
+		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
+		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
+		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
+		writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
+		writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
+		writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
+		writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
+		writel(((depth == 18) ?
+			SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
+			SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
+		       &lcdc->tcon0_frm_ctrl);
+	}
+
+	val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
+	if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
+		val |= SUNXI_LCDC_TCON_HSYNC_MASK;
+	if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW)
+		val |= SUNXI_LCDC_TCON_VSYNC_MASK;
+
+#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
+	if (for_ext_vga_dac)
+		val = 0;
+#endif
+	writel(val, &lcdc->tcon0_io_polarity);
+
+	writel(0, &lcdc->tcon0_io_tristate);
+}
+
+void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
+			 const struct display_timing *mode,
+			 bool ext_hvsync, bool is_composite)
+{
+	int bp, clk_delay, total, val, yres;
+
+	/* Use tcon1 */
+	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
+			SUNXI_LCDC_CTRL_IO_MAP_TCON1);
+
+	clk_delay = lcdc_get_clk_delay(mode, 1);
+	writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
+	       ((mode->flags & DISPLAY_FLAGS_INTERLACED) ?
+			SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
+	       SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
+
+	yres = mode->vactive.typ;
+	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
+		yres /= 2;
+	writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
+	       &lcdc->tcon1_timing_source);
+	writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
+	       &lcdc->tcon1_timing_scale);
+	writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
+	       &lcdc->tcon1_timing_out);
+
+	bp = mode->hsync_len.typ + mode->hback_porch.typ;
+	total = mode->hactive.typ + mode->hfront_porch.typ + bp;
+	writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
+	       SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
+
+	bp = mode->vsync_len.typ + mode->vback_porch.typ;
+	total = mode->vactive.typ + mode->vfront_porch.typ + bp;
+	if (!(mode->flags & DISPLAY_FLAGS_INTERLACED))
+		total *= 2;
+	writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
+	       SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
+
+	writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
+	       SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon1_timing_sync);
+
+	if (ext_hvsync) {
+		val = 0;
+		if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+			val |= SUNXI_LCDC_TCON_HSYNC_MASK;
+		if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+			val |= SUNXI_LCDC_TCON_VSYNC_MASK;
+		writel(val, &lcdc->tcon1_io_polarity);
+
+		clrbits_le32(&lcdc->tcon1_io_tristate,
+			     SUNXI_LCDC_TCON_VSYNC_MASK |
+			     SUNXI_LCDC_TCON_HSYNC_MASK);
+	}
+
+#ifdef CONFIG_MACH_SUN5I
+	if (is_composite)
+		clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
+				SUNXI_LCDC_MUX_CTRL_SRC0(1));
+#endif
+}
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
similarity index 86%
rename from drivers/video/sunxi_display.c
rename to drivers/video/sunxi/sunxi_display.c
index 6f8ee01c10..9a4631eb77 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -12,6 +12,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/display.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/lcdc.h>
 #include <asm/arch/pwm.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
@@ -23,10 +24,10 @@
 #include <i2c.h>
 #include <malloc.h>
 #include <video_fb.h>
-#include "videomodes.h"
-#include "anx9804.h"
-#include "hitachi_tx18d42vm_lcd.h"
-#include "ssd2828.h"
+#include "../videomodes.h"
+#include "../anx9804.h"
+#include "../hitachi_tx18d42vm_lcd.h"
+#include "../ssd2828.h"
 
 #ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW
 #define PWM_ON 0
@@ -630,8 +631,6 @@ static void sunxi_lcdc_init(void)
 {
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	struct sunxi_lcdc_reg * const lcdc =
-		(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 
 	/* Reset off */
 #ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -650,45 +649,7 @@ static void sunxi_lcdc_init(void)
 #endif
 #endif
 
-	/* Init lcdc */
-	writel(0, &lcdc->ctrl); /* Disable tcon */
-	writel(0, &lcdc->int0); /* Disable all interrupts */
-
-	/* Disable tcon0 dot clock */
-	clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
-
-	/* Set all io lines to tristate */
-	writel(0xffffffff, &lcdc->tcon0_io_tristate);
-	writel(0xffffffff, &lcdc->tcon1_io_tristate);
-}
-
-static void sunxi_lcdc_enable(void)
-{
-	struct sunxi_lcdc_reg * const lcdc =
-		(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
-
-	setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
-#ifdef CONFIG_VIDEO_LCD_IF_LVDS
-	setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
-	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	udelay(2); /* delay at least 1200 ns */
-	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
-	udelay(2); /* delay at least 1200 ns */
-	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
-	if (sunxi_display.depth == 18)
-		setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
-	else
-		setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
-#else
-	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
-	udelay(2); /* delay at least 1200 ns */
-	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
-	udelay(1); /* delay at least 120 ns */
-	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
-	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
-#endif
-#endif
+	lcdc_init((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE);
 }
 
 static void sunxi_lcdc_panel_enable(void)
@@ -758,17 +719,31 @@ static void sunxi_lcdc_backlight_enable(void)
 		gpio_direction_output(pin, PWM_ON);
 }
 
-static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon)
+static void sunxi_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+					      struct display_timing *timing)
 {
-	int delay;
+	timing->pixelclock.typ = mode->pixclock_khz * 1000;
 
-	delay = mode->lower_margin + mode->vsync_len + mode->upper_margin;
-	if (mode->vmode == FB_VMODE_INTERLACED)
-		delay /= 2;
-	if (tcon == 1)
-		delay -= 2;
+	timing->hactive.typ = mode->xres;
+	timing->hfront_porch.typ = mode->right_margin;
+	timing->hback_porch.typ = mode->left_margin;
+	timing->hsync_len.typ = mode->hsync_len;
+
+	timing->vactive.typ = mode->yres;
+	timing->vfront_porch.typ = mode->lower_margin;
+	timing->vback_porch.typ = mode->upper_margin;
+	timing->vsync_len.typ = mode->vsync_len;
 
-	return (delay > 30) ? 30 : delay;
+	if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+		timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+	else
+		timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
+	if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+		timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+	else
+		timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
+	if (mode->vmode == FB_VMODE_INTERLACED)
+		timing->flags |= DISPLAY_FLAGS_INTERLACED;
 }
 
 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
@@ -776,7 +751,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
 {
 	struct sunxi_lcdc_reg * const lcdc =
 		(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
-	int bp, clk_delay, clk_div, clk_double, pin, total, val;
+	int clk_div, clk_double, pin;
+	struct display_timing timing;
 
 #if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
 	for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
@@ -796,73 +772,9 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
 
 	sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
 
-	/* Use tcon0 */
-	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
-			SUNXI_LCDC_CTRL_IO_MAP_TCON0);
-
-	clk_delay = sunxi_lcdc_get_clk_delay(mode, 0);
-	writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
-	       SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
-
-	writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
-	       SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
-
-	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
-	       &lcdc->tcon0_timing_active);
-
-	bp = mode->hsync_len + mode->left_margin;
-	total = mode->xres + mode->right_margin + bp;
-	writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
-	       SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
-
-	bp = mode->vsync_len + mode->upper_margin;
-	total = mode->yres + mode->lower_margin + bp;
-	writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
-	       SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
-
-#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
-	writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
-	       &lcdc->tcon0_timing_sync);
-
-	writel(0, &lcdc->tcon0_hv_intf);
-	writel(0, &lcdc->tcon0_cpu_intf);
-#endif
-#ifdef CONFIG_VIDEO_LCD_IF_LVDS
-	val = (sunxi_display.depth == 18) ? 1 : 0;
-	writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
-	       SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
-#endif
-
-	if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
-		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
-		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
-		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
-		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
-		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
-		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
-		writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
-		writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
-		writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
-		writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
-		writel(((sunxi_display.depth == 18) ?
-			SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
-			SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
-		       &lcdc->tcon0_frm_ctrl);
-	}
-
-	val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
-	if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
-		val |= SUNXI_LCDC_TCON_HSYNC_MASK;
-	if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
-		val |= SUNXI_LCDC_TCON_VSYNC_MASK;
-
-#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
-	if (for_ext_vga_dac)
-		val = 0;
-#endif
-	writel(val, &lcdc->tcon0_io_polarity);
-
-	writel(0, &lcdc->tcon0_io_tristate);
+	sunxi_ctfb_mode_to_display_timing(mode, &timing);
+	lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
+			    sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
 }
 
 #if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
@@ -872,65 +784,17 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
 {
 	struct sunxi_lcdc_reg * const lcdc =
 		(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
-	int bp, clk_delay, total, val, yres;
-
-	/* Use tcon1 */
-	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
-			SUNXI_LCDC_CTRL_IO_MAP_TCON1);
-
-	clk_delay = sunxi_lcdc_get_clk_delay(mode, 1);
-	writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
-	       ((mode->vmode == FB_VMODE_INTERLACED) ?
-			SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
-	       SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
+	struct display_timing timing;
 
-	yres = mode->yres;
-	if (mode->vmode == FB_VMODE_INTERLACED)
-		yres /= 2;
-	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-	       &lcdc->tcon1_timing_source);
-	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-	       &lcdc->tcon1_timing_scale);
-	writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
-	       &lcdc->tcon1_timing_out);
-
-	bp = mode->hsync_len + mode->left_margin;
-	total = mode->xres + mode->right_margin + bp;
-	writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
-	       SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
-
-	bp = mode->vsync_len + mode->upper_margin;
-	total = mode->yres + mode->lower_margin + bp;
-	if (mode->vmode == FB_VMODE_NONINTERLACED)
-		total *= 2;
-	writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
-	       SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
-
-	writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
-	       &lcdc->tcon1_timing_sync);
+	sunxi_ctfb_mode_to_display_timing(mode, &timing);
+	lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
+			    sunxi_is_composite());
 
 	if (use_portd_hvsync) {
 		sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
 		sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
-
-		val = 0;
-		if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
-			val |= SUNXI_LCDC_TCON_HSYNC_MASK;
-		if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
-			val |= SUNXI_LCDC_TCON_VSYNC_MASK;
-		writel(val, &lcdc->tcon1_io_polarity);
-
-		clrbits_le32(&lcdc->tcon1_io_tristate,
-			     SUNXI_LCDC_TCON_VSYNC_MASK |
-			     SUNXI_LCDC_TCON_HSYNC_MASK);
 	}
 
-#ifdef CONFIG_MACH_SUN5I
-	if (sunxi_is_composite())
-		clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
-				SUNXI_LCDC_MUX_CTRL_SRC0(1));
-#endif
-
 	sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
 }
 #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
@@ -1223,7 +1087,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 		sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
 		sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 		sunxi_composer_enable();
-		sunxi_lcdc_enable();
+		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE, 0);
 		sunxi_hdmi_enable();
 #endif
 		break;
@@ -1253,7 +1117,8 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 		sunxi_composer_mode_set(mode, address);
 		sunxi_lcdc_tcon0_mode_set(mode, false);
 		sunxi_composer_enable();
-		sunxi_lcdc_enable();
+		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE,
+			    sunxi_display.depth);
 #ifdef CONFIG_VIDEO_LCD_SSD2828
 		sunxi_ssd2828_init(mode);
 #endif
@@ -1265,13 +1130,14 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 		sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
 		sunxi_tvencoder_mode_set();
 		sunxi_composer_enable();
-		sunxi_lcdc_enable();
+		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE, 0);
 		sunxi_tvencoder_enable();
 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
 		sunxi_composer_mode_set(mode, address);
 		sunxi_lcdc_tcon0_mode_set(mode, true);
-		sunxi_composer_enable();
-		sunxi_lcdc_enable();
+		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE,
+			    sunxi_display.depth);
+		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE, 0);
 		sunxi_vga_external_dac_enable();
 #endif
 		break;
@@ -1284,7 +1150,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 		sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
 		sunxi_tvencoder_mode_set();
 		sunxi_composer_enable();
-		sunxi_lcdc_enable();
+		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE, 0);
 		sunxi_tvencoder_enable();
 #endif
 		break;
-- 
2.12.0

[U-Boot] [PATCH 4/8] sunxi: video: Split out TCON code

[Maxime Ripard]

Hi,

Thanks for your great work.

On Thu, Mar 09, 2017 at 12:34:40AM +0100, Jernej Skrabec wrote:
> -	writel(0, &lcdc->tcon0_io_tristate);
> +	sunxi_ctfb_mode_to_display_timing(mode, &timing);
> +	lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
> +			    sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);

I'm not sure what this sunxi_ctfb_mode_to_display_timing function is
useful for, but it's introduction and the conversion of the users
would probably need to be moved to another patch.

>  #elif defined CONFIG_VIDEO_VGA_VIA_LCD
>  		sunxi_composer_mode_set(mode, address);
>  		sunxi_lcdc_tcon0_mode_set(mode, true);
> -		sunxi_composer_enable();
> -		sunxi_lcdc_enable();
> +		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE,
> +			    sunxi_display.depth);
> +		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE, 0);

That one is suspicious. Shouldn't sunxi_composer_enable be left, and
lcdc_enable called only once?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH 4/8] sunxi: video: Split out TCON code

[Jernej Škrabec]

Hi Maxime,

Dne četrtek, 09. marec 2017 ob 09:33:06 CET je Maxime Ripard napisal(a):
> Hi,
> 
> Thanks for your great work.
> 
> On Thu, Mar 09, 2017 at 12:34:40AM +0100, Jernej Skrabec wrote:
> > -	writel(0, &lcdc->tcon0_io_tristate);
> > +	sunxi_ctfb_mode_to_display_timing(mode, &timing);
> > +	lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
> > +			    sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
> 
> I'm not sure what this sunxi_ctfb_mode_to_display_timing function is
> useful for, but it's introduction and the conversion of the users
> would probably need to be moved to another patch.
> 

I forgot to explain this in commit message.

The thing is that current video display driver for Allwinner SoCs uses older 
framework called cfb console. This framework uses videomodes.h for timing 
related functions. In it, there is a structure called "struct ctfb_res_modes", 
which holds pixel clock, active resolution, sync times, all front/back porch 
values and so on. In contrast, DM video framework uses different structure 
"struct display_timing" which is defined in fdtdec.h and holds exactly the same 
timing informations. It is a bit strange to have two different structures for 
same type of informations, but at least conversion from ctfb timing to display 
timming is pretty straightforward, as you can see from the code.

It made more sense to me to use DM video timing structure because I expect 
that all new drivers will use this framework and I guess that older will be 
converted to use this framework too.

Should I move this change in new patch?

> >  #elif defined CONFIG_VIDEO_VGA_VIA_LCD
> >  
> >  		sunxi_composer_mode_set(mode, address);
> >  		sunxi_lcdc_tcon0_mode_set(mode, true);
> > 
> > -		sunxi_composer_enable();
> > -		sunxi_lcdc_enable();
> > +		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE,
> > +			    sunxi_display.depth);
> > +		lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE, 0);
> 
> That one is suspicious. Shouldn't sunxi_composer_enable be left, and
> lcdc_enable called only once?

Uh, missed that. Probably fixup error. It will be fixed in next version.

Best regards,
Jernej Škrabec

> 
> Maxime
> 
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

[U-Boot] [PATCH 4/8] sunxi: video: Split out TCON code

[Maxime Ripard]

Hi,

On Thu, Mar 09, 2017 at 06:16:27PM +0100, Jernej Škrabec wrote:
> Hi Maxime,
> 
> Dne četrtek, 09. marec 2017 ob 09:33:06 CET je Maxime Ripard napisal(a):
> > Hi,
> > 
> > Thanks for your great work.
> > 
> > On Thu, Mar 09, 2017 at 12:34:40AM +0100, Jernej Skrabec wrote:
> > > -	writel(0, &lcdc->tcon0_io_tristate);
> > > +	sunxi_ctfb_mode_to_display_timing(mode, &timing);
> > > +	lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
> > > +			    sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
> > 
> > I'm not sure what this sunxi_ctfb_mode_to_display_timing function is
> > useful for, but it's introduction and the conversion of the users
> > would probably need to be moved to another patch.
> > 
> 
> I forgot to explain this in commit message.
> 
> The thing is that current video display driver for Allwinner SoCs uses older 
> framework called cfb console. This framework uses videomodes.h for timing 
> related functions. In it, there is a structure called "struct ctfb_res_modes", 
> which holds pixel clock, active resolution, sync times, all front/back porch 
> values and so on. In contrast, DM video framework uses different structure 
> "struct display_timing" which is defined in fdtdec.h and holds exactly the same 
> timing informations. It is a bit strange to have two different structures for 
> same type of informations, but at least conversion from ctfb timing to display 
> timming is pretty straightforward, as you can see from the code.
> 
> It made more sense to me to use DM video timing structure because I expect 
> that all new drivers will use this framework and I guess that older will be 
> converted to use this framework too.

That definitely makes sense.

> Should I move this change in new patch?

Yes, please.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH 5/8] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

[Jernej Skrabec]

This is needed for HDMI, which will be added later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---

 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 54 +++++++++++++++++++++++++++
 arch/arm/mach-sunxi/clock_sun6i.c             | 40 +++++++++++++++++++-
 drivers/video/sunxi/lcdc.c                    |  4 ++
 include/configs/sun50i.h                      |  2 +
 include/configs/sun8i.h                       |  4 ++
 scripts/config_whitelist.txt                  |  1 +
 6 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 1aefd5a64c..ebb642747b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
 	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register, A33 only */
 	u32 mbus_reset;		/* 0xfc MBUS reset control, A33 only */
 	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
+#ifdef CONFIG_SUNXI_DE2
+	u32 de_clk_cfg;		/* 0x104 DE module clock */
+#else
 	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
+#endif
 	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
 	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
 	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
 	u32 mp_clk_cfg;		/* 0x114 MP module clock */
+#ifdef CONFIG_SUNXI_DE2
+	u32 lcd0_clk_cfg;	/* 0x118 LCD0 module clock */
+	u32 lcd1_clk_cfg;	/* 0x11c LCD1 module clock */
+#else
 	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
 	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
+#endif
 	u32 reserved14[3];
 	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
 	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
@@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
 	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
 	u32 reserved15;
 	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
+#ifdef CONFIG_SUNXI_DE2
+	u32 hdmi_slow_clk_cfg;	/* 0x154 HDMI slow module clock */
+#else
 	u32 ps_clk_cfg;		/* 0x154 PS module clock */
+#endif
 	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
 	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
 	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
@@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL3_CTRL_N_MASK		(0x7f << CCM_PLL3_CTRL_N_SHIFT)
 #define CCM_PLL3_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
 #define CCM_PLL3_CTRL_INTEGER_MODE	(0x1 << 24)
+#define CCM_PLL3_CTRL_LOCK		(0x1 << 28)
 #define CCM_PLL3_CTRL_EN		(0x1 << 31)
 
 #define CCM_PLL5_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
@@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
 #define CCM_MIPI_PLL_CTRL_LDO_EN	(0x3 << 22)
 #define CCM_MIPI_PLL_CTRL_EN		(0x1 << 31)
 
+#define CCM_PLL10_CTRL_M_SHIFT		0
+#define CCM_PLL10_CTRL_M_MASK		(0xf << CCM_PLL10_CTRL_M_SHIFT)
+#define CCM_PLL10_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_PLL10_CTRL_N_SHIFT		8
+#define CCM_PLL10_CTRL_N_MASK		(0x7f << CCM_PLL10_CTRL_N_SHIFT)
+#define CCM_PLL10_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
+#define CCM_PLL10_CTRL_INTEGER_MODE	(0x1 << 24)
+#define CCM_PLL10_CTRL_LOCK		(0x1 << 28)
+#define CCM_PLL10_CTRL_EN		(0x1 << 31)
+
 #define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
 #define CCM_PLL11_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
 #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
@@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_DRC0		25
 #define AHB_GATE_OFFSET_DE_FE0		14
 #define AHB_GATE_OFFSET_DE_BE0		12
+#define AHB_GATE_OFFSET_DE		12
 #define AHB_GATE_OFFSET_HDMI		11
+#ifndef CONFIG_SUNXI_DE2
 #define AHB_GATE_OFFSET_LCD1		5
 #define AHB_GATE_OFFSET_LCD0		4
+#else
+#define AHB_GATE_OFFSET_LCD1		4
+#define AHB_GATE_OFFSET_LCD0		3
+#endif
 
 #define CCM_MMC_CTRL_M(x)		((x) - 1)
 #define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
@@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
 #define CCM_LCD_CH1_CTRL_PLL7_2X	(3 << 24)
 #define CCM_LCD_CH1_CTRL_GATE		(0x1 << 31)
 
+#define CCM_LCD0_CTRL_GATE		(0x1 << 31)
+#define CCM_LCD0_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+
+#define CCM_LCD1_CTRL_GATE		(0x1 << 31)
+#define CCM_LCD1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+
 #define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
 #define CCM_HDMI_CTRL_PLL_MASK		(3 << 24)
 #define CCM_HDMI_CTRL_PLL3		(0 << 24)
@@ -366,6 +402,8 @@ struct sunxi_ccm_reg {
 #define CCM_HDMI_CTRL_DDC_GATE		(0x1 << 30)
 #define CCM_HDMI_CTRL_GATE		(0x1 << 31)
 
+#define CCM_HDMI_SLOW_CTRL_DDC_GATE	(1 << 31)
+
 #if defined(CONFIG_MACH_SUN50I)
 #define MBUS_CLK_DEFAULT		0x81000002 /* PLL6x2 / 3 */
 #elif defined(CONFIG_MACH_SUN8I)
@@ -393,9 +431,16 @@ struct sunxi_ccm_reg {
 #define AHB_RESET_OFFSET_DRC0		25
 #define AHB_RESET_OFFSET_DE_FE0		14
 #define AHB_RESET_OFFSET_DE_BE0		12
+#define AHB_RESET_OFFSET_DE		12
 #define AHB_RESET_OFFSET_HDMI		11
+#define AHB_RESET_OFFSET_HDMI2		10
+#ifndef CONFIG_SUNXI_DE2
 #define AHB_RESET_OFFSET_LCD1		5
 #define AHB_RESET_OFFSET_LCD0		4
+#else
+#define AHB_RESET_OFFSET_LCD1		4
+#define AHB_RESET_OFFSET_LCD0		3
+#endif
 
 /* ahb_reset2 offsets */
 #define AHB_RESET_OFFSET_EPHY		2
@@ -418,6 +463,13 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_PLL10		(5 << 24)
 #define CCM_DE_CTRL_GATE		(1 << 31)
 
+/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
+#define CCM_DE2_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_DE2_CTRL_PLL_MASK		(3 << 24)
+#define CCM_DE2_CTRL_PLL6_2X		(0 << 24)
+#define CCM_DE2_CTRL_PLL10		(1 << 24)
+#define CCM_DE2_CTRL_GATE		(1 << 31)
+
 /* CCU security switch, H3 only */
 #define CCM_SEC_SWITCH_MBUS_NONSEC	(1 << 2)
 #define CCM_SEC_SWITCH_BUS_NONSEC	(1 << 1)
@@ -426,7 +478,9 @@ struct sunxi_ccm_reg {
 #ifndef __ASSEMBLY__
 void clock_set_pll1(unsigned int hz);
 void clock_set_pll3(unsigned int hz);
+void clock_set_pll3_factors(int m, int n);
 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+void clock_set_pll10(unsigned int hz);
 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
 void clock_set_mipi_pll(unsigned int hz);
 unsigned int clock_get_pll3(void);
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 3c8c53fcf7..7a59f4cd74 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -35,7 +35,7 @@ void clock_init_safe(void)
 	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
 #endif
 
-#ifdef CONFIG_MACH_SUN8I_R40
+#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
 	/* Set PLL lock enable bits and switch to old lock mode */
 	writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
 #endif
@@ -150,6 +150,22 @@ void clock_set_pll3(unsigned int clk)
 	       &ccm->pll3_cfg);
 }
 
+#ifdef CONFIG_SUNXI_DE2
+void clock_set_pll3_factors(int m, int n)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* PLL3 rate = 24000000 * n / m */
+	writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+	       CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
+	       &ccm->pll3_cfg);
+
+	while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
+		;
+}
+#endif
+
 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 {
 	struct sunxi_ccm_reg * const ccm =
@@ -222,6 +238,28 @@ done:
 }
 #endif
 
+#ifdef CONFIG_SUNXI_DE2
+void clock_set_pll10(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	const int m = 2; /* 12 MHz steps */
+
+	if (clk == 0) {
+		clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
+		return;
+	}
+
+	/* PLL10 rate = 24000000 * n / m */
+	writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
+	       CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
+	       &ccm->pll10_cfg);
+
+	while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
+		;
+}
+#endif
+
 #if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 {
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 8c8fb2e4ee..7d215b713e 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -74,9 +74,11 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
 {
 	int bp, clk_delay, total, val;
 
+#ifndef CONFIG_SUNXI_DE2
 	/* Use tcon0 */
 	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 			SUNXI_LCDC_CTRL_IO_MAP_TCON0);
+#endif
 
 	clk_delay = lcdc_get_clk_delay(mode, 0);
 	writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
@@ -149,9 +151,11 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
 {
 	int bp, clk_delay, total, val, yres;
 
+#ifndef CONFIG_SUNXI_DE2
 	/* Use tcon1 */
 	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 			SUNXI_LCDC_CTRL_IO_MAP_TCON1);
+#endif
 
 	clk_delay = lcdc_get_clk_delay(mode, 1);
 	writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
index 1b7bfb6c22..146f7f4e1b 100644
--- a/include/configs/sun50i.h
+++ b/include/configs/sun50i.h
@@ -21,6 +21,8 @@
 #define GICD_BASE		0x1c81000
 #define GICC_BASE		0x1c82000
 
+#define CONFIG_SUNXI_DE2
+
 /*
  * Include common sunxi configuration where most the settings are
  */
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index a4c3fb69e4..c42b901107 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -25,6 +25,10 @@
 	#define CONFIG_SUNXI_USB_PHYS	2
 #endif
 
+#ifdef CONFIG_MACH_SUNXI_H3_H5
+#define CONFIG_SUNXI_DE2
+#endif
+
 /*
  * Include common sunxi configuration where most the settings are
  */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 8e5dc36fa7..ba0eb12665 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3102,6 +3102,7 @@ CONFIG_STV0991_HZ_CLOCK
 CONFIG_ST_SMI
 CONFIG_SUN4
 CONFIG_SUNXI_AHCI
+CONFIG_SUNXI_DE2
 CONFIG_SUNXI_EMAC
 CONFIG_SUNXI_GMAC
 CONFIG_SUNXI_GPIO
-- 
2.12.0

[U-Boot] [PATCH 5/8] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

[Simon Glass]

Hi,

On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
> This is needed for HDMI, which will be added later.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
>
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 54 +++++++++++++++++++++++++++
>  arch/arm/mach-sunxi/clock_sun6i.c             | 40 +++++++++++++++++++-
>  drivers/video/sunxi/lcdc.c                    |  4 ++
>  include/configs/sun50i.h                      |  2 +
>  include/configs/sun8i.h                       |  4 ++
>  scripts/config_whitelist.txt                  |  1 +
>  6 files changed, 104 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

Please see below.

>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index 1aefd5a64c..ebb642747b 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
>         u32 dram_pll_cfg;       /* 0xf8 PLL_DDR cfg register, A33 only */
>         u32 mbus_reset;         /* 0xfc MBUS reset control, A33 only */
>         u32 dram_clk_gate;      /* 0x100 DRAM module gating */
> +#ifdef CONFIG_SUNXI_DE2
> +       u32 de_clk_cfg;         /* 0x104 DE module clock */
> +#else
>         u32 be0_clk_cfg;        /* 0x104 BE0 module clock */
> +#endif
>         u32 be1_clk_cfg;        /* 0x108 BE1 module clock */
>         u32 fe0_clk_cfg;        /* 0x10c FE0 module clock */
>         u32 fe1_clk_cfg;        /* 0x110 FE1 module clock */
>         u32 mp_clk_cfg;         /* 0x114 MP module clock */
> +#ifdef CONFIG_SUNXI_DE2
> +       u32 lcd0_clk_cfg;       /* 0x118 LCD0 module clock */
> +       u32 lcd1_clk_cfg;       /* 0x11c LCD1 module clock */
> +#else
>         u32 lcd0_ch0_clk_cfg;   /* 0x118 LCD0 CH0 module clock */
>         u32 lcd1_ch0_clk_cfg;   /* 0x11c LCD1 CH0 module clock */
> +#endif
>         u32 reserved14[3];
>         u32 lcd0_ch1_clk_cfg;   /* 0x12c LCD0 CH1 module clock */
>         u32 lcd1_ch1_clk_cfg;   /* 0x130 LCD1 CH1 module clock */
> @@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
>         u32 dmic_clk_cfg;       /* 0x148 Digital Mic module clock*/
>         u32 reserved15;
>         u32 hdmi_clk_cfg;       /* 0x150 HDMI module clock */
> +#ifdef CONFIG_SUNXI_DE2
> +       u32 hdmi_slow_clk_cfg;  /* 0x154 HDMI slow module clock */
> +#else
>         u32 ps_clk_cfg;         /* 0x154 PS module clock */
> +#endif
>         u32 mtc_clk_cfg;        /* 0x158 MTC module clock */
>         u32 mbus0_clk_cfg;      /* 0x15c MBUS0 module clock */
>         u32 mbus1_clk_cfg;      /* 0x160 MBUS1 module clock */
> @@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
>  #define CCM_PLL3_CTRL_N_MASK           (0x7f << CCM_PLL3_CTRL_N_SHIFT)
>  #define CCM_PLL3_CTRL_N(n)             ((((n) - 1) & 0x7f) << 8)
>  #define CCM_PLL3_CTRL_INTEGER_MODE     (0x1 << 24)
> +#define CCM_PLL3_CTRL_LOCK             (0x1 << 28)
>  #define CCM_PLL3_CTRL_EN               (0x1 << 31)
>
>  #define CCM_PLL5_CTRL_M(n)             ((((n) - 1) & 0x3) << 0)
> @@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
>  #define CCM_MIPI_PLL_CTRL_LDO_EN       (0x3 << 22)
>  #define CCM_MIPI_PLL_CTRL_EN           (0x1 << 31)
>
> +#define CCM_PLL10_CTRL_M_SHIFT         0
> +#define CCM_PLL10_CTRL_M_MASK          (0xf << CCM_PLL10_CTRL_M_SHIFT)
> +#define CCM_PLL10_CTRL_M(n)            ((((n) - 1) & 0xf) << 0)
> +#define CCM_PLL10_CTRL_N_SHIFT         8
> +#define CCM_PLL10_CTRL_N_MASK          (0x7f << CCM_PLL10_CTRL_N_SHIFT)
> +#define CCM_PLL10_CTRL_N(n)            ((((n) - 1) & 0x7f) << 8)
> +#define CCM_PLL10_CTRL_INTEGER_MODE    (0x1 << 24)
> +#define CCM_PLL10_CTRL_LOCK            (0x1 << 28)
> +#define CCM_PLL10_CTRL_EN              (0x1 << 31)
> +
>  #define CCM_PLL11_CTRL_N(n)            ((((n) - 1) & 0x3f) << 8)
>  #define CCM_PLL11_CTRL_SIGMA_DELTA_EN  (0x1 << 24)
>  #define CCM_PLL11_CTRL_UPD             (0x1 << 30)
> @@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
>  #define AHB_GATE_OFFSET_DRC0           25
>  #define AHB_GATE_OFFSET_DE_FE0         14
>  #define AHB_GATE_OFFSET_DE_BE0         12
> +#define AHB_GATE_OFFSET_DE             12
>  #define AHB_GATE_OFFSET_HDMI           11
> +#ifndef CONFIG_SUNXI_DE2
>  #define AHB_GATE_OFFSET_LCD1           5
>  #define AHB_GATE_OFFSET_LCD0           4
> +#else
> +#define AHB_GATE_OFFSET_LCD1           4
> +#define AHB_GATE_OFFSET_LCD0           3
> +#endif
>
>  #define CCM_MMC_CTRL_M(x)              ((x) - 1)
>  #define CCM_MMC_CTRL_OCLK_DLY(x)       ((x) << 8)
> @@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
>  #define CCM_LCD_CH1_CTRL_PLL7_2X       (3 << 24)
>  #define CCM_LCD_CH1_CTRL_GATE          (0x1 << 31)
>
> +#define CCM_LCD0_CTRL_GATE             (0x1 << 31)
> +#define CCM_LCD0_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
> +
> +#define CCM_LCD1_CTRL_GATE             (0x1 << 31)
> +#define CCM_LCD1_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
> +
>  #define CCM_HDMI_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
>  #define CCM_HDMI_CTRL_PLL_MASK         (3 << 24)
>  #define CCM_HDMI_CTRL_PLL3             (0 << 24)
> @@ -366,6 +402,8 @@ struct sunxi_ccm_reg {
>  #define CCM_HDMI_CTRL_DDC_GATE         (0x1 << 30)
>  #define CCM_HDMI_CTRL_GATE             (0x1 << 31)
>
> +#define CCM_HDMI_SLOW_CTRL_DDC_GATE    (1 << 31)

I think 1UL << 31 would be safer.

Regards,
Simon

[U-Boot] [PATCH 5/8] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

[Jernej Škrabec]

Hi,

Dne ponedeljek, 13. marec 2017 ob 13:33:43 CET je Simon Glass napisal(a):
> Hi,
> 
> On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
> > This is needed for HDMI, which will be added later.
> > 
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > ---
> > 
> >  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 54
> >  +++++++++++++++++++++++++++ arch/arm/mach-sunxi/clock_sun6i.c           
> >   | 40 +++++++++++++++++++- drivers/video/sunxi/lcdc.c                   
> >  |  4 ++
> >  include/configs/sun50i.h                      |  2 +
> >  include/configs/sun8i.h                       |  4 ++
> >  scripts/config_whitelist.txt                  |  1 +
> >  6 files changed, 104 insertions(+), 1 deletion(-)
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> 
> Please see below.
> 
> > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> > b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index
> > 1aefd5a64c..ebb642747b 100644
> > --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> > @@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
> > 
> >         u32 dram_pll_cfg;       /* 0xf8 PLL_DDR cfg register, A33 only */
> >         u32 mbus_reset;         /* 0xfc MBUS reset control, A33 only */
> >         u32 dram_clk_gate;      /* 0x100 DRAM module gating */
> > 
> > +#ifdef CONFIG_SUNXI_DE2
> > +       u32 de_clk_cfg;         /* 0x104 DE module clock */
> > +#else
> > 
> >         u32 be0_clk_cfg;        /* 0x104 BE0 module clock */
> > 
> > +#endif
> > 
> >         u32 be1_clk_cfg;        /* 0x108 BE1 module clock */
> >         u32 fe0_clk_cfg;        /* 0x10c FE0 module clock */
> >         u32 fe1_clk_cfg;        /* 0x110 FE1 module clock */
> >         u32 mp_clk_cfg;         /* 0x114 MP module clock */
> > 
> > +#ifdef CONFIG_SUNXI_DE2
> > +       u32 lcd0_clk_cfg;       /* 0x118 LCD0 module clock */
> > +       u32 lcd1_clk_cfg;       /* 0x11c LCD1 module clock */
> > +#else
> > 
> >         u32 lcd0_ch0_clk_cfg;   /* 0x118 LCD0 CH0 module clock */
> >         u32 lcd1_ch0_clk_cfg;   /* 0x11c LCD1 CH0 module clock */
> > 
> > +#endif
> > 
> >         u32 reserved14[3];
> >         u32 lcd0_ch1_clk_cfg;   /* 0x12c LCD0 CH1 module clock */
> >         u32 lcd1_ch1_clk_cfg;   /* 0x130 LCD1 CH1 module clock */
> > 
> > @@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
> > 
> >         u32 dmic_clk_cfg;       /* 0x148 Digital Mic module clock*/
> >         u32 reserved15;
> >         u32 hdmi_clk_cfg;       /* 0x150 HDMI module clock */
> > 
> > +#ifdef CONFIG_SUNXI_DE2
> > +       u32 hdmi_slow_clk_cfg;  /* 0x154 HDMI slow module clock */
> > +#else
> > 
> >         u32 ps_clk_cfg;         /* 0x154 PS module clock */
> > 
> > +#endif
> > 
> >         u32 mtc_clk_cfg;        /* 0x158 MTC module clock */
> >         u32 mbus0_clk_cfg;      /* 0x15c MBUS0 module clock */
> >         u32 mbus1_clk_cfg;      /* 0x160 MBUS1 module clock */
> > 
> > @@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_PLL3_CTRL_N_MASK           (0x7f << CCM_PLL3_CTRL_N_SHIFT)
> >  #define CCM_PLL3_CTRL_N(n)             ((((n) - 1) & 0x7f) << 8)
> >  #define CCM_PLL3_CTRL_INTEGER_MODE     (0x1 << 24)
> > 
> > +#define CCM_PLL3_CTRL_LOCK             (0x1 << 28)
> > 
> >  #define CCM_PLL3_CTRL_EN               (0x1 << 31)
> >  
> >  #define CCM_PLL5_CTRL_M(n)             ((((n) - 1) & 0x3) << 0)
> > 
> > @@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_MIPI_PLL_CTRL_LDO_EN       (0x3 << 22)
> >  #define CCM_MIPI_PLL_CTRL_EN           (0x1 << 31)
> > 
> > +#define CCM_PLL10_CTRL_M_SHIFT         0
> > +#define CCM_PLL10_CTRL_M_MASK          (0xf << CCM_PLL10_CTRL_M_SHIFT)
> > +#define CCM_PLL10_CTRL_M(n)            ((((n) - 1) & 0xf) << 0)
> > +#define CCM_PLL10_CTRL_N_SHIFT         8
> > +#define CCM_PLL10_CTRL_N_MASK          (0x7f << CCM_PLL10_CTRL_N_SHIFT)
> > +#define CCM_PLL10_CTRL_N(n)            ((((n) - 1) & 0x7f) << 8)
> > +#define CCM_PLL10_CTRL_INTEGER_MODE    (0x1 << 24)
> > +#define CCM_PLL10_CTRL_LOCK            (0x1 << 28)
> > +#define CCM_PLL10_CTRL_EN              (0x1 << 31)
> > +
> > 
> >  #define CCM_PLL11_CTRL_N(n)            ((((n) - 1) & 0x3f) << 8)
> >  #define CCM_PLL11_CTRL_SIGMA_DELTA_EN  (0x1 << 24)
> >  #define CCM_PLL11_CTRL_UPD             (0x1 << 30)
> > 
> > @@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
> > 
> >  #define AHB_GATE_OFFSET_DRC0           25
> >  #define AHB_GATE_OFFSET_DE_FE0         14
> >  #define AHB_GATE_OFFSET_DE_BE0         12
> > 
> > +#define AHB_GATE_OFFSET_DE             12
> > 
> >  #define AHB_GATE_OFFSET_HDMI           11
> > 
> > +#ifndef CONFIG_SUNXI_DE2
> > 
> >  #define AHB_GATE_OFFSET_LCD1           5
> >  #define AHB_GATE_OFFSET_LCD0           4
> > 
> > +#else
> > +#define AHB_GATE_OFFSET_LCD1           4
> > +#define AHB_GATE_OFFSET_LCD0           3
> > +#endif
> > 
> >  #define CCM_MMC_CTRL_M(x)              ((x) - 1)
> >  #define CCM_MMC_CTRL_OCLK_DLY(x)       ((x) << 8)
> > 
> > @@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_LCD_CH1_CTRL_PLL7_2X       (3 << 24)
> >  #define CCM_LCD_CH1_CTRL_GATE          (0x1 << 31)
> > 
> > +#define CCM_LCD0_CTRL_GATE             (0x1 << 31)
> > +#define CCM_LCD0_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
> > +
> > +#define CCM_LCD1_CTRL_GATE             (0x1 << 31)
> > +#define CCM_LCD1_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
> > +
> > 
> >  #define CCM_HDMI_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
> >  #define CCM_HDMI_CTRL_PLL_MASK         (3 << 24)
> >  #define CCM_HDMI_CTRL_PLL3             (0 << 24)
> > 
> > @@ -366,6 +402,8 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_HDMI_CTRL_DDC_GATE         (0x1 << 30)
> >  #define CCM_HDMI_CTRL_GATE             (0x1 << 31)
> > 
> > +#define CCM_HDMI_SLOW_CTRL_DDC_GATE    (1 << 31)
> 
> I think 1UL << 31 would be safer.
> 

I agree, but I'm leaning more towards (0x1 << 31) to be more consistent with 
previous declarations. Any thoughts?

Regards,
Jernej

> Regards,
> Simon

[U-Boot] [linux-sunxi] Re: [PATCH 5/8] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

[Ondřej Jirman]

Hi,

Dne 14.3.2017 v 07:53 Jernej Å krabec napsal(a):
> Hi,
> 
> Dne ponedeljek, 13. marec 2017 ob 13:33:43 CET je Simon Glass napisal(a):
>> Hi,
>>
>> On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
>>> This is needed for HDMI, which will be added later.
>>>
>>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>>> ---
>>>
>>>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 54
>>>  +++++++++++++++++++++++++++ arch/arm/mach-sunxi/clock_sun6i.c           
>>>   | 40 +++++++++++++++++++- drivers/video/sunxi/lcdc.c                   
>>>  |  4 ++
>>>  include/configs/sun50i.h                      |  2 +
>>>  include/configs/sun8i.h                       |  4 ++
>>>  scripts/config_whitelist.txt                  |  1 +
>>>  6 files changed, 104 insertions(+), 1 deletion(-)
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>
>> Please see below.
>>
>>> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>>> b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index
>>> 1aefd5a64c..ebb642747b 100644
>>> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>>> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>>> @@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
>>>
>>>         u32 dram_pll_cfg;       /* 0xf8 PLL_DDR cfg register, A33 only */
>>>         u32 mbus_reset;         /* 0xfc MBUS reset control, A33 only */
>>>         u32 dram_clk_gate;      /* 0x100 DRAM module gating */
>>>
>>> +#ifdef CONFIG_SUNXI_DE2
>>> +       u32 de_clk_cfg;         /* 0x104 DE module clock */
>>> +#else
>>>
>>>         u32 be0_clk_cfg;        /* 0x104 BE0 module clock */
>>>
>>> +#endif
>>>
>>>         u32 be1_clk_cfg;        /* 0x108 BE1 module clock */
>>>         u32 fe0_clk_cfg;        /* 0x10c FE0 module clock */
>>>         u32 fe1_clk_cfg;        /* 0x110 FE1 module clock */
>>>         u32 mp_clk_cfg;         /* 0x114 MP module clock */
>>>
>>> +#ifdef CONFIG_SUNXI_DE2
>>> +       u32 lcd0_clk_cfg;       /* 0x118 LCD0 module clock */
>>> +       u32 lcd1_clk_cfg;       /* 0x11c LCD1 module clock */
>>> +#else
>>>
>>>         u32 lcd0_ch0_clk_cfg;   /* 0x118 LCD0 CH0 module clock */
>>>         u32 lcd1_ch0_clk_cfg;   /* 0x11c LCD1 CH0 module clock */
>>>
>>> +#endif
>>>
>>>         u32 reserved14[3];
>>>         u32 lcd0_ch1_clk_cfg;   /* 0x12c LCD0 CH1 module clock */
>>>         u32 lcd1_ch1_clk_cfg;   /* 0x130 LCD1 CH1 module clock */
>>>
>>> @@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
>>>
>>>         u32 dmic_clk_cfg;       /* 0x148 Digital Mic module clock*/
>>>         u32 reserved15;
>>>         u32 hdmi_clk_cfg;       /* 0x150 HDMI module clock */
>>>
>>> +#ifdef CONFIG_SUNXI_DE2
>>> +       u32 hdmi_slow_clk_cfg;  /* 0x154 HDMI slow module clock */
>>> +#else
>>>
>>>         u32 ps_clk_cfg;         /* 0x154 PS module clock */
>>>
>>> +#endif
>>>
>>>         u32 mtc_clk_cfg;        /* 0x158 MTC module clock */
>>>         u32 mbus0_clk_cfg;      /* 0x15c MBUS0 module clock */
>>>         u32 mbus1_clk_cfg;      /* 0x160 MBUS1 module clock */
>>>
>>> @@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
>>>
>>>  #define CCM_PLL3_CTRL_N_MASK           (0x7f << CCM_PLL3_CTRL_N_SHIFT)
>>>  #define CCM_PLL3_CTRL_N(n)             ((((n) - 1) & 0x7f) << 8)
>>>  #define CCM_PLL3_CTRL_INTEGER_MODE     (0x1 << 24)
>>>
>>> +#define CCM_PLL3_CTRL_LOCK             (0x1 << 28)
>>>
>>>  #define CCM_PLL3_CTRL_EN               (0x1 << 31)
>>>  
>>>  #define CCM_PLL5_CTRL_M(n)             ((((n) - 1) & 0x3) << 0)
>>>
>>> @@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
>>>
>>>  #define CCM_MIPI_PLL_CTRL_LDO_EN       (0x3 << 22)
>>>  #define CCM_MIPI_PLL_CTRL_EN           (0x1 << 31)
>>>
>>> +#define CCM_PLL10_CTRL_M_SHIFT         0
>>> +#define CCM_PLL10_CTRL_M_MASK          (0xf << CCM_PLL10_CTRL_M_SHIFT)
>>> +#define CCM_PLL10_CTRL_M(n)            ((((n) - 1) & 0xf) << 0)
>>> +#define CCM_PLL10_CTRL_N_SHIFT         8
>>> +#define CCM_PLL10_CTRL_N_MASK          (0x7f << CCM_PLL10_CTRL_N_SHIFT)
>>> +#define CCM_PLL10_CTRL_N(n)            ((((n) - 1) & 0x7f) << 8)
>>> +#define CCM_PLL10_CTRL_INTEGER_MODE    (0x1 << 24)
>>> +#define CCM_PLL10_CTRL_LOCK            (0x1 << 28)
>>> +#define CCM_PLL10_CTRL_EN              (0x1 << 31)
>>> +
>>>
>>>  #define CCM_PLL11_CTRL_N(n)            ((((n) - 1) & 0x3f) << 8)
>>>  #define CCM_PLL11_CTRL_SIGMA_DELTA_EN  (0x1 << 24)
>>>  #define CCM_PLL11_CTRL_UPD             (0x1 << 30)
>>>
>>> @@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
>>>
>>>  #define AHB_GATE_OFFSET_DRC0           25
>>>  #define AHB_GATE_OFFSET_DE_FE0         14
>>>  #define AHB_GATE_OFFSET_DE_BE0         12
>>>
>>> +#define AHB_GATE_OFFSET_DE             12
>>>
>>>  #define AHB_GATE_OFFSET_HDMI           11
>>>
>>> +#ifndef CONFIG_SUNXI_DE2
>>>
>>>  #define AHB_GATE_OFFSET_LCD1           5
>>>  #define AHB_GATE_OFFSET_LCD0           4
>>>
>>> +#else
>>> +#define AHB_GATE_OFFSET_LCD1           4
>>> +#define AHB_GATE_OFFSET_LCD0           3
>>> +#endif
>>>
>>>  #define CCM_MMC_CTRL_M(x)              ((x) - 1)
>>>  #define CCM_MMC_CTRL_OCLK_DLY(x)       ((x) << 8)
>>>
>>> @@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
>>>
>>>  #define CCM_LCD_CH1_CTRL_PLL7_2X       (3 << 24)
>>>  #define CCM_LCD_CH1_CTRL_GATE          (0x1 << 31)
>>>
>>> +#define CCM_LCD0_CTRL_GATE             (0x1 << 31)
>>> +#define CCM_LCD0_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
>>> +
>>> +#define CCM_LCD1_CTRL_GATE             (0x1 << 31)
>>> +#define CCM_LCD1_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
>>> +
>>>
>>>  #define CCM_HDMI_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
>>>  #define CCM_HDMI_CTRL_PLL_MASK         (3 << 24)
>>>  #define CCM_HDMI_CTRL_PLL3             (0 << 24)
>>>
>>> @@ -366,6 +402,8 @@ struct sunxi_ccm_reg {
>>>
>>>  #define CCM_HDMI_CTRL_DDC_GATE         (0x1 << 30)
>>>  #define CCM_HDMI_CTRL_GATE             (0x1 << 31)
>>>
>>> +#define CCM_HDMI_SLOW_CTRL_DDC_GATE    (1 << 31)
>>
>> I think 1UL << 31 would be safer.
>>
> 
> I agree, but I'm leaning more towards (0x1 << 31) to be more consistent with 
> previous declarations. Any thoughts?

(0x1 << n) is still of a signed int type in most cases if that matters
here. But it probably does not.

See page 55 of C standard.

http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1124.pdf

  o.

> Regards,
> Jernej
> 
>> Regards,
>> Simon
> 
> 

[U-Boot] [PATCH 6/8] sunxi: video: Add A64/H3/H5 HDMI driver

[Jernej Skrabec]

This commit adds support for HDMI output.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---

 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |   8 +
 arch/arm/include/asm/arch-sunxi/display2.h  | 124 +++++++++
 board/sunxi/Kconfig                         |  10 +
 drivers/video/sunxi/Makefile                |   1 +
 drivers/video/sunxi/sunxi_de2.c             | 258 ++++++++++++++++++
 drivers/video/sunxi/sunxi_dw_hdmi.c         | 389 ++++++++++++++++++++++++++++
 include/configs/sunxi-common.h              |   5 +
 7 files changed, 795 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/display2.h
 create mode 100644 drivers/video/sunxi/sunxi_de2.c
 create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi.c

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index ea672fe844..3ce46d024e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -18,6 +18,8 @@
 #define SUNXI_SRAM_D_BASE		0x00010000	/* 4 kiB */
 #define SUNXI_SRAM_B_BASE		0x00020000	/* 64 kiB (secure) */
 
+#define SUNXI_DE2_BASE			0x01000000
+
 #ifdef CONFIG_MACH_SUN8I_A83T
 #define SUNXI_CPUCFG_BASE		0x01700000
 #endif
@@ -46,7 +48,9 @@
 #define SUNXI_USB1_BASE			0x01c14000
 #endif
 #define SUNXI_SS_BASE			0x01c15000
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
 #define SUNXI_HDMI_BASE			0x01c16000
+#endif
 #define SUNXI_SPI2_BASE			0x01c17000
 #define SUNXI_SATA_BASE			0x01c18000
 #ifdef CONFIG_SUNXI_GEN_SUN4I
@@ -164,6 +168,10 @@ defined(CONFIG_MACH_SUN50I)
 #define SUNXI_MP_BASE			0x01e80000
 #define SUNXI_AVG_BASE			0x01ea0000
 
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define SUNXI_HDMI_BASE			0x01ee0000
+#endif
+
 #define SUNXI_RTC_BASE			0x01f00000
 #define SUNXI_PRCM_BASE			0x01f01400
 
diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h
new file mode 100644
index 0000000000..b5875f9605
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/display2.h
@@ -0,0 +1,124 @@
+/*
+ * Sunxi platform display controller register and constant defines
+ *
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * Based on out of tree Linux DRM driver defines:
+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
+*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_DISPLAY2_H
+#define _SUNXI_DISPLAY2_H
+
+/* internal clock settings */
+struct de_clk {
+	u32 gate_cfg;
+	u32 bus_cfg;
+	u32 rst_cfg;
+	u32 div_cfg;
+	u32 sel_cfg;
+};
+
+/* global control */
+struct de_glb {
+	u32 ctl;
+	u32 status;
+	u32 dbuff;
+	u32 size;
+};
+
+/* alpha blending */
+struct de_bld {
+	u32 fcolor_ctl;
+	struct {
+		u32 fcolor;
+		u32 insize;
+		u32 offset;
+		u32 dum;
+	} attr[4];
+	u32 dum0[15];
+	u32 route;
+	u32 premultiply;
+	u32 bkcolor;
+	u32 output_size;
+	u32 bld_mode[4];
+	u32 dum1[4];
+	u32 ck_ctl;
+	u32 ck_cfg;
+	u32 dum2[2];
+	u32 ck_max[4];
+	u32 dum3[4];
+	u32 ck_min[4];
+	u32 dum4[3];
+	u32 out_ctl;
+};
+
+/* VI channel */
+struct de_vi {
+	struct {
+		u32 attr;
+		u32 size;
+		u32 coord;
+		u32 pitch[3];
+		u32 top_laddr[3];
+		u32 bot_laddr[3];
+	} cfg[4];
+	u32 fcolor[4];
+	u32 top_haddr[3];
+	u32 bot_haddr[3];
+	u32 ovl_size[2];
+	u32 hori[2];
+	u32 vert[2];
+};
+
+struct de_ui {
+	struct {
+		u32 attr;
+		u32 size;
+		u32 coord;
+		u32 pitch;
+		u32 top_laddr;
+		u32 bot_laddr;
+		u32 fcolor;
+		u32 dum;
+	} cfg[4];
+	u32 top_haddr;
+	u32 bot_haddr;
+	u32 ovl_size;
+};
+
+/*
+ * DE register constants.
+ */
+#define SUNXI_DE2_MUX0_BASE			(SUNXI_DE2_BASE + 0x100000)
+#define SUNXI_DE2_MUX1_BASE			(SUNXI_DE2_BASE + 0x200000)
+
+#define SUNXI_DE2_MUX_GLB_REGS			0x00000
+#define SUNXI_DE2_MUX_BLD_REGS			0x01000
+#define SUNXI_DE2_MUX_CHAN_REGS			0x02000
+#define SUNXI_DE2_MUX_CHAN_SZ			0x1000
+#define SUNXI_DE2_MUX_VSU_REGS			0x20000
+#define SUNXI_DE2_MUX_GSU1_REGS			0x30000
+#define SUNXI_DE2_MUX_GSU2_REGS			0x40000
+#define SUNXI_DE2_MUX_GSU3_REGS			0x50000
+#define SUNXI_DE2_MUX_FCE_REGS			0xa0000
+#define SUNXI_DE2_MUX_BWS_REGS			0xa2000
+#define SUNXI_DE2_MUX_LTI_REGS			0xa4000
+#define SUNXI_DE2_MUX_PEAK_REGS			0xa6000
+#define SUNXI_DE2_MUX_ASE_REGS			0xa8000
+#define SUNXI_DE2_MUX_FCC_REGS			0xaa000
+#define SUNXI_DE2_MUX_DCSC_REGS			0xb0000
+
+#define SUNXI_DE2_FORMAT_XRGB_8888		4
+#define SUNXI_DE2_FORMAT_RGB_565		10
+
+#define SUNXI_DE2_MUX_GLB_CTL_EN		(1 << 0)
+#define SUNXI_DE2_UI_CFG_ATTR_EN		(1 << 0)
+#define SUNXI_DE2_UI_CFG_ATTR_FMT(f)		((f & 0xf) << 8)
+
+#define SUNXI_DE2_WH(w, h)			(((h - 1) << 16) | (w - 1))
+
+#endif /* _SUNXI_DISPLAY2_H */
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 3e0e262473..7347ad61cd 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -704,6 +704,16 @@ config VIDEO_LCD_TL059WV5C0
 
 endchoice
 
+config VIDEO_DE2
+	bool"Display Engine 2 video driver"
+	depends on  MACH_SUNXI_H3_H5 || MACH_SUN50I
+	select DM_VIDEO
+	select DISPLAY
+	default y
+	---help---
+	Say y here if you want to build DE2 video driver which is present on
+	newer SoCs. Currently only HDMI output is supported.
+
 
 config GMAC_TX_DELAY
 	int "GMAC Transmit Clock Delay Chain"
diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile
index dfc9b47a1f..b8afd892ad 100644
--- a/drivers/video/sunxi/Makefile
+++ b/drivers/video/sunxi/Makefile
@@ -6,3 +6,4 @@
 #
 
 obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o ../videomodes.o
+obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
new file mode 100644
index 0000000000..47872b4c6d
--- /dev/null
+++ b/drivers/video/sunxi/sunxi_de2.c
@@ -0,0 +1,258 @@
+/*
+ * Allwinner DE2 display driver
+ *
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <display.h>
+#include <dm.h>
+#include <edid.h>
+#include <video.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/display2.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	/* Maximum LCD size we support */
+	LCD_MAX_WIDTH		= 3840,
+	LCD_MAX_HEIGHT		= 2160,
+	LCD_MAX_LOG2_BPP	= VIDEO_BPP32,
+};
+
+static void sunxi_de2_composer_init(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#ifdef CONFIG_MACH_SUN50I
+	u32 reg_value;
+
+	/* set SRAM for video use (A64 only) */
+	reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
+	reg_value &= ~(0x01 << 24);
+	writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
+#endif
+
+	clock_set_pll10(432000000);
+
+	/* Set DE parent to pll10 */
+	clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
+			CCM_DE2_CTRL_PLL10);
+
+	/* Set ahb gating to pass */
+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
+	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
+
+	/* Clock on */
+	setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
+}
+
+static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
+			       int bpp, ulong address)
+{
+	ulong de_mux_base = (mux == 0) ?
+			    SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
+	struct de_clk * const de_clk_regs =
+		(struct de_clk *)(SUNXI_DE2_BASE);
+	struct de_glb * const de_glb_regs =
+		(struct de_glb *)(de_mux_base +
+				  SUNXI_DE2_MUX_GLB_REGS);
+	struct de_bld * const de_bld_regs =
+		(struct de_bld *)(de_mux_base +
+				  SUNXI_DE2_MUX_BLD_REGS);
+	struct de_ui * const de_ui_regs =
+		(struct de_ui *)(de_mux_base +
+				 SUNXI_DE2_MUX_CHAN_REGS +
+				 SUNXI_DE2_MUX_CHAN_SZ * 1);
+	u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
+	int channel;
+	u32 format;
+
+	/* enable clock */
+#ifdef CONFIG_MACH_SUN8I_H3
+	setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
+#else
+	setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
+#endif
+	setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
+	setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
+
+	clrbits_le32(&de_clk_regs->sel_cfg, 1);
+
+	writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
+	writel(0, &de_glb_regs->status);
+	writel(1, &de_glb_regs->dbuff);
+	writel(size, &de_glb_regs->size);
+
+	for (channel = 0; channel < 4; channel++) {
+		void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
+				    SUNXI_DE2_MUX_CHAN_SZ * channel);
+		memset(ch, 0, (channel == 0) ?
+			sizeof(struct de_vi) : sizeof(struct de_ui));
+	}
+	memset(de_bld_regs, 0, sizeof(struct de_bld));
+
+	writel(0x00000101, &de_bld_regs->fcolor_ctl);
+
+	writel(1, &de_bld_regs->route);
+
+	writel(0, &de_bld_regs->premultiply);
+	writel(0xff000000, &de_bld_regs->bkcolor);
+
+	writel(0x03010301, &de_bld_regs->bld_mode[0]);
+
+	writel(size, &de_bld_regs->output_size);
+	writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
+	       &de_bld_regs->out_ctl);
+	writel(0, &de_bld_regs->ck_ctl);
+
+	writel(0xff000000, &de_bld_regs->attr[0].fcolor);
+	writel(size, &de_bld_regs->attr[0].insize);
+
+	/* Disable all other units */
+	writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
+	writel(0, de_mux_base + SUNXI_DE2_MUX_DCSC_REGS);
+
+	switch (bpp) {
+	case 16:
+		format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
+		break;
+	case 32:
+	default:
+		format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
+		break;
+	}
+
+	writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
+	writel(size, &de_ui_regs->cfg[0].size);
+	writel(0, &de_ui_regs->cfg[0].coord);
+	writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
+	writel(address, &de_ui_regs->cfg[0].top_laddr);
+	writel(size, &de_ui_regs->ovl_size);
+
+	/* apply settings */
+	writel(1, &de_glb_regs->dbuff);
+}
+
+static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
+			  enum video_log2_bpp l2bpp,
+			  struct udevice *disp, int mux)
+{
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct display_timing timing;
+	struct display_plat *disp_uc_plat;
+	int ret;
+
+	disp_uc_plat = dev_get_uclass_platdata(disp);
+	debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
+	if (display_in_use(disp)) {
+		debug("   - device in use\n");
+		return -EBUSY;
+	}
+
+	disp_uc_plat->source_id = mux;
+
+	ret = device_probe(disp);
+	if (ret) {
+		debug("%s: device '%s' display won't probe (ret=%d)\n",
+		      __func__, dev->name, ret);
+		return ret;
+	}
+
+	ret = display_read_timing(disp, &timing);
+	if (ret) {
+		debug("%s: Failed to read timings\n", __func__);
+		return ret;
+	}
+
+	sunxi_de2_composer_init();
+	sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase);
+
+	ret = display_enable(disp, 1 << l2bpp, &timing);
+	if (ret) {
+		debug("%s: Failed to enable display\n", __func__);
+		return ret;
+	}
+
+	uc_priv->xsize = timing.hactive.typ;
+	uc_priv->ysize = timing.vactive.typ;
+	uc_priv->bpix = l2bpp;
+	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
+
+	return 0;
+}
+
+static int sunxi_de2_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct udevice *disp;
+	int ret;
+	int mux;
+
+	/* Before relocation we don't need to do anything */
+	if (!(gd->flags & GD_FLG_RELOC))
+		return 0;
+
+	ret = uclass_find_device_by_name(UCLASS_DISPLAY,
+					 "sunxi_dw_hdmi", &disp);
+	if (ret) {
+		debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
+		return ret;
+	}
+
+	if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
+		mux = 0;
+	else
+		mux = 1;
+
+	ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP16, disp, mux);
+	if (ret)
+		return ret;
+
+	video_set_flush_dcache(dev, 1);
+
+	return 0;
+}
+
+static int sunxi_de2_bind(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+
+	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
+		(1 << LCD_MAX_LOG2_BPP) / 8;
+
+	return 0;
+}
+
+static const struct video_ops sunxi_de2_ops = {
+};
+
+U_BOOT_DRIVER(sunxi_de2) = {
+	.name	= "sunxi_de2",
+	.id	= UCLASS_VIDEO,
+	.ops	= &sunxi_de2_ops,
+	.bind	= sunxi_de2_bind,
+	.probe	= sunxi_de2_probe,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DEVICE(sunxi_de2) = {
+	.name = "sunxi_de2"
+};
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
new file mode 100644
index 0000000000..33920a2b67
--- /dev/null
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -0,0 +1,389 @@
+/*
+ * Allwinner DW HDMI bridge
+ *
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <display.h>
+#include <dm.h>
+#include <dw_hdmi.h>
+#include <edid.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/lcdc.h>
+
+struct sunxi_dw_hdmi_priv {
+	struct dw_hdmi hdmi;
+	int mux;
+};
+
+struct sunxi_hdmi_phy {
+	u32 pol;
+	u32 res1[3];
+	u32 read_en;
+	u32 unscramble;
+	u32 res2[2];
+	u32 ctrl;
+	u32 unk1;
+	u32 unk2;
+	u32 pll;
+	u32 clk;
+	u32 unk3;
+	u32 status;
+};
+
+#define HDMI_PHY_OFFS 0x10000
+
+static int sunxi_dw_hdmi_get_divider(uint clock)
+{
+	/*
+	 * Due to missing documentaion of HDMI PHY, we know correct
+	 * settings only for following four PHY dividers. Select one
+	 * based on clock speed.
+	 */
+	if (clock <= 27000000)
+		return 11;
+	else if (clock <= 74250000)
+		return 4;
+	else if (clock <= 148500000)
+		return 2;
+	else
+		return 1;
+}
+
+static void sunxi_dw_hdmi_phy_init(void)
+{
+	struct sunxi_hdmi_phy * const phy =
+		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+	unsigned long tmo;
+	u32 tmp;
+
+	/*
+	 * HDMI PHY settings are taken as-is from Allwinner BSP code.
+	 * There is no documentation.
+	 */
+	writel(0, &phy->ctrl);
+	setbits_le32(&phy->ctrl, BIT(0));
+	udelay(5);
+	setbits_le32(&phy->ctrl, BIT(16));
+	setbits_le32(&phy->ctrl, BIT(1));
+	udelay(10);
+	setbits_le32(&phy->ctrl, BIT(2));
+	udelay(5);
+	setbits_le32(&phy->ctrl, BIT(3));
+	udelay(40);
+	setbits_le32(&phy->ctrl, BIT(19));
+	udelay(100);
+	setbits_le32(&phy->ctrl, BIT(18));
+	setbits_le32(&phy->ctrl, 7 << 4);
+
+	/* Note that Allwinner code doesn't fail in case of timeout */
+	tmo = timer_get_us() + 2000;
+	while ((readl(&phy->status) & 0x80) == 0) {
+		if (timer_get_us() > tmo) {
+			printf("Warning: HDMI PHY init timeout!\n");
+			break;
+		}
+	}
+
+	setbits_le32(&phy->ctrl, 0xf << 8);
+	setbits_le32(&phy->ctrl, BIT(7));
+
+	writel(0x39dc5040, &phy->pll);
+	writel(0x80084343, &phy->clk);
+	udelay(10000);
+	writel(1, &phy->unk3);
+	setbits_le32(&phy->pll, BIT(25));
+	udelay(100000);
+	tmp = (readl(&phy->status) & 0x1f800) >> 11;
+	setbits_le32(&phy->pll, BIT(31) | BIT(30));
+	setbits_le32(&phy->pll, tmp);
+	writel(0x01FF0F7F, &phy->ctrl);
+	writel(0x80639000, &phy->unk1);
+	writel(0x0F81C405, &phy->unk2);
+
+	/* enable read access to HDMI controller */
+	writel(0x54524545, &phy->read_en);
+	/* descramble register offsets */
+	writel(0x42494E47, &phy->unscramble);
+}
+
+static int sunxi_dw_hdmi_get_plug_in_status(void)
+{
+	struct sunxi_hdmi_phy * const phy =
+		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+
+	return !!(readl(&phy->status) & (1 << 19));
+}
+
+static int sunxi_dw_hdmi_wait_for_hpd(void)
+{
+	ulong start;
+
+	start = get_timer(0);
+	do {
+		if (sunxi_dw_hdmi_get_plug_in_status())
+			return 0;
+		udelay(100);
+	} while (get_timer(start) < 300);
+
+	return -1;
+}
+
+static void sunxi_dw_hdmi_phy_set(uint clock)
+{
+	struct sunxi_hdmi_phy * const phy =
+		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+	int div = sunxi_dw_hdmi_get_divider(clock);
+	u32 tmp;
+
+	/*
+	 * Unfortunately, we don't know much about those magic
+	 * numbers. They are taken from Allwinner BSP driver.
+	 */
+	switch (div) {
+	case 1:
+		writel(0x30dc5fc0, &phy->pll);
+		writel(0x800863C0, &phy->clk);
+		mdelay(10);
+		writel(0x00000001, &phy->unk3);
+		setbits_le32(&phy->pll, BIT(25));
+		mdelay(200);
+		tmp = (readl(&phy->status) & 0x1f800) >> 11;
+		setbits_le32(&phy->pll, BIT(31) | BIT(30));
+		if (tmp < 0x3d)
+			setbits_le32(&phy->pll, tmp + 2);
+		else
+			setbits_le32(&phy->pll, 0x3f);
+		mdelay(100);
+		writel(0x01FFFF7F, &phy->ctrl);
+		writel(0x8063b000, &phy->unk1);
+		writel(0x0F8246B5, &phy->unk2);
+		break;
+	case 2:
+		writel(0x39dc5040, &phy->pll);
+		writel(0x80084381, &phy->clk);
+		mdelay(10);
+		writel(0x00000001, &phy->unk3);
+		setbits_le32(&phy->pll, BIT(25));
+		mdelay(100);
+		tmp = (readl(&phy->status) & 0x1f800) >> 11;
+		setbits_le32(&phy->pll, BIT(31) | BIT(30));
+		setbits_le32(&phy->pll, tmp);
+		writel(0x01FFFF7F, &phy->ctrl);
+		writel(0x8063a800, &phy->unk1);
+		writel(0x0F81C485, &phy->unk2);
+		break;
+	case 4:
+		writel(0x39dc5040, &phy->pll);
+		writel(0x80084343, &phy->clk);
+		mdelay(10);
+		writel(0x00000001, &phy->unk3);
+		setbits_le32(&phy->pll, BIT(25));
+		mdelay(100);
+		tmp = (readl(&phy->status) & 0x1f800) >> 11;
+		setbits_le32(&phy->pll, BIT(31) | BIT(30));
+		setbits_le32(&phy->pll, tmp);
+		writel(0x01FFFF7F, &phy->ctrl);
+		writel(0x8063b000, &phy->unk1);
+		writel(0x0F81C405, &phy->unk2);
+		break;
+	case 11:
+		writel(0x39dc5040, &phy->pll);
+		writel(0x8008430a, &phy->clk);
+		mdelay(10);
+		writel(0x00000001, &phy->unk3);
+		setbits_le32(&phy->pll, BIT(25));
+		mdelay(100);
+		tmp = (readl(&phy->status) & 0x1f800) >> 11;
+		setbits_le32(&phy->pll, BIT(31) | BIT(30));
+		setbits_le32(&phy->pll, tmp);
+		writel(0x01FFFF7F, &phy->ctrl);
+		writel(0x8063b000, &phy->unk1);
+		writel(0x0F81C405, &phy->unk2);
+		break;
+	}
+}
+
+static void sunxi_dw_hdmi_pll_set(uint clk_khz)
+{
+	int value, n, m, div = 0, diff;
+	int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
+
+	div = sunxi_dw_hdmi_get_divider(clk_khz * 1000);
+
+	/*
+	 * Find the lowest divider resulting in a matching clock. If there
+	 * is no match, pick the closest lower clock, as monitors tend to
+	 * not sync to higher frequencies.
+	 */
+	for (m = 1; m <= 16; m++) {
+		n = (m * div * clk_khz) / 24000;
+
+		if ((n >= 1) && (n <= 128)) {
+			value = (24000 * n) / m / div;
+			diff = clk_khz - value;
+			if (diff < best_diff) {
+				best_diff = diff;
+				best_m = m;
+				best_n = n;
+			}
+		}
+	}
+
+	clock_set_pll3_factors(best_m, best_n);
+	debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
+	      clk_khz, (clock_get_pll3() / 1000) / div,
+	      best_n, best_m, div);
+}
+
+static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
+				    int bpp)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ);
+	struct sunxi_lcdc_reg *lcdc;
+
+	if (mux == 0) {
+		lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+
+		/* Reset off */
+		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
+
+		/* Clock on */
+		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
+		writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
+		       &ccm->lcd0_clk_cfg);
+	} else {
+		lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
+
+		/* Reset off */
+		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
+
+		/* Clock on */
+		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
+		writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
+		       &ccm->lcd1_clk_cfg);
+	}
+
+	lcdc_init(lcdc);
+	lcdc_tcon1_mode_set(lcdc, edid, false, false);
+	lcdc_enable(lcdc, bpp);
+}
+
+static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
+{
+	sunxi_dw_hdmi_pll_set(mpixelclock/1000);
+	sunxi_dw_hdmi_phy_set(mpixelclock);
+
+	return 0;
+}
+
+static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
+{
+	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
+
+	return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
+}
+
+static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
+				const struct display_timing *edid)
+{
+	struct sunxi_hdmi_phy * const phy =
+		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = dw_hdmi_enable(&priv->hdmi, edid);
+	if (ret)
+		return ret;
+
+	sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
+
+	/*
+	 * Condition in original code is a bit weird. This is attempt
+	 * to make it more reasonable and it works. It could be that
+	 * bits and conditions are related and should be separated.
+	 */
+	if (!((edid->flags & DISPLAY_FLAGS_HSYNC_HIGH) &&
+	      (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH))) {
+		setbits_le32(&phy->pol, 0x300);
+	}
+
+	setbits_le32(&phy->ctrl, 0xf << 12);
+
+	/*
+	 * This is last hdmi access before boot, so scramble addresses
+	 * again or othwerwise BSP driver won't work. Dummy read is
+	 * needed or otherwise last write doesn't get written correctly.
+	 */
+	(void)readb(SUNXI_HDMI_BASE);
+	writel(0, &phy->unscramble);
+
+	return 0;
+}
+
+static int sunxi_dw_hdmi_probe(struct udevice *dev)
+{
+	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
+	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int ret;
+
+	/* Set pll3 to 297 MHz */
+	clock_set_pll3(297000000);
+
+	/* Set hdmi parent to pll3 */
+	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
+			CCM_HDMI_CTRL_PLL3);
+
+	/* Set ahb gating to pass */
+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
+	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
+	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
+
+	/* Clock on */
+	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
+
+	sunxi_dw_hdmi_phy_init();
+
+	ret = sunxi_dw_hdmi_wait_for_hpd();
+	if (ret < 0) {
+		debug("hdmi can not get hpd signal\n");
+		return -1;
+	}
+
+	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
+	priv->hdmi.i2c_clk_high = 0xd8;
+	priv->hdmi.i2c_clk_low = 0xfe;
+	priv->hdmi.reg_io_width = 1;
+	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
+	priv->mux = uc_plat->source_id;
+
+	dw_hdmi_init(&priv->hdmi);
+
+	return 0;
+}
+
+static const struct dm_display_ops sunxi_dw_hdmi_ops = {
+	.read_edid = sunxi_dw_hdmi_read_edid,
+	.enable = sunxi_dw_hdmi_enable,
+};
+
+U_BOOT_DRIVER(sunxi_dw_hdmi) = {
+	.name	= "sunxi_dw_hdmi",
+	.id	= UCLASS_DISPLAY,
+	.ops	= &sunxi_dw_hdmi_ops,
+	.probe	= sunxi_dw_hdmi_probe,
+	.priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
+};
+
+U_BOOT_DEVICE(sunxi_dw_hdmi) = {
+	.name = "sunxi_dw_hdmi"
+};
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 5c9657ad13..936eda5c9b 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -463,6 +463,11 @@ extern int soft_i2c_gpio_scl;
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial,vga\0" \
 	"stderr=serial,vga\0"
+#elif CONFIG_DM_VIDEO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONSOLE_STDOUT_SETTINGS \
+	"stdout=serial,vidconsole\0" \
+	"stderr=serial,vidconsole\0"
 #else
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial\0" \
-- 
2.12.0

[U-Boot] [PATCH 6/8] sunxi: video: Add A64/H3/H5 HDMI driver

[Simon Glass]

On 8 March 2017 at 16:34, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
> This commit adds support for HDMI output.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
>
>  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |   8 +
>  arch/arm/include/asm/arch-sunxi/display2.h  | 124 +++++++++
>  board/sunxi/Kconfig                         |  10 +
>  drivers/video/sunxi/Makefile                |   1 +
>  drivers/video/sunxi/sunxi_de2.c             | 258 ++++++++++++++++++
>  drivers/video/sunxi/sunxi_dw_hdmi.c         | 389 ++++++++++++++++++++++++++++
>  include/configs/sunxi-common.h              |   5 +
>  7 files changed, 795 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-sunxi/display2.h
>  create mode 100644 drivers/video/sunxi/sunxi_de2.c
>  create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi.c

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 7/8] sunxi: Enable A64/H3/H5 video driver in defconfigs

[Jernej Skrabec]

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---

 configs/orangepi_2_defconfig       | 1 +
 configs/orangepi_lite_defconfig    | 1 +
 configs/orangepi_one_defconfig     | 1 +
 configs/orangepi_pc2_defconfig     | 1 +
 configs/orangepi_pc_defconfig      | 1 +
 configs/orangepi_pc_plus_defconfig | 1 +
 configs/orangepi_plus2e_defconfig  | 1 +
 configs/orangepi_plus_defconfig    | 1 +
 configs/pine64_plus_defconfig      | 1 +
 9 files changed, 9 insertions(+)

diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 74712c6d6e..6af44691ad 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -19,3 +19,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
index 38f4583fd0..79b6b335a1 100644
--- a/configs/orangepi_lite_defconfig
+++ b/configs/orangepi_lite_defconfig
@@ -15,3 +15,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 56c9a871b1..17b287c925 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -16,3 +16,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 19a5c2b882..7cd8c5c23b 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -17,3 +17,4 @@ CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SPL_SPI_SUNXI=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 8d331bdf91..1df0721493 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -18,3 +18,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig
index 636599c361..116f532157 100644
--- a/configs/orangepi_pc_plus_defconfig
+++ b/configs/orangepi_pc_plus_defconfig
@@ -19,3 +19,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index 60f4eaa655..ff88613b7d 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -20,3 +20,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 78be69eec5..d889adb63c 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -21,3 +21,4 @@ CONFIG_SPL=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 7c7d86ff80..ade7a64ab8 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -14,3 +14,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO_DE2=y
-- 
2.12.0

[U-Boot] [PATCH 8/8] [DO NOT MERGE] sunxi: power: add AXP803 support

[Jernej Skrabec]

From: Icenowy Zheng <icenowy@aosc.xyz>

The A64 uses the AXP803 as its PMIC.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---

 arch/arm/mach-sunxi/Makefile   |   3 +
 arch/arm/mach-sunxi/pmic_bus.c |   6 +-
 arch/arm/mach-sunxi/rsb.c      |   2 +-
 board/sunxi/board.c            |  31 ++---
 drivers/power/Kconfig          |  87 ++++++++------
 drivers/power/Makefile         |   1 +
 drivers/power/axp803.c         | 256 +++++++++++++++++++++++++++++++++++++++++
 drivers/power/axp818.c         |   2 +-
 include/axp803.h               |  73 ++++++++++++
 include/axp_pmic.h             |   3 +
 10 files changed, 414 insertions(+), 50 deletions(-)
 create mode 100644 drivers/power/axp803.c
 create mode 100644 include/axp803.h

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index efab4811ee..861a52c6d0 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -19,9 +19,11 @@ endif
 obj-$(CONFIG_MACH_SUN6I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN8I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN9I)	+= prcm.o
+obj-$(CONFIG_MACH_SUN50I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN6I)	+= p2wi.o
 obj-$(CONFIG_MACH_SUN8I)	+= rsb.o
 obj-$(CONFIG_MACH_SUN9I)	+= rsb.o
+obj-$(CONFIG_MACH_SUN50I)	+= rsb.o
 obj-$(CONFIG_MACH_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= clock_sun6i.o
@@ -37,6 +39,7 @@ obj-$(CONFIG_MACH_SUN9I)	+= clock_sun9i.o gtbus_sun9i.o
 obj-$(CONFIG_AXP152_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP209_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP221_POWER)	+= pmic_bus.o
+obj-$(CONFIG_AXP803_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP809_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP818_POWER)	+= pmic_bus.o
 
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 7c57f02792..0ac64a97cf 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -36,7 +36,7 @@ int pmic_bus_init(void)
 	if (!needs_init)
 		return 0;
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	p2wi_init();
 	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 	return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_read(reg, data);
 # else
@@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data)
 	return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_write(reg, data);
 # else
diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c
index 6fd11f1529..28d05e962a 100644
--- a/arch/arm/mach-sunxi/rsb.c
+++ b/arch/arm/mach-sunxi/rsb.c
@@ -20,7 +20,7 @@ static int rsb_set_device_mode(void);
 
 static void rsb_cfg_io(void)
 {
-#ifdef CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN50I
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
 	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b9660128e5..75e53bebbd 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -487,26 +487,27 @@ void sunxi_board_init(void)
 #endif
 
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
-	defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-	defined CONFIG_AXP818_POWER
+	defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed = axp_init();
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-	defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
 #endif
 	power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
 	power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
-#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
+#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP803_POWER) && \
+	!defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
 #endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-	defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
 #endif
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-	defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
 #endif
 	power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
@@ -517,8 +518,8 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
 #endif
 
-#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
-	defined(CONFIG_AXP818_POWER)
+#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP803_POWER) || \
+	defined(CONFIG_AXP809_POWER) || defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
 	power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
 #if !defined CONFIG_AXP809_POWER
@@ -530,13 +531,17 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
 #endif
 
-#ifdef CONFIG_AXP818_POWER
+#if defined CONFIG_AXP803_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
 	power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
+#endif
+
+#ifdef CONFIG_AXP818_POWER
 	power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
 #endif
 
-#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
 #endif
 #endif
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 64e5bc2f74..4907002ed6 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -11,8 +11,9 @@ choice
 	depends on ARCH_SUNXI
 	default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
+	default AXP803_POWER if MACH_SUN50I
 	default AXP818_POWER if MACH_SUN8I_A83T
-	default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I
+	default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5
 
 config SUNXI_NO_PMIC
 	bool "board without a pmic"
@@ -43,6 +44,13 @@ config AXP221_POWER
 	Select this to enable support for the axp221/axp223 pmic found on most
 	A23 and A31 boards.
 
+config AXP803_POWER
+	bool "axp803 pmic support"
+	depends on MACH_SUN50I
+	select CMD_POWEROFF
+	---help---
+	Say y here to enable support for the axp803 pmic found on A64 boards.
+
 config AXP809_POWER
 	bool "axp809 pmic support"
 	depends on MACH_SUN9I
@@ -69,25 +77,25 @@ endchoice
 
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
-	default 3300 if AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
+	default 3300 if AXP818_POWER || MACH_SUN50I
 	default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
 	disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for
 	generic 3.3V IO voltage for external devices like the lcd-panal and
 	sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to
-	save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
-	dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally
-	powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG.
+	save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T and
+	A64 dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1
+	normally powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG.
 
 config AXP_DCDC2_VOLT
 	int "axp pmic dcdc2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 900 if AXP818_POWER
 	default 1400 if AXP152_POWER || AXP209_POWER
 	default 1200 if MACH_SUN6I
-	default 1100 if MACH_SUN8I
+	default 1100 if MACH_SUN8I || MACH_SUN50I
 	default 0 if MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to
@@ -97,15 +105,17 @@ config AXP_DCDC2_VOLT
 	On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
 	On A80 boards dcdc2 powers the GPU and can be left off.
 	On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
+	On A64 boards dcdc2 is used with dcdc3 for VDD-CPU and should be 1.1V.
 
 config AXP_DCDC3_VOLT
 	int "axp pmic dcdc3 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 900 if AXP809_POWER || AXP818_POWER
 	default 1500 if AXP152_POWER
 	default 1250 if AXP209_POWER
 	default 1200 if MACH_SUN6I || MACH_SUN8I
-	---help---
+	default 1100 if MACH_SUN50I
+---help---
 	Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to
 	disable dcdc3.
 	On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and
@@ -114,39 +124,42 @@ config AXP_DCDC3_VOLT
 	On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
 	On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 	On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
+	On A64 boards dcdc3 is used with dcdc2 for VDD-CPU and should be 1.1V.
 
 config AXP_DCDC4_VOLT
 	int "axp pmic dcdc4 voltage"
-	depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 1250 if AXP152_POWER
 	default 1200 if MACH_SUN6I
 	default 0 if MACH_SUN8I
 	default 900 if MACH_SUN9I
+	default 0 if MACH_SUN50I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to
 	disable dcdc4.
 	On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V.
 	On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V.
-	On A23 / A33 boards dcdc4 is unused and should be disabled.
+	On A23 / A33 / A64 boards dcdc4 is unused and should be disabled.
 	On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V.
 	On A83T boards dcdc4 is used for VDD-GPU.
 
 config AXP_DCDC5_VOLT
 	int "axp pmic dcdc5 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
-	default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
+	depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
+	default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I || MACH_SUN50I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
 	disable dcdc5.
-	On A23 / A31 / A33 / A80 / A83T boards dcdc5 is VCC-DRAM and
+	On A23 / A31 / A33 / A64 / A80 / A83T boards dcdc5 is VCC-DRAM and
 	should be 1.5V, 1.35V if DDR3L is used.
 
 config AXP_ALDO1_VOLT
 	int "axp pmic (a)ldo1 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 0 if MACH_SUN6I
 	default 1800 if MACH_SUN8I_A83T
 	default 3000 if MACH_SUN8I || MACH_SUN9I
+	default 2800 if MACH_SUN50I
 	---help---
 	Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to
 	disable aldo1.
@@ -155,14 +168,16 @@ config AXP_ALDO1_VOLT
 	On A80 boards aldo1 powers the USB hosts and should be 3.0V.
 	On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and
 	should be 1.8V.
+	On A64 boards aldo1 powers PE pingroup and CSI and should be 2.8V.
 
 config AXP_ALDO2_VOLT
 	int "axp pmic (a)ldo2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 3000 if AXP152_POWER || AXP209_POWER
 	default 0 if MACH_SUN6I || MACH_SUN9I
 	default 1800 if MACH_SUN8I_A83T
 	default 2500 if MACH_SUN8I
+	default 1800 if MACH_SUN50I
 	---help---
 	Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to
 	disable aldo2.
@@ -173,17 +188,19 @@ config AXP_ALDO2_VOLT
 	On A80 boards aldo2 powers PB pingroup and camera IO and can be left off.
 	On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
 	LPDDR2, and the codec. It should be 1.8V.
+	On A64 boards aldo2 powers PL pingroup and should be 1.8V.
 
 config AXP_ALDO3_VOLT
 	int "axp pmic (a)ldo3 voltage"
-	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 0 if AXP209_POWER || MACH_SUN9I
-	default 3000 if MACH_SUN6I || MACH_SUN8I
+	default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN50I
 	---help---
 	Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
 	disable aldo3.
 	On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
-	On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V.
+	On A23 / A31 / A33 / A64 boards aldo3 is VCC-PLL and AVCC
+	and should be 3.0V.
 	On A80 boards aldo3 is normally not used.
 	On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
 	3.0V.
@@ -199,17 +216,19 @@ config AXP_ALDO4_VOLT
 
 config AXP_DLDO1_VOLT
 	int "axp pmic dldo1 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
+	default 3300 if MACH_SUN50I
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to
 	disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used
 	to power the ethernet phy. On A23, A33 and A80 boards this is often
-	used to power the wifi.
+	used to power the wifi. On A64 boards this is often used to power the
+	HDMI.
 
 config AXP_DLDO2_VOLT
 	int "axp pmic dldo2 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 3000 if MACH_SUN9I
 	default 0
 	---help---
@@ -219,7 +238,7 @@ config AXP_DLDO2_VOLT
 
 config AXP_DLDO3_VOLT
 	int "axp pmic dldo3 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to
@@ -227,7 +246,7 @@ config AXP_DLDO3_VOLT
 
 config AXP_DLDO4_VOLT
 	int "axp pmic dldo4 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to
@@ -235,15 +254,17 @@ config AXP_DLDO4_VOLT
 
 config AXP_ELDO1_VOLT
 	int "axp pmic eldo1 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
+	default 1800 if MACH_SUN50I
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to
 	disable eldo1.
+	On A64 boards it's used for the codec and should be 1.8V.
 
 config AXP_ELDO2_VOLT
 	int "axp pmic eldo2 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to
@@ -251,7 +272,7 @@ config AXP_ELDO2_VOLT
 
 config AXP_ELDO3_VOLT
 	int "axp pmic eldo3 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default 3000 if MACH_SUN9I
 	default 0
 	---help---
@@ -263,8 +284,8 @@ config AXP_ELDO3_VOLT
 
 config AXP_FLDO1_VOLT
 	int "axp pmic fldo1 voltage"
-	depends on AXP818_POWER
-	default 0 if MACH_SUN8I_A83T
+	depends on AXP803_POWER || AXP818_POWER
+	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to
 	disable fldo1.
@@ -273,11 +294,13 @@ config AXP_FLDO1_VOLT
 
 config AXP_FLDO2_VOLT
 	int "axp pmic fldo2 voltage"
-	depends on AXP818_POWER
+	depends on AXP803_POWER || AXP818_POWER
+	default 1100 if MACH_SUN50I
 	default 900 if MACH_SUN8I_A83T
 	---help---
 	Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to
 	disable fldo2.
+	On A64 boards fldo2 is VCC-CPUS and should be 1.1V.
 	On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V.
 
 config AXP_FLDO3_VOLT
@@ -290,7 +313,7 @@ config AXP_FLDO3_VOLT
 
 config AXP_SW_ON
 	bool "axp pmic sw on"
-	depends on AXP809_POWER || AXP818_POWER
+	depends on AXP803_POWER || AXP809_POWER || AXP818_POWER
 	default n
 	---help---
 	Enable to turn on axp pmic sw.
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index b43523e628..1449e875ce 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_AS3722_POWER)	+= as3722.o
 obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 obj-$(CONFIG_AXP209_POWER)	+= axp209.o
 obj-$(CONFIG_AXP221_POWER)	+= axp221.o
+obj-$(CONFIG_AXP803_POWER)	+= axp803.o
 obj-$(CONFIG_AXP809_POWER)	+= axp809.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
diff --git a/drivers/power/axp803.c b/drivers/power/axp803.c
new file mode 100644
index 0000000000..93b9d95234
--- /dev/null
+++ b/drivers/power/axp803.c
@@ -0,0 +1,256 @@
+/*
+ * AXP803 driver based on AXP818 driver
+ *
+ * Based on axp818.c
+ * (C) Copyright 2015 Vishnu Patekar <vishnuptekar0510@gmail.com>
+ *
+ * Based on axp221.c
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pmic_bus.h>
+#include <axp_pmic.h>
+
+static u8 axp803_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+	if (mvolt < min)
+		mvolt = min;
+	else if (mvolt > max)
+		mvolt = max;
+
+	return  (mvolt - min) / div;
+}
+
+int axp_set_dcdc1(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp803_mvolt_to_cfg(mvolt, 1600, 3400, 100);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1,
+					AXP803_OUTPUT_CTRL1_DCDC1_EN);
+
+	ret = pmic_bus_write(AXP803_DCDC1_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP803_OUTPUT_CTRL1,
+				AXP803_OUTPUT_CTRL1_DCDC1_EN);
+}
+
+int axp_set_dcdc2(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (mvolt >= 1220)
+		cfg = 70 + axp803_mvolt_to_cfg(mvolt, 1220, 1300, 20);
+	else
+		cfg = axp803_mvolt_to_cfg(mvolt, 500, 1200, 10);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1,
+					AXP803_OUTPUT_CTRL1_DCDC2_EN);
+
+	ret = pmic_bus_write(AXP803_DCDC2_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP803_OUTPUT_CTRL1,
+				AXP803_OUTPUT_CTRL1_DCDC2_EN);
+}
+
+int axp_set_dcdc3(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (mvolt >= 1220)
+		cfg = 70 + axp803_mvolt_to_cfg(mvolt, 1220, 1300, 20);
+	else
+		cfg = axp803_mvolt_to_cfg(mvolt, 500, 1200, 10);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1,
+					AXP803_OUTPUT_CTRL1_DCDC3_EN);
+
+	ret = pmic_bus_write(AXP803_DCDC3_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP803_OUTPUT_CTRL1,
+				AXP803_OUTPUT_CTRL1_DCDC3_EN);
+}
+
+int axp_set_dcdc5(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (mvolt >= 1140)
+		cfg = 32 + axp803_mvolt_to_cfg(mvolt, 1140, 1840, 20);
+	else
+		cfg = axp803_mvolt_to_cfg(mvolt, 800, 1120, 10);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1,
+					AXP803_OUTPUT_CTRL1_DCDC5_EN);
+
+	ret = pmic_bus_write(AXP803_DCDC5_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP803_OUTPUT_CTRL1,
+				AXP803_OUTPUT_CTRL1_DCDC5_EN);
+}
+
+int axp_set_aldo(int aldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (aldo_num < 1 || aldo_num > 3)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP803_OUTPUT_CTRL3,
+				AXP803_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1));
+
+	cfg = axp803_mvolt_to_cfg(mvolt, 700, 3300, 100);
+	ret = pmic_bus_write(AXP803_ALDO1_CTRL + (aldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP803_OUTPUT_CTRL3,
+				AXP803_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1));
+}
+
+/* TODO: re-work other AXP drivers to consolidate ALDO functions. */
+int axp_set_aldo1(unsigned int mvolt)
+{
+	return axp_set_aldo(1, mvolt);
+}
+
+int axp_set_aldo2(unsigned int mvolt)
+{
+	return axp_set_aldo(2, mvolt);
+}
+
+int axp_set_aldo3(unsigned int mvolt)
+{
+	return axp_set_aldo(3, mvolt);
+}
+
+int axp_set_dldo(int dldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (dldo_num < 1 || dldo_num > 4)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2,
+				AXP803_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+
+	cfg = axp803_mvolt_to_cfg(mvolt, 700, 3300, 100);
+	if (dldo_num == 2 && mvolt > 3300)
+		cfg += 1 + axp803_mvolt_to_cfg(mvolt, 3400, 4200, 200);
+	ret = pmic_bus_write(AXP803_DLDO1_CTRL + (dldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP803_OUTPUT_CTRL2,
+				AXP803_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+}
+
+int axp_set_eldo(int eldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (eldo_num < 1 || eldo_num > 3)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2,
+				AXP803_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+
+	cfg = axp803_mvolt_to_cfg(mvolt, 700, 1900, 50);
+	ret = pmic_bus_write(AXP803_ELDO1_CTRL + (eldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP803_OUTPUT_CTRL2,
+				AXP803_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+}
+
+int axp_set_fldo(int fldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (fldo_num < 1 || fldo_num > 2)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP803_OUTPUT_CTRL3,
+				AXP803_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
+
+	cfg = axp803_mvolt_to_cfg(mvolt, 700, 1450, 50);
+	ret = pmic_bus_write(AXP803_FLDO1_CTRL + (fldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP803_OUTPUT_CTRL3,
+				AXP803_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
+}
+
+int axp_set_sw(bool on)
+{
+	if (on)
+		return pmic_bus_setbits(AXP803_OUTPUT_CTRL2,
+					AXP803_OUTPUT_CTRL2_SW_EN);
+
+	return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2,
+				AXP803_OUTPUT_CTRL2_SW_EN);
+}
+
+int axp_init(void)
+{
+	u8 axp_chip_id;
+	int ret;
+
+	ret = pmic_bus_init();
+	if (ret)
+		return ret;
+
+	ret = pmic_bus_read(AXP803_CHIP_ID, &axp_chip_id);
+	if (ret)
+		return ret;
+
+	if (!(axp_chip_id == 0x51))
+		return -ENODEV;
+	else
+		return ret;
+
+	return 0;
+}
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmic_bus_write(AXP803_SHUTDOWN, AXP803_SHUTDOWN_POWEROFF);
+
+	/* infinite loop during shutdown */
+	while (1)
+		;
+
+	/* not reached */
+	return 0;
+}
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index af4d7a6903..ad0c330ca5 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -162,7 +162,7 @@ int axp_set_dldo(int dldo_num, unsigned int mvolt)
 	cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100);
 	if (dldo_num == 2 && mvolt > 3300)
 		cfg += 1 + axp818_mvolt_to_cfg(mvolt, 3400, 4200, 200);
-	ret = pmic_bus_write(AXP818_ELDO1_CTRL + (dldo_num - 1), cfg);
+	ret = pmic_bus_write(AXP818_DLDO1_CTRL + (dldo_num - 1), cfg);
 	if (ret)
 		return ret;
 
diff --git a/include/axp803.h b/include/axp803.h
new file mode 100644
index 0000000000..b382f3a5ec
--- /dev/null
+++ b/include/axp803.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on axp818.h, which is:
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * X-Powers AXP803 Power Management IC driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define AXP803_CHIP_ID		0x03
+
+#define AXP803_OUTPUT_CTRL1	0x10
+#define AXP803_OUTPUT_CTRL1_DCDC1_EN	(1 << 0)
+#define AXP803_OUTPUT_CTRL1_DCDC2_EN	(1 << 1)
+#define AXP803_OUTPUT_CTRL1_DCDC3_EN	(1 << 2)
+#define AXP803_OUTPUT_CTRL1_DCDC4_EN	(1 << 3)
+#define AXP803_OUTPUT_CTRL1_DCDC5_EN	(1 << 4)
+#define AXP803_OUTPUT_CTRL1_DCDC6_EN	(1 << 5)
+#define AXP803_OUTPUT_CTRL2	0x12
+#define AXP803_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP803_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP803_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP803_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP803_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP803_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)
+#define AXP803_OUTPUT_CTRL2_DLDO4_EN	(1 << 6)
+#define AXP803_OUTPUT_CTRL2_SW_EN	(1 << 7)
+#define AXP803_OUTPUT_CTRL3	0x13
+#define AXP803_OUTPUT_CTRL3_FLDO1_EN	(1 << 2)
+#define AXP803_OUTPUT_CTRL3_FLDO2_EN	(1 << 3)
+#define AXP803_OUTPUT_CTRL3_ALDO1_EN	(1 << 5)
+#define AXP803_OUTPUT_CTRL3_ALDO2_EN	(1 << 6)
+#define AXP803_OUTPUT_CTRL3_ALDO3_EN	(1 << 7)
+
+#define AXP803_DLDO1_CTRL	0x15
+#define AXP803_DLDO2_CTRL	0x16
+#define AXP803_DLDO3_CTRL	0x17
+#define AXP803_DLDO4_CTRL	0x18
+#define AXP803_ELDO1_CTRL	0x19
+#define AXP803_ELDO2_CTRL	0x1a
+#define AXP803_ELDO3_CTRL	0x1b
+#define AXP803_FLDO1_CTRL	0x1c
+#define AXP803_FLDO2_CTRL	0x1d
+#define AXP803_DCDC1_CTRL	0x20
+#define AXP803_DCDC2_CTRL	0x21
+#define AXP803_DCDC3_CTRL	0x22
+#define AXP803_DCDC4_CTRL	0x23
+#define AXP803_DCDC5_CTRL	0x24
+#define AXP803_DCDC6_CTRL	0x25
+
+#define AXP803_ALDO1_CTRL	0x28
+#define AXP803_ALDO2_CTRL	0x29
+#define AXP803_ALDO3_CTRL	0x2a
+
+#define AXP803_SHUTDOWN		0x32
+#define AXP803_SHUTDOWN_POWEROFF	(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		0
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index d789ad8086..8cb4d5763c 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -16,6 +16,9 @@
 #ifdef CONFIG_AXP221_POWER
 #include <axp221.h>
 #endif
+#ifdef CONFIG_AXP803_POWER
+#include <axp803.h>
+#endif
 #ifdef CONFIG_AXP809_POWER
 #include <axp809.h>
 #endif
-- 
2.12.0