[U-Boot] [PATCH 2/3] x86: quark: Turn on legacy segments decode

[U-Boot] [PATCH 2/3] x86: quark: Turn on legacy segments decode

[Bin Meng]

By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F segment.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/quark/quark.c              | 12 ++++++++++++
 arch/x86/include/asm/arch-quark/quark.h |  7 +++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index e4b19c2..4ffa437 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -72,6 +72,15 @@ static void quark_setup_bars(void)
 		       CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
 }
 
+static void quark_enable_legacy_seg(void)
+{
+	u32 hmisc2;
+
+	hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2);
+	hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
+	msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2);
+}
+
 int arch_cpu_init(void)
 {
 	struct pci_controller *hose;
@@ -96,6 +105,9 @@ int arch_cpu_init(void)
 	 */
 	quark_setup_bars();
 
+	/* Turn on legacy segments (A/B/E/F) decode to system RAM */
+	quark_enable_legacy_seg();
+
 	unprotect_spi_flash();
 
 	return 0;
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
index ceb583e..6dd02fd 100644
--- a/arch/x86/include/asm/arch-quark/quark.h
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -21,6 +21,13 @@
 
 /* Port 0x03: Host Bridge Message Port Registers */
 
+/* Host Miscellaneous Controls 2 */
+#define HMISC2			0x03
+
+#define HMISC2_SEGE		0x00000002
+#define HMISC2_SEGF		0x00000004
+#define HMISC2_SEGAB		0x00000010
+
 /* Host Memory I/O Boundary */
 #define HM_BOUND		0x08
 
-- 
1.8.2.1

[U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

[Bin Meng]

Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 arch/x86/cpu/quark/Makefile              |   2 +-
 arch/x86/cpu/quark/irq.c                 | 173 +++++++++++++++++++++++++++++++
 arch/x86/cpu/quark/quark.c               |   8 ++
 arch/x86/include/asm/arch-quark/device.h |  70 ++++++++++---
 arch/x86/include/asm/arch-quark/irq.h    |  55 ++++++++++
 arch/x86/include/asm/arch-quark/quark.h  |  15 +++
 configs/galileo_defconfig                |   1 +
 include/configs/galileo.h                |   1 +
 8 files changed, 309 insertions(+), 16 deletions(-)
 create mode 100644 arch/x86/cpu/quark/irq.c
 create mode 100644 arch/x86/include/asm/arch-quark/irq.h

diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index e87b424..1e37802 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += car.o dram.o msg_port.o quark.o
+obj-y += car.o dram.o irq.o msg_port.o quark.o
 obj-y += mrc.o mrc_util.o hte.o smc.o
 obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/quark/irq.c b/arch/x86/cpu/quark/irq.c
new file mode 100644
index 0000000..d6edd0c
--- /dev/null
+++ b/arch/x86/cpu/quark/irq.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/pirq_routing.h>
+#include <asm/arch/device.h>
+#include <asm/arch/quark.h>
+#include <asm/arch/irq.h>
+
+static struct irq_routing_table *pirq_routing_table;
+
+bool pirq_check_irq_routed(int link, u8 irq)
+{
+	u8 pirq;
+
+	pirq = x86_pci_read_config8(QUARK_LEGACY_BRIDGE, LINK_N2V(link));
+	pirq &= 0xf;
+
+	/* IRQ# 0/1/2/8/13 are reserved */
+	if (pirq < 3 || pirq == 8 || pirq == 13)
+		return false;
+
+	return pirq == irq ? true : false;
+}
+
+int pirq_translate_link(int link)
+{
+	return LINK_V2N(link);
+}
+
+void pirq_assign_irq(int link, u8 irq)
+{
+	/* IRQ# 0/1/2/8/13 are reserved */
+	if (irq < 3 || irq == 8 || irq == 13)
+		return;
+
+	x86_pci_write_config8(QUARK_LEGACY_BRIDGE, LINK_N2V(link), irq);
+}
+
+static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
+				 u8 device, u8 func, u8 pin, u8 pirq)
+{
+	struct irq_info *slot = *slotp;
+
+	slot->bus = bus;
+	slot->devfn = (device << 3) | func;
+	slot->irq[pin - 1].link = LINK_N2V(pirq);
+	slot->irq[pin - 1].bitmap = PIRQ_BITMAP;
+	(*entries)++;
+	(*slotp)++;
+}
+
+__weak int board_fill_irq_info(struct irq_info *slot)
+{
+	return 0;
+}
+
+static int create_pirq_routing_table(void)
+{
+	struct irq_routing_table *rt;
+	struct irq_info *slot;
+	int irq_entries = 0;
+
+	rt = malloc(sizeof(struct irq_routing_table));
+	if (!rt)
+		return -ENOMEM;
+	memset((char *)rt, 0, sizeof(struct irq_routing_table));
+
+	/* Populate the PIRQ table fields */
+	rt->signature = PIRQ_SIGNATURE;
+	rt->version = PIRQ_VERSION;
+	rt->rtr_bus = 0;
+	rt->rtr_devfn = (QUARK_LGC_BRIDGE_DEV << 3) | QUARK_LGC_BRIDGE_FUNC;
+	rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
+	rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
+
+	slot = rt->slots;
+
+	/* Now fill in the irq_info entries in the PIRQ table */
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20,
+		      QUARK_MMC_SDIO_FUNC, INTA, PIRQE);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20,
+		      QUARK_UART0_FUNC, INTB, PIRQF);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20,
+		      QUARK_USB_DEVICE_FUNC, INTC, PIRQG);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20,
+		      QUARK_USB_EHCI_FUNC, INTD, PIRQH);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20,
+		      QUARK_USB_OHCI_FUNC, INTD, PIRQH);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20,
+		      QUARK_UART1_FUNC, INTB, PIRQF);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20,
+		      QUARK_EMAC0_FUNC, INTC, PIRQG);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20,
+		      QUARK_EMAC1_FUNC, INTC, PIRQG);
+
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_21,
+		      QUARK_SPI0_FUNC, INTA, PIRQE);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_21,
+		      QUARK_SPI1_FUNC, INTA, PIRQE);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_21,
+		      QUARK_I2C_GPIO_FUNC, INTC, PIRQG);
+
+	/*
+	 * TODO:
+	 *
+	 * For some unknown reason, the PCI enumeration process hangs
+	 * when it scans to the PCIe root port 0 (D23:F0) & 1 (D23:F1).
+	 *
+	 * For now we just skip these two devices, and this needs to
+	 * be revisited later.
+	 */
+#ifdef TODO
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_23,
+		      QUARK_PCIE0_FUNC, INTA, PIRQA);
+	fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_23,
+		      QUARK_PCIE1_FUNC, INTA, PIRQA);
+#endif
+
+	/* Call board-specific routine to fill in add-in card's irq info */
+	irq_entries += board_fill_irq_info(slot);
+
+	rt->size = irq_entries * sizeof(struct irq_info) + 32;
+
+	pirq_routing_table = rt;
+
+	return 0;
+}
+
+void pirq_init(void)
+{
+	struct quark_rcba *rcba;
+	u32 base;
+
+	base = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, LB_RCBA);
+	base &= ~MEM_BAR_EN;
+	rcba = (struct quark_rcba *)base;
+
+	/*
+	 * Route Quark PCI device interrupt pin to PIRQ
+	 *
+	 * Route device#23's INTA/B/C/D to PIRQA/B/C/D
+	 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
+	 */
+	writew(PIRQC, &rcba->rmu_ir);
+	writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
+	       &rcba->d23_ir);
+	writew(PIRQD, &rcba->core_ir);
+	writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
+	       &rcba->d20d21_ir);
+
+	if (create_pirq_routing_table()) {
+		debug("Failed to create pirq routing table\n");
+	} else {
+		/* Route PIRQ */
+		pirq_route_irqs(pirq_routing_table->slots,
+				get_irq_slot_count(pirq_routing_table));
+	}
+}
+
+u32 write_pirq_routing_table(u32 addr)
+{
+	return copy_pirq_routing_table(addr, pirq_routing_table);
+}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 4ffa437..7a8f936 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -13,6 +13,7 @@
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/device.h>
+#include <asm/arch/irq.h>
 #include <asm/arch/msg_port.h>
 #include <asm/arch/quark.h>
 
@@ -147,3 +148,10 @@ int cpu_eth_init(bd_t *bis)
 	else
 		return 0;
 }
+
+int arch_misc_init(void)
+{
+	pirq_init();
+
+	return 0;
+}
diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h
index 4af3ded..7882f33 100644
--- a/arch/x86/include/asm/arch-quark/device.h
+++ b/arch/x86/include/asm/arch-quark/device.h
@@ -9,20 +9,60 @@
 
 #include <pci.h>
 
-#define QUARK_HOST_BRIDGE	PCI_BDF(0, 0, 0)
-#define QUARK_MMC_SDIO		PCI_BDF(0, 20, 0)
-#define QUARK_UART0		PCI_BDF(0, 20, 1)
-#define QUARK_USB_DEVICE	PCI_BDF(0, 20, 2)
-#define QUARK_USB_EHCI		PCI_BDF(0, 20, 3)
-#define QUARK_USB_OHCI		PCI_BDF(0, 20, 4)
-#define QUARK_UART1		PCI_BDF(0, 20, 5)
-#define QUARK_EMAC0		PCI_BDF(0, 20, 6)
-#define QUARK_EMAC1		PCI_BDF(0, 20, 7)
-#define QUARK_SPI0		PCI_BDF(0, 21, 0)
-#define QUARK_SPI1		PCI_BDF(0, 21, 1)
-#define QUARK_I2C_GPIO		PCI_BDF(0, 21, 2)
-#define QUARK_PCIE0		PCI_BDF(0, 23, 0)
-#define QUARK_PCIE1		PCI_BDF(0, 23, 1)
-#define QUARK_LEGACY_BRIDGE	PCI_BDF(0, 31, 0)
+#define QUARK_HOST_BRIDGE_DEV	0
+#define QUARK_HOST_BRIDGE_FUNC	0
+
+#define QUARK_DEV_20		20
+#define QUARK_MMC_SDIO_FUNC	0
+#define QUARK_UART0_FUNC	1
+#define QUARK_USB_DEVICE_FUNC	2
+#define QUARK_USB_EHCI_FUNC	3
+#define QUARK_USB_OHCI_FUNC	4
+#define QUARK_UART1_FUNC	5
+#define QUARK_EMAC0_FUNC	6
+#define QUARK_EMAC1_FUNC	7
+
+#define QUARK_DEV_21		21
+#define QUARK_SPI0_FUNC		0
+#define QUARK_SPI1_FUNC		1
+#define QUARK_I2C_GPIO_FUNC	2
+
+#define QUARK_DEV_23		23
+#define QUARK_PCIE0_FUNC	0
+#define QUARK_PCIE1_FUNC	1
+
+#define QUARK_LGC_BRIDGE_DEV	31
+#define QUARK_LGC_BRIDGE_FUNC	0
+
+#define QUARK_HOST_BRIDGE	\
+	PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
+#define QUARK_MMC_SDIO		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC)
+#define QUARK_UART0		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC)
+#define QUARK_USB_DEVICE	\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC)
+#define QUARK_USB_EHCI		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC)
+#define QUARK_USB_OHCI		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC)
+#define QUARK_UART1		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC)
+#define QUARK_EMAC0		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC)
+#define QUARK_EMAC1		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC)
+#define QUARK_SPI0		\
+	PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC)
+#define QUARK_SPI1		\
+	PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC)
+#define QUARK_I2C_GPIO		\
+	PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC)
+#define QUARK_PCIE0		\
+	PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC)
+#define QUARK_PCIE1		\
+	PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
+#define QUARK_LEGACY_BRIDGE	\
+	PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
 
 #endif /* _QUARK_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h
new file mode 100644
index 0000000..f69fb8c
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/irq.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARCH_IRQ_H_
+#define _ARCH_IRQ_H_
+
+enum pci_int_pin {
+	INTX,
+	INTA,
+	INTB,
+	INTC,
+	INTD
+};
+
+enum pirq_pin {
+	PIRQA,
+	PIRQB,
+	PIRQC,
+	PIRQD,
+	PIRQE,
+	PIRQF,
+	PIRQG,
+	PIRQH
+};
+
+/* PIRQ link number and value conversion */
+#define LINK_V2N(link)	(link - 0x60)
+#define LINK_N2V(link)	(link + 0x60)
+
+#define PIRQ_BITMAP	0xdef8
+
+struct irq_info;
+
+/**
+ * board_fill_irq_info() - Board-specific irq_info fill routine
+ *
+ * This fills the irq_info table for any board-specific add-in cards.
+ *
+ * @slot:	pointer to the struct irq_info that is to be filled in
+ * @return:	number of entries were written to the struct irq_info
+ */
+int board_fill_irq_info(struct irq_info *slot);
+
+/**
+ * pirq_init() - Initialize platform PIRQ routing
+ *
+ * This initializes the PIRQ routing on the platform and configures all PCI
+ * devices' interrupt line register to a working IRQ number on the 8259 PIC.
+ */
+void pirq_init(void);
+
+#endif /* _ARCH_IRQ_H_ */
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
index 6dd02fd..c997928 100644
--- a/arch/x86/include/asm/arch-quark/quark.h
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -76,4 +76,19 @@
 #define LB_BC			0xd8
 #define LB_RCBA			0xf0
 
+#ifndef __ASSEMBLY__
+
+/* Root Complex Register Block */
+struct quark_rcba {
+	u32	rctl;
+	u32	esd;
+	u32	rsvd1[3150];
+	u16	rmu_ir;
+	u16	d23_ir;
+	u16	core_ir;
+	u16	d20d21_ir;
+};
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* _QUARK_H_ */
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 9b0f969..0c77278 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -7,3 +7,4 @@ CONFIG_DEFAULT_DEVICE_TREE="galileo"
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_NETDEVICES=y
 CONFIG_NET=y
+CONFIG_GENERATE_PIRQ_TABLE=y
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 9b0b650..961d087 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -15,6 +15,7 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(1 << 20)
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
 
 #define CONFIG_NR_DRAM_BANKS		1
 
-- 
1.8.2.1

[U-Boot] [PATCH 2/3] x86: quark: Turn on legacy segments decode

[Simon Glass]

On 27 April 2015 at 00:16, Bin Meng <bmeng.cn@gmail.com> wrote:
> By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
> do not decode to system RAM. Turn on the decode so that we can
> write configuration tables in the F segment.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/quark/quark.c              | 12 ++++++++++++
>  arch/x86/include/asm/arch-quark/quark.h |  7 +++++++
>  2 files changed, 19 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

[Simon Glass]

Hi Bin,

On 27 April 2015 at 00:16, Bin Meng <bmeng.cn@gmail.com> wrote:
> Intel Quark SoC has the same interrupt routing mechanism as the
> Queensbay platform, only the difference is that PCI devices'
> INTA/B/C/D are harcoded and cannot be changed freely.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
>  arch/x86/cpu/quark/Makefile              |   2 +-
>  arch/x86/cpu/quark/irq.c                 | 173 +++++++++++++++++++++++++++++++
>  arch/x86/cpu/quark/quark.c               |   8 ++
>  arch/x86/include/asm/arch-quark/device.h |  70 ++++++++++---
>  arch/x86/include/asm/arch-quark/irq.h    |  55 ++++++++++
>  arch/x86/include/asm/arch-quark/quark.h  |  15 +++
>  configs/galileo_defconfig                |   1 +
>  include/configs/galileo.h                |   1 +
>  8 files changed, 309 insertions(+), 16 deletions(-)
>  create mode 100644 arch/x86/cpu/quark/irq.c
>  create mode 100644 arch/x86/include/asm/arch-quark/irq.h

Before going too far down this path I'd like to see if we can put the
IRQ data in the device tree. What do you think?

Regards,
Simon

[U-Boot] [PATCH 2/3] x86: quark: Turn on legacy segments decode

[Simon Glass]

On 28 April 2015 at 08:05, Simon Glass <sjg@chromium.org> wrote:
> On 27 April 2015 at 00:16, Bin Meng <bmeng.cn@gmail.com> wrote:
>> By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
>> do not decode to system RAM. Turn on the decode so that we can
>> write configuration tables in the F segment.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/quark/quark.c              | 12 ++++++++++++
>>  arch/x86/include/asm/arch-quark/quark.h |  7 +++++++
>>  2 files changed, 19 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

[Bin Meng]

Hi Simon,

On Tue, Apr 28, 2015 at 10:05 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 27 April 2015 at 00:16, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Intel Quark SoC has the same interrupt routing mechanism as the
>> Queensbay platform, only the difference is that PCI devices'
>> INTA/B/C/D are harcoded and cannot be changed freely.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>>  arch/x86/cpu/quark/Makefile              |   2 +-
>>  arch/x86/cpu/quark/irq.c                 | 173 +++++++++++++++++++++++++++++++
>>  arch/x86/cpu/quark/quark.c               |   8 ++
>>  arch/x86/include/asm/arch-quark/device.h |  70 ++++++++++---
>>  arch/x86/include/asm/arch-quark/irq.h    |  55 ++++++++++
>>  arch/x86/include/asm/arch-quark/quark.h  |  15 +++
>>  configs/galileo_defconfig                |   1 +
>>  include/configs/galileo.h                |   1 +
>>  8 files changed, 309 insertions(+), 16 deletions(-)
>>  create mode 100644 arch/x86/cpu/quark/irq.c
>>  create mode 100644 arch/x86/include/asm/arch-quark/irq.h
>
> Before going too far down this path I'd like to see if we can put the
> IRQ data in the device tree. What do you think?
>

Device tree might work, and we might come up with a standard intel irq
router driver to configure this based on device tree input. But I will
need study more chipset datasheet to do that.

Regards,
Bin

[U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

[Simon Glass]

Hi Bin,

On 4 May 2015 at 00:27, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Tue, Apr 28, 2015 at 10:05 PM, Simon Glass <sjg@chromium.org> wrote:
> > Hi Bin,
> >
> > On 27 April 2015 at 00:16, Bin Meng <bmeng.cn@gmail.com> wrote:
> >> Intel Quark SoC has the same interrupt routing mechanism as the
> >> Queensbay platform, only the difference is that PCI devices'
> >> INTA/B/C/D are harcoded and cannot be changed freely.
> >>
> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >>
> >> ---
> >>
> >>  arch/x86/cpu/quark/Makefile              |   2 +-
> >>  arch/x86/cpu/quark/irq.c                 | 173 +++++++++++++++++++++++++++++++
> >>  arch/x86/cpu/quark/quark.c               |   8 ++
> >>  arch/x86/include/asm/arch-quark/device.h |  70 ++++++++++---
> >>  arch/x86/include/asm/arch-quark/irq.h    |  55 ++++++++++
> >>  arch/x86/include/asm/arch-quark/quark.h  |  15 +++
> >>  configs/galileo_defconfig                |   1 +
> >>  include/configs/galileo.h                |   1 +
> >>  8 files changed, 309 insertions(+), 16 deletions(-)
> >>  create mode 100644 arch/x86/cpu/quark/irq.c
> >>  create mode 100644 arch/x86/include/asm/arch-quark/irq.h
> >
> > Before going too far down this path I'd like to see if we can put the
> > IRQ data in the device tree. What do you think?
> >
>
> Device tree might work, and we might come up with a standard intel irq
> router driver to configure this based on device tree input. But I will
> need study more chipset datasheet to do that.

OK let's wait for that. It does seem like a job for device tree. Even
if we can get a binding that works for modern chips that would be a
win. Let me know what you find.

Regards,
Simon

[U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

[Bin Meng]

Hi Simon,

On Tue, May 5, 2015 at 10:05 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 4 May 2015 at 00:27, Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> Hi Simon,
>>
>> On Tue, Apr 28, 2015 at 10:05 PM, Simon Glass <sjg@chromium.org> wrote:
>> > Hi Bin,
>> >
>> > On 27 April 2015 at 00:16, Bin Meng <bmeng.cn@gmail.com> wrote:
>> >> Intel Quark SoC has the same interrupt routing mechanism as the
>> >> Queensbay platform, only the difference is that PCI devices'
>> >> INTA/B/C/D are harcoded and cannot be changed freely.
>> >>
>> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> >>
>> >> ---
>> >>
>> >>  arch/x86/cpu/quark/Makefile              |   2 +-
>> >>  arch/x86/cpu/quark/irq.c                 | 173 +++++++++++++++++++++++++++++++
>> >>  arch/x86/cpu/quark/quark.c               |   8 ++
>> >>  arch/x86/include/asm/arch-quark/device.h |  70 ++++++++++---
>> >>  arch/x86/include/asm/arch-quark/irq.h    |  55 ++++++++++
>> >>  arch/x86/include/asm/arch-quark/quark.h  |  15 +++
>> >>  configs/galileo_defconfig                |   1 +
>> >>  include/configs/galileo.h                |   1 +
>> >>  8 files changed, 309 insertions(+), 16 deletions(-)
>> >>  create mode 100644 arch/x86/cpu/quark/irq.c
>> >>  create mode 100644 arch/x86/include/asm/arch-quark/irq.h
>> >
>> > Before going too far down this path I'd like to see if we can put the
>> > IRQ data in the device tree. What do you think?
>> >
>>
>> Device tree might work, and we might come up with a standard intel irq
>> router driver to configure this based on device tree input. But I will
>> need study more chipset datasheet to do that.
>
> OK let's wait for that. It does seem like a job for device tree. Even
> if we can get a binding that works for modern chips that would be a
> win. Let me know what you find.
>

I've refactored current PIRQ support using device tree on queensbay.
Next is on quark and qemu. A patch will be sent out soon.

Regards,
Bin