[U-Boot] [PATCH v2 01/11] video: vesa_fb: Look up VGA device by class instead of id

[U-Boot] [PATCH v2 01/11] video: vesa_fb: Look up VGA device by class instead of id

[Bin Meng]

Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 drivers/video/vesa_fb.c | 16 ++--------------
 1 file changed, 2 insertions(+), 14 deletions(-)

diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index 47f824a..909f8e8 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -1,6 +1,5 @@
 /*
- *
- * Vesa frame buffer driver for x86
+ * VESA frame buffer driver
  *
  * Copyright (C) 2014 Google, Inc
  *
@@ -17,16 +16,6 @@
  */
 GraphicDevice ctfb;
 
-/* Devices to allow - only the last one works fully */
-struct pci_device_id vesa_video_ids[] = {
-	{ .vendor = 0x102b, .device = 0x0525 },
-	{ .vendor = 0x1002, .device = 0x5159 },
-	{ .vendor = 0x1002, .device = 0x4752 },
-	{ .vendor = 0x1002, .device = 0x5452 },
-	{ .vendor = 0x8086, .device = 0x0f31 },
-	{},
-};
-
 void *video_hw_init(void)
 {
 	GraphicDevice *gdev = &ctfb;
@@ -36,8 +25,7 @@ void *video_hw_init(void)
 
 	printf("Video: ");
 	if (vbe_get_video_info(gdev)) {
-		/* TODO: Should we look these up by class? */
-		dev = pci_find_devices(vesa_video_ids, 0);
+		dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
 		if (dev == -1) {
 			printf("no card detected\n");
 			return NULL;
-- 
1.8.2.1

[U-Boot] [PATCH v2 02/11] x86: bios: Synchronize stack between real and protected mode

[Bin Meng]

From: Jian Luo <jian.luo4@boschrexroth.de>

PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- Add comments for the changes in the assembly codes

 arch/x86/lib/bios_asm.S | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/x86/lib/bios_asm.S b/arch/x86/lib/bios_asm.S
index 4faa70e..e559228 100644
--- a/arch/x86/lib/bios_asm.S
+++ b/arch/x86/lib/bios_asm.S
@@ -246,6 +246,9 @@ __interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
 	push	%fs
 	push	%gs
 
+	/* Save real mode SS */
+	movw	%ss, %cs:__realmode_ss
+
 	/* Clear DF to not break ABI assumptions */
 	cld
 
@@ -258,12 +261,29 @@ __interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
 
 	enter_protected_mode
 
+	/*
+	 * Now we are in protect mode. We need compute the right ESP based on
+	 * saved real mode SS otherwise interrupt_handler() won't get correct
+	 * parameters from the stack.
+	 */
+	movzwl	%cs:__realmode_ss, %ecx
+	shll	$4, %ecx
+	addl	%ecx, %esp
+
 	/* Call the C interrupt handler */
 	movl	$interrupt_handler, %eax
 	call	*%eax
 
+	/* Restore read mode ESP based on saved SS */
+	movzwl	%cs:__realmode_ss, %ecx
+	shll	$4, %ecx
+	subl	%ecx, %esp
+
 	enter_real_mode
 
+	/* Restore real mode SS */
+	movw	%cs:__realmode_ss, %ss
+
 	/*
 	 * Restore all registers, including those manipulated by the C
 	 * handler
@@ -276,6 +296,9 @@ __interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
 	popal
 	iret
 
+__realmode_ss = PTR_TO_REAL_MODE(.)
+	.word	0
+
 	.globl asm_realmode_code_size
 asm_realmode_code_size:
 	.long  . - asm_realmode_code
-- 
1.8.2.1

[U-Boot] [PATCH v2 03/11] x86: bios: Allow pci config read/write to host bridge in int1a_handler

[Bin Meng]

From: Jian Luo <jian.luo4@boschrexroth.de>

We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/lib/bios_interrupts.c | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c
index 290990a..47d9f59 100644
--- a/arch/x86/lib/bios_interrupts.c
+++ b/arch/x86/lib/bios_interrupts.c
@@ -161,15 +161,7 @@ int int1a_handler(void)
 		bus = M.x86.R_EBX >> 8;
 		reg = M.x86.R_EDI;
 		dev = PCI_BDF(bus, devfn >> 3, devfn & 7);
-		if (!dev) {
-			debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func,
-			      bus, devfn);
-			/* Or are we supposed to return PCIBIOS_NODEV? */
-			M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
-			M.x86.R_EAX |= PCIBIOS_BADREG;
-			retval = 0;
-			return retval;
-		}
+
 		switch (func) {
 		case 0xb108: /* Read Config Byte */
 			byte = x86_pci_read_config8(dev, reg);
-- 
1.8.2.1

[U-Boot] [PATCH v2 04/11] video: Add 32-bit color depth support for VBE

[Bin Meng]

From: Jian Luo <jian.luo4@boschrexroth.de>

The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 drivers/pci/pci_rom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index e6f4806..83c69a5 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -202,6 +202,7 @@ int vbe_get_video_info(struct graphic_device *gdev)
 	gdev->gdfBytesPP = vesa->bits_per_pixel / 8;
 
 	switch (vesa->bits_per_pixel) {
+	case 32:
 	case 24:
 		gdev->gdfIndex = GDF_32BIT_X888RGB;
 		break;
-- 
1.8.2.1

[U-Boot] [PATCH v2 05/11] x86: Setup fixed range MTRRs for legacy regions

[Bin Meng]

We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/cpu.c          | 22 ++++++++++++++++++++++
 arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++-----------
 2 files changed, 38 insertions(+), 11 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index d108ee5..9afdafb 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -28,6 +28,8 @@
 #include <asm/cpu.h>
 #include <asm/lapic.h>
 #include <asm/mp.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/processor-flags.h>
@@ -352,6 +354,26 @@ int x86_cpu_init_f(void)
 		gd->arch.has_mtrr = has_mtrr();
 	}
 
+	/* Configure fixed range MTRRs for some legacy regions */
+	if (gd->arch.has_mtrr) {
+		u64 mtrr_cap;
+
+		mtrr_cap = native_read_msr(MTRR_CAP_MSR);
+		if (mtrr_cap & MTRR_CAP_FIX) {
+			/* Mark the VGA RAM area as uncacheable */
+			native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);
+
+			/* Mark the PCI ROM area as uncacheable */
+			native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);
+			native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);
+			native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);
+			native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);
+
+			/* Enable the fixed range MTRRs */
+			msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
+		}
+	}
+
 	return 0;
 }
 
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 3ad617c..70762ee 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -21,6 +21,11 @@
 #define MTRR_CAP_MSR		0x0fe
 #define MTRR_DEF_TYPE_MSR	0x2ff
 
+#define MTRR_CAP_SMRR		(1 << 11)
+#define MTRR_CAP_WC		(1 << 10)
+#define MTRR_CAP_FIX		(1 << 8)
+#define MTRR_CAP_VCNT_MASK	0xff
+
 #define MTRR_DEF_TYPE_EN	(1 << 11)
 #define MTRR_DEF_TYPE_FIX_EN	(1 << 10)
 
@@ -38,17 +43,17 @@
 #define RANGES_PER_FIXED_MTRR	8
 #define NUM_FIXED_RANGES	(NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)
 
-#define MTRR_FIX_64K_00000_MSR 0x250
-#define MTRR_FIX_16K_80000_MSR 0x258
-#define MTRR_FIX_16K_A0000_MSR 0x259
-#define MTRR_FIX_4K_C0000_MSR 0x268
-#define MTRR_FIX_4K_C8000_MSR 0x269
-#define MTRR_FIX_4K_D0000_MSR 0x26a
-#define MTRR_FIX_4K_D8000_MSR 0x26b
-#define MTRR_FIX_4K_E0000_MSR 0x26c
-#define MTRR_FIX_4K_E8000_MSR 0x26d
-#define MTRR_FIX_4K_F0000_MSR 0x26e
-#define MTRR_FIX_4K_F8000_MSR 0x26f
+#define MTRR_FIX_64K_00000_MSR	0x250
+#define MTRR_FIX_16K_80000_MSR	0x258
+#define MTRR_FIX_16K_A0000_MSR	0x259
+#define MTRR_FIX_4K_C0000_MSR	0x268
+#define MTRR_FIX_4K_C8000_MSR	0x269
+#define MTRR_FIX_4K_D0000_MSR	0x26a
+#define MTRR_FIX_4K_D8000_MSR	0x26b
+#define MTRR_FIX_4K_E0000_MSR	0x26c
+#define MTRR_FIX_4K_E8000_MSR	0x26d
+#define MTRR_FIX_4K_F0000_MSR	0x26e
+#define MTRR_FIX_4K_F8000_MSR	0x26f
 
 #if !defined(__ASSEMBLER__)
 
-- 
1.8.2.1

[U-Boot] [PATCH v2 06/11] x86: queensbay: Change CPU_ADDR_BITS to 32

[Bin Meng]

Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/queensbay/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 397e599..fbf85f2 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -38,4 +38,8 @@ config CMC_ADDR
 	  The default base address of 0xfffb0000 indicates that the binary must
 	  be located at offset 0xb0000 from the beginning of a 1MB flash device.
 
+config CPU_ADDR_BITS
+	int
+	default 32
+
 endif
-- 
1.8.2.1

[U-Boot] [PATCH v2 07/11] x86: cmd_mtrr: Improve MTRR list information

[Bin Meng]

Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/lib/cmd_mtrr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/cmd_mtrr.c b/arch/x86/lib/cmd_mtrr.c
index 7e0506b..f632f49 100644
--- a/arch/x86/lib/cmd_mtrr.c
+++ b/arch/x86/lib/cmd_mtrr.c
@@ -37,7 +37,8 @@ static int do_mtrr_list(void)
 		valid = mask & MTRR_PHYS_MASK_VALID;
 		type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
 		printf("%d   %-5s %-12s %016llx %016llx %016llx\n", i,
-		       valid ? "Y" : "N", type, base, mask, size);
+		       valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
+		       mask & ~MTRR_PHYS_MASK_VALID, size);
 	}
 
 	return 0;
-- 
1.8.2.1

[U-Boot] [PATCH v2 08/11] x86: Move VGA option rom macros to Kconfig

[Bin Meng]

Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 Makefile                            |  4 ++--
 arch/x86/Kconfig                    | 22 ++++++++++++++++++++++
 configs/chromebook_link_defconfig   |  1 +
 configs/chromebox_panther_defconfig |  1 +
 configs/minnowmax_defconfig         |  1 +
 doc/README.x86                      |  2 +-
 drivers/pci/pci_rom.c               |  6 +++---
 include/configs/minnowmax.h         |  3 ---
 include/configs/x86-chromebook.h    |  3 ---
 9 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/Makefile b/Makefile
index 0a674bf..2601e87 100644
--- a/Makefile
+++ b/Makefile
@@ -1034,8 +1034,8 @@ ifneq ($(CONFIG_HAVE_CMC),)
 IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
 endif
 
-ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
+ifneq ($(CONFIG_HAVE_VGA_BIOS),)
+IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
 endif
 
 quiet_cmd_ifdtool = IFDTOOL $@
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 6b46ec4..0e308ce 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -293,6 +293,28 @@ config TSC_FREQ_IN_MHZ
 	help
 	  The running frequency in MHz of Time-Stamp Counter (TSC).
 
+config HAVE_VGA_BIOS
+	bool "Add a VGA BIOS image"
+	help
+	  Select this option if you have a VGA BIOS image that you would
+	  like to add to your ROM.
+
+config VGA_BIOS_FILE
+	string "VGA BIOS image filename"
+	depends on HAVE_VGA_BIOS
+	default "vga.bin"
+	help
+	  The filename of the VGA BIOS image in the board directory.
+
+config VGA_BIOS_ADDR
+	hex "VGA BIOS image location"
+	depends on HAVE_VGA_BIOS
+	default 0xfff90000
+	help
+	  The location of VGA BIOS image in the SPI flash. For example, base
+	  address of 0xfff90000 indicates that the image will be put at offset
+	  0x90000 from the beginning of a 1MB flash device.
+
 menu "System tables"
 
 config GENERATE_PIRQ_TABLE
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 4f7f779..08743f0 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
 CONFIG_TARGET_CHROMEBOOK_LINK=y
 CONFIG_HAVE_MRC=y
+CONFIG_HAVE_VGA_BIOS=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CMD_NET=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 941033f..9cd422a 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
 CONFIG_TARGET_CHROMEBOX_PANTHER=y
 CONFIG_HAVE_MRC=y
+CONFIG_HAVE_VGA_BIOS=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CMD_NET=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 744aca3..bfe2cdf 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
 CONFIG_TARGET_MINNOWMAX=y
 CONFIG_HAVE_INTEL_ME=y
+CONFIG_HAVE_VGA_BIOS=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/doc/README.x86 b/doc/README.x86
index 49d6e83..7f3914f 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -79,7 +79,7 @@ Find the following files:
 * ./northbridge/intel/sandybridge/systemagent-r6.bin
 
 The 3rd one should be renamed to mrc.bin.
-As for the video ROM, you can get it here [3].
+As for the video ROM, you can get it here [3] and rename it to vga.bin.
 Make sure all these binary blobs are put in the board directory.
 
 Now you can build U-Boot and obtain u-boot.rom:
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 83c69a5..4a91033 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -79,8 +79,8 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 	if (vendev != mapped_vendev)
 		debug("Device ID mapped to %#08x\n", mapped_vendev);
 
-#ifdef CONFIG_X86_OPTION_ROM_ADDR
-	rom_address = CONFIG_X86_OPTION_ROM_ADDR;
+#ifdef CONFIG_VGA_BIOS_ADDR
+	rom_address = CONFIG_VGA_BIOS_ADDR;
 #else
 
 	pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
@@ -103,7 +103,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 	if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
 		printf("Incorrect expansion ROM header signature %04x\n",
 		       le16_to_cpu(rom_header->signature));
-#ifndef CONFIG_X86_OPTION_ROM_ADDR
+#ifndef CONFIG_VGA_BIOS_ADDR
 		/* Disable expansion ROM address decoding */
 		pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address);
 #endif
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 547765d..8ee84a6 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -52,9 +52,6 @@
 #undef CONFIG_USB_MAX_CONTROLLER_COUNT
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 
-#define CONFIG_X86_OPTION_ROM_FILE		vga.bin
-#define CONFIG_X86_OPTION_ROM_ADDR		0xfff90000
-
 #define VIDEO_IO_OFFSET				0
 #define CONFIG_X86EMU_RAW_IO
 #define CONFIG_VGA_AS_SINGLE_DEVICE
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index e0e7fca..408cbb1 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -26,9 +26,6 @@
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
 
-#define CONFIG_X86_OPTION_ROM_FILE		pci8086,0166.bin
-#define CONFIG_X86_OPTION_ROM_ADDR		0xfff90000
-
 #define CONFIG_PCI_MEM_BUS	0xe0000000
 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
 #define CONFIG_PCI_MEM_SIZE	0x10000000
-- 
1.8.2.1

[U-Boot] [PATCH v2 09/11] x86: Remove MARK_GRAPHICS_MEM_WRCOMB

[Bin Meng]

MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/Kconfig                       | 8 --------
 board/google/chromebook_link/Kconfig   | 1 -
 board/google/chromebox_panther/Kconfig | 1 -
 3 files changed, 10 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0e308ce..0036344 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -194,14 +194,6 @@ config X86_RAMTEST
 	  to work correctly. It is not exhaustive but can save time by
 	  detecting obvious failures.
 
-config MARK_GRAPHICS_MEM_WRCOMB
-	bool "Mark graphics memory as write-combining"
-	default n
-	help
-	  The graphics performance may increase if the graphics
-	  memory is set as write-combining cache type. This option
-	  enables marking the graphics memory as write-combining.
-
 config HAVE_FSP
 	bool "Add an Firmware Support Package binary"
 	help
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 9c8d020..d3644a9 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select SOUTHBRIDGE_INTEL_C216
 	select HAVE_ACPI_RESUME
-	select MARK_GRAPHICS_MEM_WRCOMB
 	select BOARD_ROMSIZE_KB_8192
 
 config PCIE_ECAM_BASE
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index e3604eb..d56d903 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select SOUTHBRIDGE_INTEL_C216
 	select HAVE_ACPI_RESUME
-	select MARK_GRAPHICS_MEM_WRCOMB
 	select BOARD_ROMSIZE_KB_8192
 
 config SYS_CAR_ADDR
-- 
1.8.2.1

[U-Boot] [PATCH v2 10/11] x86: crownbay: Enable graphics support

[Bin Meng]

Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 configs/crownbay_defconfig |  3 +++
 doc/README.x86             | 20 +++++++++++++-------
 include/configs/crownbay.h | 14 +++++++-------
 3 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index e4edad0..de24bb6 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -4,10 +4,13 @@ CONFIG_DEFAULT_DEVICE_TREE="crownbay"
 CONFIG_TARGET_CROWNBAY=y
 CONFIG_SMP=y
 CONFIG_MAX_CPUS=2
+CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_CMD_CPU=y
 CONFIG_CMD_NET=y
 CONFIG_OF_CONTROL=y
 CONFIG_CPU=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_DM_RTC=y
diff --git a/doc/README.x86 b/doc/README.x86
index 7f3914f..646eff1 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -113,6 +113,10 @@ binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
 binary, change the following five bytes values from orginally E8 42 FF FF FF
 to B8 00 80 0B 00.
 
+As for the video ROM, you need manually extract it from the Intel provided
+BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM
+ID 8086:4108, extract and save it as vga.bin in the board directory.
+
 Now you can build U-Boot and obtain u-boot.rom
 
 $ make crownbay_defconfig
@@ -254,7 +258,7 @@ If you want to check both consoles, use '-serial stdio'.
 
 CPU Microcode
 -------------
-Modern CPUs usually require a special bit stream called microcode [6] to be
+Modern CPUs usually require a special bit stream called microcode [8] to be
 loaded on the processor after power up in order to function properly. U-Boot
 has already integrated these as hex dumps in the source tree.
 
@@ -265,9 +269,9 @@ Additional application processors (AP) can be brought up by U-Boot. In order to
 have an SMP kernel to discover all of the available processors, U-Boot needs to
 prepare configuration tables which contain the multi-CPUs information before
 loading the OS kernel. Currently U-Boot supports generating two types of tables
-for SMP, called Simple Firmware Interface (SFI) [7] and Multi-Processor (MP) [8]
-tables. The writing of these two tables are controlled by two Kconfig options
-GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
+for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP)
+[10] tables. The writing of these two tables are controlled by two Kconfig
+options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
 
 Driver Model
 ------------
@@ -372,6 +376,8 @@ References
 [3] http://www.coreboot.org/~stepan/pci8086,0166.rom
 [4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
 [5] http://www.intel.com/fsp
-[6] http://en.wikipedia.org/wiki/Microcode
-[7] http://simplefirmware.org
-[8] http://www.intel.com/design/archives/processors/pro/docs/242016.htm
+[6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
+[7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
+[8] http://en.wikipedia.org/wiki/Microcode
+[9] http://simplefirmware.org
+[10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 0e1f046..6cf53a3 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -32,15 +32,16 @@
 #define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE		0xe000
 
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
 #define CONFIG_E1000
 
-#define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
-					"stdout=serial\0" \
-					"stderr=serial\0"
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,vga,usbkbd\0" \
+					"stdout=serial,vga\0" \
+					"stderr=serial,vga\0"
 
-#define CONFIG_SCSI_DEV_LIST            \
+#define CONFIG_SCSI_DEV_LIST		\
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
 
 #define CONFIG_SPI_FLASH_SST
@@ -55,9 +56,8 @@
 #define CONFIG_PCH_GBE
 #define CONFIG_PHYLIB
 
-/* Video is not supported */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
+/* TunnelCreek IGD support */
+#define CONFIG_VGA_AS_SINGLE_DEVICE
 
 /* Environment configuration */
 #define CONFIG_ENV_SECT_SIZE		0x1000
-- 
1.8.2.1

[U-Boot] [PATCH v2 11/11] x86: Configure VESA parameters before loading Linux kernel

[Bin Meng]

Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>

---

Changes in v2: None

 arch/x86/include/asm/zimage.h |  1 +
 arch/x86/lib/zimage.c         |  2 ++
 drivers/pci/pci_rom.c         | 28 ++++++++++++++++++++++++++++
 include/vbe.h                 |  4 ++--
 4 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 8e7dd42..bf351ed 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -38,5 +38,6 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 				ulong *load_addressp);
 int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 		 unsigned long initrd_addr, unsigned long initrd_size);
+void setup_video(struct screen_info *screen_info);
 
 #endif
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index c3f8a73..144471c 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -273,6 +273,8 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 		build_command_line(cmd_line, auto_boot);
 	}
 
+	setup_video(&setup_base->screen_info);
+
 	return 0;
 }
 
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 4a91033..a33efae 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -31,6 +31,7 @@
 #include <pci_rom.h>
 #include <vbe.h>
 #include <video_fb.h>
+#include <linux/screen_info.h>
 
 #ifdef CONFIG_HAVE_ACPI_RESUME
 #include <asm/acpi.h>
@@ -229,6 +230,33 @@ int vbe_get_video_info(struct graphic_device *gdev)
 #endif
 }
 
+void setup_video(struct screen_info *screen_info)
+{
+#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE
+	struct vesa_mode_info *vesa = &mode_info.vesa;
+
+	screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB;
+
+	screen_info->lfb_width = vesa->x_resolution;
+	screen_info->lfb_height = vesa->y_resolution;
+	screen_info->lfb_depth = vesa->bits_per_pixel;
+	screen_info->lfb_linelength = vesa->bytes_per_scanline;
+	screen_info->lfb_base = vesa->phys_base_ptr;
+	screen_info->lfb_size =
+		ALIGN(screen_info->lfb_linelength * screen_info->lfb_height,
+		      65536);
+	screen_info->lfb_size >>= 16;
+	screen_info->red_size = vesa->red_mask_size;
+	screen_info->red_pos = vesa->red_mask_pos;
+	screen_info->green_size = vesa->green_mask_size;
+	screen_info->green_pos = vesa->green_mask_pos;
+	screen_info->blue_size = vesa->blue_mask_size;
+	screen_info->blue_pos = vesa->blue_mask_pos;
+	screen_info->rsvd_size = vesa->reserved_mask_size;
+	screen_info->rsvd_pos = vesa->reserved_mask_pos;
+#endif
+}
+
 int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
 {
 	struct pci_rom_header *rom, *ram;
diff --git a/include/vbe.h b/include/vbe.h
index c5deee9..1a86db8 100644
--- a/include/vbe.h
+++ b/include/vbe.h
@@ -12,7 +12,7 @@
 #define _VBE_H
 
 /* these structs are for input from and output to OF */
-struct __packed screen_info {
+struct __packed vbe_screen_info {
 	u8 display_type;	/* 0=NONE, 1= analog, 2=digital */
 	u16 screen_width;
 	u16 screen_height;
@@ -23,7 +23,7 @@ struct __packed screen_info {
 	u8 edid_block_zero[128];
 };
 
-struct __packed screen_info_input {
+struct __packed vbe_screen_info_input {
 	u8 signature[4];
 	u16 size_reserved;
 	u8 monitor_number;
-- 
1.8.2.1

[U-Boot] [PATCH v2 02/11] x86: bios: Synchronize stack between real and protected mode

[Bin Meng]

Hi Simon,

On Mon, Jul 6, 2015 at 4:31 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> From: Jian Luo <jian.luo4@boschrexroth.de>
>
> PCI option rom may use different SS during its execution, so it is not
> safe to assume esp pointed to the same location in the protected mode.
>
> Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v2:
> - Add comments for the changes in the assembly codes
>
>  arch/x86/lib/bios_asm.S | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/arch/x86/lib/bios_asm.S b/arch/x86/lib/bios_asm.S
> index 4faa70e..e559228 100644
> --- a/arch/x86/lib/bios_asm.S
> +++ b/arch/x86/lib/bios_asm.S
> @@ -246,6 +246,9 @@ __interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
>         push    %fs
>         push    %gs
>
> +       /* Save real mode SS */
> +       movw    %ss, %cs:__realmode_ss
> +
>         /* Clear DF to not break ABI assumptions */
>         cld
>
> @@ -258,12 +261,29 @@ __interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
>
>         enter_protected_mode
>
> +       /*
> +        * Now we are in protect mode. We need compute the right ESP based on
> +        * saved real mode SS otherwise interrupt_handler() won't get correct
> +        * parameters from the stack.
> +        */
> +       movzwl  %cs:__realmode_ss, %ecx
> +       shll    $4, %ecx
> +       addl    %ecx, %esp
> +
>         /* Call the C interrupt handler */
>         movl    $interrupt_handler, %eax
>         call    *%eax
>
> +       /* Restore read mode ESP based on saved SS */
> +       movzwl  %cs:__realmode_ss, %ecx
> +       shll    $4, %ecx
> +       subl    %ecx, %esp
> +
>         enter_real_mode
>
> +       /* Restore real mode SS */
> +       movw    %cs:__realmode_ss, %ss
> +
>         /*
>          * Restore all registers, including those manipulated by the C
>          * handler
> @@ -276,6 +296,9 @@ __interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
>         popal
>         iret
>
> +__realmode_ss = PTR_TO_REAL_MODE(.)
> +       .word   0
> +
>         .globl asm_realmode_code_size
>  asm_realmode_code_size:
>         .long  . - asm_realmode_code
> --

Sorry I have to respin this patch. Please check the new one here:
http://patchwork.ozlabs.org/patch/491496/

Regards,
Bin

[U-Boot] [PATCH v2 01/11] video: vesa_fb: Look up VGA device by class instead of id

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> Per PCI spec, VGA device reports its class as standard 030000h in
> its configuration space, so we can use it to determine if we need
> run option rom instead of testing the supported vendor/device ids.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  drivers/video/vesa_fb.c | 16 ++--------------
>  1 file changed, 2 insertions(+), 14 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 03/11] x86: bios: Allow pci config read/write to host bridge in int1a_handler

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> From: Jian Luo <jian.luo4@boschrexroth.de>
>
> We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
> in the int1a_handler() which is a valid pci device.
>
> Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/lib/bios_interrupts.c | 10 +---------
>  1 file changed, 1 insertion(+), 9 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 04/11] video: Add 32-bit color depth support for VBE

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> From: Jian Luo <jian.luo4@boschrexroth.de>
>
> The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
> color depth is configured. Since 24-bit mode already uses 4 bytes
> internally, it should be OK to just add this option in switch case.
>
> Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  drivers/pci/pci_rom.c | 1 +
>  1 file changed, 1 insertion(+)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 05/11] x86: Setup fixed range MTRRs for legacy regions

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> We should setup fixed range MTRRs for some legacy regions like VGA
> RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
> other cache settings, but we can override this in x86_cpu_init_f().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/cpu.c          | 22 ++++++++++++++++++++++
>  arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++-----------
>  2 files changed, 38 insertions(+), 11 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 06/11] x86: queensbay: Change CPU_ADDR_BITS to 32

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> Per CPUID:80000008h result, the maximum physical address bits of
> TunnelCreek processor is 32 instead of default 36. This will fix
> the incorrect decoding of MTRR range mask.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/queensbay/Kconfig | 4 ++++
>  1 file changed, 4 insertions(+)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 07/11] x86: cmd_mtrr: Improve MTRR list information

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> Print the meaningful base address and mask of an MTRR range without showing
> the memory type encoding or valid bit.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/lib/cmd_mtrr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 08/11] x86: Move VGA option rom macros to Kconfig

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
> and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
> HAVE_VGA_BIOS. The new names are consistent with other x86 binary
> blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  Makefile                            |  4 ++--
>  arch/x86/Kconfig                    | 22 ++++++++++++++++++++++
>  configs/chromebook_link_defconfig   |  1 +
>  configs/chromebox_panther_defconfig |  1 +
>  configs/minnowmax_defconfig         |  1 +
>  doc/README.x86                      |  2 +-
>  drivers/pci/pci_rom.c               |  6 +++---
>  include/configs/minnowmax.h         |  3 ---
>  include/configs/x86-chromebook.h    |  3 ---
>  9 files changed, 31 insertions(+), 12 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 09/11] x86: Remove MARK_GRAPHICS_MEM_WRCOMB

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
> hence remove it.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/Kconfig                       | 8 --------
>  board/google/chromebook_link/Kconfig   | 1 -
>  board/google/chromebox_panther/Kconfig | 1 -
>  3 files changed, 10 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 10/11] x86: crownbay: Enable graphics support

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> Enable graphics support on Intel Crown Bay board With the help of
> vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
> panel connected to X4 connector and SDVO adapter connected to X9
> connector on the board.
>
> Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  configs/crownbay_defconfig |  3 +++
>  doc/README.x86             | 20 +++++++++++++-------
>  include/configs/crownbay.h | 14 +++++++-------
>  3 files changed, 23 insertions(+), 14 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 11/11] x86: Configure VESA parameters before loading Linux kernel

[Simon Glass]

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> Store VESA parameters to Linux setup header so that vesafb driver
> in the kernel could work.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
>
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/zimage.h |  1 +
>  arch/x86/lib/zimage.c         |  2 ++
>  drivers/pci/pci_rom.c         | 28 ++++++++++++++++++++++++++++
>  include/vbe.h                 |  4 ++--
>  4 files changed, 33 insertions(+), 2 deletions(-)

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 05/11] x86: Setup fixed range MTRRs for legacy regions

[Simon Glass]

Hi Bin,

On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> We should setup fixed range MTRRs for some legacy regions like VGA
> RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
> other cache settings, but we can override this in x86_cpu_init_f().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/cpu.c          | 22 ++++++++++++++++++++++
>  arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++-----------
>  2 files changed, 38 insertions(+), 11 deletions(-)
>
> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
> index d108ee5..9afdafb 100644
> --- a/arch/x86/cpu/cpu.c
> +++ b/arch/x86/cpu/cpu.c
> @@ -28,6 +28,8 @@
>  #include <asm/cpu.h>
>  #include <asm/lapic.h>
>  #include <asm/mp.h>
> +#include <asm/msr.h>
> +#include <asm/mtrr.h>
>  #include <asm/post.h>
>  #include <asm/processor.h>
>  #include <asm/processor-flags.h>
> @@ -352,6 +354,26 @@ int x86_cpu_init_f(void)
>                 gd->arch.has_mtrr = has_mtrr();
>         }
>
> +       /* Configure fixed range MTRRs for some legacy regions */
> +       if (gd->arch.has_mtrr) {
> +               u64 mtrr_cap;
> +
> +               mtrr_cap = native_read_msr(MTRR_CAP_MSR);
> +               if (mtrr_cap & MTRR_CAP_FIX) {
> +                       /* Mark the VGA RAM area as uncacheable */
> +                       native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);
> +
> +                       /* Mark the PCI ROM area as uncacheable */
> +                       native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);
> +                       native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);
> +                       native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);
> +                       native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);

I just noticed that setting this up makes the Minnowmax ROM execution
go really slowly. Do we need to turn off the cache? It goes from <1s
to >4s.

> +
> +                       /* Enable the fixed range MTRRs */
> +                       msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
> +               }
> +       }
> +
>         return 0;
>  }
>
> diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
> index 3ad617c..70762ee 100644
> --- a/arch/x86/include/asm/mtrr.h
> +++ b/arch/x86/include/asm/mtrr.h
> @@ -21,6 +21,11 @@
>  #define MTRR_CAP_MSR           0x0fe
>  #define MTRR_DEF_TYPE_MSR      0x2ff
>
> +#define MTRR_CAP_SMRR          (1 << 11)
> +#define MTRR_CAP_WC            (1 << 10)
> +#define MTRR_CAP_FIX           (1 << 8)
> +#define MTRR_CAP_VCNT_MASK     0xff
> +
>  #define MTRR_DEF_TYPE_EN       (1 << 11)
>  #define MTRR_DEF_TYPE_FIX_EN   (1 << 10)
>
> @@ -38,17 +43,17 @@
>  #define RANGES_PER_FIXED_MTRR  8
>  #define NUM_FIXED_RANGES       (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)
>
> -#define MTRR_FIX_64K_00000_MSR 0x250
> -#define MTRR_FIX_16K_80000_MSR 0x258
> -#define MTRR_FIX_16K_A0000_MSR 0x259
> -#define MTRR_FIX_4K_C0000_MSR 0x268
> -#define MTRR_FIX_4K_C8000_MSR 0x269
> -#define MTRR_FIX_4K_D0000_MSR 0x26a
> -#define MTRR_FIX_4K_D8000_MSR 0x26b
> -#define MTRR_FIX_4K_E0000_MSR 0x26c
> -#define MTRR_FIX_4K_E8000_MSR 0x26d
> -#define MTRR_FIX_4K_F0000_MSR 0x26e
> -#define MTRR_FIX_4K_F8000_MSR 0x26f
> +#define MTRR_FIX_64K_00000_MSR 0x250
> +#define MTRR_FIX_16K_80000_MSR 0x258
> +#define MTRR_FIX_16K_A0000_MSR 0x259
> +#define MTRR_FIX_4K_C0000_MSR  0x268
> +#define MTRR_FIX_4K_C8000_MSR  0x269
> +#define MTRR_FIX_4K_D0000_MSR  0x26a
> +#define MTRR_FIX_4K_D8000_MSR  0x26b
> +#define MTRR_FIX_4K_E0000_MSR  0x26c
> +#define MTRR_FIX_4K_E8000_MSR  0x26d
> +#define MTRR_FIX_4K_F0000_MSR  0x26e
> +#define MTRR_FIX_4K_F8000_MSR  0x26f
>
>  #if !defined(__ASSEMBLER__)
>
> --
> 1.8.2.1
>

Regards,
Simon

[U-Boot] [PATCH v2 05/11] x86: Setup fixed range MTRRs for legacy regions

[Bin Meng]

Hi Simon,

On Fri, Jul 10, 2015 at 8:55 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
>> We should setup fixed range MTRRs for some legacy regions like VGA
>> RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
>> other cache settings, but we can override this in x86_cpu_init_f().
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  arch/x86/cpu/cpu.c          | 22 ++++++++++++++++++++++
>>  arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++-----------
>>  2 files changed, 38 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
>> index d108ee5..9afdafb 100644
>> --- a/arch/x86/cpu/cpu.c
>> +++ b/arch/x86/cpu/cpu.c
>> @@ -28,6 +28,8 @@
>>  #include <asm/cpu.h>
>>  #include <asm/lapic.h>
>>  #include <asm/mp.h>
>> +#include <asm/msr.h>
>> +#include <asm/mtrr.h>
>>  #include <asm/post.h>
>>  #include <asm/processor.h>
>>  #include <asm/processor-flags.h>
>> @@ -352,6 +354,26 @@ int x86_cpu_init_f(void)
>>                 gd->arch.has_mtrr = has_mtrr();
>>         }
>>
>> +       /* Configure fixed range MTRRs for some legacy regions */
>> +       if (gd->arch.has_mtrr) {
>> +               u64 mtrr_cap;
>> +
>> +               mtrr_cap = native_read_msr(MTRR_CAP_MSR);
>> +               if (mtrr_cap & MTRR_CAP_FIX) {
>> +                       /* Mark the VGA RAM area as uncacheable */
>> +                       native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);
>> +
>> +                       /* Mark the PCI ROM area as uncacheable */
>> +                       native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);
>> +                       native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);
>> +                       native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);
>> +                       native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);
>
> I just noticed that setting this up makes the Minnowmax ROM execution
> go really slowly. Do we need to turn off the cache? It goes from <1s
> to >4s.

Oops, that's bad. I guess we should turn on the cache for the rom
execution then. BTW I found the tunnelcreek vbios changed the Cseg
MTRR to write-through itself.

>
>> +
>> +                       /* Enable the fixed range MTRRs */
>> +                       msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
>> +               }
>> +       }
>> +
>>         return 0;
>>  }
>>

[snip]

Regards,
Bin

[U-Boot] [PATCH v2 05/11] x86: Setup fixed range MTRRs for legacy regions

[Simon Glass]

Hi Bin,

On 10 July 2015 at 09:39, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Fri, Jul 10, 2015 at 8:55 PM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> We should setup fixed range MTRRs for some legacy regions like VGA
>>> RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
>>> other cache settings, but we can override this in x86_cpu_init_f().
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>> Changes in v2: None
>>>
>>>  arch/x86/cpu/cpu.c          | 22 ++++++++++++++++++++++
>>>  arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++-----------
>>>  2 files changed, 38 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
>>> index d108ee5..9afdafb 100644
>>> --- a/arch/x86/cpu/cpu.c
>>> +++ b/arch/x86/cpu/cpu.c
>>> @@ -28,6 +28,8 @@
>>>  #include <asm/cpu.h>
>>>  #include <asm/lapic.h>
>>>  #include <asm/mp.h>
>>> +#include <asm/msr.h>
>>> +#include <asm/mtrr.h>
>>>  #include <asm/post.h>
>>>  #include <asm/processor.h>
>>>  #include <asm/processor-flags.h>
>>> @@ -352,6 +354,26 @@ int x86_cpu_init_f(void)
>>>                 gd->arch.has_mtrr = has_mtrr();
>>>         }
>>>
>>> +       /* Configure fixed range MTRRs for some legacy regions */
>>> +       if (gd->arch.has_mtrr) {
>>> +               u64 mtrr_cap;
>>> +
>>> +               mtrr_cap = native_read_msr(MTRR_CAP_MSR);
>>> +               if (mtrr_cap & MTRR_CAP_FIX) {
>>> +                       /* Mark the VGA RAM area as uncacheable */
>>> +                       native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);
>>> +
>>> +                       /* Mark the PCI ROM area as uncacheable */
>>> +                       native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);
>>> +                       native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);
>>> +                       native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);
>>> +                       native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);
>>
>> I just noticed that setting this up makes the Minnowmax ROM execution
>> go really slowly. Do we need to turn off the cache? It goes from <1s
>> to >4s.
>
> Oops, that's bad. I guess we should turn on the cache for the rom
> execution then. BTW I found the tunnelcreek vbios changed the Cseg
> MTRR to write-through itself.

OK - can you try to do a patch for that? But first, why do we need to
make the area uncacheable?

Regards,
Simon

[U-Boot] [PATCH v2 05/11] x86: Setup fixed range MTRRs for legacy regions

[Bin Meng]

Hi Simon,

On Sat, Jul 11, 2015 at 12:09 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 10 July 2015 at 09:39, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Fri, Jul 10, 2015 at 8:55 PM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> We should setup fixed range MTRRs for some legacy regions like VGA
>>>> RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
>>>> other cache settings, but we can override this in x86_cpu_init_f().
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>> ---
>>>>
>>>> Changes in v2: None
>>>>
>>>>  arch/x86/cpu/cpu.c          | 22 ++++++++++++++++++++++
>>>>  arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++-----------
>>>>  2 files changed, 38 insertions(+), 11 deletions(-)
>>>>
>>>> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
>>>> index d108ee5..9afdafb 100644
>>>> --- a/arch/x86/cpu/cpu.c
>>>> +++ b/arch/x86/cpu/cpu.c
>>>> @@ -28,6 +28,8 @@
>>>>  #include <asm/cpu.h>
>>>>  #include <asm/lapic.h>
>>>>  #include <asm/mp.h>
>>>> +#include <asm/msr.h>
>>>> +#include <asm/mtrr.h>
>>>>  #include <asm/post.h>
>>>>  #include <asm/processor.h>
>>>>  #include <asm/processor-flags.h>
>>>> @@ -352,6 +354,26 @@ int x86_cpu_init_f(void)
>>>>                 gd->arch.has_mtrr = has_mtrr();
>>>>         }
>>>>
>>>> +       /* Configure fixed range MTRRs for some legacy regions */
>>>> +       if (gd->arch.has_mtrr) {
>>>> +               u64 mtrr_cap;
>>>> +
>>>> +               mtrr_cap = native_read_msr(MTRR_CAP_MSR);
>>>> +               if (mtrr_cap & MTRR_CAP_FIX) {
>>>> +                       /* Mark the VGA RAM area as uncacheable */
>>>> +                       native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);
>>>> +
>>>> +                       /* Mark the PCI ROM area as uncacheable */
>>>> +                       native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);
>>>> +                       native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);
>>>> +                       native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);
>>>> +                       native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);
>>>
>>> I just noticed that setting this up makes the Minnowmax ROM execution
>>> go really slowly. Do we need to turn off the cache? It goes from <1s
>>> to >4s.
>>
>> Oops, that's bad. I guess we should turn on the cache for the rom
>> execution then. BTW I found the tunnelcreek vbios changed the Cseg
>> MTRR to write-through itself.
>
> OK - can you try to do a patch for that? But first, why do we need to
> make the area uncacheable?
>

Yep, I can prepare a patch. I was referring to several chipset
datasheet before, which mentions the suggested MTRR settings to UC,
but this seems wrong.

Regards,
Bin