* [RFC PATCH v3 0/3] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support
[not found] <CGME20200518131814eucas1p18b2f895c127708ac6b55b033fb7a43d2@eucas1p1.samsung.com>
@ 2020-05-18 13:17 ` Marek Szyprowski
[not found] ` <CGME20200518131816eucas1p1aa84fb661559b858fd976d414212c254@eucas1p1.samsung.com>
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Marek Szyprowski @ 2020-05-18 13:17 UTC (permalink / raw)
To: u-boot
Hi All,
This patchset add support for creating a mapping for the arbitrary
physical address at the given virtual address. This is needed to enable
support for XHCI USB controller on PCIe bridge on Raspberry Pi 4 board,
on which the USB controller's MMIO area 0x600000000 has to be remapped
somewhere to fit in 4GiB virtual address space when running in ARM 32bit
mode.
This patchset is a continuation of the Raspberry Pi 4 XHCI/PCIe patchset:
https://patchwork.ozlabs.org/project/uboot/list/?series=176453
and the following discussion:
https://lists.denx.de/pipermail/u-boot/2020-May/411086.html
Best regards
Marek Szyprowski
Samsung R&D Institute Poland
Changelog:
v3:
- fixed broken RPi3 and lack of the identity mapping for map_physmem
(for example for the itest command was broken)
- added a patch fixing a new build warning
v2: https://lists.denx.de/pipermail/u-boot/2020-May/411765.html
- fixed ARM64 build
v1: https://lists.denx.de/pipermail/u-boot/2020-May/411765.html
- initial RFC
Patch summary:
Marek Szyprowski (2):
arm: provide a function for boards init code to modify MMU
virtual-physical map
rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM
32bit)
Seung-Woo Kim (1):
mmc: bcm283x: fix int to pointer cast
arch/arm/include/asm/mmu.h | 8 ++++++++
arch/arm/include/asm/system.h | 11 +++++++++++
arch/arm/lib/cache-cp15.c | 24 ++++++++++++++++++------
arch/arm/mach-bcm283x/Kconfig | 1 +
arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
drivers/mmc/bcm2835_sdhci.c | 2 +-
include/configs/rpi.h | 7 +++++++
8 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/include/asm/mmu.h
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC PATCH v3 1/3] arm: provide a function for boards init code to modify MMU virtual-physical map
[not found] ` <CGME20200518131816eucas1p1aa84fb661559b858fd976d414212c254@eucas1p1.samsung.com>
@ 2020-05-18 13:17 ` Marek Szyprowski
0 siblings, 0 replies; 11+ messages in thread
From: Marek Szyprowski @ 2020-05-18 13:17 UTC (permalink / raw)
To: u-boot
Provide a function for setting arbitrary virtual-physical MMU mapping
for the given region.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm/include/asm/mmu.h | 8 ++++++++
arch/arm/include/asm/system.h | 11 +++++++++++
arch/arm/lib/cache-cp15.c | 24 ++++++++++++++++++------
3 files changed, 37 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/include/asm/mmu.h
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
new file mode 100644
index 0000000..fe3d793
--- /dev/null
+++ b/arch/arm/include/asm/mmu.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_ARM_MMU_H
+#define __ASM_ARM_MMU_H
+
+#ifdef CONFIG_ADDR_MAP
+extern void init_addr_map(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 81ccead..5b9f31c 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -573,6 +573,17 @@ s32 psci_features(u32 function_id, u32 psci_fid);
void save_boot_params_ret(void);
/**
+ * Change the virt/phys mapping and cache settings for a region.
+ *
+ * \param virt virtual start address of memory region to change
+ * \param phys physical address for the memory region to set
+ * \param size size of memory region to change
+ * \param option dcache option to select
+ */
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
+ size_t size, enum dcache_option option);
+
+/**
* Change the cache settings for a region.
*
* \param start start address of memory region to change
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f8d2096..84ddad3 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -24,7 +24,8 @@ __weak void arm_init_domains(void)
{
}
-void set_section_dcache(int section, enum dcache_option option)
+static void set_section_phys(int section, phys_addr_t phys,
+ enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
u64 *page_table = (u64 *)gd->arch.tlb_addr;
@@ -36,7 +37,7 @@ void set_section_dcache(int section, enum dcache_option option)
#endif
/* Add the page offset */
- value |= ((u32)section << MMU_SECTION_SHIFT);
+ value |= phys;
/* Add caching bits */
value |= option;
@@ -45,13 +46,18 @@ void set_section_dcache(int section, enum dcache_option option)
page_table[section] = value;
}
+void set_section_dcache(int section, enum dcache_option option)
+{
+ set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
+}
+
__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
debug("%s: Warning: not implemented\n", __func__);
}
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
- enum dcache_option option)
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
+ size_t size, enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
u64 *page_table = (u64 *)gd->arch.tlb_addr;
@@ -70,8 +76,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
option);
#endif
- for (upto = start; upto < end; upto++)
- set_section_dcache(upto, option);
+ for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
+ set_section_phys(upto, phys, option);
/*
* Make sure range is cache line aligned
@@ -86,6 +92,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
mmu_page_table_flush(startpt, stoppt);
}
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ enum dcache_option option)
+{
+ mmu_set_region_dcache_behaviour_phys(start, start, size, option);
+}
+
__weak void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RFC PATCH v3 2/3] mmc: bcm283x: fix int to pointer cast
[not found] ` <CGME20200518131816eucas1p2344d0e25b136ee0d2f07517af488358e@eucas1p2.samsung.com>
@ 2020-05-18 13:18 ` Marek Szyprowski
0 siblings, 0 replies; 11+ messages in thread
From: Marek Szyprowski @ 2020-05-18 13:18 UTC (permalink / raw)
To: u-boot
From: Seung-Woo Kim <sw0312.kim@samsung.com>
On build with 32 bit, there is a warning for int-to-pointer-cast.
Fix the int to pointer cast by using uintptr_t.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/mmc/bcm2835_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 39c93db..c31f099 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -209,7 +209,7 @@ static int bcm2835_sdhci_probe(struct udevice *dev)
priv->last_write = 0;
host->name = dev->name;
- host->ioaddr = (void *)base;
+ host->ioaddr = (void *)(uintptr_t)base;
host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
host->max_clk = emmc_freq;
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
[not found] ` <CGME20200518131817eucas1p16d37a356ad7f18a9a0f75ccbe9663905@eucas1p1.samsung.com>
@ 2020-05-18 13:18 ` Marek Szyprowski
2020-05-18 22:38 ` Simon Glass
0 siblings, 1 reply; 11+ messages in thread
From: Marek Szyprowski @ 2020-05-18 13:18 UTC (permalink / raw)
To: u-boot
Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff800000 CPU virtual address.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm/mach-bcm283x/Kconfig | 1 +
arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
include/configs/rpi.h | 7 +++++++
4 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 00419bf..bcb7f1d 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+ select PHYS_64BIT
config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae398..4ccaf69 100644
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -8,4 +8,12 @@
extern unsigned long rpi_bcm283x_base;
+#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#include <addr_map.h>
+#define phys_to_virt addrmap_phys_to_virt
+#define virt_to_phys addrmap_virt_to_phys
+#endif
+#endif
+
#endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9f5bca3..008b312 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -145,6 +145,26 @@ int mach_cpu_init(void)
}
#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
+#include <addr_map.h>
+
+void init_addr_map(void)
+{
+ mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+ DCACHE_OFF);
+
+ /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+ addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
+ /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+ addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
+}
+#endif
+
void enable_caches(void)
{
dcache_enable();
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index b53a4b6..296e8ee 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -63,6 +63,13 @@
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#endif
+#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 2
+#endif
+#endif
+
/* Devices */
/* GPIO */
#define CONFIG_BCM2835_GPIO
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
2020-05-18 13:18 ` [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Marek Szyprowski
@ 2020-05-18 22:38 ` Simon Glass
2020-05-19 12:00 ` Marek Szyprowski
0 siblings, 1 reply; 11+ messages in thread
From: Simon Glass @ 2020-05-18 22:38 UTC (permalink / raw)
To: u-boot
Hi Marek,
On Mon, 18 May 2020 at 07:18, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>
> Create a non-cacheable mapping for the 0x600000000 physical memory region,
> where MMIO registers for the PCIe XHCI controller are instantiated by the
> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
> 32bit mode, this region is mapped at 0xff800000 CPU virtual address.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> arch/arm/mach-bcm283x/Kconfig | 1 +
> arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
> arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
> include/configs/rpi.h | 7 +++++++
> 4 files changed, 36 insertions(+)
>
> diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
> index 00419bf..bcb7f1d 100644
> --- a/arch/arm/mach-bcm283x/Kconfig
> +++ b/arch/arm/mach-bcm283x/Kconfig
> @@ -36,6 +36,7 @@ config BCM2711_32B
> select BCM2711
> select ARMV7_LPAE
> select CPU_V7A
> + select PHYS_64BIT
>
> config BCM2711_64B
> bool "Broadcom BCM2711 SoC 64-bit support"
> diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
> index c4ae398..4ccaf69 100644
> --- a/arch/arm/mach-bcm283x/include/mach/base.h
> +++ b/arch/arm/mach-bcm283x/include/mach/base.h
> @@ -8,4 +8,12 @@
>
> extern unsigned long rpi_bcm283x_base;
>
> +#ifdef CONFIG_ARMV7_LPAE
> +#ifdef CONFIG_TARGET_RPI_4_32B
> +#include <addr_map.h>
> +#define phys_to_virt addrmap_phys_to_virt
> +#define virt_to_phys addrmap_virt_to_phys
> +#endif
> +#endif
> +
> #endif
> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
> index 9f5bca3..008b312 100644
> --- a/arch/arm/mach-bcm283x/init.c
> +++ b/arch/arm/mach-bcm283x/init.c
> @@ -145,6 +145,26 @@ int mach_cpu_init(void)
> }
>
> #ifdef CONFIG_ARMV7_LPAE
> +#ifdef CONFIG_TARGET_RPI_4_32B
> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
> +#include <addr_map.h>
> +
> +void init_addr_map(void)
> +{
> + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
> + DCACHE_OFF);
> +
> + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
> + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
> + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
> + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
> +}
> +#endif
> +
> void enable_caches(void)
> {
> dcache_enable();
> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
> index b53a4b6..296e8ee 100644
> --- a/include/configs/rpi.h
> +++ b/include/configs/rpi.h
> @@ -63,6 +63,13 @@
> #define CONFIG_SYS_BOOTM_LEN SZ_64M
> #endif
>
> +#ifdef CONFIG_ARMV7_LPAE
> +#ifdef CONFIG_TARGET_RPI_4_32B
> +#define CONFIG_ADDR_MAP 1
> +#define CONFIG_SYS_NUM_ADDR_MAP 2
> +#endif
> +#endif
We should be removing things from the config files. Can you move this
to devicetree or Kconfig?
> +
> /* Devices */
> /* GPIO */
> #define CONFIG_BCM2835_GPIO
> --
> 1.9.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
2020-05-18 22:38 ` Simon Glass
@ 2020-05-19 12:00 ` Marek Szyprowski
2020-05-19 16:47 ` Simon Glass
0 siblings, 1 reply; 11+ messages in thread
From: Marek Szyprowski @ 2020-05-19 12:00 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 19.05.2020 00:38, Simon Glass wrote:
> On Mon, 18 May 2020 at 07:18, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>> Create a non-cacheable mapping for the 0x600000000 physical memory region,
>> where MMIO registers for the PCIe XHCI controller are instantiated by the
>> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
>> 32bit mode, this region is mapped at 0xff800000 CPU virtual address.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>> arch/arm/mach-bcm283x/Kconfig | 1 +
>> arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
>> arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
>> include/configs/rpi.h | 7 +++++++
>> 4 files changed, 36 insertions(+)
>>
>> diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
>> index 00419bf..bcb7f1d 100644
>> --- a/arch/arm/mach-bcm283x/Kconfig
>> +++ b/arch/arm/mach-bcm283x/Kconfig
>> @@ -36,6 +36,7 @@ config BCM2711_32B
>> select BCM2711
>> select ARMV7_LPAE
>> select CPU_V7A
>> + select PHYS_64BIT
>>
>> config BCM2711_64B
>> bool "Broadcom BCM2711 SoC 64-bit support"
>> diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
>> index c4ae398..4ccaf69 100644
>> --- a/arch/arm/mach-bcm283x/include/mach/base.h
>> +++ b/arch/arm/mach-bcm283x/include/mach/base.h
>> @@ -8,4 +8,12 @@
>>
>> extern unsigned long rpi_bcm283x_base;
>>
>> +#ifdef CONFIG_ARMV7_LPAE
>> +#ifdef CONFIG_TARGET_RPI_4_32B
>> +#include <addr_map.h>
>> +#define phys_to_virt addrmap_phys_to_virt
>> +#define virt_to_phys addrmap_virt_to_phys
>> +#endif
>> +#endif
>> +
>> #endif
>> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
>> index 9f5bca3..008b312 100644
>> --- a/arch/arm/mach-bcm283x/init.c
>> +++ b/arch/arm/mach-bcm283x/init.c
>> @@ -145,6 +145,26 @@ int mach_cpu_init(void)
>> }
>>
>> #ifdef CONFIG_ARMV7_LPAE
>> +#ifdef CONFIG_TARGET_RPI_4_32B
>> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
>> +#include <addr_map.h>
>> +
>> +void init_addr_map(void)
>> +{
>> + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
>> + DCACHE_OFF);
>> +
>> + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
>> + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
>> + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
>> + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
>> +}
>> +#endif
>> +
>> void enable_caches(void)
>> {
>> dcache_enable();
>> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
>> index b53a4b6..296e8ee 100644
>> --- a/include/configs/rpi.h
>> +++ b/include/configs/rpi.h
>> @@ -63,6 +63,13 @@
>> #define CONFIG_SYS_BOOTM_LEN SZ_64M
>> #endif
>>
>> +#ifdef CONFIG_ARMV7_LPAE
>> +#ifdef CONFIG_TARGET_RPI_4_32B
>> +#define CONFIG_ADDR_MAP 1
>> +#define CONFIG_SYS_NUM_ADDR_MAP 2
>> +#endif
>> +#endif
> We should be removing things from the config files. Can you move this
> to devicetree or Kconfig?
I can move them to Kconfig, no problem. However I would like to get some
comments if the approach I presented in this patchset is fine.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
2020-05-19 12:00 ` Marek Szyprowski
@ 2020-05-19 16:47 ` Simon Glass
2020-05-22 5:56 ` Marek Szyprowski
0 siblings, 1 reply; 11+ messages in thread
From: Simon Glass @ 2020-05-19 16:47 UTC (permalink / raw)
To: u-boot
Hi Marek,
On Tue, 19 May 2020 at 06:00, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>
> Hi Simon,
>
> On 19.05.2020 00:38, Simon Glass wrote:
> > On Mon, 18 May 2020 at 07:18, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >> Create a non-cacheable mapping for the 0x600000000 physical memory region,
> >> where MMIO registers for the PCIe XHCI controller are instantiated by the
> >> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
> >> 32bit mode, this region is mapped at 0xff800000 CPU virtual address.
> >>
> >> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> >> ---
> >> arch/arm/mach-bcm283x/Kconfig | 1 +
> >> arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
> >> arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
> >> include/configs/rpi.h | 7 +++++++
> >> 4 files changed, 36 insertions(+)
> >>
> >> diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
> >> index 00419bf..bcb7f1d 100644
> >> --- a/arch/arm/mach-bcm283x/Kconfig
> >> +++ b/arch/arm/mach-bcm283x/Kconfig
> >> @@ -36,6 +36,7 @@ config BCM2711_32B
> >> select BCM2711
> >> select ARMV7_LPAE
> >> select CPU_V7A
> >> + select PHYS_64BIT
> >>
> >> config BCM2711_64B
> >> bool "Broadcom BCM2711 SoC 64-bit support"
> >> diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
> >> index c4ae398..4ccaf69 100644
> >> --- a/arch/arm/mach-bcm283x/include/mach/base.h
> >> +++ b/arch/arm/mach-bcm283x/include/mach/base.h
> >> @@ -8,4 +8,12 @@
> >>
> >> extern unsigned long rpi_bcm283x_base;
> >>
> >> +#ifdef CONFIG_ARMV7_LPAE
> >> +#ifdef CONFIG_TARGET_RPI_4_32B
> >> +#include <addr_map.h>
> >> +#define phys_to_virt addrmap_phys_to_virt
> >> +#define virt_to_phys addrmap_virt_to_phys
> >> +#endif
> >> +#endif
> >> +
> >> #endif
> >> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
> >> index 9f5bca3..008b312 100644
> >> --- a/arch/arm/mach-bcm283x/init.c
> >> +++ b/arch/arm/mach-bcm283x/init.c
> >> @@ -145,6 +145,26 @@ int mach_cpu_init(void)
> >> }
> >>
> >> #ifdef CONFIG_ARMV7_LPAE
> >> +#ifdef CONFIG_TARGET_RPI_4_32B
> >> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
> >> +#include <addr_map.h>
> >> +
> >> +void init_addr_map(void)
> >> +{
> >> + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
> >> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
> >> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
> >> + DCACHE_OFF);
> >> +
> >> + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
> >> + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
> >> + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
> >> + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
> >> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
> >> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
> >> +}
> >> +#endif
> >> +
> >> void enable_caches(void)
> >> {
> >> dcache_enable();
> >> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
> >> index b53a4b6..296e8ee 100644
> >> --- a/include/configs/rpi.h
> >> +++ b/include/configs/rpi.h
> >> @@ -63,6 +63,13 @@
> >> #define CONFIG_SYS_BOOTM_LEN SZ_64M
> >> #endif
> >>
> >> +#ifdef CONFIG_ARMV7_LPAE
> >> +#ifdef CONFIG_TARGET_RPI_4_32B
> >> +#define CONFIG_ADDR_MAP 1
> >> +#define CONFIG_SYS_NUM_ADDR_MAP 2
> >> +#endif
> >> +#endif
> > We should be removing things from the config files. Can you move this
> > to devicetree or Kconfig?
>
> I can move them to Kconfig, no problem. However I would like to get some
> comments if the approach I presented in this patchset is fine.
Yes, no problem.
I suspect we may need to expand the DMA drivers, perhaps, or some
other way to map memory on a per-device basis using driver model.
Regards,
SImon
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
2020-05-19 16:47 ` Simon Glass
@ 2020-05-22 5:56 ` Marek Szyprowski
2020-05-22 13:42 ` Simon Glass
0 siblings, 1 reply; 11+ messages in thread
From: Marek Szyprowski @ 2020-05-22 5:56 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 19.05.2020 18:47, Simon Glass wrote:
> On Tue, 19 May 2020 at 06:00, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>> On 19.05.2020 00:38, Simon Glass wrote:
>>> On Mon, 18 May 2020 at 07:18, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>>>> Create a non-cacheable mapping for the 0x600000000 physical memory region,
>>>> where MMIO registers for the PCIe XHCI controller are instantiated by the
>>>> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
>>>> 32bit mode, this region is mapped at 0xff800000 CPU virtual address.
>>>>
>>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>>> ---
>>>> arch/arm/mach-bcm283x/Kconfig | 1 +
>>>> arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
>>>> arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
>>>> include/configs/rpi.h | 7 +++++++
>>>> 4 files changed, 36 insertions(+)
>>>>
>>>> diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
>>>> index 00419bf..bcb7f1d 100644
>>>> --- a/arch/arm/mach-bcm283x/Kconfig
>>>> +++ b/arch/arm/mach-bcm283x/Kconfig
>>>> @@ -36,6 +36,7 @@ config BCM2711_32B
>>>> select BCM2711
>>>> select ARMV7_LPAE
>>>> select CPU_V7A
>>>> + select PHYS_64BIT
>>>>
>>>> config BCM2711_64B
>>>> bool "Broadcom BCM2711 SoC 64-bit support"
>>>> diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
>>>> index c4ae398..4ccaf69 100644
>>>> --- a/arch/arm/mach-bcm283x/include/mach/base.h
>>>> +++ b/arch/arm/mach-bcm283x/include/mach/base.h
>>>> @@ -8,4 +8,12 @@
>>>>
>>>> extern unsigned long rpi_bcm283x_base;
>>>>
>>>> +#ifdef CONFIG_ARMV7_LPAE
>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
>>>> +#include <addr_map.h>
>>>> +#define phys_to_virt addrmap_phys_to_virt
>>>> +#define virt_to_phys addrmap_virt_to_phys
>>>> +#endif
>>>> +#endif
>>>> +
>>>> #endif
>>>> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
>>>> index 9f5bca3..008b312 100644
>>>> --- a/arch/arm/mach-bcm283x/init.c
>>>> +++ b/arch/arm/mach-bcm283x/init.c
>>>> @@ -145,6 +145,26 @@ int mach_cpu_init(void)
>>>> }
>>>>
>>>> #ifdef CONFIG_ARMV7_LPAE
>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
>>>> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
>>>> +#include <addr_map.h>
>>>> +
>>>> +void init_addr_map(void)
>>>> +{
>>>> + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
>>>> + DCACHE_OFF);
>>>> +
>>>> + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
>>>> + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
>>>> + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
>>>> + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
>>>> +}
>>>> +#endif
>>>> +
>>>> void enable_caches(void)
>>>> {
>>>> dcache_enable();
>>>> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
>>>> index b53a4b6..296e8ee 100644
>>>> --- a/include/configs/rpi.h
>>>> +++ b/include/configs/rpi.h
>>>> @@ -63,6 +63,13 @@
>>>> #define CONFIG_SYS_BOOTM_LEN SZ_64M
>>>> #endif
>>>>
>>>> +#ifdef CONFIG_ARMV7_LPAE
>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
>>>> +#define CONFIG_ADDR_MAP 1
>>>> +#define CONFIG_SYS_NUM_ADDR_MAP 2
>>>> +#endif
>>>> +#endif
>>> We should be removing things from the config files. Can you move this
>>> to devicetree or Kconfig?
>> I can move them to Kconfig, no problem. However I would like to get some
>> comments if the approach I presented in this patchset is fine.
> Yes, no problem.
>
> I suspect we may need to expand the DMA drivers, perhaps, or some
> other way to map memory on a per-device basis using driver model.
I'm not sure that we really need such a complex solution. Usually the
board (or even SoC), if ever, needs one or two such non-identity
mappings, which can be easily created by the respective init code. The
PowerPC case mentioned here looks a bit different, because it simply
copies the mappings already configured in the CPU registers by the
earlier firmware. Anyway, I don't think that we would ever need to
manage physical/virtual mapping dynamically in the u-boot. All that
cover current (and most future?) cases would be a simple function to map
an arbitrary physical address at the predefined virtual one.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
2020-05-22 5:56 ` Marek Szyprowski
@ 2020-05-22 13:42 ` Simon Glass
2020-05-25 10:48 ` Marek Szyprowski
0 siblings, 1 reply; 11+ messages in thread
From: Simon Glass @ 2020-05-22 13:42 UTC (permalink / raw)
To: u-boot
Hi Marek,
On Thu, 21 May 2020 at 23:56, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>
> Hi Simon,
>
> On 19.05.2020 18:47, Simon Glass wrote:
> > On Tue, 19 May 2020 at 06:00, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >> On 19.05.2020 00:38, Simon Glass wrote:
> >>> On Mon, 18 May 2020 at 07:18, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >>>> Create a non-cacheable mapping for the 0x600000000 physical memory region,
> >>>> where MMIO registers for the PCIe XHCI controller are instantiated by the
> >>>> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
> >>>> 32bit mode, this region is mapped at 0xff800000 CPU virtual address.
> >>>>
> >>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> >>>> ---
> >>>> arch/arm/mach-bcm283x/Kconfig | 1 +
> >>>> arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
> >>>> arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
> >>>> include/configs/rpi.h | 7 +++++++
> >>>> 4 files changed, 36 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
> >>>> index 00419bf..bcb7f1d 100644
> >>>> --- a/arch/arm/mach-bcm283x/Kconfig
> >>>> +++ b/arch/arm/mach-bcm283x/Kconfig
> >>>> @@ -36,6 +36,7 @@ config BCM2711_32B
> >>>> select BCM2711
> >>>> select ARMV7_LPAE
> >>>> select CPU_V7A
> >>>> + select PHYS_64BIT
> >>>>
> >>>> config BCM2711_64B
> >>>> bool "Broadcom BCM2711 SoC 64-bit support"
> >>>> diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
> >>>> index c4ae398..4ccaf69 100644
> >>>> --- a/arch/arm/mach-bcm283x/include/mach/base.h
> >>>> +++ b/arch/arm/mach-bcm283x/include/mach/base.h
> >>>> @@ -8,4 +8,12 @@
> >>>>
> >>>> extern unsigned long rpi_bcm283x_base;
> >>>>
> >>>> +#ifdef CONFIG_ARMV7_LPAE
> >>>> +#ifdef CONFIG_TARGET_RPI_4_32B
> >>>> +#include <addr_map.h>
> >>>> +#define phys_to_virt addrmap_phys_to_virt
> >>>> +#define virt_to_phys addrmap_virt_to_phys
> >>>> +#endif
> >>>> +#endif
> >>>> +
> >>>> #endif
> >>>> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
> >>>> index 9f5bca3..008b312 100644
> >>>> --- a/arch/arm/mach-bcm283x/init.c
> >>>> +++ b/arch/arm/mach-bcm283x/init.c
> >>>> @@ -145,6 +145,26 @@ int mach_cpu_init(void)
> >>>> }
> >>>>
> >>>> #ifdef CONFIG_ARMV7_LPAE
> >>>> +#ifdef CONFIG_TARGET_RPI_4_32B
> >>>> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
> >>>> +#include <addr_map.h>
> >>>> +
> >>>> +void init_addr_map(void)
> >>>> +{
> >>>> + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
> >>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
> >>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
> >>>> + DCACHE_OFF);
> >>>> +
> >>>> + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
> >>>> + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
> >>>> + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
> >>>> + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
> >>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
> >>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
> >>>> +}
> >>>> +#endif
> >>>> +
> >>>> void enable_caches(void)
> >>>> {
> >>>> dcache_enable();
> >>>> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
> >>>> index b53a4b6..296e8ee 100644
> >>>> --- a/include/configs/rpi.h
> >>>> +++ b/include/configs/rpi.h
> >>>> @@ -63,6 +63,13 @@
> >>>> #define CONFIG_SYS_BOOTM_LEN SZ_64M
> >>>> #endif
> >>>>
> >>>> +#ifdef CONFIG_ARMV7_LPAE
> >>>> +#ifdef CONFIG_TARGET_RPI_4_32B
> >>>> +#define CONFIG_ADDR_MAP 1
> >>>> +#define CONFIG_SYS_NUM_ADDR_MAP 2
> >>>> +#endif
> >>>> +#endif
> >>> We should be removing things from the config files. Can you move this
> >>> to devicetree or Kconfig?
> >> I can move them to Kconfig, no problem. However I would like to get some
> >> comments if the approach I presented in this patchset is fine.
> > Yes, no problem.
> >
> > I suspect we may need to expand the DMA drivers, perhaps, or some
> > other way to map memory on a per-device basis using driver model.
>
> I'm not sure that we really need such a complex solution. Usually the
> board (or even SoC), if ever, needs one or two such non-identity
> mappings, which can be easily created by the respective init code. The
> PowerPC case mentioned here looks a bit different, because it simply
> copies the mappings already configured in the CPU registers by the
> earlier firmware. Anyway, I don't think that we would ever need to
> manage physical/virtual mapping dynamically in the u-boot. All that
> cover current (and most future?) cases would be a simple function to map
> an arbitrary physical address at the predefined virtual one.
OK, well see how you go. When I see CONFIG options that specify values
I often think there should be a driver and device-tree node. We can
see how things go in the future as to whether we need a driver.
Regards,
Simon
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
2020-05-22 13:42 ` Simon Glass
@ 2020-05-25 10:48 ` Marek Szyprowski
2020-05-25 14:57 ` Simon Glass
0 siblings, 1 reply; 11+ messages in thread
From: Marek Szyprowski @ 2020-05-25 10:48 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 22.05.2020 15:42, Simon Glass wrote:
> On Thu, 21 May 2020 at 23:56, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>> On 19.05.2020 18:47, Simon Glass wrote:
>>> On Tue, 19 May 2020 at 06:00, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>>>> On 19.05.2020 00:38, Simon Glass wrote:
>>>>> On Mon, 18 May 2020 at 07:18, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>>>>>> Create a non-cacheable mapping for the 0x600000000 physical memory region,
>>>>>> where MMIO registers for the PCIe XHCI controller are instantiated by the
>>>>>> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
>>>>>> 32bit mode, this region is mapped at 0xff800000 CPU virtual address.
>>>>>>
>>>>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>>>>> ---
>>>>>> arch/arm/mach-bcm283x/Kconfig | 1 +
>>>>>> arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
>>>>>> arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
>>>>>> include/configs/rpi.h | 7 +++++++
>>>>>> 4 files changed, 36 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
>>>>>> index 00419bf..bcb7f1d 100644
>>>>>> --- a/arch/arm/mach-bcm283x/Kconfig
>>>>>> +++ b/arch/arm/mach-bcm283x/Kconfig
>>>>>> @@ -36,6 +36,7 @@ config BCM2711_32B
>>>>>> select BCM2711
>>>>>> select ARMV7_LPAE
>>>>>> select CPU_V7A
>>>>>> + select PHYS_64BIT
>>>>>>
>>>>>> config BCM2711_64B
>>>>>> bool "Broadcom BCM2711 SoC 64-bit support"
>>>>>> diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
>>>>>> index c4ae398..4ccaf69 100644
>>>>>> --- a/arch/arm/mach-bcm283x/include/mach/base.h
>>>>>> +++ b/arch/arm/mach-bcm283x/include/mach/base.h
>>>>>> @@ -8,4 +8,12 @@
>>>>>>
>>>>>> extern unsigned long rpi_bcm283x_base;
>>>>>>
>>>>>> +#ifdef CONFIG_ARMV7_LPAE
>>>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
>>>>>> +#include <addr_map.h>
>>>>>> +#define phys_to_virt addrmap_phys_to_virt
>>>>>> +#define virt_to_phys addrmap_virt_to_phys
>>>>>> +#endif
>>>>>> +#endif
>>>>>> +
>>>>>> #endif
>>>>>> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
>>>>>> index 9f5bca3..008b312 100644
>>>>>> --- a/arch/arm/mach-bcm283x/init.c
>>>>>> +++ b/arch/arm/mach-bcm283x/init.c
>>>>>> @@ -145,6 +145,26 @@ int mach_cpu_init(void)
>>>>>> }
>>>>>>
>>>>>> #ifdef CONFIG_ARMV7_LPAE
>>>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
>>>>>> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
>>>>>> +#include <addr_map.h>
>>>>>> +
>>>>>> +void init_addr_map(void)
>>>>>> +{
>>>>>> + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
>>>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
>>>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
>>>>>> + DCACHE_OFF);
>>>>>> +
>>>>>> + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
>>>>>> + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
>>>>>> + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
>>>>>> + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
>>>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
>>>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
>>>>>> +}
>>>>>> +#endif
>>>>>> +
>>>>>> void enable_caches(void)
>>>>>> {
>>>>>> dcache_enable();
>>>>>> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
>>>>>> index b53a4b6..296e8ee 100644
>>>>>> --- a/include/configs/rpi.h
>>>>>> +++ b/include/configs/rpi.h
>>>>>> @@ -63,6 +63,13 @@
>>>>>> #define CONFIG_SYS_BOOTM_LEN SZ_64M
>>>>>> #endif
>>>>>>
>>>>>> +#ifdef CONFIG_ARMV7_LPAE
>>>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
>>>>>> +#define CONFIG_ADDR_MAP 1
>>>>>> +#define CONFIG_SYS_NUM_ADDR_MAP 2
>>>>>> +#endif
>>>>>> +#endif
>>>>> We should be removing things from the config files. Can you move this
>>>>> to devicetree or Kconfig?
>>>> I can move them to Kconfig, no problem. However I would like to get some
>>>> comments if the approach I presented in this patchset is fine.
>>> Yes, no problem.
>>>
>>> I suspect we may need to expand the DMA drivers, perhaps, or some
>>> other way to map memory on a per-device basis using driver model.
>> I'm not sure that we really need such a complex solution. Usually the
>> board (or even SoC), if ever, needs one or two such non-identity
>> mappings, which can be easily created by the respective init code. The
>> PowerPC case mentioned here looks a bit different, because it simply
>> copies the mappings already configured in the CPU registers by the
>> earlier firmware. Anyway, I don't think that we would ever need to
>> manage physical/virtual mapping dynamically in the u-boot. All that
>> cover current (and most future?) cases would be a simple function to map
>> an arbitrary physical address at the predefined virtual one.
> OK, well see how you go. When I see CONFIG options that specify values
> I often think there should be a driver and device-tree node. We can
> see how things go in the future as to whether we need a driver.
In this case (CONFIG_ADDR_MAP) the values provided by the board's
config.h (CONFIG_SYS_NUM_ADDR_MAP) only allows the code to use a simple
static array instead of allocating things dynamically. It has no
relation to the drivers nor device-tree.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
2020-05-25 10:48 ` Marek Szyprowski
@ 2020-05-25 14:57 ` Simon Glass
0 siblings, 0 replies; 11+ messages in thread
From: Simon Glass @ 2020-05-25 14:57 UTC (permalink / raw)
To: u-boot
Hi Marek,
On Mon, 25 May 2020 at 04:48, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>
> Hi Simon,
>
> On 22.05.2020 15:42, Simon Glass wrote:
> > On Thu, 21 May 2020 at 23:56, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >> On 19.05.2020 18:47, Simon Glass wrote:
> >>> On Tue, 19 May 2020 at 06:00, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >>>> On 19.05.2020 00:38, Simon Glass wrote:
> >>>>> On Mon, 18 May 2020 at 07:18, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >>>>>> Create a non-cacheable mapping for the 0x600000000 physical memory region,
> >>>>>> where MMIO registers for the PCIe XHCI controller are instantiated by the
> >>>>>> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
> >>>>>> 32bit mode, this region is mapped at 0xff800000 CPU virtual address.
> >>>>>>
> >>>>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> >>>>>> ---
> >>>>>> arch/arm/mach-bcm283x/Kconfig | 1 +
> >>>>>> arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
> >>>>>> arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++++
> >>>>>> include/configs/rpi.h | 7 +++++++
> >>>>>> 4 files changed, 36 insertions(+)
> >>>>>>
> >>>>>> diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
> >>>>>> index 00419bf..bcb7f1d 100644
> >>>>>> --- a/arch/arm/mach-bcm283x/Kconfig
> >>>>>> +++ b/arch/arm/mach-bcm283x/Kconfig
> >>>>>> @@ -36,6 +36,7 @@ config BCM2711_32B
> >>>>>> select BCM2711
> >>>>>> select ARMV7_LPAE
> >>>>>> select CPU_V7A
> >>>>>> + select PHYS_64BIT
> >>>>>>
> >>>>>> config BCM2711_64B
> >>>>>> bool "Broadcom BCM2711 SoC 64-bit support"
> >>>>>> diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
> >>>>>> index c4ae398..4ccaf69 100644
> >>>>>> --- a/arch/arm/mach-bcm283x/include/mach/base.h
> >>>>>> +++ b/arch/arm/mach-bcm283x/include/mach/base.h
> >>>>>> @@ -8,4 +8,12 @@
> >>>>>>
> >>>>>> extern unsigned long rpi_bcm283x_base;
> >>>>>>
> >>>>>> +#ifdef CONFIG_ARMV7_LPAE
> >>>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
> >>>>>> +#include <addr_map.h>
> >>>>>> +#define phys_to_virt addrmap_phys_to_virt
> >>>>>> +#define virt_to_phys addrmap_virt_to_phys
> >>>>>> +#endif
> >>>>>> +#endif
> >>>>>> +
> >>>>>> #endif
> >>>>>> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
> >>>>>> index 9f5bca3..008b312 100644
> >>>>>> --- a/arch/arm/mach-bcm283x/init.c
> >>>>>> +++ b/arch/arm/mach-bcm283x/init.c
> >>>>>> @@ -145,6 +145,26 @@ int mach_cpu_init(void)
> >>>>>> }
> >>>>>>
> >>>>>> #ifdef CONFIG_ARMV7_LPAE
> >>>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
> >>>>>> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
> >>>>>> +#include <addr_map.h>
> >>>>>> +
> >>>>>> +void init_addr_map(void)
> >>>>>> +{
> >>>>>> + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
> >>>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
> >>>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
> >>>>>> + DCACHE_OFF);
> >>>>>> +
> >>>>>> + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
> >>>>>> + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
> >>>>>> + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
> >>>>>> + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
> >>>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
> >>>>>> + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
> >>>>>> +}
> >>>>>> +#endif
> >>>>>> +
> >>>>>> void enable_caches(void)
> >>>>>> {
> >>>>>> dcache_enable();
> >>>>>> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
> >>>>>> index b53a4b6..296e8ee 100644
> >>>>>> --- a/include/configs/rpi.h
> >>>>>> +++ b/include/configs/rpi.h
> >>>>>> @@ -63,6 +63,13 @@
> >>>>>> #define CONFIG_SYS_BOOTM_LEN SZ_64M
> >>>>>> #endif
> >>>>>>
> >>>>>> +#ifdef CONFIG_ARMV7_LPAE
> >>>>>> +#ifdef CONFIG_TARGET_RPI_4_32B
> >>>>>> +#define CONFIG_ADDR_MAP 1
> >>>>>> +#define CONFIG_SYS_NUM_ADDR_MAP 2
> >>>>>> +#endif
> >>>>>> +#endif
> >>>>> We should be removing things from the config files. Can you move this
> >>>>> to devicetree or Kconfig?
> >>>> I can move them to Kconfig, no problem. However I would like to get some
> >>>> comments if the approach I presented in this patchset is fine.
> >>> Yes, no problem.
> >>>
> >>> I suspect we may need to expand the DMA drivers, perhaps, or some
> >>> other way to map memory on a per-device basis using driver model.
> >> I'm not sure that we really need such a complex solution. Usually the
> >> board (or even SoC), if ever, needs one or two such non-identity
> >> mappings, which can be easily created by the respective init code. The
> >> PowerPC case mentioned here looks a bit different, because it simply
> >> copies the mappings already configured in the CPU registers by the
> >> earlier firmware. Anyway, I don't think that we would ever need to
> >> manage physical/virtual mapping dynamically in the u-boot. All that
> >> cover current (and most future?) cases would be a simple function to map
> >> an arbitrary physical address at the predefined virtual one.
> > OK, well see how you go. When I see CONFIG options that specify values
> > I often think there should be a driver and device-tree node. We can
> > see how things go in the future as to whether we need a driver.
> In this case (CONFIG_ADDR_MAP) the values provided by the board's
> config.h (CONFIG_SYS_NUM_ADDR_MAP) only allows the code to use a simple
> static array instead of allocating things dynamically. It has no
> relation to the drivers nor device-tree.
We are working to remove the board config.h files and move everything
to Kconfig.
If there really is no need for a driver here, then we could perhaps
use a weak function for the interface? (Tom, note :-)
Regards,
Simon
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-05-25 14:57 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <CGME20200518131814eucas1p18b2f895c127708ac6b55b033fb7a43d2@eucas1p1.samsung.com>
2020-05-18 13:17 ` [RFC PATCH v3 0/3] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support Marek Szyprowski
[not found] ` <CGME20200518131816eucas1p1aa84fb661559b858fd976d414212c254@eucas1p1.samsung.com>
2020-05-18 13:17 ` [RFC PATCH v3 1/3] arm: provide a function for boards init code to modify MMU virtual-physical map Marek Szyprowski
[not found] ` <CGME20200518131816eucas1p2344d0e25b136ee0d2f07517af488358e@eucas1p2.samsung.com>
2020-05-18 13:18 ` [RFC PATCH v3 2/3] mmc: bcm283x: fix int to pointer cast Marek Szyprowski
[not found] ` <CGME20200518131817eucas1p16d37a356ad7f18a9a0f75ccbe9663905@eucas1p1.samsung.com>
2020-05-18 13:18 ` [RFC PATCH v3 3/3] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Marek Szyprowski
2020-05-18 22:38 ` Simon Glass
2020-05-19 12:00 ` Marek Szyprowski
2020-05-19 16:47 ` Simon Glass
2020-05-22 5:56 ` Marek Szyprowski
2020-05-22 13:42 ` Simon Glass
2020-05-25 10:48 ` Marek Szyprowski
2020-05-25 14:57 ` Simon Glass
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