* [U-Boot] [PATCH v2] arm: cache: always flush cache line size for page table
@ 2016-08-04 5:41 Stefan Agner
2016-08-05 1:31 ` Fabio Estevam
2016-08-05 1:34 ` Simon Glass
0 siblings, 2 replies; 3+ messages in thread
From: Stefan Agner @ 2016-08-04 5:41 UTC (permalink / raw)
To: u-boot
From: Stefan Agner <stefan.agner@toradex.com>
The page table is maintained by the CPU, hence it is safe to always
align cache flush to a whole cache line size. This allows to use
mmu_page_table_flush for a single page table, e.g. when configure
only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---
Changes since v1:
- Move cache line alignment from mmu_page_table_flush to
mmu_set_region_dcache_behaviour
arch/arm/lib/cache-cp15.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1121dc3..bf79edd 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -62,6 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
u32 *page_table = (u32 *)gd->arch.tlb_addr;
+ phys_addr_t startpt, stoppt;
unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
@@ -70,7 +71,17 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
option);
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
- mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+
+ /*
+ * Make sure range is cache line aligned
+ * Only CPU maintains page tables, hence it is save to always
+ * flush complete cache lines...
+ */
+ startpt = (phys_addr_t)&page_table[start];
+ startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ stoppt = (phys_addr_t)&page_table[end];
+ stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+ mmu_page_table_flush(startpt, stoppt);
}
__weak void dram_bank_mmu_setup(int bank)
--
2.9.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v2] arm: cache: always flush cache line size for page table
2016-08-04 5:41 [U-Boot] [PATCH v2] arm: cache: always flush cache line size for page table Stefan Agner
@ 2016-08-05 1:31 ` Fabio Estevam
2016-08-05 1:34 ` Simon Glass
1 sibling, 0 replies; 3+ messages in thread
From: Fabio Estevam @ 2016-08-05 1:31 UTC (permalink / raw)
To: u-boot
Hi Stefan,
On Thu, Aug 4, 2016 at 2:41 AM, Stefan Agner <stefan@agner.ch> wrote:
> - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
> +
> + /*
> + * Make sure range is cache line aligned
> + * Only CPU maintains page tables, hence it is save to always
s/save/safe
This fixes the cache warnings on a mx7dsabresd, thanks:
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v2] arm: cache: always flush cache line size for page table
2016-08-04 5:41 [U-Boot] [PATCH v2] arm: cache: always flush cache line size for page table Stefan Agner
2016-08-05 1:31 ` Fabio Estevam
@ 2016-08-05 1:34 ` Simon Glass
1 sibling, 0 replies; 3+ messages in thread
From: Simon Glass @ 2016-08-05 1:34 UTC (permalink / raw)
To: u-boot
On 3 August 2016 at 23:41, Stefan Agner <stefan@agner.ch> wrote:
> From: Stefan Agner <stefan.agner@toradex.com>
>
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions through mmu_set_region_dcache_behaviour.
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> ---
> Changes since v1:
> - Move cache line alignment from mmu_page_table_flush to
> mmu_set_region_dcache_behaviour
>
> arch/arm/lib/cache-cp15.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2016-08-05 1:34 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2016-08-04 5:41 [U-Boot] [PATCH v2] arm: cache: always flush cache line size for page table Stefan Agner
2016-08-05 1:31 ` Fabio Estevam
2016-08-05 1:34 ` Simon Glass
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