* [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig
@ 2022-11-12 22:36 Tom Rini
2022-11-12 22:36 ` [PATCH 02/10] Remove unused symbols Tom Rini
` (10 more replies)
0 siblings, 11 replies; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This converts the following to Kconfig:
CONFIG_SYS_NAND_DBW_8
CONFIG_SYS_NAND_DBW_16
Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16
being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of
the configs set CONFIG_SYS_NAND_DBW_8. So we introduce
CONFIG_SYS_NAND_DBW_16 as an option.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/mtd/nand/raw/Kconfig | 12 ++++++++++++
include/configs/at91sam9260ek.h | 1 -
include/configs/at91sam9261ek.h | 1 -
include/configs/at91sam9263ek.h | 1 -
include/configs/at91sam9m10g45ek.h | 1 -
include/configs/at91sam9rlek.h | 1 -
include/configs/at91sam9x5ek.h | 1 -
include/configs/corvus.h | 1 -
include/configs/ethernut5.h | 1 -
include/configs/gardena-smart-gateway-at91sam.h | 1 -
include/configs/meesc.h | 1 -
include/configs/pm9261.h | 1 -
include/configs/pm9263.h | 1 -
include/configs/pm9g45.h | 1 -
include/configs/smartweb.h | 1 -
include/configs/snapper9g45.h | 1 -
include/configs/taurus.h | 1 -
17 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index da2c5795bc32..48a7507c643b 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -83,6 +83,18 @@ config SPL_GENERATE_ATMEL_PMECC_HEADER
help
Generate Programmable Multibit ECC (PMECC) header for SPL image.
+choice
+ prompt "NAND bus width (bits)"
+ default SYS_NAND_DBW_8
+
+config SYS_NAND_DBW_8
+ bool "NAND bus width is 8 bits"
+
+config SYS_NAND_DBW_16
+ bool "NAND bus width is 16 bits"
+
+endchoice
+
endif
config NAND_BRCMNAND
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index d51da9d50678..60b47379e5e2 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -44,7 +44,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 5dc8f21a8535..d80a686e9eef 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -25,7 +25,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index d31a7742a175..89a8e43e1e09 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -151,7 +151,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 01085476a430..55edd706ead9 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -21,7 +21,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index c60c248b747e..0a512c217f8e 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -26,7 +26,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 71a2863bfc2b..b8a14d571d6f 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -28,7 +28,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 0596afbf9fa2..3e7c0c0d883b 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -38,7 +38,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 22647abee0d3..a18920d3f09e 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -38,7 +38,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index 52b9fe2b1711..3d62efb38ff9 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -23,7 +23,6 @@
/* NAND flash */
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 9f913fad168f..30267e29a126 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -53,7 +53,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
-# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 278f1b5cc622..6a89fb1fa9a4 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -130,7 +130,6 @@
/* NAND flash */
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 7c23206a3006..c56db4d793d3 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -147,7 +147,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 35fd52568363..7d3a326deaf0 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -26,7 +26,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index a77215d19bec..c8f5816fed99 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -55,7 +55,6 @@
/* NAND flash settings */
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index c56fb378312b..6aba1d3194c3 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -31,7 +31,6 @@
/* NAND Flash */
#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 45780d9a4ea0..ca9616d8af5a 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -55,7 +55,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 02/10] Remove unused symbols
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 03/10] Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig Tom Rini
` (9 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This commit removes the following unused symbols:
CONFIG_SYS_NAND_DDR_LAW
CONFIG_SYS_NAND_ECCSTEPS
CONFIG_SYS_NAND_ECCTOTAL
CONFIG_SYS_NAND_ENABLE_PIN_SPL
CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
CONFIG_SYS_NAND_U_BOOT_RELOC_SP
Signed-off-by: Tom Rini <trini@konsulko.com>
---
include/configs/P1010RDB.h | 2 --
include/configs/T102xRDB.h | 1 -
include/configs/T104xRDB.h | 1 -
include/configs/T208xQDS.h | 1 -
include/configs/T208xRDB.h | 1 -
include/configs/T4240RDB.h | 1 -
include/configs/colibri_imx7.h | 1 -
include/configs/da850evm.h | 4 ----
include/configs/omapl138_lcdk.h | 4 ----
include/configs/siemens-am33x-common.h | 4 ----
include/configs/smartweb.h | 1 -
include/configs/taurus.h | 1 -
12 files changed, 22 deletions(-)
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index addb306d57fc..3448766d8e5d 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -235,8 +235,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_NAND_FTIM3 0x0
#endif
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 62c4177f3093..4b2327d32329 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -234,7 +234,6 @@
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index ad8037e7a8c7..e7d82bf4118e 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -210,7 +210,6 @@
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 2dcaeda78b8d..08195505b1dc 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -198,7 +198,6 @@
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 223c85675171..75d9200d568c 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -174,7 +174,6 @@
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 12edfdd68db0..d79789af0e1a 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -231,7 +231,6 @@
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 7380440ae7aa..5c7a9f2e69f2 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -167,7 +167,6 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
#endif
/* USB Configs */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 281cbe37f9d9..262a79be015c 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -117,10 +117,6 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
- CONFIG_SYS_NAND_U_BOOT_SIZE - \
- CONFIG_SYS_MALLOC_LEN - \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { \
24, 25, 26, 27, 28, \
29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 410393024158..4b24d614e1ad 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -116,10 +116,6 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
- CONFIG_SYS_NAND_U_BOOT_SIZE - \
- CONFIG_SYS_MALLOC_LEN - \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { \
6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 87da5e4232c2..dd247d2fd981 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -59,10 +59,6 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ECCSTEPS 4
-#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
- CONFIG_SYS_NAND_ECCSTEPS)
-
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/*
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index c8f5816fed99..538aad9a7bbb 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -92,7 +92,6 @@
/* Defines for SPL */
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index ca9616d8af5a..5ab087da8bd0 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -126,7 +126,6 @@
/* Defines for SPL */
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 03/10] Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
2022-11-12 22:36 ` [PATCH 02/10] Remove unused symbols Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 04/10] Convert CONFIG_SYS_NAND_HW_ECC " Tom Rini
` (8 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This converts the following to Kconfig:
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Signed-off-by: Tom Rini <trini@konsulko.com>
---
README | 4 ----
configs/da850evm_nand_defconfig | 1 +
configs/omapl138_lcdk_defconfig | 1 +
drivers/mtd/nand/raw/Kconfig | 5 +++++
include/configs/da850evm.h | 1 -
include/configs/omapl138_lcdk.h | 1 -
6 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/README b/README
index d75c3fbc8596..4309d9338664 100644
--- a/README
+++ b/README
@@ -1378,10 +1378,6 @@ The following options need to be configured:
CONFIG_SYS_NAND_U_BOOT_START
Entry point in loaded image to jump to
- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
- Define this if you need to first read the OOB and then the
- data. This is used, for example, on davinci platforms.
-
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 30454a3787a9..84563b2a3c7f 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -87,6 +87,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
+CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 51c78dc51ad5..a067c0177940 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -84,6 +84,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
+CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 48a7507c643b..49b7a4b04bb4 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -712,6 +712,11 @@ config SPL_NAND_SIMPLE
help
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
+
+config SYS_NAND_HW_ECC_OOBFIRST
+ bool "In SPL, read the OOB first and then the data from NAND"
+ depends on SPL_NAND_SIMPLE
+
endif
endif # if NAND
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 262a79be015c..abf5db934c50 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -113,7 +113,6 @@
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 4b24d614e1ad..184360f7e900 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -111,7 +111,6 @@
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 04/10] Convert CONFIG_SYS_NAND_HW_ECC to Kconfig
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
2022-11-12 22:36 ` [PATCH 02/10] Remove unused symbols Tom Rini
2022-11-12 22:36 ` [PATCH 03/10] Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 05/10] mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly Tom Rini
` (7 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This converts the following to Kconfig:
CONFIG_SYS_NAND_HW_ECC
Signed-off-by: Tom Rini <trini@konsulko.com>
---
configs/da850evm_nand_defconfig | 1 -
configs/k2e_evm_defconfig | 1 -
configs/k2e_hs_evm_defconfig | 1 -
configs/k2hk_evm_defconfig | 1 -
configs/k2hk_hs_evm_defconfig | 1 -
configs/k2l_evm_defconfig | 1 -
configs/k2l_hs_evm_defconfig | 1 -
configs/omapl138_lcdk_defconfig | 1 -
drivers/mtd/nand/raw/Kconfig | 14 +++++++++++++-
drivers/mtd/nand/raw/davinci_nand.c | 7 +++----
include/configs/da850evm.h | 1 -
include/configs/omapl138_lcdk.h | 1 -
12 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 84563b2a3c7f..a7aaf46ea517 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -86,7 +86,6 @@ CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 9bf2e862b063..977348e73fcc 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -79,7 +79,6 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index afa4dc1b4198..afba285ffb22 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -54,7 +54,6 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index cbf948f578ee..6c4563912b5b 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -79,7 +79,6 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 2480547a51c6..33624badae0e 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -54,7 +54,6 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index f4c8c5e233a6..e28054bcc72c 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -79,7 +79,6 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index 051cd234818f..8f8bb5491305 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -57,7 +57,6 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index a067c0177940..ff3b5f0857bf 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -83,7 +83,6 @@ CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 49b7a4b04bb4..0e428418b25d 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -148,9 +148,21 @@ config NAND_DAVINCI
Enable this driver for NAND flash controllers available in TI Davinci
and Keystone2 platforms
+choice
+ prompt "Type of ECC used on NAND"
+ default SYS_NAND_4BIT_HW_ECC_OOBFIRST
+ depends on NAND_DAVINCI
+
+config SYS_NAND_HW_ECC
+ bool "Use 1-bit HW ECC"
+
config SYS_NAND_4BIT_HW_ECC_OOBFIRST
bool "Use 4-bit HW ECC with OOB at the front"
- depends on NAND_DAVINCI
+
+config SYS_NAND_SOFT_ECC
+ bool "Use software ECC"
+
+endchoice
config KEYSTONE_RBL_NAND
depends on ARCH_KEYSTONE
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 9158d94de25a..54aed1363889 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -766,10 +766,7 @@ static void davinci_nand_init(struct nand_chip *nand)
nand->ecc.calculate = nand_davinci_calculate_ecc;
nand->ecc.correct = nand_davinci_correct_data;
nand->ecc.hwctl = nand_davinci_enable_hwecc;
-#else
- nand->ecc.mode = NAND_ECC_SOFT;
-#endif /* CONFIG_SYS_NAND_HW_ECC */
-#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#elif defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
nand->ecc.size = 512;
nand->ecc.bytes = 10;
@@ -778,6 +775,8 @@ static void davinci_nand_init(struct nand_chip *nand)
nand->ecc.correct = nand_davinci_4bit_correct_data;
nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
+#elif defined(CONFIG_SYS_NAND_SOFT_ECC)
+ nand->ecc.mode = NAND_ECC_SOFT;
#endif
/* Set address of hardware control function */
nand->cmd_ctrl = nand_davinci_hwcontrol;
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index abf5db934c50..11f104bcb86d 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -112,7 +112,6 @@
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 184360f7e900..233e7b4ee53e 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -110,7 +110,6 @@
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 05/10] mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
` (2 preceding siblings ...)
2022-11-12 22:36 ` [PATCH 04/10] Convert CONFIG_SYS_NAND_HW_ECC " Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 06/10] Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig Tom Rini
` (6 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This is the only driver, and only one platform makes use of, setting
CONFIG_SYS_NAND_ECC_BASE. Reference ATMEL_BASE_ECC directly in this
case.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/mtd/nand/raw/atmel_nand.c | 18 +++++++++---------
include/configs/snapper9g45.h | 1 -
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index 61bfd175be40..a541af6db4a4 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c
@@ -1012,13 +1012,13 @@ static int atmel_nand_calculate(struct mtd_info *mtd,
unsigned int ecc_value;
/* get the first 2 ECC bytes */
- ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
+ ecc_value = ecc_readl(ATMEL_BASE_ECC, PR);
ecc_code[0] = ecc_value & 0xFF;
ecc_code[1] = (ecc_value >> 8) & 0xFF;
/* get the last 2 ECC bytes */
- ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
+ ecc_value = ecc_readl(ATMEL_BASE_ECC, NPR) & ATMEL_ECC_NPARITY;
ecc_code[2] = ecc_value & 0xFF;
ecc_code[3] = (ecc_value >> 8) & 0xFF;
@@ -1101,16 +1101,16 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
unsigned int ecc_word, ecc_bit;
/* get the status from the Status Register */
- ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
+ ecc_status = ecc_readl(ATMEL_BASE_ECC, SR);
/* if there's no error */
if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
return 0;
/* get error bit offset (4 bits) */
- ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
+ ecc_bit = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_BITADDR;
/* get word address (12 bits) */
- ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
+ ecc_word = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_WORDADDR;
ecc_word >>= 4;
/* if there are multiple errors */
@@ -1180,22 +1180,22 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
switch (mtd->writesize) {
case 512:
nand->ecc.layout = &atmel_oobinfo_small;
- ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+ ecc_writel(ATMEL_BASE_ECC, MR,
ATMEL_ECC_PAGESIZE_528);
break;
case 1024:
nand->ecc.layout = &atmel_oobinfo_large;
- ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+ ecc_writel(ATMEL_BASE_ECC, MR,
ATMEL_ECC_PAGESIZE_1056);
break;
case 2048:
nand->ecc.layout = &atmel_oobinfo_large;
- ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+ ecc_writel(ATMEL_BASE_ECC, MR,
ATMEL_ECC_PAGESIZE_2112);
break;
case 4096:
nand->ecc.layout = &atmel_oobinfo_large;
- ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+ ecc_writel(ATMEL_BASE_ECC, MR,
ATMEL_ECC_PAGESIZE_4224);
break;
default:
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index 6aba1d3194c3..29462c526ec5 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -29,7 +29,6 @@
/* Mem test settings */
/* NAND Flash */
-#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 06/10] Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
` (3 preceding siblings ...)
2022-11-12 22:36 ` [PATCH 05/10] mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 07/10] Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE " Tom Rini
` (5 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This converts the following to Kconfig:
CONFIG_SYS_NAND_MAX_OOBFREE
CONFIG_SYS_NAND_MAX_ECCPOS
Signed-off-by: Tom Rini <trini@konsulko.com>
---
configs/CHIP_pro_defconfig | 1 +
configs/Nintendo_NES_Classic_Edition_defconfig | 1 +
configs/am3517_evm_defconfig | 2 ++
configs/ls1088aqds_defconfig | 2 ++
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 ++
configs/ls1088aqds_qspi_defconfig | 2 ++
configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++
configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++
configs/ls1088aqds_tfa_defconfig | 2 ++
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 ++
configs/ls1088ardb_qspi_defconfig | 2 ++
...s1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 ++
configs/ls1088ardb_sdcard_qspi_defconfig | 2 ++
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 ++
configs/ls1088ardb_tfa_defconfig | 2 ++
configs/ls2080aqds_SECURE_BOOT_defconfig | 2 ++
configs/ls2080aqds_defconfig | 2 ++
configs/ls2080aqds_nand_defconfig | 2 ++
configs/ls2080aqds_qspi_defconfig | 2 ++
configs/ls2080aqds_sdcard_defconfig | 2 ++
configs/ls2080ardb_SECURE_BOOT_defconfig | 2 ++
configs/ls2080ardb_defconfig | 2 ++
configs/ls2080ardb_nand_defconfig | 2 ++
configs/ls2088aqds_tfa_defconfig | 2 ++
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 ++
configs/ls2088ardb_tfa_defconfig | 2 ++
configs/omap35_logic_defconfig | 2 ++
configs/omap35_logic_somlv_defconfig | 2 ++
configs/omap3_logic_defconfig | 2 ++
configs/omap3_logic_somlv_defconfig | 2 ++
doc/README.nand | 10 ----------
drivers/mtd/Kconfig | 18 ++++++++++++++++++
include/configs/T4240RDB.h | 2 --
include/configs/am3517_evm.h | 2 --
include/configs/ls1088aqds.h | 3 ---
include/configs/ls1088ardb.h | 3 ---
include/configs/ls2080aqds.h | 3 ---
include/configs/ls2080ardb.h | 3 ---
include/configs/omap3_logic.h | 2 --
include/configs/sunxi-common.h | 4 ----
40 files changed, 76 insertions(+), 32 deletions(-)
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index 0e7d5e7c96f2..2f558454e81e 100644
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig
@@ -25,6 +25,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0x100
+CONFIG_SYS_NAND_MAX_ECCPOS=1664
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_CONS_INDEX=2
diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
index 94060ab107ab..1b7a4574083e 100644
--- a/configs/Nintendo_NES_Classic_Edition_defconfig
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_MAX_ECCPOS=1664
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_ELDO2_VOLT=1800
CONFIG_CONS_INDEX=5
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 45332e2d60f5..0839d366cfde 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -81,6 +81,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_DRIVER_TI_EMAC_USE_RMII=y
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index 1e865909aa14..8556c003555c 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig
@@ -83,6 +83,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index cfe15406e8dd..d4f2268041f0 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -69,6 +69,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index 4e0e7c302a32..af63278bb3c4 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -72,6 +72,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 0a7541d5e681..6b42170ffbd6 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -104,6 +104,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index d9f27816ebf5..dedefb3a0a3f 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -92,6 +92,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index cce2d9ab1953..60f26f018308 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -91,6 +91,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index 4c46384a6f84..a819ebfefffa 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -72,6 +72,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 796264502daa..c56975333813 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -75,6 +75,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 504db1369683..2b96382f2482 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -95,6 +95,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 8053bc17bb00..426363538408 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -95,6 +95,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 7ba594048106..2e812943fd39 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -71,6 +71,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index ff5784bf6c50..9c12f2be9ce0 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -77,6 +77,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 8899fd930f05..817ae8d728b3 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -74,6 +74,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index a9f52ae5a1f1..b3e75847cca3 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -77,6 +77,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 0b70e7b02b8e..effcd33629b8 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -91,6 +91,8 @@ CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 648a5390507f..eb57948414df 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -71,6 +71,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 318822bd83dd..e5702b815923 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -85,6 +85,8 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 8ae8b52f6a85..face1e05320a 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -76,6 +76,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index d548bcab3f1c..ba6f5090d471 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -79,6 +79,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index a49fe87f71dd..500029003031 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -100,6 +100,8 @@ CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 4c1e7421bf37..9c6012460b37 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -88,6 +88,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index 93be74d00cd4..dc9a47463f49 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -81,6 +81,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index c2bf451dd900..361098568097 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -88,6 +88,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 93daa460baf5..84e267da5849 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -80,6 +80,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PINCTRL=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index de33825d13d1..471e0556fa88 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -88,6 +88,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PINCTRL=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index e2c6dfcf48c9..67db3afd7fc7 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -79,6 +79,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PINCTRL=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 3237c4280a8d..e18cbaa5c18c 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -89,6 +89,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PINCTRL=y
diff --git a/doc/README.nand b/doc/README.nand
index d1ce30768b92..a3c3ab4b9501 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -99,16 +99,6 @@ Configuration Options:
CONFIG_CMD_NAND_TORTURE
Enables the torture command (see description of this command below).
- CONFIG_SYS_NAND_MAX_ECCPOS
- If specified, overrides the maximum number of ECC bytes
- supported. Useful for reducing image size, especially with SPL.
- This must be at least 48 if nand_base.c is used.
-
- CONFIG_SYS_NAND_MAX_OOBFREE
- If specified, overrides the maximum number of free OOB regions
- supported. Useful for reducing image size, especially with SPL.
- This must be at least 2 if nand_base.c is used.
-
CONFIG_SYS_NAND_MAX_CHIPS
The maximum number of NAND chips per device to be supported.
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index fcdb450f77aa..d8e2dec0a8d0 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -212,6 +212,24 @@ config SYS_MAX_FLASH_BANKS_DETECT
source "drivers/mtd/nand/Kconfig"
+config SYS_NAND_MAX_OOBFREE
+ int "Maximum number of free OOB regions supported"
+ depends on SAMSUNG_ONENAND || MTD_RAW_NAND
+ range 2 32
+ default 32
+ help
+ Set the maximum number of free OOB regions supported. Useful for
+ reducing image size, especially with SPL.
+
+config SYS_NAND_MAX_ECCPOS
+ int "Maximum number of ECC bytes supported"
+ depends on SAMSUNG_ONENAND || MTD_RAW_NAND
+ range 48 2147483647
+ default 680
+ help
+ Set the maximum number of ECC bytes supported. Useful for reducing
+ image size, especially with SPL.
+
config SYS_NAND_MAX_CHIPS
int "NAND max chips"
depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index d79789af0e1a..cfd9cb3e7c8d 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -197,8 +197,6 @@
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index e0f5f2b04408..2eb7a51ce2eb 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -25,8 +25,6 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* NAND block size is 128 KiB. Synchronize these values with
* corresponding Device Tree entries in Linux:
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index d50b76b89ae5..3a2fba6b04ee 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -69,9 +69,6 @@
#endif
#endif
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 4edf40b0b722..e2ae3026c29e 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -53,9 +53,6 @@
#endif
#endif
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 1fa4aa3734d1..e6019870d8a3 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -70,9 +70,6 @@
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index e1c66c5dcc0d..382d516c08bc 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -67,9 +67,6 @@
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 442a3cad2206..7c0bdcbb1151 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -26,8 +26,6 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#endif
/* Environment information */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 720768629d67..d9e4c8b699f4 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -71,10 +71,6 @@
#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
-#ifdef CONFIG_NAND_SUNXI
-#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
-#endif
-
/* mmc config */
#define CONFIG_MMC_SUNXI_SLOT 0
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 07/10] Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE to Kconfig
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
` (4 preceding siblings ...)
2022-11-12 22:36 ` [PATCH 06/10] Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 08/10] Convert CONFIG_SYS_NAND_PAGE_2K et al " Tom Rini
` (4 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This converts the following to Kconfig:
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Signed-off-by: Tom Rini <trini@konsulko.com>
---
README | 5 -----
configs/k2e_evm_defconfig | 1 +
configs/k2e_hs_evm_defconfig | 1 +
configs/k2hk_evm_defconfig | 1 +
configs/k2hk_hs_evm_defconfig | 1 +
configs/k2l_evm_defconfig | 1 +
configs/k2l_hs_evm_defconfig | 1 +
drivers/mtd/nand/raw/Kconfig | 4 ++++
include/configs/ti_armv7_keystone2.h | 1 -
9 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/README b/README
index 4309d9338664..f24decf5e43d 100644
--- a/README
+++ b/README
@@ -1806,11 +1806,6 @@ Low Level (hardware related) configuration options:
If defined, the x86 reset vector code is included. This is not
needed when U-Boot is running from Coreboot.
-- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
- Option to disable subpage write in NAND driver
- driver that uses this:
- drivers/mtd/nand/raw/davinci_nand.c
-
Freescale QE/FMAN Firmware Support:
-----------------------------------
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 977348e73fcc..25007793b3a0 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index afba285ffb22..6c8a284e7c70 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -53,6 +53,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 6c4563912b5b..fec29f2c9119 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 33624badae0e..f6ac484f2e85 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -53,6 +53,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index e28054bcc72c..bb91aa3534a9 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index 8f8bb5491305..d10965a70fc8 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -56,6 +56,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 0e428418b25d..3585031ddfa8 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -41,6 +41,10 @@ config SYS_NAND_USE_FLASH_BBT
help
Enable the BBT (Bad Block Table) usage.
+config SYS_NAND_NO_SUBPAGE_WRITE
+ bool "Disable subpage write support"
+ depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
+
config NAND_ATMEL
bool "Support Atmel NAND controller"
select SYS_NAND_SELF_INIT
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 6c01ab813e5a..b8b4b28b3d67 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -68,7 +68,6 @@
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
-#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define DFU_ALT_INFO_MMC \
"dfu_alt_info_mmc=" \
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 08/10] Convert CONFIG_SYS_NAND_PAGE_2K et al to Kconfig
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
` (5 preceding siblings ...)
2022-11-12 22:36 ` [PATCH 07/10] Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE " Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 09/10] Convert CONFIG_SYS_NAND_SIZE " Tom Rini
` (3 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This converts the following to Kconfig:
CONFIG_SYS_NAND_PAGE_2K
CONFIG_SYS_NAND_PAGE_4K
Signed-off-by: Tom Rini <trini@konsulko.com>
---
configs/k2l_evm_defconfig | 1 +
configs/k2l_hs_evm_defconfig | 1 +
drivers/mtd/nand/raw/Kconfig | 13 +++++++++++++
include/configs/da850evm.h | 1 -
include/configs/k2e_evm.h | 3 ---
include/configs/k2g_evm.h | 3 ---
include/configs/k2hk_evm.h | 3 ---
include/configs/k2l_evm.h | 3 ---
include/configs/omapl138_lcdk.h | 1 -
9 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index bb91aa3534a9..13d612ac3fb6 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -80,6 +80,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_PAGE_4K=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index d10965a70fc8..59ec3a6346f3 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -58,6 +58,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_PAGE_4K=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 3585031ddfa8..5483efeb39b4 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -168,6 +168,19 @@ config SYS_NAND_SOFT_ECC
endchoice
+choice
+ prompt "NAND page size"
+ depends on NAND_DAVINCI
+ default SYS_NAND_PAGE_2K
+
+config SYS_NAND_PAGE_2K
+ bool "Page size is 2K"
+
+config SYS_NAND_PAGE_4K
+ bool "Page size is 4K"
+
+endchoice
+
config KEYSTONE_RBL_NAND
depends on ARCH_KEYSTONE
def_bool y
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 11f104bcb86d..5a5c65da16c6 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -107,7 +107,6 @@
* Flash & Environment
*/
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE 0x10
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 9b25c3498223..bbc58be511e4 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -36,9 +36,6 @@
#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
-/* NAND Configuration */
-#define CONFIG_SYS_NAND_PAGE_2K
-
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 9
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 887fda90d6a0..bb91751d5d90 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -50,9 +50,6 @@
"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
"name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
-/* NAND Configuration */
-#define CONFIG_SYS_NAND_PAGE_2K
-
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 2
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index cfc34c7da6d7..68cbe98b553b 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -36,9 +36,6 @@
#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
-/* NAND Configuration */
-#define CONFIG_SYS_NAND_PAGE_2K
-
/* Network */
#define CONFIG_KSNET_NETCP_V1_0
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 65988fff06ed..a18158a7eb33 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -36,9 +36,6 @@
#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
-/* NAND Configuration */
-#define CONFIG_SYS_NAND_PAGE_4K
-
/* Network */
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 233e7b4ee53e..d9f70c75323f 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -105,7 +105,6 @@
* Flash & Environment
*/
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE 0x10
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 09/10] Convert CONFIG_SYS_NAND_SIZE to Kconfig
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
` (6 preceding siblings ...)
2022-11-12 22:36 ` [PATCH 08/10] Convert CONFIG_SYS_NAND_PAGE_2K et al " Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 10/10] global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_* Tom Rini
` (2 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
This converts the following to Kconfig:
CONFIG_SYS_NAND_SIZE
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/mtd/nand/raw/Kconfig | 5 +++++
include/configs/M5329EVB.h | 1 -
include/configs/M5373EVB.h | 1 -
include/configs/m53menlo.h | 6 ------
include/configs/smartweb.h | 1 -
include/configs/taurus.h | 1 -
6 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 5483efeb39b4..eb37b6275998 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -461,6 +461,11 @@ config NAND_MXC
This enables the NAND driver for the NAND flash controller on the
i.MX27 / i.MX31 / i.MX5 processors.
+config SYS_NAND_SIZE
+ int "Size of NAND in kilobytes"
+ depends on NAND_MXC && SPL_NAND_SUPPORT
+ default 268435456
+
config NAND_MXS
bool "MXS NAND support"
depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 47ea51c50724..a39fe5f28a87 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -94,7 +94,6 @@
#ifdef CONFIG_CMD_NAND
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
-# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#endif
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index a2e36cc86736..f0734712eaa5 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -95,7 +95,6 @@
#endif
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
-# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index a20b41bdf07c..36522419172e 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -85,12 +85,6 @@
/* Watchdog */
-/*
- * NAND SPL
- */
-
-#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
-
/*
* Extra Environments
*/
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 538aad9a7bbb..5460c12a17e8 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -96,7 +96,6 @@
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_SIZE (SZ_256M)
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 5ab087da8bd0..f130c630dde8 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -130,7 +130,6 @@
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 10/10] global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
` (7 preceding siblings ...)
2022-11-12 22:36 ` [PATCH 09/10] Convert CONFIG_SYS_NAND_SIZE " Tom Rini
@ 2022-11-12 22:36 ` Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-14 22:49 ` [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Simon Glass
2022-12-06 2:06 ` Tom Rini
10 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2022-11-12 22:36 UTC (permalink / raw)
To: u-boot
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
README | 10 +--
arch/arm/include/asm/arch-lpc32xx/config.h | 8 +-
arch/arm/include/asm/ti-common/davinci_nand.h | 8 +-
arch/arm/mach-kirkwood/include/mach/config.h | 2 +-
arch/arm/mach-omap2/mem-common.c | 2 +-
arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 20 ++---
arch/powerpc/cpu/mpc83xx/spl_minimal.c | 10 +--
board/atmel/at91sam9260ek/at91sam9260ek.c | 4 +-
board/atmel/at91sam9261ek/at91sam9261ek.c | 4 +-
board/atmel/at91sam9263ek/at91sam9263ek.c | 4 +-
.../atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 4 +-
board/atmel/at91sam9rlek/at91sam9rlek.c | 4 +-
board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 +-
board/atmel/sam9x60ek/sam9x60ek.c | 4 +-
board/bluewater/gurnard/gurnard.c | 8 +-
board/calao/usb_a9263/usb_a9263.c | 8 +-
board/egnite/ethernut5/ethernut5.c | 6 +-
board/esd/meesc/meesc.c | 4 +-
board/freescale/common/p_corenet/law.c | 4 +-
board/freescale/common/p_corenet/tlb.c | 4 +-
board/freescale/ls1043aqds/ls1043aqds.c | 32 ++++----
board/freescale/ls1043ardb/ls1043ardb.c | 34 ++++----
board/freescale/ls1046aqds/ls1046aqds.c | 32 ++++----
board/freescale/ls1088a/ls1088a.c | 32 ++++----
board/freescale/p1010rdb/law.c | 2 +-
board/freescale/p1010rdb/spl_minimal.c | 6 +-
board/freescale/p1010rdb/tlb.c | 2 +-
board/freescale/p1_p2_rdb_pc/law.c | 4 +-
board/freescale/p1_p2_rdb_pc/spl_minimal.c | 6 +-
board/freescale/p1_p2_rdb_pc/tlb.c | 4 +-
board/freescale/t102xrdb/law.c | 4 +-
board/freescale/t102xrdb/tlb.c | 4 +-
board/freescale/t104xrdb/law.c | 4 +-
board/freescale/t104xrdb/tlb.c | 4 +-
board/freescale/t208xqds/law.c | 4 +-
board/freescale/t208xqds/tlb.c | 4 +-
board/freescale/t208xrdb/law.c | 4 +-
board/freescale/t208xrdb/tlb.c | 4 +-
board/freescale/t4rdb/law.c | 4 +-
board/freescale/t4rdb/tlb.c | 4 +-
board/gardena/smart-gateway-at91sam/spl.c | 4 +-
board/keymile/kmcent2/law.c | 2 +-
board/keymile/kmcent2/tlb.c | 2 +-
board/ronetix/pm9261/pm9261.c | 4 +-
board/ronetix/pm9263/pm9263.c | 4 +-
board/ronetix/pm9g45/pm9g45.c | 6 +-
board/siemens/corvus/board.c | 8 +-
board/siemens/smartweb/smartweb.c | 8 +-
board/siemens/taurus/taurus.c | 10 +--
board/socrates/nand.c | 2 +-
common/spl/spl_nand.c | 8 +-
doc/README.arm-relocation | 8 +-
doc/README.omap3 | 6 +-
doc/board/ti/am335x_evm.rst | 2 +-
drivers/mtd/nand/raw/am335x_spl_bch.c | 12 +--
drivers/mtd/nand/raw/atmel_nand.c | 40 +++++-----
drivers/mtd/nand/raw/davinci_nand.c | 14 ++--
drivers/mtd/nand/raw/denali_spl.c | 4 +-
drivers/mtd/nand/raw/fsl_elbc_nand.c | 6 +-
drivers/mtd/nand/raw/fsl_elbc_spl.c | 12 +--
drivers/mtd/nand/raw/fsl_ifc_nand.c | 6 +-
drivers/mtd/nand/raw/fsl_ifc_spl.c | 20 ++---
drivers/mtd/nand/raw/fsmc_nand.c | 2 +-
drivers/mtd/nand/raw/kmeter1_nand.c | 4 +-
drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 22 +++---
drivers/mtd/nand/raw/mxc_nand.c | 6 +-
drivers/mtd/nand/raw/mxc_nand_spl.c | 8 +-
drivers/mtd/nand/raw/nand.c | 6 +-
drivers/mtd/nand/raw/nand_spl_load.c | 6 +-
drivers/mtd/nand/raw/nand_spl_simple.c | 16 ++--
drivers/mtd/nand/raw/omap_gpmc.c | 2 +-
drivers/mtd/nand/raw/vf610_nfc.c | 2 +-
include/configs/M5329EVB.h | 4 +-
include/configs/M5373EVB.h | 4 +-
include/configs/MCR3000.h | 2 +-
include/configs/MPC837XERDB.h | 2 +-
include/configs/P1010RDB.h | 78 +++++++++----------
include/configs/P2041RDB.h | 12 +--
include/configs/T102xRDB.h | 64 +++++++--------
include/configs/T104xRDB.h | 62 +++++++--------
include/configs/T208xQDS.h | 60 +++++++-------
include/configs/T208xRDB.h | 60 +++++++-------
include/configs/T4240RDB.h | 54 ++++++-------
include/configs/am335x_evm.h | 6 +-
include/configs/am335x_guardian.h | 6 +-
include/configs/am335x_igep003x.h | 6 +-
include/configs/am3517_evm.h | 8 +-
include/configs/am43xx_evm.h | 6 +-
include/configs/at91sam9260ek.h | 10 +--
include/configs/at91sam9261ek.h | 10 +--
include/configs/at91sam9263ek.h | 10 +--
include/configs/at91sam9m10g45ek.h | 18 ++---
include/configs/at91sam9n12ek.h | 10 +--
include/configs/at91sam9rlek.h | 10 +--
include/configs/at91sam9x5ek.h | 10 +--
include/configs/baltos.h | 8 +-
include/configs/chiliboard.h | 6 +-
include/configs/cm_fx6.h | 2 +-
include/configs/cm_t43.h | 6 +-
include/configs/colibri-imx6ull.h | 4 +-
include/configs/colibri_imx7.h | 2 +-
include/configs/corvus.h | 22 +++---
include/configs/da850evm.h | 20 ++---
include/configs/devkit3250.h | 10 +--
include/configs/devkit8000.h | 8 +-
include/configs/dra7xx_evm.h | 6 +-
include/configs/etamin.h | 18 ++---
include/configs/ethernut5.h | 8 +-
.../configs/gardena-smart-gateway-at91sam.h | 16 ++--
include/configs/imx27lite-common.h | 2 +-
include/configs/imx6-engicam.h | 4 +-
include/configs/imx6_logic.h | 4 +-
include/configs/imx6ulz_smm_m2.h | 2 +-
include/configs/imx8mn_bsh_smm_s2.h | 2 +-
include/configs/imx8mp_rsb3720.h | 2 +-
include/configs/km/km-mpc83xx.h | 2 +-
include/configs/km/pg-wcom-ls102xa.h | 42 +++++-----
include/configs/kmcent2.h | 38 ++++-----
include/configs/kmcoge5ne.h | 2 +-
include/configs/ls1021aqds.h | 60 +++++++-------
include/configs/ls1043a_common.h | 4 +-
include/configs/ls1043aqds.h | 72 ++++++++---------
include/configs/ls1043ardb.h | 72 ++++++++---------
include/configs/ls1046a_common.h | 4 +-
include/configs/ls1046afrwy.h | 38 ++++-----
include/configs/ls1046aqds.h | 72 ++++++++---------
include/configs/ls1046ardb.h | 38 ++++-----
include/configs/ls1088a_common.h | 4 +-
include/configs/ls1088aqds.h | 66 ++++++++--------
include/configs/ls1088ardb.h | 34 ++++----
include/configs/ls2080a_common.h | 8 +-
include/configs/ls2080aqds.h | 54 ++++++-------
include/configs/ls2080ardb.h | 54 ++++++-------
include/configs/m53menlo.h | 4 +-
include/configs/meesc.h | 10 +--
include/configs/mx6sabreauto.h | 2 +-
include/configs/mx6sxsabreauto.h | 2 +-
include/configs/mx7dsabresd.h | 2 +-
include/configs/mxs.h | 2 +-
include/configs/mys_6ulx.h | 2 +-
include/configs/npi_imx6ull.h | 2 +-
include/configs/omap3_beagle.h | 6 +-
include/configs/omap3_evm.h | 6 +-
include/configs/omap3_igep00x0.h | 6 +-
include/configs/omap3_logic.h | 6 +-
include/configs/omapl138_lcdk.h | 20 ++---
include/configs/p1_p2_rdb_pc.h | 26 +++----
include/configs/pcl063.h | 2 +-
include/configs/pcl063_ull.h | 2 +-
include/configs/phycore_am335x_r2.h | 6 +-
include/configs/pm9261.h | 10 +--
include/configs/pm9263.h | 10 +--
include/configs/pm9g45.h | 18 ++---
include/configs/presidio_asic.h | 4 +-
include/configs/sam9x60ek.h | 10 +--
include/configs/sama5d2_ptc_ek.h | 6 +-
include/configs/sama5d3_xplained.h | 6 +-
include/configs/sama5d3xek.h | 6 +-
include/configs/sama5d4_xplained.h | 6 +-
include/configs/sama5d4ek.h | 6 +-
include/configs/siemens-am33x-common.h | 10 +--
include/configs/smartweb.h | 22 +++---
include/configs/snapper9g45.h | 10 +--
include/configs/socfpga_common.h | 4 +-
include/configs/socrates.h | 2 +-
include/configs/taurus.h | 22 +++---
include/configs/ti816x_evm.h | 8 +-
include/configs/ti_armv7_common.h | 2 +-
include/configs/ti_armv7_keystone2.h | 10 +--
include/configs/ti_armv7_omap.h | 4 +-
include/configs/ti_omap3_common.h | 2 +-
include/configs/uniphier.h | 4 +-
include/configs/usb_a9263.h | 10 +--
include/configs/vf610twr.h | 2 +-
include/configs/work_92105.h | 6 +-
175 files changed, 1106 insertions(+), 1106 deletions(-)
diff --git a/README b/README
index f24decf5e43d..f5407576276c 100644
--- a/README
+++ b/README
@@ -1364,18 +1364,18 @@ The following options need to be configured:
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
- CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
- CONFIG_SYS_NAND_ECCBYTES
+ CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+ CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
- CONFIG_SYS_NAND_U_BOOT_DST
+ CFG_SYS_NAND_U_BOOT_DST
Location in memory to load U-Boot to
- CONFIG_SYS_NAND_U_BOOT_SIZE
+ CFG_SYS_NAND_U_BOOT_SIZE
Size of image to load
- CONFIG_SYS_NAND_U_BOOT_START
+ CFG_SYS_NAND_U_BOOT_START
Entry point in loaded image to jump to
CONFIG_SPL_RAM_DEVICE
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index dc414c7d8452..5dd90b47f939 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -32,17 +32,17 @@
#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
+#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
#else
#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
#endif
-#define CONFIG_SYS_NAND_ECCSIZE 0x100
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCSIZE 0x100
+#define CFG_SYS_NAND_ECCBYTES 3
#endif /* CONFIG_NAND_LPC32XX_SLC */
/* NOR Flash */
diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index a4cc27e920d8..38a1a6ea0d7b 100644
--- a/arch/arm/include/asm/ti-common/davinci_nand.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -18,13 +18,13 @@
#define MASK_CLE 0x10
#define MASK_ALE 0x08
-#ifdef CONFIG_SYS_NAND_MASK_CLE
+#ifdef CFG_SYS_NAND_MASK_CLE
#undef MASK_CLE
-#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#define MASK_CLE CFG_SYS_NAND_MASK_CLE
#endif
-#ifdef CONFIG_SYS_NAND_MASK_ALE
+#ifdef CFG_SYS_NAND_MASK_ALE
#undef MASK_ALE
-#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#define MASK_ALE CFG_SYS_NAND_MASK_ALE
#endif
struct davinci_emif_regs {
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index d877be119fc8..ae1f6fee531e 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -35,7 +35,7 @@
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
+#define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
#endif
diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c
index 2dcf0cf9c373..803dc7fb71d6 100644
--- a/arch/arm/mach-omap2/mem-common.c
+++ b/arch/arm/mach-omap2/mem-common.c
@@ -135,7 +135,7 @@ void set_gpmc_cs0(int flash_type)
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
case MTD_DEV_TYPE_NAND:
gpmc_regs = gpmc_regs_nand;
- base = CONFIG_SYS_NAND_BASE;
+ base = CFG_SYS_NAND_BASE;
size = GPMC_SIZE_16M;
break;
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
index e795cd10cb95..b0b9a1e99e24 100644
--- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
+++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
@@ -1,16 +1,16 @@
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index d8f6cfe2b4aa..8fcf20854ed9 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -71,16 +71,16 @@ void cpu_init_f (volatile immap_t * im)
* has been determined
*/
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) \
- && defined(CONFIG_SYS_NAND_OR_PRELIM) \
+#if defined(CFG_SYS_NAND_BR_PRELIM) \
+ && defined(CFG_SYS_NAND_OR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+ set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else
-#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
+#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
#endif
}
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index a9ea9b558a9e..d2c6ada66838 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -56,10 +56,10 @@ static void at91sam9260ek_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 0c53325ba715..2992353199fe 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -78,10 +78,10 @@ static void at91sam9261ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 3e232aa87fb1..b2b709308050 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -69,10 +69,10 @@ static void at91sam9263ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOCDE);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 3af70971f34a..2f3a772b81fa 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -63,10 +63,10 @@ void at91sam9m10g45ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index f05ee322d094..bca7c8d9af52 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -64,10 +64,10 @@ static void at91sam9rlek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOD);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index b5af35bc7e5d..817aa2fef707 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -65,9 +65,9 @@ static void at91sam9x5ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOCD);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c
index 7035fab8788c..786de18f8c64 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -36,9 +36,9 @@ static void sam9x60ek_nand_hw_init(void)
at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
index f547ce3cc21a..35c74ba9dd28 100644
--- a/board/bluewater/gurnard/gurnard.c
+++ b/board/bluewater/gurnard/gurnard.c
@@ -100,16 +100,16 @@ static int gurnard_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
- ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+ ret = gpio_request(CFG_SYS_NAND_READY_PIN, "nand_rdy");
if (ret)
return ret;
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+ ret = gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand_ce");
if (ret)
return ret;
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
return 0;
}
diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c
index c0a5c518ca8b..c89ad0bfe3d4 100644
--- a/board/calao/usb_a9263/usb_a9263.c
+++ b/board/calao/usb_a9263/usb_a9263.c
@@ -54,12 +54,12 @@ static void usb_a9263_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOCDE);
/* Configure RDY/BSY */
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_request(CFG_SYS_NAND_READY_PIN, "NAND ready/busy");
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable");
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
index 559fdd2f646d..a5d79d8e3e1a 100644
--- a/board/egnite/ethernut5/ethernut5.c
+++ b/board/egnite/ethernut5/ethernut5.c
@@ -117,11 +117,11 @@ static void ethernut5_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
/* Ready pin is optional. */
- at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1);
#endif
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index a3eee63e3758..98043b020c52 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -84,10 +84,10 @@ static void meesc_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 603384ac4f9f..8951fae32d3b 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -28,8 +28,8 @@ struct law_entry law_table[] = {
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
};
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index c0ab1a5fd14e..ef46353a3670 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -135,13 +135,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_4M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index b02f649910f6..481d3a5d9bd9 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -84,15 +84,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
@@ -113,15 +113,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 799900e9c949..7f3212819885 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -47,15 +47,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
@@ -76,15 +76,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
@@ -355,7 +355,7 @@ void nand_fixup(void)
return;
/* Change NAND Flash PGS/SPRZ configuration */
- csor = CONFIG_SYS_NAND_CSOR;
+ csor = CFG_SYS_NAND_CSOR;
if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index dfdc9f06ab14..de6828673b50 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -68,15 +68,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
@@ -97,15 +97,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index ae81740dc36c..b70c198188bf 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -73,15 +73,15 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
@@ -105,15 +105,15 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
index debf571482ba..2dcee79b3aee 100644
--- a/board/freescale/p1010rdb/law.c
+++ b/board/freescale/p1010rdb/law.c
@@ -10,7 +10,7 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index a262d5ca4af7..9cd46c966410 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -22,9 +22,9 @@ void board_init_f(ulong bootflag)
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 7992666e9307..aa7517a74d81 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -68,7 +68,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 6bdfb356eede..8f3f4840e604 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -13,8 +13,8 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
};
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index e467c7adc190..2fd8a2874333 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -21,9 +21,9 @@ void board_init_f(ulong bootflag)
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 65cedd42a0df..85d41327aa24 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -67,9 +67,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
index 04a4239797c5..850ece0110ef 100644
--- a/board/freescale/t102xrdb/law.c
+++ b/board/freescale/t102xrdb/law.c
@@ -23,8 +23,8 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
index 97080eb95e59..8fdff7576fe5 100644
--- a/board/freescale/t102xrdb/tlb.c
+++ b/board/freescale/t102xrdb/tlb.c
@@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+#ifdef CFG_SYS_NAND_BASE
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
index 0f6b71a8c22f..2f00d8010698 100644
--- a/board/freescale/t104xrdb/law.c
+++ b/board/freescale/t104xrdb/law.c
@@ -23,8 +23,8 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 9dcba7933ff9..8a3d67449c27 100644
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -101,13 +101,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
index 40fdcf61c057..f97467e84455 100644
--- a/board/freescale/t208xqds/law.c
+++ b/board/freescale/t208xqds/law.c
@@ -25,8 +25,8 @@ struct law_entry law_table[] = {
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#endif
};
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index 1e501da363d4..f27faf5d2437 100644
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
@@ -116,13 +116,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c
index d3b263f59d9d..3ff4c773d599 100644
--- a/board/freescale/t208xrdb/law.c
+++ b/board/freescale/t208xrdb/law.c
@@ -25,8 +25,8 @@ struct law_entry law_table[] = {
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#endif
};
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 542ab1e034f3..da03aadb1733 100644
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -116,13 +116,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c
index 038f60565f7e..438589604f19 100644
--- a/board/freescale/t4rdb/law.c
+++ b/board/freescale/t4rdb/law.c
@@ -22,8 +22,8 @@ struct law_entry law_table[] = {
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index b927dd8484f8..059449af1edf 100644
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c
@@ -98,13 +98,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c
index 3ab6760df733..2807c4e31141 100644
--- a/board/gardena/smart-gateway-at91sam/spl.c
+++ b/board/gardena/smart-gateway-at91sam/spl.c
@@ -53,10 +53,10 @@ static void at91sam9x5ek_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOCD);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c
index aa0f29f44fc1..b04a8e20dce9 100644
--- a/board/keymile/kmcent2/law.c
+++ b/board/keymile/kmcent2/law.c
@@ -14,7 +14,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
/* other application LAW are not used in u-boot */
diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c
index dbd3b9b064cc..095fc7e96146 100644
--- a/board/keymile/kmcent2/tlb.c
+++ b/board/keymile/kmcent2/tlb.c
@@ -76,7 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 9, BOOKE_PAGESZ_4M, 1),
/* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
/* QRIO */
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index fe52c7c1764f..07febe69dc7c 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -66,10 +66,10 @@ static void pm9261_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 84926cdc689f..76f62ddde912 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -62,10 +62,10 @@ static void pm9263_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 8d5825c7f131..23b55e3e0302 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -65,13 +65,13 @@ static void pm9g45_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
/* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
#endif
/* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index 90fece7f958d..d87628097d0d 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -40,8 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
static void corvus_request_gpio(void)
{
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PD7, "d0");
gpio_request(AT91_PIN_PD8, "d1");
gpio_request(AT91_PIN_PA12, "d2");
@@ -110,8 +110,8 @@ static void corvus_nand_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOA);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
}
#if defined(CONFIG_SPL_BUILD)
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index d500a6214d56..ce6c877959ad 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -42,8 +42,8 @@ DECLARE_GLOBAL_DATA_PTR;
static void smartweb_request_gpio(void)
{
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PA26, "ena PHY");
}
@@ -72,10 +72,10 @@ static void smartweb_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
static void smartweb_macb_hw_init(void)
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 6c44afb44875..47d3f6aef22e 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR;
static void taurus_request_gpio(void)
{
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PA25, "ena PHY");
}
@@ -73,10 +73,10 @@ static void taurus_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#if defined(CONFIG_SPL_BUILD)
@@ -149,7 +149,7 @@ void spl_board_init(void)
} else {
puts("erase spi flash sector 0\n");
spi_flash_erase(flash, 0,
- CONFIG_SYS_NAND_U_BOOT_SIZE);
+ CFG_SYS_NAND_U_BOOT_SIZE);
}
}
}
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 9b7ffee83a41..b1e38c511e5f 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -6,7 +6,7 @@
#include <common.h>
-#if defined(CONFIG_SYS_NAND_BASE)
+#if defined(CFG_SYS_NAND_BASE)
#include <nand.h>
#include <linux/errno.h>
#include <linux/mtd/rawnand.h>
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 25a38be65ed2..dc45204fc0e6 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -26,12 +26,12 @@ static int spl_nand_load_image(struct spl_image_info *spl_image,
nand_init();
printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n",
- CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- CONFIG_SYS_NAND_U_BOOT_DST);
+ CONFIG_SYS_NAND_U_BOOT_OFFS, CFG_SYS_NAND_U_BOOT_SIZE,
+ CFG_SYS_NAND_U_BOOT_DST);
nand_spl_load_image(spl_nand_get_uboot_raw_page(),
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CFG_SYS_NAND_U_BOOT_DST);
spl_set_header_raw_uboot(spl_image);
nand_deselect();
diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation
index 6bb4e178474d..69882a76a362 100644
--- a/doc/README.arm-relocation
+++ b/doc/README.arm-relocation
@@ -53,8 +53,8 @@ c) end executes this code
d) this initialize CPU, RAM, ... and copy itself to RAM
(this bin must fit in one page, so board_init_f()
don;t fit in it ... )
-e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and
- starts this image @ CONFIG_SYS_NAND_U_BOOT_START
+e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and
+ starts this image @ CFG_SYS_NAND_U_BOOT_START
f) u-boot code steps through board_init_f() and calculates
the relocation address and copy itself to it
@@ -86,8 +86,8 @@ Relocation with SPL (example for the tx25 booting from NAND Flash):
- The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c
which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads
- the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
- @CONFIG_SYS_NAND_U_BOOT_START
+ the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution
+ @CFG_SYS_NAND_U_BOOT_START
- This u-boot does no RAM init, nor CPU register setup. Just look
where it has to copy and relocate itself to this address. If
diff --git a/doc/README.omap3 b/doc/README.omap3
index 208714ad6585..3a1ac8101d64 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -146,11 +146,11 @@ implementation for OMAP3 works for you so the u-boot version should also.
When you require the SPL to read with BCH8 there are two more configs to
change:
- * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
+ * CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in
GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
arch/arm/include/asm/arch-omap3/omap_gpmc.h)
- * CONFIG_SYS_NAND_ECCSIZE must be 512
- * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
+ * CFG_SYS_NAND_ECCSIZE must be 512
+ * CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
Acknowledgements
================
diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst
index a90f32da7aea..0b230cf7c752 100644
--- a/doc/board/ti/am335x_evm.rst
+++ b/doc/board/ti/am335x_evm.rst
@@ -54,7 +54,7 @@ Step-1: Building u-boot for NAND boot
CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block
- CONFIG_SYS_NAND_ECCPOS ECC map for NAND page
+ CFG_SYS_NAND_ECCPOS ECC map for NAND page
CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
Step-2: Flashing NAND via MMC/SD
diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c
index 83590a63ccaf..6ab3f1f42c54 100644
--- a/drivers/mtd/nand/raw/am335x_spl_bch.c
+++ b/drivers/mtd/nand/raw/am335x_spl_bch.c
@@ -16,13 +16,13 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
/*
@@ -155,8 +155,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
uint32_t data_pos = 0;
@@ -207,7 +207,7 @@ void nand_init(void)
*/
mtd = nand_to_mtd(&nand_chip);
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index a541af6db4a4..9fbb0b57cf1d 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c
@@ -1227,16 +1227,16 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
- | CONFIG_SYS_NAND_MASK_CLE);
+ IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE
+ | CFG_SYS_NAND_MASK_CLE);
if (ctrl & NAND_CLE)
- IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
+ IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE;
if (ctrl & NAND_ALE)
- IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
+ IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE;
-#ifdef CONFIG_SYS_NAND_ENABLE_PIN
- at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
+#ifdef CFG_SYS_NAND_ENABLE_PIN
+ at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN,
!(ctrl & NAND_NCE));
#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
@@ -1246,10 +1246,10 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
writeb(cmd, this->IO_ADDR_W);
}
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd)
{
- return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
+ return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN);
}
#endif
@@ -1314,10 +1314,10 @@ static int nand_is_bad_block(int block)
}
#ifdef CONFIG_SPL_NAND_ECC
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
static int nand_read_page(int block, int page, void *dst)
{
@@ -1325,8 +1325,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
int i;
uint8_t *p = dst;
@@ -1415,7 +1415,7 @@ int board_nand_init(struct nand_chip *nand)
nand->read_buf = nand_read_buf;
#endif
nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#else
nand->dev_ready = at91_nand_wait_ready;
@@ -1439,8 +1439,8 @@ void nand_init(void)
mtd = nand_to_mtd(&nand_chip);
mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
- nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+ nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_ECC
@@ -1464,11 +1464,11 @@ void nand_deselect(void)
#else
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
int atmel_nand_chip_init(int devnum, ulong base_addr)
{
@@ -1487,7 +1487,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
nand->options = NAND_BUSWIDTH_16;
#endif
nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#endif
nand->chip_delay = 75;
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 54aed1363889..e4e144bd7c83 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -170,7 +170,7 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
u_int32_t ecc = 0;
ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ CFG_SYS_NAND_CS - 2]));
return ecc;
}
@@ -183,8 +183,8 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
- val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
- val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS);
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
@@ -486,8 +486,8 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
*/
val = __raw_readl(&davinci_emif_regs->nandfcr);
val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
- val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
- val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_START;
__raw_writel(val, &davinci_emif_regs->nandfcr);
break;
@@ -794,8 +794,8 @@ static int davinci_nand_probe(struct udevice *dev)
struct mtd_info *mtd = nand_to_mtd(nand);
int ret;
- nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+ nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
davinci_nand_init(nand);
diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c
index f72142817e7f..690279c9976b 100644
--- a/drivers/mtd/nand/raw/denali_spl.c
+++ b/drivers/mtd/nand/raw/denali_spl.c
@@ -25,9 +25,9 @@
#define BANK(x) ((x) << 24)
static void __iomem *denali_flash_mem =
- (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+ (void __iomem *)CFG_SYS_NAND_DATA_BASE;
static void __iomem *denali_flash_reg =
- (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+ (void __iomem *)CFG_SYS_NAND_REGS_BASE;
static const int flash_bank;
static int page_size, oob_size, pages_per_block;
diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index 4f0acd7c89bb..7853c3f74e2a 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -819,12 +819,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev)
#ifndef CONFIG_NAND_FSL_ELBC_DT
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
- CONFIG_SYS_NAND_BASE_LIST;
+ CFG_SYS_NAND_BASE_LIST;
void board_nand_init(void)
{
diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c
index e55b40f8f13c..26aaab08e893 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c
@@ -46,8 +46,8 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
#endif
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
- const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
+ uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
+ const int large = CFG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
const int block_shift = large ? 17 : 14;
const int block_size = 1 << block_shift;
const int page_size = large ? 2048 : 512;
@@ -143,8 +143,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -161,13 +161,13 @@ void nand_boot(void)
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
#endif
puts("transfering control\n");
/*
* Jump to U-Boot image
*/
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
(*uboot)();
}
diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index e5ff937872e4..59de3256405b 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -1053,12 +1053,12 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
return 0;
}
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
- CONFIG_SYS_NAND_BASE_LIST;
+ CFG_SYS_NAND_BASE_LIST;
void board_nand_init(void)
{
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index 4d11922a6503..7d4b77dd11d4 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -110,7 +110,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
{
struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
struct fsl_ifc_runtime *ifc = NULL;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
+ uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
int page_size;
int port_size;
int pages_per_blk;
@@ -129,8 +129,8 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
ifc = runtime_regs_address();
/* Get NAND Flash configuration */
- csor = CONFIG_SYS_NAND_CSOR;
- cspr = CONFIG_SYS_NAND_CSPR;
+ csor = CFG_SYS_NAND_CSOR;
+ cspr = CFG_SYS_NAND_CSPR;
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
@@ -250,8 +250,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -270,7 +270,7 @@ void nand_boot(void)
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
@@ -279,11 +279,11 @@ void nand_boot(void)
* calculate U-boot header address using U-boot header size.
*/
#define CONFIG_U_BOOT_HDR_ADDR \
- ((CONFIG_SYS_NAND_U_BOOT_START + \
- CONFIG_SYS_NAND_U_BOOT_SIZE) - \
+ ((CFG_SYS_NAND_U_BOOT_START + \
+ CFG_SYS_NAND_U_BOOT_SIZE) - \
CONFIG_U_BOOT_HDR_SIZE)
spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
- CONFIG_SYS_NAND_U_BOOT_START);
+ CFG_SYS_NAND_U_BOOT_START);
/*
* In case of failure in validation, spl_validate_uboot would
* not return back in case of Production environment with ITS=1.
@@ -293,7 +293,7 @@ void nand_boot(void)
*/
#endif
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
uboot();
}
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index a92c6252a5dc..d795864949c0 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -427,7 +427,7 @@ int fsmc_nand_init(struct nand_chip *nand)
nand->ecc.hwctl = fsmc_enable_hwecc;
nand->cmd_ctrl = fsmc_nand_hwcontrol;
nand->IO_ADDR_R = nand->IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
nand->badblockbits = 7;
mtd = nand_to_mtd(nand);
diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c
index b838164bf2e4..84564b2f70a5 100644
--- a/drivers/mtd/nand/raw/kmeter1_nand.c
+++ b/drivers/mtd/nand/raw/kmeter1_nand.c
@@ -10,8 +10,8 @@
#include <linux/delay.h>
#include <linux/mtd/rawnand.h>
-#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
-#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
+#define CONFIG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000)
+#define CONFIG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000)
#define read_mode() in_8(CONFIG_NAND_MODE_REG)
#define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index 3d6cb1dc6350..f4f1b22f5e21 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
@@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = {
};
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
-#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
/*
* DMA Descriptors
@@ -187,7 +187,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
DMAC_CHAN_DEST_AHB1;
/* CTRL descriptor entry for reading/writing Data */
- ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
+ ctrl = (CFG_SYS_NAND_ECCSIZE / 4) |
DMAC_CHAN_SRC_BURST_4 |
DMAC_CHAN_DEST_BURST_4 |
DMAC_CHAN_SRC_WIDTH_32 |
@@ -241,7 +241,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
*/
- for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
+ for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) {
dmalist_cur = &dmalist[i * 2];
dmalist_cur_ecc = &dmalist[(i * 2) + 1];
@@ -337,9 +337,9 @@ static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
{
int i;
- for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
- i += CONFIG_SYS_NAND_ECCBYTES) {
- u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
+ for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES);
+ i += CFG_SYS_NAND_ECCBYTES) {
+ u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES];
ce = ~(ce << 2) & 0xFFFFFF;
spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
@@ -386,9 +386,9 @@ int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
u16 data_offset = 0;
for (i = 0 ; i < ECCSTEPS ; i++) {
- r += CONFIG_SYS_NAND_ECCBYTES;
- c += CONFIG_SYS_NAND_ECCBYTES;
- data_offset += CONFIG_SYS_NAND_ECCSIZE;
+ r += CFG_SYS_NAND_ECCBYTES;
+ c += CFG_SYS_NAND_ECCBYTES;
+ data_offset += CFG_SYS_NAND_ECCSIZE;
ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
if (ret1 < 0)
@@ -568,8 +568,8 @@ int board_nand_init(struct nand_chip *lpc32xx_chip)
* These values are predefined
* for both small and large page NAND flash devices.
*/
- lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+ lpc32xx_chip->ecc.size = CFG_SYS_NAND_ECCSIZE;
+ lpc32xx_chip->ecc.bytes = CFG_SYS_NAND_ECCBYTES;
lpc32xx_chip->ecc.strength = 1;
if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 2b8a132a5fcb..fa903e324c59 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -50,7 +50,7 @@ static struct mxc_nand_host *host = &mxc_host;
/* OOB placement block for use with hardware ecc generation */
#if defined(MXC_NFC_V1)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 5,
.eccpos = {6, 7, 8, 9, 10},
@@ -69,7 +69,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = {
};
#endif
#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
@@ -1219,7 +1219,7 @@ int board_nand_init(struct nand_chip *this)
if (is_16bit_nand())
this->options |= NAND_BUSWIDTH_16;
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
+#ifdef CFG_SYS_NAND_LARGEPAGE
host->pagesize_2k = 1;
this->ecc.layout = &nand_hw_eccoob2k;
#else
diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c
index 0fea307ea461..309e75d01e5a 100644
--- a/drivers/mtd/nand/raw/mxc_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxc_nand_spl.c
@@ -332,14 +332,14 @@ __used void nand_boot(void)
__attribute__((noreturn)) void (*uboot)(void);
/*
- * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
+ * CONFIG_SYS_NAND_U_BOOT_OFFS and CFG_SYS_NAND_U_BOOT_SIZE must
* be aligned to full pages
*/
if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CFG_SYS_NAND_U_BOOT_DST)) {
/* Copy from NAND successful, start U-Boot */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
uboot();
} else {
/* Unrecoverable error when copying from NAND */
diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c
index 14bca12024b0..eacd99c4e275 100644
--- a/drivers/mtd/nand/raw/nand.c
+++ b/drivers/mtd/nand/raw/nand.c
@@ -11,8 +11,8 @@
#include <linux/mtd/concat.h>
#include <linux/mtd/rawnand.h>
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
int nand_curr_device = -1;
@@ -21,7 +21,7 @@ static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
#endif
static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
diff --git a/drivers/mtd/nand/raw/nand_spl_load.c b/drivers/mtd/nand/raw/nand_spl_load.c
index ecd373e054bf..7ac9bf4d1206 100644
--- a/drivers/mtd/nand/raw/nand_spl_load.c
+++ b/drivers/mtd/nand/raw/nand_spl_load.c
@@ -20,8 +20,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -36,6 +36,6 @@ void nand_boot(void)
/*
* Jump to U-Boot image
*/
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
(*uboot)();
}
diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c
index 727861c8f7ee..2f3af9edd4c2 100644
--- a/drivers/mtd/nand/raw/nand_spl_simple.c
+++ b/drivers/mtd/nand/raw/nand_spl_simple.c
@@ -10,13 +10,13 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
@@ -139,8 +139,8 @@ static int nand_read_page(int block, int page, uchar *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
@@ -170,8 +170,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
@@ -212,7 +212,7 @@ void nand_init(void)
*/
mtd = nand_to_mtd(&nand_chip);
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_SOFTECC
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 8b9ff4de1891..b7d261d8ce18 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -407,7 +407,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
- *buf++ = readl(CONFIG_SYS_NAND_BASE);
+ *buf++ = readl(CFG_SYS_NAND_BASE);
len -= 4;
}
} while (len);
diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index 13fd631cb402..d4b40e810f08 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c
@@ -812,7 +812,7 @@ void board_nand_init(void)
return;
}
- nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE;
err = vf610_nfc_nand_init(nfc, 0);
if (err)
printf("VF610 NAND init failed (err %d)\n", err);
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index a39fe5f28a87..fc21af56ec7b 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -93,8 +93,8 @@
#endif
#ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
-# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
+# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#endif
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index f0734712eaa5..f7c09a2333cb 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -94,8 +94,8 @@
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
-# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
+# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
index b0809332bb5a..a5518d3d50f2 100644
--- a/include/configs/MCR3000.h
+++ b/include/configs/MCR3000.h
@@ -82,6 +82,6 @@
/* Ethernet configuration part */
/* NAND configuration part */
-#define CONFIG_SYS_NAND_BASE 0x0C000000
+#define CFG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index bb93c2874417..c4cde1cc512e 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -141,7 +141,7 @@
/*
* NAND Flash on the Local Bus
*/
-#define CONFIG_SYS_NAND_BASE 0xE0600000
+#define CFG_SYS_NAND_BASE 0xE0600000
/* Vitesse 7385 */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 3448766d8e5d..3288969ce8ca 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -36,18 +36,18 @@
#ifdef CONFIG_MTD_RAW_NAND
#ifdef CONFIG_NXP_ESBC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
+#define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#else
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CFG_SYS_NAND_U_BOOT_START (0x11000000)
#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
+#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
+#define CFG_SYS_NAND_U_BOOT_START 0xD0000000
#endif
#endif
#endif
@@ -167,23 +167,23 @@ extern unsigned long get_sdram_size(void);
/* CFI for NOR Flash */
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
+#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
#define CONFIG_MTD_PARTITION
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
@@ -192,7 +192,7 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -201,49 +201,49 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_TARGET_P1010RDB_PA)
/* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
+#define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP(0x0C) | \
FTIM0_NAND_TWCHT(0x04) | \
FTIM0_NAND_TWH(0x05)
-#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
+#define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
FTIM1_NAND_TWBE(0x1d) | \
FTIM1_NAND_TRR(0x07) | \
FTIM1_NAND_TRP(0x0c)
-#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
+#define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
FTIM2_NAND_TREH(0x05) | \
FTIM2_NAND_TWHRE(0x0f)
-#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
+#define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
#elif defined(CONFIG_TARGET_P1010RDB_PB)
/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
#endif
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
@@ -259,13 +259,13 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
/* CPLD on IFC */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 08c1bccb2b74..b9311fc5e4f9 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -111,22 +111,22 @@
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CFG_SYS_NAND_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
+#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
+#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE}
/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+#define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 4b2327d32329..6eaa4144959d 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -22,9 +22,9 @@
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
+#define CFG_SYS_NAND_U_BOOT_START 0x30000000
#endif
#ifdef CONFIG_SPIFLASH
@@ -189,21 +189,21 @@
#endif
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -211,7 +211,7 @@
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
@@ -221,30 +221,30 @@
#endif
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@@ -262,14 +262,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index e7d82bf4118e..a9e6cfad4bc1 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -25,13 +25,13 @@
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image.
*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
+#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
CONFIG_U_BOOT_HDR_SIZE)
#else
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#endif
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
+#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
+#define CFG_SYS_NAND_U_BOOT_START 0x30000000
#endif
#ifdef CONFIG_SPIFLASH
@@ -178,17 +178,17 @@
#define CONFIG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -197,30 +197,30 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@@ -238,14 +238,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 08195505b1dc..47f499031e89 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -29,9 +29,9 @@
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#endif
#ifdef CONFIG_SPIFLASH
@@ -166,17 +166,17 @@
#define CONFIG_SYS_CS3_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@@ -185,30 +185,30 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@@ -242,14 +242,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 75d9200d568c..111f2e6245f9 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -24,9 +24,9 @@
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#endif
#ifdef CONFIG_SPIFLASH
@@ -142,17 +142,17 @@
#define CONFIG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@@ -161,30 +161,30 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@@ -202,14 +202,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index cfd9cb3e7c8d..b8232986be68 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -197,17 +197,17 @@
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@@ -216,30 +216,30 @@
| CSOR_NAND_PB(128)) /*Page Per Block = 128*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
@@ -257,14 +257,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 8eefaf24b28d..13b1ff3bce6e 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -171,7 +171,7 @@
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -179,8 +179,8 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* !CONFIG_MTD_RAW_NAND */
/* USB Device Firmware Update support */
diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h
index 7fa1847c1fc2..cb649b598fed 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h
@@ -91,7 +91,7 @@
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -113,8 +113,8 @@
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 26
#define MTDIDS_DEFAULT "nand0=nand.0"
#endif /* CONFIG_MTD_RAW_NAND */
diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index 3952783ee1a7..b7b1cb0cfe19 100644
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h
@@ -95,7 +95,7 @@
/* NAND support */
/* NAND config */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -103,7 +103,7 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* ! __CONFIG_IGEP003X_H */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 2eb7a51ce2eb..a9a4c8d17fc0 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -16,16 +16,16 @@
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
11, 12, 13, 14, 16, 17, 18, 19, 20, \
21, 22, 23, 24, 25, 26, 27, 28, 30, \
31, 32, 33, 34, 35, 36, 37, 38, 39, \
40, 41, 42, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56 }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 13
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* NAND block size is 128 KiB. Synchronize these values with
* corresponding Device Tree entries in Linux:
* MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index fc82a8c003e5..a0951fbf6235 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -120,7 +120,7 @@
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -142,8 +142,8 @@
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 26
#define NANDARGS \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 60b47379e5e2..574bfe37e9ad 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -43,11 +43,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
#endif
/* USB */
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index d80a686e9eef..2c785ad4264d 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -24,13 +24,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
+#define CFG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
+#define CFG_SYS_NAND_MASK_CLE (1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC15
#endif
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 89a8e43e1e09..bba8574b1c86 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -150,13 +150,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PA22
#endif
/* USB */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 55edd706ead9..3ce264a4a90b 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -20,23 +20,23 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
#ifdef CONFIG_SD_BOOT
#elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 00f57749ad4f..5e3ded241fa9 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -21,11 +21,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
+#define CFG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 0a512c217f8e..b79c8ba5bf86 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -25,13 +25,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD17
#endif
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index b8a14d571d6f..40ea4ed49e8a 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -27,13 +27,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif
/* SPL */
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index f4161d7a6de5..31f107a465c1 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -195,7 +195,7 @@
#ifndef CONFIG_NOR_BOOT
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -203,9 +203,9 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
#endif
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index fdbcbf5d96e2..bfa076b5cc98 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -108,7 +108,7 @@
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -116,7 +116,7 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* ! __CONFIG_CHILIBOARD_H */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 874c0eb2175a..2cb09fa30da2 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -128,7 +128,7 @@
#include <config_distro_bootcmd.h>
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* APBH DMA is required for NAND support */
/* Ethernet */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index f0fbbe2870bc..9061eba6686a 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -22,9 +22,9 @@
#endif
/* NAND support */
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index d7e181b942a2..afe8badd6502 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -122,8 +122,8 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
-/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
-#define CONFIG_SYS_NAND_BASE -1
+/* used to initialize CFG_SYS_NAND_BASE_LIST which is unused */
+#define CFG_SYS_NAND_BASE -1
#endif
/* USB Configs */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 5c7a9f2e69f2..f9bf849ae980 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -166,7 +166,7 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
#endif
/* USB Configs */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 3e7c0c0d883b..9d44e6723e2a 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -37,13 +37,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
/* DFU class support */
@@ -53,13 +53,13 @@
/* Defines for SPL */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 5a5c65da16c6..f8ba4e828194 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -107,21 +107,21 @@
* Flash & Environment
*/
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_ECCPOS { \
+#define CFG_SYS_NAND_CS 3
+#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE 0x10
+#define CFG_SYS_NAND_MASK_ALE 0x8
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x40000
+#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS { \
24, 25, 26, 27, 28, \
29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 10
#endif
#ifdef CONFIG_MTD_NOR_FLASH
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 42366123cb1e..5244b9cf5cc8 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -35,8 +35,8 @@
/*
* NAND controller
*/
-#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE SLC_NAND_BASE
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/*
* NAND chip timings
@@ -79,10 +79,10 @@
*/
/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x60000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
/* See common/spl/spl.c spl_set_header_raw_uboot() */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index d45115bdf683..46410595c2bc 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -100,12 +100,12 @@
/* Defines for SPL */
/* NAND boot config */
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x200000
#endif /* __CONFIG_H */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 6cf716e293d6..93201be485d6 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -75,15 +75,15 @@
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* !CONFIG_MTD_RAW_NAND */
/* Parallel NOR Support */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index 75322a37322c..6cae663cb8a0 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -14,10 +14,10 @@
#include "siemens-am33x-common.h"
/* NAND specific changes for etamin due to different page size */
-#undef CONFIG_SYS_NAND_ECCPOS
+#undef CFG_SYS_NAND_ECCPOS
#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -40,14 +40,14 @@
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
-#undef CONFIG_SYS_NAND_ECCSIZE
-#undef CONFIG_SYS_NAND_ECCBYTES
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
+#undef CFG_SYS_NAND_ECCSIZE
+#undef CFG_SYS_NAND_ECCBYTES
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 26
-#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
- CONFIG_SYS_NAND_BASE2}
+#define CFG_SYS_NAND_BASE2 (0x18000000) /* physical address */
+#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE, \
+ CFG_SYS_NAND_BASE2}
#define DDR_PLL_FREQ 303
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index a18920d3f09e..f19e12d90904 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -37,12 +37,12 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#endif
/* JFFS2 */
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index 3d62efb38ff9..ba098316e083 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -22,13 +22,13 @@
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NAND flash */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CFG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CFG_SYS_NAND_MASK_CLE BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
/* SPL */
@@ -37,8 +37,8 @@
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
#endif
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 232f7868cc25..974dff8f6f44 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -96,7 +96,7 @@
* NAND
*/
#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
-#define CONFIG_SYS_NAND_BASE 0xd8000000
+#define CFG_SYS_NAND_BASE 0xd8000000
#define CONFIG_MXC_NAND_HWECC
/*
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
index f52367cc1a0a..e430efad42e3 100644
--- a/include/configs/imx6-engicam.h
+++ b/include/configs/imx6-engicam.h
@@ -126,8 +126,8 @@
/* NAND */
#ifdef CONFIG_NAND_MXS
-# define CONFIG_SYS_NAND_BASE 0x40000000
-# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+# define CFG_SYS_NAND_BASE 0x40000000
+# define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* MTD device */
#endif
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 008fc079a65a..7760c8c418a1 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -116,8 +116,8 @@
/* Environment organization */
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* USB Configs */
#ifdef CONFIG_CMD_USB
diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h
index 46a96f1f828e..d42eb750d01b 100644
--- a/include/configs/imx6ulz_smm_m2.h
+++ b/include/configs/imx6ulz_smm_m2.h
@@ -72,6 +72,6 @@
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CFG_SYS_NAND_BASE 0x20000000
#endif
diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h
index a2323bd6716f..a768ff355109 100644
--- a/include/configs/imx8mn_bsh_smm_s2.h
+++ b/include/configs/imx8mn_bsh_smm_s2.h
@@ -44,6 +44,6 @@
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CFG_SYS_NAND_BASE 0x20000000
#endif /* __IMX8MN_BSH_SMM_S2_H */
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index 5be46090a145..8f2b474817d9 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -166,7 +166,7 @@
#ifdef CONFIG_NAND_MXS
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CFG_SYS_NAND_BASE 0x20000000
#endif /* CONFIG_NAND_MXS */
#endif /* __IMX8MP_RSB3720_H */
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 181ed1b8fae1..a658cbc07c20 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -59,7 +59,7 @@
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
+#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
#endif
/*
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index 0613b77e966f..d883b188ce3a 100644
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -77,17 +77,17 @@
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
/* NAND Flash Definitions */
-#define CONFIG_SYS_NAND_BASE 0x68000000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x68000000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_TE | \
CSPR_MSEL_NAND | \
CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
| CSOR_NAND_ECC_DEC_EN \
| CSOR_NAND_ECC_MODE_4 \
| CSOR_NAND_RAL_3 \
@@ -97,29 +97,29 @@
| CSOR_NAND_TRHZ_40 \
| CSOR_NAND_BCTLD)
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
FTIM0_NAND_TWCHT(0x3) | \
FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
FTIM1_NAND_TWBE(0x1e) | \
FTIM1_NAND_TRR(0x6) | \
FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
FTIM2_NAND_TREH(0x5) | \
FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */
#define CONFIG_SYS_QRIO_BASE 0x70000000
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 2e1459e3e4f2..51ee68655333 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -231,18 +231,18 @@
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC CS1*/
-#define CONFIG_SYS_NAND_BASE 0xfa000000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xfa000000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT (0x0f)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
0x00000010 | /* drive TE high */\
CSPR_MSEL_NAND | /* MSEL = NAND */\
CSPR_V) /* valid */
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \
CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \
CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \
@@ -253,30 +253,30 @@
CSOR_NAND_BCTLD) /**/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
FTIM0_NAND_TWCHT(0x3) | \
FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
FTIM1_NAND_TWBE(0x1e) | \
FTIM1_NAND_TRR(0x6) | \
FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
FTIM2_NAND_TREH(0x5) | \
FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
/* More NAND Flash Params */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO on IFC CS2 */
#define CONFIG_SYS_QRIO_BASE 0xfb000000
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index d6b60d8139a3..b95402987472 100644
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -12,7 +12,7 @@
#define CONFIG_NAND_ECC_BCH
#define CONFIG_NAND_KMETER1
#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 926c85805b79..7d89b5389522 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -11,9 +11,9 @@
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
@@ -70,17 +70,17 @@
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
@@ -88,20 +88,20 @@
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
/*
@@ -156,14 +156,14 @@
#endif
#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@@ -205,14 +205,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 8c19468141a8..47367845a07f 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -59,8 +59,8 @@
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index d207e475fc06..21263705c803 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -79,17 +79,17 @@
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
@@ -97,25 +97,25 @@
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10)
#endif
#if defined(CONFIG_TFABOOT) || \
@@ -188,14 +188,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
@@ -206,14 +206,14 @@
#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@@ -255,14 +255,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 206de7e1380c..51667f202580 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -51,16 +51,16 @@
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
@@ -68,24 +68,24 @@
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
#endif
/*
@@ -126,24 +126,24 @@
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
@@ -163,14 +163,14 @@
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#endif
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 7e1a724387ef..07ec2c956379 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -59,8 +59,8 @@
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
/* GPIO */
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 48408f285834..8402eac4184c 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -14,16 +14,16 @@
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
@@ -31,31 +31,31 @@
| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
/* EEPROM */
#define I2C_RETIMER_ADDR 0x18
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 037d462b5dfc..d51209c60f2d 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -95,17 +95,17 @@
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
@@ -113,25 +113,25 @@
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#endif
#if defined(CONFIG_TFABOOT) || \
@@ -204,14 +204,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
@@ -222,14 +222,14 @@
#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
@@ -271,14 +271,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 769349336af9..0df689159892 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -19,16 +19,16 @@
#define CONFIG_SYS_UBOOT_BASE 0x40100000
#endif
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
@@ -36,20 +36,20 @@
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
/*
@@ -78,14 +78,14 @@
#define CONFIG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 73e4ac3e3d4c..dec661d6b194 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -88,8 +88,8 @@ unsigned long long get_qixis_addr(void);
#define QIXIS_BASE_PHYS_EARLY 0xC000000
-#define CONFIG_SYS_NAND_BASE 0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
+#define CFG_SYS_NAND_BASE 0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS 0x30000000
/* MC firmware */
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 3a2fba6b04ee..ae452075ac0d 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -69,14 +69,14 @@
#endif
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -85,20 +85,20 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
@@ -174,14 +174,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
@@ -193,14 +193,14 @@
#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
@@ -230,14 +230,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index e2ae3026c29e..2ca1384c2315 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -53,14 +53,14 @@
#endif
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -69,20 +69,20 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
@@ -132,14 +132,14 @@
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 53a3af1baaca..d8997208e973 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -81,8 +81,8 @@ unsigned long long get_qixis_addr(void);
#define QIXIS_SDID_MASK 0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
-#define CONFIG_SYS_NAND_BASE 0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
+#define CFG_SYS_NAND_BASE 0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS 0x30000000
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
@@ -129,8 +129,8 @@ unsigned long long get_qixis_addr(void);
" 0x580e00000 \0"
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_U_BOOT_DST 0x80400000
+#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
#endif
#include <asm/arch/soc.h>
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index e6019870d8a3..d9e11cc19179 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -70,14 +70,14 @@
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -86,20 +86,20 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
@@ -163,16 +163,16 @@
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
#endif
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
@@ -194,14 +194,14 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 382d516c08bc..086c46902c86 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -67,14 +67,14 @@
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -83,20 +83,20 @@
| CSOR_NAND_PB(128)) /* Pages Per Block 128*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
FTIM0_NAND_TWP(0x30) | \
FTIM0_NAND_TWCHT(0x0e) | \
FTIM0_NAND_TWH(0x14))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
FTIM1_NAND_TWBE(0xab) | \
FTIM1_NAND_TRR(0x1c) | \
FTIM1_NAND_TRP(0x30))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
FTIM2_NAND_TREH(0x14) | \
FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
@@ -146,16 +146,16 @@
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
@@ -166,14 +166,14 @@
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 36522419172e..1734f323f929 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -44,10 +44,10 @@
* NAND
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
+#define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC
#endif
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 30267e29a126..cd3910ee4ba6 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -52,11 +52,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
-# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
+# define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
+# define CFG_SYS_NAND_MASK_ALE (1 << 21)
+# define CFG_SYS_NAND_MASK_CLE (1 << 22)
+# define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
+# define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
#endif
/* hw-controller addresses */
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
index 61570b7af534..8176566f3f61 100644
--- a/include/configs/mx6sabreauto.h
+++ b/include/configs/mx6sabreauto.h
@@ -36,7 +36,7 @@
#define CFG_SYS_FSL_USDHC_NUM 2
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 0d9764e3b4c1..a41e428eb8ad 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -86,7 +86,7 @@
#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 2a97d2fac465..af176583814f 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -93,7 +93,7 @@
*/
#ifdef CONFIG_NAND_MXS
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
#endif
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index e8610386f04e..9d6b3d404844 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -83,7 +83,7 @@
/* NAND */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CFG_SYS_NAND_BASE 0x60000000
#endif
/* OCOTP */
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index a777305ec76e..e18d16cc99c7 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h
@@ -30,7 +30,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h
index ccc203f5f24d..2a5288508299 100644
--- a/include/configs/npi_imx6ull.h
+++ b/include/configs/npi_imx6ull.h
@@ -31,7 +31,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index d46ca337d5f8..0890f51eff28 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -21,10 +21,10 @@
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 3
/* NAND: SPL falcon mode configs */
#endif /* CONFIG_MTD_RAW_NAND */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 77629d7fc1ea..6eec955e88f7 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -26,10 +26,10 @@
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 3
#endif /* CONFIG_MTD_RAW_NAND */
#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 97f47ea5b710..10f6ba63601a 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -70,14 +70,14 @@
#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
/* NAND config */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 7c0bdcbb1151..6001037ae886 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -17,15 +17,15 @@
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND devices */
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
13, 14, 16, 17, 18, 19, 20, 21, 22, \
23, 24, 25, 26, 27, 28, 30, 31, 32, \
33, 34, 35, 36, 37, 38, 39, 40, 41, \
42, 44, 45, 46, 47, 48, 49, 50, 51, \
52, 53, 54, 55, 56}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 13
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 13
#endif
/* Environment information */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index d9f70c75323f..81ca68de9bcc 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -105,21 +105,21 @@
* Flash & Environment
*/
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
+#define CFG_SYS_NAND_CS 3
+#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE 0x10
+#define CFG_SYS_NAND_MASK_ALE 0x8
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_ECCPOS { \
+#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
+#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS { \
6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 10
#endif
/*
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 778bf5112af1..38f360b53ca0 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -98,13 +98,13 @@
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CFG_SYS_NAND_U_BOOT_START (0x11000000)
#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CFG_SYS_NAND_U_BOOT_START 0xf8f80000
#endif /* not CONFIG_TPL_BUILD */
#endif
@@ -207,22 +207,22 @@
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
+#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
+#define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
@@ -231,7 +231,7 @@
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#else
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
+#define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index dea87122ebc6..bc04c5082188 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -42,7 +42,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index 2bdae8afa8c1..817fabfb97ce 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -44,7 +44,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
index f69d8adb91ca..c5817b010f8a 100644
--- a/include/configs/phycore_am335x_r2.h
+++ b/include/configs/phycore_am335x_r2.h
@@ -84,7 +84,7 @@
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -92,8 +92,8 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* !CONFIG_MTD_RAW_NAND */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 6a89fb1fa9a4..adb2f43ea4d1 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -129,13 +129,13 @@
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* NAND flash */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
+#define CFG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
+#define CFG_SYS_NAND_MASK_CLE (1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
/* NOR flash */
#define PHYS_FLASH_1 0x10000000
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index c56db4d793d3..4352a242de33 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -146,13 +146,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
#endif
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 7d3a326deaf0..a7deaa321371 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -25,13 +25,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CFG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
+#define CFG_SYS_NAND_MASK_CLE BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD3
#endif
#ifdef CONFIG_NAND_BOOT
@@ -44,11 +44,11 @@
#ifdef CONFIG_SD_BOOT
#elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
index ebf5467ef41e..f9decb2a4c2c 100644
--- a/include/configs/presidio_asic.h
+++ b/include/configs/presidio_asic.h
@@ -58,8 +58,8 @@
/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
- #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
- #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+ #define CFG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
+ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
#endif /* __PRESIDIO_ASIC_H */
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index 70c6ec5b65c6..7c5bfdb2e6d3 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -28,11 +28,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
-#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CFG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_MASK_ALE BIT(21)
+#define CFG_SYS_NAND_MASK_CLE BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif
#endif
diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h
index 9281c7ccc402..09cc4dddb2ad 100644
--- a/include/configs/sama5d2_ptc_ek.h
+++ b/include/configs/sama5d2_ptc_ek.h
@@ -21,11 +21,11 @@
/* NAND Flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CFG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
+#define CFG_SYS_NAND_MASK_CLE BIT(22)
#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index eed688d6b3e4..1c9af9b6759a 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -29,11 +29,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CFG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#endif
/* SPL */
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index b05fa59d7226..afb9b9a2fbf6 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -38,11 +38,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CFG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#endif
/* SPL */
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index c4552c269752..0daadec5536b 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -17,11 +17,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x80000000
+#define CFG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#endif
/* SPL */
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index d7199921ba3c..d59899f0baa0 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -17,11 +17,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x80000000
+#define CFG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#endif
/* SPL */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index dd247d2fd981..d071f590f106 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -48,7 +48,7 @@
/* Defines for SPL */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -56,10 +56,10 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
@@ -361,7 +361,7 @@
*/
-#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
+#define CFG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
/* CS0 */
#endif
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 5460c12a17e8..7c8f1676be26 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -54,11 +54,11 @@
*/
/* NAND flash settings */
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
/* serial console */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
@@ -92,13 +92,13 @@
/* Defines for SPL */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index 29462c526ec5..7c35c912e597 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -29,11 +29,11 @@
/* Mem test settings */
/* NAND Flash */
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
+#define CFG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
/* UARTs/Serial console */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 704a7141d7e3..70a24ed267ef 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -71,8 +71,8 @@
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
-#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
+#define CFG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
+#define CFG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
/*
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 3c978f5ee4ec..388a4e42efb9 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -99,7 +99,7 @@
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
+#define CFG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index f130c630dde8..dd1fe0af7cd2 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -54,11 +54,11 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
#endif
#if defined(CONFIG_BOARD_TAURUS)
@@ -126,13 +126,13 @@
/* Defines for SPL */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 82add65ec0dd..efd3a0db04eb 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -42,13 +42,13 @@
* GPMC NAND block. We support 1 device and the physical address to
* access CS0 at is 0x8000000.
*/
-#define CONFIG_SYS_NAND_BASE 0x8000000
+#define CFG_SYS_NAND_BASE 0x8000000
/* NAND: SPL related configs */
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -56,8 +56,8 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
/* SPL */
/* Defines for SPL */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 05536c3eedc8..b289b9e26a00 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -123,7 +123,7 @@
/* General parts of the framework, required. */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
#endif /* !CONFIG_NOR_BOOT */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index b8b4b28b3d67..a4a45fad9dc8 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -62,12 +62,12 @@
/* EEPROM definitions */
/* NAND Configuration */
-#define CONFIG_SYS_NAND_MASK_CLE 0x4000
-#define CONFIG_SYS_NAND_MASK_ALE 0x2000
-#define CONFIG_SYS_NAND_CS 2
+#define CFG_SYS_NAND_MASK_CLE 0x4000
+#define CFG_SYS_NAND_MASK_ALE 0x2000
+#define CFG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
+#define CFG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_BASE_LIST { 0x30000000, }
#define DFU_ALT_INFO_MMC \
"dfu_alt_info_mmc=" \
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index 44706c7733a0..d34042af4682 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h
@@ -16,8 +16,8 @@
* access CS0 at is 0x8000000.
*/
#ifdef CONFIG_MTD_RAW_NAND
-#ifndef CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE 0x8000000
+#ifndef CFG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x8000000
#endif
#endif
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 47f3c813b333..6cc443c8e9cb 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -55,7 +55,7 @@
/* SPL */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_BASE 0x30000000
+#define CFG_SYS_NAND_BASE 0x30000000
#endif
/* Now bring in the rest of the common code. */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 32b47db346f7..a57ecffd5961 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -40,8 +40,8 @@
#define CONFIG_SYS_TIMER_RATE 1000000
#endif
-#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
-#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
+#define CFG_SYS_NAND_REGS_BASE 0x68100000
+#define CFG_SYS_NAND_DATA_BASE 0x68000000
/*
* Network Configuration
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 44eaeda432a7..2cdc3fbf737f 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -33,13 +33,13 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
#endif
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 7e3d3473b442..215149af2e0b 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -14,7 +14,7 @@
/* NAND support */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
+#define CFG_SYS_NAND_BASE NFC_BASE_ADDR
/* Dynamic MTD partition support */
#endif
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index a7c805c2d6fc..054eb89d49ca 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -43,7 +43,7 @@
/* driver configuration */
#define CONFIG_SYS_MAX_NAND_CHIPS 1
-#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
+#define CFG_SYS_NAND_BASE MLC_NAND_BASE
/*
* GPIO
@@ -63,8 +63,8 @@
/* SPL will use serial */
/* SPL will load U-Boot from NAND offset 0x40000 */
/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
/*
* Include SoC specific configuration
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
` (8 preceding siblings ...)
2022-11-12 22:36 ` [PATCH 10/10] global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_* Tom Rini
@ 2022-11-14 22:49 ` Simon Glass
2022-12-06 2:06 ` Tom Rini
10 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:49 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:37, Tom Rini <trini@konsulko.com> wrote:
>
> This converts the following to Kconfig:
> CONFIG_SYS_NAND_DBW_8
> CONFIG_SYS_NAND_DBW_16
>
> Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16
> being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of
> the configs set CONFIG_SYS_NAND_DBW_8. So we introduce
> CONFIG_SYS_NAND_DBW_16 as an option.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> drivers/mtd/nand/raw/Kconfig | 12 ++++++++++++
> include/configs/at91sam9260ek.h | 1 -
> include/configs/at91sam9261ek.h | 1 -
> include/configs/at91sam9263ek.h | 1 -
> include/configs/at91sam9m10g45ek.h | 1 -
> include/configs/at91sam9rlek.h | 1 -
> include/configs/at91sam9x5ek.h | 1 -
> include/configs/corvus.h | 1 -
> include/configs/ethernut5.h | 1 -
> include/configs/gardena-smart-gateway-at91sam.h | 1 -
> include/configs/meesc.h | 1 -
> include/configs/pm9261.h | 1 -
> include/configs/pm9263.h | 1 -
> include/configs/pm9g45.h | 1 -
> include/configs/smartweb.h | 1 -
> include/configs/snapper9g45.h | 1 -
> include/configs/taurus.h | 1 -
> 17 files changed, 12 insertions(+), 16 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 02/10] Remove unused symbols
2022-11-12 22:36 ` [PATCH 02/10] Remove unused symbols Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:37, Tom Rini <trini@konsulko.com> wrote:
>
> This commit removes the following unused symbols:
> CONFIG_SYS_NAND_DDR_LAW
> CONFIG_SYS_NAND_ECCSTEPS
> CONFIG_SYS_NAND_ECCTOTAL
> CONFIG_SYS_NAND_ENABLE_PIN_SPL
> CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
> CONFIG_SYS_NAND_U_BOOT_RELOC_SP
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> include/configs/P1010RDB.h | 2 --
> include/configs/T102xRDB.h | 1 -
> include/configs/T104xRDB.h | 1 -
> include/configs/T208xQDS.h | 1 -
> include/configs/T208xRDB.h | 1 -
> include/configs/T4240RDB.h | 1 -
> include/configs/colibri_imx7.h | 1 -
> include/configs/da850evm.h | 4 ----
> include/configs/omapl138_lcdk.h | 4 ----
> include/configs/siemens-am33x-common.h | 4 ----
> include/configs/smartweb.h | 1 -
> include/configs/taurus.h | 1 -
> 12 files changed, 22 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 03/10] Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig
2022-11-12 22:36 ` [PATCH 03/10] Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:37, Tom Rini <trini@konsulko.com> wrote:
>
> This converts the following to Kconfig:
> CONFIG_SYS_NAND_HW_ECC_OOBFIRST
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> README | 4 ----
> configs/da850evm_nand_defconfig | 1 +
> configs/omapl138_lcdk_defconfig | 1 +
> drivers/mtd/nand/raw/Kconfig | 5 +++++
> include/configs/da850evm.h | 1 -
> include/configs/omapl138_lcdk.h | 1 -
> 6 files changed, 7 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 04/10] Convert CONFIG_SYS_NAND_HW_ECC to Kconfig
2022-11-12 22:36 ` [PATCH 04/10] Convert CONFIG_SYS_NAND_HW_ECC " Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:38, Tom Rini <trini@konsulko.com> wrote:
>
> This converts the following to Kconfig:
> CONFIG_SYS_NAND_HW_ECC
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> configs/da850evm_nand_defconfig | 1 -
> configs/k2e_evm_defconfig | 1 -
> configs/k2e_hs_evm_defconfig | 1 -
> configs/k2hk_evm_defconfig | 1 -
> configs/k2hk_hs_evm_defconfig | 1 -
> configs/k2l_evm_defconfig | 1 -
> configs/k2l_hs_evm_defconfig | 1 -
> configs/omapl138_lcdk_defconfig | 1 -
> drivers/mtd/nand/raw/Kconfig | 14 +++++++++++++-
> drivers/mtd/nand/raw/davinci_nand.c | 7 +++----
> include/configs/da850evm.h | 1 -
> include/configs/omapl138_lcdk.h | 1 -
> 12 files changed, 16 insertions(+), 15 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 05/10] mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly
2022-11-12 22:36 ` [PATCH 05/10] mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:37, Tom Rini <trini@konsulko.com> wrote:
>
> This is the only driver, and only one platform makes use of, setting
> CONFIG_SYS_NAND_ECC_BASE. Reference ATMEL_BASE_ECC directly in this
> case.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> drivers/mtd/nand/raw/atmel_nand.c | 18 +++++++++---------
> include/configs/snapper9g45.h | 1 -
> 2 files changed, 9 insertions(+), 10 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 06/10] Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig
2022-11-12 22:36 ` [PATCH 06/10] Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:38, Tom Rini <trini@konsulko.com> wrote:
>
> This converts the following to Kconfig:
> CONFIG_SYS_NAND_MAX_OOBFREE
> CONFIG_SYS_NAND_MAX_ECCPOS
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> configs/CHIP_pro_defconfig | 1 +
> configs/Nintendo_NES_Classic_Edition_defconfig | 1 +
> configs/am3517_evm_defconfig | 2 ++
> configs/ls1088aqds_defconfig | 2 ++
> configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 ++
> configs/ls1088aqds_qspi_defconfig | 2 ++
> configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++
> configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++
> configs/ls1088aqds_tfa_defconfig | 2 ++
> configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 ++
> configs/ls1088ardb_qspi_defconfig | 2 ++
> ...s1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 ++
> configs/ls1088ardb_sdcard_qspi_defconfig | 2 ++
> configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 ++
> configs/ls1088ardb_tfa_defconfig | 2 ++
> configs/ls2080aqds_SECURE_BOOT_defconfig | 2 ++
> configs/ls2080aqds_defconfig | 2 ++
> configs/ls2080aqds_nand_defconfig | 2 ++
> configs/ls2080aqds_qspi_defconfig | 2 ++
> configs/ls2080aqds_sdcard_defconfig | 2 ++
> configs/ls2080ardb_SECURE_BOOT_defconfig | 2 ++
> configs/ls2080ardb_defconfig | 2 ++
> configs/ls2080ardb_nand_defconfig | 2 ++
> configs/ls2088aqds_tfa_defconfig | 2 ++
> configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 ++
> configs/ls2088ardb_tfa_defconfig | 2 ++
> configs/omap35_logic_defconfig | 2 ++
> configs/omap35_logic_somlv_defconfig | 2 ++
> configs/omap3_logic_defconfig | 2 ++
> configs/omap3_logic_somlv_defconfig | 2 ++
> doc/README.nand | 10 ----------
> drivers/mtd/Kconfig | 18 ++++++++++++++++++
> include/configs/T4240RDB.h | 2 --
> include/configs/am3517_evm.h | 2 --
> include/configs/ls1088aqds.h | 3 ---
> include/configs/ls1088ardb.h | 3 ---
> include/configs/ls2080aqds.h | 3 ---
> include/configs/ls2080ardb.h | 3 ---
> include/configs/omap3_logic.h | 2 --
> include/configs/sunxi-common.h | 4 ----
> 40 files changed, 76 insertions(+), 32 deletions(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 07/10] Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE to Kconfig
2022-11-12 22:36 ` [PATCH 07/10] Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE " Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:37, Tom Rini <trini@konsulko.com> wrote:
>
> This converts the following to Kconfig:
> CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> README | 5 -----
> configs/k2e_evm_defconfig | 1 +
> configs/k2e_hs_evm_defconfig | 1 +
> configs/k2hk_evm_defconfig | 1 +
> configs/k2hk_hs_evm_defconfig | 1 +
> configs/k2l_evm_defconfig | 1 +
> configs/k2l_hs_evm_defconfig | 1 +
> drivers/mtd/nand/raw/Kconfig | 4 ++++
> include/configs/ti_armv7_keystone2.h | 1 -
> 9 files changed, 10 insertions(+), 6 deletions(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 08/10] Convert CONFIG_SYS_NAND_PAGE_2K et al to Kconfig
2022-11-12 22:36 ` [PATCH 08/10] Convert CONFIG_SYS_NAND_PAGE_2K et al " Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:38, Tom Rini <trini@konsulko.com> wrote:
>
> This converts the following to Kconfig:
> CONFIG_SYS_NAND_PAGE_2K
> CONFIG_SYS_NAND_PAGE_4K
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> configs/k2l_evm_defconfig | 1 +
> configs/k2l_hs_evm_defconfig | 1 +
> drivers/mtd/nand/raw/Kconfig | 13 +++++++++++++
> include/configs/da850evm.h | 1 -
> include/configs/k2e_evm.h | 3 ---
> include/configs/k2g_evm.h | 3 ---
> include/configs/k2hk_evm.h | 3 ---
> include/configs/k2l_evm.h | 3 ---
> include/configs/omapl138_lcdk.h | 1 -
> 9 files changed, 15 insertions(+), 14 deletions(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 09/10] Convert CONFIG_SYS_NAND_SIZE to Kconfig
2022-11-12 22:36 ` [PATCH 09/10] Convert CONFIG_SYS_NAND_SIZE " Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sat, 12 Nov 2022 at 15:38, Tom Rini <trini@konsulko.com> wrote:
>
> This converts the following to Kconfig:
> CONFIG_SYS_NAND_SIZE
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> drivers/mtd/nand/raw/Kconfig | 5 +++++
> include/configs/M5329EVB.h | 1 -
> include/configs/M5373EVB.h | 1 -
> include/configs/m53menlo.h | 6 ------
> include/configs/smartweb.h | 1 -
> include/configs/taurus.h | 1 -
> 6 files changed, 5 insertions(+), 10 deletions(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 10/10] global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*
2022-11-12 22:36 ` [PATCH 10/10] global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_* Tom Rini
@ 2022-11-14 22:50 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2022-11-14 22:50 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
n Sat, 12 Nov 2022 at 15:38, Tom Rini <trini@konsulko.com> wrote:
>
> The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
> namespace do not easily transition to Kconfig. In many cases they likely
> should come from the device tree instead. Move these out of CONFIG
> namespace and in to CFG namespace.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> README | 10 +--
> arch/arm/include/asm/arch-lpc32xx/config.h | 8 +-
> arch/arm/include/asm/ti-common/davinci_nand.h | 8 +-
> arch/arm/mach-kirkwood/include/mach/config.h | 2 +-
> arch/arm/mach-omap2/mem-common.c | 2 +-
> arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 20 ++---
> arch/powerpc/cpu/mpc83xx/spl_minimal.c | 10 +--
> board/atmel/at91sam9260ek/at91sam9260ek.c | 4 +-
> board/atmel/at91sam9261ek/at91sam9261ek.c | 4 +-
> board/atmel/at91sam9263ek/at91sam9263ek.c | 4 +-
> .../atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 4 +-
> board/atmel/at91sam9rlek/at91sam9rlek.c | 4 +-
> board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 +-
> board/atmel/sam9x60ek/sam9x60ek.c | 4 +-
> board/bluewater/gurnard/gurnard.c | 8 +-
> board/calao/usb_a9263/usb_a9263.c | 8 +-
> board/egnite/ethernut5/ethernut5.c | 6 +-
> board/esd/meesc/meesc.c | 4 +-
> board/freescale/common/p_corenet/law.c | 4 +-
> board/freescale/common/p_corenet/tlb.c | 4 +-
> board/freescale/ls1043aqds/ls1043aqds.c | 32 ++++----
> board/freescale/ls1043ardb/ls1043ardb.c | 34 ++++----
> board/freescale/ls1046aqds/ls1046aqds.c | 32 ++++----
> board/freescale/ls1088a/ls1088a.c | 32 ++++----
> board/freescale/p1010rdb/law.c | 2 +-
> board/freescale/p1010rdb/spl_minimal.c | 6 +-
> board/freescale/p1010rdb/tlb.c | 2 +-
> board/freescale/p1_p2_rdb_pc/law.c | 4 +-
> board/freescale/p1_p2_rdb_pc/spl_minimal.c | 6 +-
> board/freescale/p1_p2_rdb_pc/tlb.c | 4 +-
> board/freescale/t102xrdb/law.c | 4 +-
> board/freescale/t102xrdb/tlb.c | 4 +-
> board/freescale/t104xrdb/law.c | 4 +-
> board/freescale/t104xrdb/tlb.c | 4 +-
> board/freescale/t208xqds/law.c | 4 +-
> board/freescale/t208xqds/tlb.c | 4 +-
> board/freescale/t208xrdb/law.c | 4 +-
> board/freescale/t208xrdb/tlb.c | 4 +-
> board/freescale/t4rdb/law.c | 4 +-
> board/freescale/t4rdb/tlb.c | 4 +-
> board/gardena/smart-gateway-at91sam/spl.c | 4 +-
> board/keymile/kmcent2/law.c | 2 +-
> board/keymile/kmcent2/tlb.c | 2 +-
> board/ronetix/pm9261/pm9261.c | 4 +-
> board/ronetix/pm9263/pm9263.c | 4 +-
> board/ronetix/pm9g45/pm9g45.c | 6 +-
> board/siemens/corvus/board.c | 8 +-
> board/siemens/smartweb/smartweb.c | 8 +-
> board/siemens/taurus/taurus.c | 10 +--
> board/socrates/nand.c | 2 +-
> common/spl/spl_nand.c | 8 +-
> doc/README.arm-relocation | 8 +-
> doc/README.omap3 | 6 +-
> doc/board/ti/am335x_evm.rst | 2 +-
> drivers/mtd/nand/raw/am335x_spl_bch.c | 12 +--
> drivers/mtd/nand/raw/atmel_nand.c | 40 +++++-----
> drivers/mtd/nand/raw/davinci_nand.c | 14 ++--
> drivers/mtd/nand/raw/denali_spl.c | 4 +-
> drivers/mtd/nand/raw/fsl_elbc_nand.c | 6 +-
> drivers/mtd/nand/raw/fsl_elbc_spl.c | 12 +--
> drivers/mtd/nand/raw/fsl_ifc_nand.c | 6 +-
> drivers/mtd/nand/raw/fsl_ifc_spl.c | 20 ++---
> drivers/mtd/nand/raw/fsmc_nand.c | 2 +-
> drivers/mtd/nand/raw/kmeter1_nand.c | 4 +-
> drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 22 +++---
> drivers/mtd/nand/raw/mxc_nand.c | 6 +-
> drivers/mtd/nand/raw/mxc_nand_spl.c | 8 +-
> drivers/mtd/nand/raw/nand.c | 6 +-
> drivers/mtd/nand/raw/nand_spl_load.c | 6 +-
> drivers/mtd/nand/raw/nand_spl_simple.c | 16 ++--
> drivers/mtd/nand/raw/omap_gpmc.c | 2 +-
> drivers/mtd/nand/raw/vf610_nfc.c | 2 +-
> include/configs/M5329EVB.h | 4 +-
> include/configs/M5373EVB.h | 4 +-
> include/configs/MCR3000.h | 2 +-
> include/configs/MPC837XERDB.h | 2 +-
> include/configs/P1010RDB.h | 78 +++++++++----------
> include/configs/P2041RDB.h | 12 +--
> include/configs/T102xRDB.h | 64 +++++++--------
> include/configs/T104xRDB.h | 62 +++++++--------
> include/configs/T208xQDS.h | 60 +++++++-------
> include/configs/T208xRDB.h | 60 +++++++-------
> include/configs/T4240RDB.h | 54 ++++++-------
> include/configs/am335x_evm.h | 6 +-
> include/configs/am335x_guardian.h | 6 +-
> include/configs/am335x_igep003x.h | 6 +-
> include/configs/am3517_evm.h | 8 +-
> include/configs/am43xx_evm.h | 6 +-
> include/configs/at91sam9260ek.h | 10 +--
> include/configs/at91sam9261ek.h | 10 +--
> include/configs/at91sam9263ek.h | 10 +--
> include/configs/at91sam9m10g45ek.h | 18 ++---
> include/configs/at91sam9n12ek.h | 10 +--
> include/configs/at91sam9rlek.h | 10 +--
> include/configs/at91sam9x5ek.h | 10 +--
> include/configs/baltos.h | 8 +-
> include/configs/chiliboard.h | 6 +-
> include/configs/cm_fx6.h | 2 +-
> include/configs/cm_t43.h | 6 +-
> include/configs/colibri-imx6ull.h | 4 +-
> include/configs/colibri_imx7.h | 2 +-
> include/configs/corvus.h | 22 +++---
> include/configs/da850evm.h | 20 ++---
> include/configs/devkit3250.h | 10 +--
> include/configs/devkit8000.h | 8 +-
> include/configs/dra7xx_evm.h | 6 +-
> include/configs/etamin.h | 18 ++---
> include/configs/ethernut5.h | 8 +-
> .../configs/gardena-smart-gateway-at91sam.h | 16 ++--
> include/configs/imx27lite-common.h | 2 +-
> include/configs/imx6-engicam.h | 4 +-
> include/configs/imx6_logic.h | 4 +-
> include/configs/imx6ulz_smm_m2.h | 2 +-
> include/configs/imx8mn_bsh_smm_s2.h | 2 +-
> include/configs/imx8mp_rsb3720.h | 2 +-
> include/configs/km/km-mpc83xx.h | 2 +-
> include/configs/km/pg-wcom-ls102xa.h | 42 +++++-----
> include/configs/kmcent2.h | 38 ++++-----
> include/configs/kmcoge5ne.h | 2 +-
> include/configs/ls1021aqds.h | 60 +++++++-------
> include/configs/ls1043a_common.h | 4 +-
> include/configs/ls1043aqds.h | 72 ++++++++---------
> include/configs/ls1043ardb.h | 72 ++++++++---------
> include/configs/ls1046a_common.h | 4 +-
> include/configs/ls1046afrwy.h | 38 ++++-----
> include/configs/ls1046aqds.h | 72 ++++++++---------
> include/configs/ls1046ardb.h | 38 ++++-----
> include/configs/ls1088a_common.h | 4 +-
> include/configs/ls1088aqds.h | 66 ++++++++--------
> include/configs/ls1088ardb.h | 34 ++++----
> include/configs/ls2080a_common.h | 8 +-
> include/configs/ls2080aqds.h | 54 ++++++-------
> include/configs/ls2080ardb.h | 54 ++++++-------
> include/configs/m53menlo.h | 4 +-
> include/configs/meesc.h | 10 +--
> include/configs/mx6sabreauto.h | 2 +-
> include/configs/mx6sxsabreauto.h | 2 +-
> include/configs/mx7dsabresd.h | 2 +-
> include/configs/mxs.h | 2 +-
> include/configs/mys_6ulx.h | 2 +-
> include/configs/npi_imx6ull.h | 2 +-
> include/configs/omap3_beagle.h | 6 +-
> include/configs/omap3_evm.h | 6 +-
> include/configs/omap3_igep00x0.h | 6 +-
> include/configs/omap3_logic.h | 6 +-
> include/configs/omapl138_lcdk.h | 20 ++---
> include/configs/p1_p2_rdb_pc.h | 26 +++----
> include/configs/pcl063.h | 2 +-
> include/configs/pcl063_ull.h | 2 +-
> include/configs/phycore_am335x_r2.h | 6 +-
> include/configs/pm9261.h | 10 +--
> include/configs/pm9263.h | 10 +--
> include/configs/pm9g45.h | 18 ++---
> include/configs/presidio_asic.h | 4 +-
> include/configs/sam9x60ek.h | 10 +--
> include/configs/sama5d2_ptc_ek.h | 6 +-
> include/configs/sama5d3_xplained.h | 6 +-
> include/configs/sama5d3xek.h | 6 +-
> include/configs/sama5d4_xplained.h | 6 +-
> include/configs/sama5d4ek.h | 6 +-
> include/configs/siemens-am33x-common.h | 10 +--
> include/configs/smartweb.h | 22 +++---
> include/configs/snapper9g45.h | 10 +--
> include/configs/socfpga_common.h | 4 +-
> include/configs/socrates.h | 2 +-
> include/configs/taurus.h | 22 +++---
> include/configs/ti816x_evm.h | 8 +-
> include/configs/ti_armv7_common.h | 2 +-
> include/configs/ti_armv7_keystone2.h | 10 +--
> include/configs/ti_armv7_omap.h | 4 +-
> include/configs/ti_omap3_common.h | 2 +-
> include/configs/uniphier.h | 4 +-
> include/configs/usb_a9263.h | 10 +--
> include/configs/vf610twr.h | 2 +-
> include/configs/work_92105.h | 6 +-
> 175 files changed, 1106 insertions(+), 1106 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
` (9 preceding siblings ...)
2022-11-14 22:49 ` [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Simon Glass
@ 2022-12-06 2:06 ` Tom Rini
10 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2022-12-06 2:06 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 571 bytes --]
On Sat, Nov 12, 2022 at 05:36:42PM -0500, Tom Rini wrote:
> This converts the following to Kconfig:
> CONFIG_SYS_NAND_DBW_8
> CONFIG_SYS_NAND_DBW_16
>
> Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16
> being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of
> the configs set CONFIG_SYS_NAND_DBW_8. So we introduce
> CONFIG_SYS_NAND_DBW_16 as an option.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
For the series, applied to u-boot/next, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2022-12-06 2:06 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-12 22:36 [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Tom Rini
2022-11-12 22:36 ` [PATCH 02/10] Remove unused symbols Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 03/10] Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 04/10] Convert CONFIG_SYS_NAND_HW_ECC " Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 05/10] mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 06/10] Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 07/10] Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE " Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 08/10] Convert CONFIG_SYS_NAND_PAGE_2K et al " Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 09/10] Convert CONFIG_SYS_NAND_SIZE " Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-12 22:36 ` [PATCH 10/10] global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_* Tom Rini
2022-11-14 22:50 ` Simon Glass
2022-11-14 22:49 ` [PATCH 01/10] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig Simon Glass
2022-12-06 2:06 ` Tom Rini
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