* [U-Boot] [PATCH v8 0/2] pinctrl: at91: Add pinctrl driver
@ 2017-03-23 4:44 Wenyou Yang
2017-03-23 4:44 ` [U-Boot] [PATCH v8 1/2] gpio: at91_gpio: remove CPU_HAS_PIO3 macro Wenyou Yang
2017-03-23 4:44 ` [U-Boot] [PATCH v8 2/2] pinctrl: at91: add pinctrl driver Wenyou Yang
0 siblings, 2 replies; 6+ messages in thread
From: Wenyou Yang @ 2017-03-23 4:44 UTC (permalink / raw)
To: u-boot
The purpose of this patch set is to add the pinctrl driver for AT91
PIO controller.
Changes in v8:
- Rebase on v2017.03.
Changes in v7:
- Fix the missing conversion for the at91_emac driver when building
the at91rm9200 devices.
Changes in v6:
- Move PIO_SCDR_DIV define from mach/<soc.h> to mach/at91_pio.h
to fix the build error.
Changes in v5:
- Rebase on the master branch on git://git.denx.de/u-boot-atmel.git
commit: 0ff27d4a94637d4b1937c625d33212375bd118d9
Changes in v4:
- Fix the incomplete conversion of the peripheral configurations on
the sama5d3, sam9x5, and sam9n12.
Changes in v3:
- Add support for OUTPUT config
Changes in v2:
- Add more information for the PINCTRL_AT91 option's help.
- Add more comments for the callback of struct at91_pinctrl_mux_ops.
- Use clrsetbits_le32() in set_drive_strength().
- Add the brackets for readability.
- Use debug() to print the message to debug, instead of printf().
- Remove not veryuseful at91_bank_base().
- Add Reviewed-by tag.
Wenyou Yang (2):
gpio: at91_gpio: remove CPU_HAS_PIO3 macro
pinctrl: at91: add pinctrl driver
arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 106 ++---
arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 112 ++---
arch/arm/mach-at91/armv7/sama5d3_devices.c | 140 +++----
arch/arm/mach-at91/include/mach/at91_pio.h | 69 ++--
arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 -
arch/arm/mach-at91/include/mach/sama5d3.h | 2 -
arch/arm/mach-at91/include/mach/sama5d4.h | 2 -
board/atmel/at91sam9n12ek/at91sam9n12ek.c | 10 +-
board/atmel/at91sam9x5ek/at91sam9x5ek.c | 90 ++--
board/atmel/sama5d3xek/sama5d3xek.c | 64 +--
board/atmel/sama5d4_xplained/sama5d4_xplained.c | 148 +++----
board/atmel/sama5d4ek/sama5d4ek.c | 136 +++----
board/denx/ma5d4evk/ma5d4evk.c | 178 ++++----
board/l+g/vinco/vinco.c | 70 ++--
drivers/gpio/at91_gpio.c | 142 +++++--
drivers/net/at91_emac.c | 4 +-
drivers/pinctrl/Kconfig | 14 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-at91.c | 453 +++++++++++++++++++++
include/dt-bindings/pinctrl/at91.h | 2 +
20 files changed, 1135 insertions(+), 610 deletions(-)
create mode 100644 drivers/pinctrl/pinctrl-at91.c
--
2.11.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v8 1/2] gpio: at91_gpio: remove CPU_HAS_PIO3 macro
2017-03-23 4:44 [U-Boot] [PATCH v8 0/2] pinctrl: at91: Add pinctrl driver Wenyou Yang
@ 2017-03-23 4:44 ` Wenyou Yang
2017-04-01 4:21 ` Simon Glass
2017-03-23 4:44 ` [U-Boot] [PATCH v8 2/2] pinctrl: at91: add pinctrl driver Wenyou Yang
1 sibling, 1 reply; 6+ messages in thread
From: Wenyou Yang @ 2017-03-23 4:44 UTC (permalink / raw)
To: u-boot
The intention of the removal is the preparation to introduce the
new AT91 PIO pinctrl driver.
Use the union to make the PIO3 and PIO2's registers be together
and make their offset aligned.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
Changes in v8: None
Changes in v7:
- Fix the missing conversion for the at91_emac driver when building
the at91rm9200 devices.
Changes in v6:
- Move PIO_SCDR_DIV define from mach/<soc.h> to mach/at91_pio.h
to fix the build error.
Changes in v5: None
Changes in v4:
- Fix the incomplete conversion of the peripheral configurations on
the sama5d3, sam9x5, and sam9n12.
Changes in v3: None
Changes in v2: None
arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 106 ++++++------
arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 112 ++++++-------
arch/arm/mach-at91/armv7/sama5d3_devices.c | 140 ++++++++--------
arch/arm/mach-at91/include/mach/at91_pio.h | 63 ++++----
arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 -
arch/arm/mach-at91/include/mach/sama5d3.h | 2 -
arch/arm/mach-at91/include/mach/sama5d4.h | 2 -
board/atmel/at91sam9n12ek/at91sam9n12ek.c | 10 +-
board/atmel/at91sam9x5ek/at91sam9x5ek.c | 90 +++++------
board/atmel/sama5d3xek/sama5d3xek.c | 64 ++++----
board/atmel/sama5d4_xplained/sama5d4_xplained.c | 148 ++++++++---------
board/atmel/sama5d4ek/sama5d4ek.c | 136 ++++++++--------
board/denx/ma5d4evk/ma5d4evk.c | 178 ++++++++++-----------
board/l+g/vinco/vinco.c | 70 ++++----
drivers/gpio/at91_gpio.c | 142 ++++++++++------
drivers/net/at91_emac.c | 4 +-
16 files changed, 660 insertions(+), 609 deletions(-)
diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c
index a03abfc310..28c8cf260a 100644
--- a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c
@@ -18,45 +18,45 @@ unsigned int has_lcdc()
void at91_serial0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void at91_serial3_hw_init(void)
{
- at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
- at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
at91_periph_clk_enable(ATMEL_ID_USART3);
}
void at91_seriald_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_periph_clk_enable(ATMEL_ID_SYS);
}
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI0);
@@ -72,9 +72,9 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI1);
@@ -91,12 +91,12 @@ void at91_spi1_hw_init(unsigned long cs_mask)
void at91_mci_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
at91_periph_clk_enable(ATMEL_ID_HSMCI0);
}
@@ -104,37 +104,37 @@ void at91_mci_hw_init(void)
#ifdef CONFIG_LCD
void at91_lcd_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
-
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
- at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
- at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
at91_periph_clk_enable(ATMEL_ID_LCDC);
}
diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c
index 3e4555a1a1..8de086efd6 100644
--- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c
@@ -64,32 +64,32 @@ char *get_cpu_name()
void at91_seriald_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
at91_periph_clk_enable(ATMEL_ID_SYS);
}
void at91_serial0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
at91_periph_clk_enable(ATMEL_ID_USART2);
}
@@ -97,12 +97,12 @@ void at91_serial2_hw_init(void)
void at91_mci_hw_init(void)
{
/* Initialize the MCI0 */
- at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
at91_periph_clk_enable(ATMEL_ID_HSMCI0);
}
@@ -110,20 +110,20 @@ void at91_mci_hw_init(void)
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0))
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);
if (cs_mask & (1 << 1))
- at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 7, 0);
if (cs_mask & (1 << 2))
- at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 1, 0);
if (cs_mask & (1 << 3))
- at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
+ at91_pio3_set_b_periph(AT91_PIO_PORTB, 3, 0);
if (cs_mask & (1 << 4))
at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
if (cs_mask & (1 << 5))
@@ -136,20 +136,20 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0))
- at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 8, 0);
if (cs_mask & (1 << 1))
- at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 0, 0);
if (cs_mask & (1 << 2))
- at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 31, 0);
if (cs_mask & (1 << 3))
- at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
+ at91_pio3_set_b_periph(AT91_PIO_PORTA, 30, 0);
if (cs_mask & (1 << 4))
at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
if (cs_mask & (1 << 5))
@@ -181,45 +181,45 @@ void at91_macb_hw_init(void)
/* Enable EMAC0 clock */
at91_periph_clk_enable(ATMEL_ID_EMAC0);
/* EMAC0 pins setup */
- at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
}
if (has_emac1()) {
/* Enable EMAC1 clock */
at91_periph_clk_enable(ATMEL_ID_EMAC1);
/* EMAC1 pins setup */
- at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
- at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
- at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
- at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
- at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
- at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
- at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
- at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
- at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
- at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
}
#ifndef CONFIG_RMII
/* Only emac0 support MII */
if (has_emac0()) {
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
}
#endif
}
diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c
index 64ac262818..6becdd7fee 100644
--- a/arch/arm/mach-at91/armv7/sama5d3_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c
@@ -52,8 +52,8 @@ char *get_cpu_name()
void at91_serial0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART0);
@@ -61,8 +61,8 @@ void at91_serial0_hw_init(void)
void at91_serial1_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART1);
@@ -70,8 +70,8 @@ void at91_serial1_hw_init(void)
void at91_serial2_hw_init(void)
{
- at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
- at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART2);
@@ -79,8 +79,8 @@ void at91_serial2_hw_init(void)
void at91_seriald_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
- at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_DBGU);
@@ -89,9 +89,9 @@ void at91_seriald_hw_init(void)
#if defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
if (cs_mask & (1 << 0))
at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
@@ -110,18 +110,18 @@ void at91_spi0_hw_init(unsigned long cs_mask)
#ifdef CONFIG_GENERIC_ATMEL_MCI
void at91_mci_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
- at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
- at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
- at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
- at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
#ifdef CONFIG_ATMEL_MCI_8BIT
- at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
- at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
- at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
- at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
#endif
- at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI0);
@@ -131,16 +131,16 @@ void at91_mci_hw_init(void)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_EMAC);
@@ -148,23 +148,23 @@ void at91_macb_hw_init(void)
void at91_gmac_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
-
- at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
-
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC);
@@ -174,30 +174,30 @@ void at91_gmac_hw_init(void)
#ifdef CONFIG_LCD
void at91_lcd_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
- at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
- at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
/* The lower 16-bit of LCD only available on Port A */
- at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index 301227880a..946f076714 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -32,6 +32,8 @@
#define AT91_ASM_PIOD_ASR \
(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
+#define PIO_SCDR_DIV 0x3fff /* Slow Clock Divider Selection for Debouncing Mask */
+
#ifndef __ASSEMBLY__
typedef struct at91_port {
@@ -63,28 +65,32 @@ typedef struct at91_port {
u32 puer; /* 0x64 Pull-up Enable Register */
u32 pusr; /* 0x68 Pad Pull-up Status Register */
u32 reserved4;
-#if defined(CPU_HAS_PIO3)
- u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
- u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
- u32 reserved5[2];
- u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
- u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
- u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
- u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
- u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
- u32 ppder; /* 0x94 Pad Pull-down Enable Register */
- u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
- u32 reserved6; /* */
-#else
- u32 asr; /* 0x70 Select A Register */
- u32 bsr; /* 0x74 Select B Register */
- u32 absr; /* 0x78 AB Select Status Register */
- u32 reserved5[9]; /* */
-#endif
+ union {
+ struct {
+ u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
+ u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
+ u32 reserved5[2];
+ u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
+ u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
+ u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
+ u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
+ u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
+ u32 ppder; /* 0x94 Pad Pull-down Enable Register */
+ u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
+ u32 reserved6; /* */
+ } pio3;
+
+ struct {
+ u32 asr; /* 0x70 Select A Register */
+ u32 bsr; /* 0x74 Select B Register */
+ u32 absr; /* 0x78 AB Select Status Register */
+ u32 reserved5[9]; /* */
+ } pio2;
+ } mux;
+
u32 ower; /* 0xA0 Output Write Enable Register */
u32 owdr; /* 0xA4 Output Write Disable Register */
u32 owsr; /* OxA8 Output Write Status Register */
-#if defined(CPU_HAS_PIO3)
u32 reserved7; /* */
u32 aimer; /* 0xB0 Additional INT Modes Enable Register */
u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */
@@ -104,9 +110,6 @@ typedef struct at91_port {
u32 reserved11[5]; /* */
u32 schmitt; /* 0x100 Schmitt Trigger Register */
u32 reserved12[63];
-#else
- u32 reserved6[85];
-#endif
} at91_port_t;
typedef union at91_pio {
@@ -123,13 +126,6 @@ typedef union at91_pio {
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
-#if defined(CPU_HAS_PIO3)
-int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
-int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
-#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int value);
@@ -138,6 +134,15 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
int at91_set_pio_value(unsigned port, unsigned pin, int value);
int at91_get_pio_value(unsigned port, unsigned pin);
+
+int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
+int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
#endif
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 8100ebed4b..e7224e432d 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -171,8 +171,6 @@
* Other misc defines
*/
#define ATMEL_PIO_PORTS 4
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
#define ATMEL_ID_UHP ATMEL_ID_UHPHS
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 33f6c97c11..d558f95141 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -188,8 +188,6 @@
* Other misc defines
*/
#define ATMEL_PIO_PORTS 5
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV 0x3fff
#define CPU_HAS_PCR
/* Timer */
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index 90085da1c6..78cc2a7a0a 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -174,8 +174,6 @@
* Other misc defines
*/
#define ATMEL_PIO_PORTS 5
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV 0x3fff
#define CPU_HAS_PCR
#define CPU_HAS_H32MXDIV
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index fc4f50d219..58da2d27f8 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -71,10 +71,10 @@ static void at91sam9n12ek_nand_hw_init(void)
/* Configure ENABLE pin for NandFlash */
at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
- at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
- at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
- at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
}
#endif
@@ -194,7 +194,7 @@ void at91sam9n12ek_ks8851_hw_init(void)
&smc->cs[2].mode);
/* Configure NCS2 PIN */
- at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
+ at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
}
#endif
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index b0d440d728..cc81776f9b 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -77,18 +77,18 @@ static void at91sam9x5ek_nand_hw_init(void)
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
- at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
- at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
- at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
- at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
- at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
}
#endif
@@ -128,49 +128,49 @@ vidinfo_t panel_info = {
void lcd_enable(void)
{
if (has_lcdc())
- at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
}
void lcd_disable(void)
{
if (has_lcdc())
- at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
}
static void at91sam9x5ek_lcd_hw_init(void)
{
if (has_lcdc()) {
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
- at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
-
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
- at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
- at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
at91_periph_clk_enable(ATMEL_ID_LCDC);
}
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index ce67478f0b..134c2fe1eb 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -95,31 +95,31 @@ static void sama5d3xek_nor_hw_init(void)
&smc->cs[0].mode);
/* Address pin (A1 ~ A23) configuration */
- at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
- at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
/* CS0 pin configuration */
- at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
+ at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
}
#endif
@@ -170,14 +170,14 @@ static void sama5d3xek_lcd_hw_init(void)
gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
/* The higher 8 bit of LCD is board related */
- at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
- at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
- at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
- at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
- at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
- at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
- at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
- at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
/* Configure lower 16 bit of LCD and enable clock */
at91_lcd_hw_init();
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 23ec274468..47f0bae8c1 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -45,9 +45,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
static void sama5d4_xplained_spi0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
@@ -82,20 +82,20 @@ static void sama5d4_xplained_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
- at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
- at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
}
#endif
@@ -134,39 +134,39 @@ unsigned int has_lcdc(void)
static void sama5d4_xplained_lcd_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
- at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
- at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
-
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
-
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
- at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
@@ -203,12 +203,12 @@ void lcd_show_board_info(void)
#ifdef CONFIG_GENERIC_ATMEL_MCI
void sama5d4_xplained_mci1_hw_init(void)
{
- at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
- at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
- at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
- at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
- at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
- at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
@@ -216,12 +216,12 @@ void sama5d4_xplained_mci1_hw_init(void)
* the power consumption will increase, so disable the interanl pull
* down to save the power.
*/
- at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI1);
@@ -239,16 +239,16 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MACB
void sama5d4_xplained_macb0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
@@ -257,8 +257,8 @@ void sama5d4_xplained_macb0_hw_init(void)
static void sama5d4_xplained_serial3_hw_init(void)
{
- at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
- at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART3);
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index 72bad23087..d1b5ff5797 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -45,9 +45,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
static void sama5d4ek_spi0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
@@ -82,20 +82,20 @@ static void sama5d4ek_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
- at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
- at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
}
#endif
@@ -135,33 +135,33 @@ unsigned int has_lcdc(void)
static void sama5d4ek_lcd_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
- at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
- at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
-
- at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
-
- at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
-
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
- at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
@@ -199,12 +199,12 @@ void lcd_show_board_info(void)
#ifdef CONFIG_GENERIC_ATMEL_MCI
void sama5d4ek_mci1_hw_init(void)
{
- at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
- at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
- at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
- at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
- at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
- at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
@@ -212,12 +212,12 @@ void sama5d4ek_mci1_hw_init(void)
* the power consumption will increase, so disable the interanl pull
* down to save the power.
*/
- at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI1);
@@ -235,16 +235,16 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MACB
void sama5d4ek_macb0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
@@ -253,8 +253,8 @@ void sama5d4ek_macb0_hw_init(void)
static void sama5d4ek_serial3_hw_init(void)
{
- at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
- at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART3);
diff --git a/board/denx/ma5d4evk/ma5d4evk.c b/board/denx/ma5d4evk/ma5d4evk.c
index ec0fa28f3e..81463712fa 100644
--- a/board/denx/ma5d4evk/ma5d4evk.c
+++ b/board/denx/ma5d4evk/ma5d4evk.c
@@ -44,9 +44,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
static void ma5d4evk_spi0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
@@ -90,39 +90,39 @@ unsigned int has_lcdc(void)
static void ma5d4evk_lcd_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
- at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
- at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
-
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
-
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
- at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
@@ -134,16 +134,16 @@ static void ma5d4evk_lcd_hw_init(void)
/* On-SoM eMMC */
void ma5d4evk_mci0_hw_init(void)
{
- at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
- at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
- at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
- at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
- at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
- at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
- at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
- at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
- at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
- at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
@@ -151,16 +151,16 @@ void ma5d4evk_mci0_hw_init(void)
* the power consumption will increase, so disable the internal pull
* down to save the power.
*/
- at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI0);
@@ -169,12 +169,12 @@ void ma5d4evk_mci0_hw_init(void)
/* On-board MicroSD slot */
void ma5d4evk_mci1_hw_init(void)
{
- at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
- at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
- at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
- at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
- at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
- at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
+ at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
@@ -182,16 +182,16 @@ void ma5d4evk_mci1_hw_init(void)
* the power consumption will increase, so disable the internal pull
* down to save the power.
*/
- at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
/* Deal with WP pin on the microSD slot. */
at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI1);
@@ -203,7 +203,7 @@ int board_mmc_init(bd_t *bis)
/* De-assert reset on On-SoM eMMC */
at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
- at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
ret = atmel_mci_init((void *)ATMEL_BASE_MCI0);
if (ret) /* eMMC init failed, skip it. */
@@ -223,16 +223,16 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MACB
void ma5d4evk_macb0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
@@ -242,17 +242,17 @@ void ma5d4evk_macb0_hw_init(void)
static void ma5d4evk_serial_hw_init(void)
{
/* USART0 */
- at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
- at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
- at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
at91_periph_clk_enable(ATMEL_ID_USART0);
/* USART1 */
- at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
- at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
- at91_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
at91_periph_clk_enable(ATMEL_ID_USART1);
}
@@ -273,7 +273,7 @@ int board_early_init_f(void)
at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
udelay(100);
at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
- at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
ma5d4evk_serial_hw_init();
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
index 3d7af092e8..a938a2c2e1 100644
--- a/board/l+g/vinco/vinco.c
+++ b/board/l+g/vinco/vinco.c
@@ -51,9 +51,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
static void vinco_spi0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
+ at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
@@ -76,16 +76,16 @@ static void vinco_usb_hw_init(void)
#ifdef CONFIG_GENERIC_ATMEL_MCI
void vinco_mci0_hw_init(void)
{
- at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */
- at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */
- at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */
- at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */
- at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */
- at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
- at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
- at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
- at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */
- at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
@@ -93,16 +93,16 @@ void vinco_mci0_hw_init(void)
* the power consumption will increase, so disable the interanl pull
* down to save the power.
*/
- at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
- at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
+ at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI0);
@@ -120,16 +120,16 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MACB
void vinco_macb0_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
@@ -141,8 +141,8 @@ void vinco_macb0_hw_init(void)
static void vinco_serial3_hw_init(void)
{
- at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
- at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
+ at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART3);
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 8e52e3dad0..2f9e44b620 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -59,11 +59,6 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
-#if defined(CPU_HAS_PIO3)
- if (use_pullup)
- at91_set_pio_pulldown(port, pin, 0);
-#endif
-
if (at91_port && (pin < GPIO_PER_BANK))
at91_set_port_pullup(at91_port, pin, use_pullup);
@@ -100,14 +95,7 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
-#if defined(CPU_HAS_PIO3)
- writel(readl(&at91_port->abcdsr1) & ~mask,
- &at91_port->abcdsr1);
- writel(readl(&at91_port->abcdsr2) & ~mask,
- &at91_port->abcdsr2);
-#else
- writel(mask, &at91_port->asr);
-#endif
+ writel(mask, &at91_port->mux.pio2.asr);
writel(mask, &at91_port->pdr);
}
@@ -126,25 +114,62 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
-#if defined(CPU_HAS_PIO3)
- writel(readl(&at91_port->abcdsr1) | mask,
- &at91_port->abcdsr1);
- writel(readl(&at91_port->abcdsr2) & ~mask,
- &at91_port->abcdsr2);
-#else
- writel(mask, &at91_port->bsr);
-#endif
+ writel(mask, &at91_port->mux.pio2.bsr);
+ writel(mask, &at91_port->pdr);
+ }
+
+ return 0;
+}
+
+/*
+ * mux the pin to the "A" internal peripheral role.
+ */
+int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
+{
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
+
+ if (at91_port && (pin < GPIO_PER_BANK)) {
+ mask = 1 << pin;
+ writel(mask, &at91_port->idr);
+ at91_set_pio_pullup(port, pin, use_pullup);
+ writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
+ &at91_port->mux.pio3.abcdsr1);
+ writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
+ &at91_port->mux.pio3.abcdsr2);
+
writel(mask, &at91_port->pdr);
}
return 0;
}
-#if defined(CPU_HAS_PIO3)
+/*
+ * mux the pin to the "B" internal peripheral role.
+ */
+int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
+{
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
+
+ if (at91_port && (pin < GPIO_PER_BANK)) {
+ mask = 1 << pin;
+ writel(mask, &at91_port->idr);
+ at91_set_pio_pullup(port, pin, use_pullup);
+ writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
+ &at91_port->mux.pio3.abcdsr1);
+ writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
+ &at91_port->mux.pio3.abcdsr2);
+
+ writel(mask, &at91_port->pdr);
+ }
+
+ return 0;
+}
/*
* mux the pin to the "C" internal peripheral role.
*/
-int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
+int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -153,10 +178,10 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
- writel(readl(&at91_port->abcdsr1) & ~mask,
- &at91_port->abcdsr1);
- writel(readl(&at91_port->abcdsr2) | mask,
- &at91_port->abcdsr2);
+ writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
+ &at91_port->mux.pio3.abcdsr1);
+ writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
+ &at91_port->mux.pio3.abcdsr2);
writel(mask, &at91_port->pdr);
}
@@ -166,7 +191,7 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
/*
* mux the pin to the "D" internal peripheral role.
*/
-int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
+int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -175,16 +200,15 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
- writel(readl(&at91_port->abcdsr1) | mask,
- &at91_port->abcdsr1);
- writel(readl(&at91_port->abcdsr2) | mask,
- &at91_port->abcdsr2);
+ writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
+ &at91_port->mux.pio3.abcdsr1);
+ writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
+ &at91_port->mux.pio3.abcdsr2);
writel(mask, &at91_port->pdr);
}
return 0;
}
-#endif
#ifdef CONFIG_DM_GPIO
static bool at91_get_port_output(struct at91_port *at91_port, int offset)
@@ -263,10 +287,27 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
+ if (is_on)
+ writel(mask, &at91_port->ifer);
+ else
+ writel(mask, &at91_port->ifdr);
+ }
+
+ return 0;
+}
+
+/*
+ * enable/disable the glitch filter. mostly used with IRQ handling.
+ */
+int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
+{
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
+
+ if (at91_port && (pin < GPIO_PER_BANK)) {
+ mask = 1 << pin;
if (is_on) {
-#if defined(CPU_HAS_PIO3)
- writel(mask, &at91_port->ifscdr);
-#endif
+ writel(mask, &at91_port->mux.pio3.ifscdr);
writel(mask, &at91_port->ifer);
} else {
writel(mask, &at91_port->ifdr);
@@ -276,11 +317,10 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
return 0;
}
-#if defined(CPU_HAS_PIO3)
/*
* enable/disable the debounce filter.
*/
-int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
+int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -288,8 +328,8 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
if (is_on) {
- writel(mask, &at91_port->ifscer);
- writel(div & PIO_SCDR_DIV, &at91_port->scdr);
+ writel(mask, &at91_port->mux.pio3.ifscer);
+ writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
writel(mask, &at91_port->ifer);
} else {
writel(mask, &at91_port->ifdr);
@@ -303,7 +343,7 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
* enable/disable the pull-down.
* If pull-up already enabled while calling the function, we disable it.
*/
-int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
+int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -312,18 +352,31 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
mask = 1 << pin;
if (is_on) {
at91_set_pio_pullup(port, pin, 0);
- writel(mask, &at91_port->ppder);
+ writel(mask, &at91_port->mux.pio3.ppder);
} else
- writel(mask, &at91_port->ppddr);
+ writel(mask, &at91_port->mux.pio3.ppddr);
}
return 0;
}
+int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
+{
+ struct at91_port *at91_port = at91_pio_get_port(port);
+
+ if (use_pullup)
+ at91_pio3_set_pio_pulldown(port, pin, 0);
+
+ if (at91_port && (pin < GPIO_PER_BANK))
+ at91_set_port_pullup(at91_port, pin, use_pullup);
+
+ return 0;
+}
+
/*
* disable Schmitt trigger
*/
-int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
+int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -336,7 +389,6 @@ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
return 0;
}
-#endif
/*
* enable/disable the multi-driver. This is only valid for output and
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index be3d82e67e..eb8d2b31ec 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -333,7 +333,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
writel(value, &pio->pioa.pdr);
- writel(value, &pio->pioa.asr);
+ writel(value, &pio->pioa.mux.pio2.asr);
#ifdef CONFIG_RMII
value = ATMEL_PMX_BA_ERXCK;
@@ -344,7 +344,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
#endif
writel(value, &pio->piob.pdr);
- writel(value, &pio->piob.bsr);
+ writel(value, &pio->piob.mux.pio2.bsr);
at91_periph_clk_enable(ATMEL_ID_EMAC);
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v8 2/2] pinctrl: at91: add pinctrl driver
2017-03-23 4:44 [U-Boot] [PATCH v8 0/2] pinctrl: at91: Add pinctrl driver Wenyou Yang
2017-03-23 4:44 ` [U-Boot] [PATCH v8 1/2] gpio: at91_gpio: remove CPU_HAS_PIO3 macro Wenyou Yang
@ 2017-03-23 4:44 ` Wenyou Yang
2017-04-13 21:16 ` Simon Glass
1 sibling, 1 reply; 6+ messages in thread
From: Wenyou Yang @ 2017-03-23 4:44 UTC (permalink / raw)
To: u-boot
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Rebase on v2017.03.
Changes in v7: None
Changes in v6: None
Changes in v5:
- Rebase on the master branch on git://git.denx.de/u-boot-atmel.git
commit: 0ff27d4a94637d4b1937c625d33212375bd118d9
Changes in v4: None
Changes in v3:
- Add support for OUTPUT config
Changes in v2:
- Add more information for the PINCTRL_AT91 option's help.
- Add more comments for the callback of struct at91_pinctrl_mux_ops.
- Use clrsetbits_le32() in set_drive_strength().
- Add the brackets for readability.
- Use debug() to print the message to debug, instead of printf().
- Remove not veryuseful at91_bank_base().
- Add Reviewed-by tag.
arch/arm/mach-at91/include/mach/at91_pio.h | 6 +-
drivers/pinctrl/Kconfig | 14 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-at91.c | 453 +++++++++++++++++++++++++++++
include/dt-bindings/pinctrl/at91.h | 2 +
5 files changed, 475 insertions(+), 1 deletion(-)
create mode 100644 drivers/pinctrl/pinctrl-at91.c
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index 946f076714..4840a2b8f2 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -109,7 +109,11 @@ typedef struct at91_port {
u32 wpsr; /* 0xE8 Write Protect Status Register */
u32 reserved11[5]; /* */
u32 schmitt; /* 0x100 Schmitt Trigger Register */
- u32 reserved12[63];
+ u32 reserved12[4]; /* 0x104 ~ 0x110 */
+ u32 driver1; /* 0x114 I/O Driver Register1(AT91SAM9x5's driver1) */
+ u32 driver12; /* 0x118 I/O Driver Register12(AT91SAM9x5's driver2 or SAMA5D3x's driver1 ) */
+ u32 driver2; /* 0x11C I/O Driver Register2(SAMA5D3x's driver2) */
+ u32 reserved13[12]; /* 0x120 ~ 0x14C */
} at91_port_t;
typedef union at91_pio {
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0003..106510c8f7 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -141,6 +141,20 @@ config ROCKCHIP_RK3288_PINCTRL
definitions and pin control functions for each available multiplex
function.
+config PINCTRL_AT91
+ bool "AT91 pinctrl driver"
+ depends on DM
+ help
+ This option is to enable the AT91 pinctrl driver for AT91 PIO
+ controller. AT91 PIO controller is a combined gpio-controller,
+ pin-mux and pin-config module. Each I/O pin may be dedicated as
+ a general-purpose I/O or be assigned to a function of an embedded
+ peripheral. Each I/O pin has a glitch filter providing rejection of
+ glitches lower than one-half of peripheral clock cycle and
+ a debouncing filter providing rejection of unwanted pulses from key
+ or push button operations. You can also control the multi-driver
+ capability, pull-up and pull-down feature on each I/O pin.
+
config PINCTRL_AT91PIO4
bool "AT91 PIO4 pinctrl driver"
depends on DM
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 512112af64..c461605cd8 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,6 +5,7 @@
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
+obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-y += nxp/
obj-$(CONFIG_ARCH_ATH79) += ath79/
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
new file mode 100644
index 0000000000..904e1bdc68
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -0,0 +1,453 @@
+/*
+ * Atmel PIO pinctrl driver
+ *
+ * Copyright (C) 2016 Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <mach/at91_pio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_GPIO_BANKS 5
+#define MAX_NB_GPIO_PER_BANK 32
+
+#define MAX_PINMUX_ENTRIES 200
+
+struct at91_pinctrl_priv {
+ struct at91_port *reg_base[MAX_GPIO_BANKS];
+ u32 nbanks;
+};
+
+#define PULL_UP BIT(0)
+#define MULTI_DRIVE BIT(1)
+#define DEGLITCH BIT(2)
+#define PULL_DOWN BIT(3)
+#define DIS_SCHMIT BIT(4)
+#define DRIVE_STRENGTH_SHIFT 5
+#define DRIVE_STRENGTH_MASK 0x3
+#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
+#define OUTPUT BIT(7)
+#define OUTPUT_VAL_SHIFT 8
+#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
+#define DEBOUNCE BIT(16)
+#define DEBOUNCE_VAL_SHIFT 17
+#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
+
+/**
+ * These defines will translated the dt binding settings to our internal
+ * settings. They are not necessarily the same value as the register setting.
+ * The actual drive strength current of low, medium and high must be looked up
+ * from the corresponding device datasheet. This value is different for pins
+ * that are even in the same banks. It is also dependent on VCC.
+ * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
+ * strength when there is no dt config for it.
+ */
+#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
+
+enum at91_mux {
+ AT91_MUX_GPIO = 0,
+ AT91_MUX_PERIPH_A = 1,
+ AT91_MUX_PERIPH_B = 2,
+ AT91_MUX_PERIPH_C = 3,
+ AT91_MUX_PERIPH_D = 4,
+};
+
+/**
+ * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
+ * on new IP with support for periph C and D the way to mux in
+ * periph A and B has changed
+ * So provide the right callbacks
+ * if not present means the IP does not support it
+ * @mux_A_periph: assign the corresponding pin to the peripheral A function.
+ * @mux_B_periph: assign the corresponding pin to the peripheral B function.
+ * @mux_C_periph: assign the corresponding pin to the peripheral C function.
+ * @mux_D_periph: assign the corresponding pin to the peripheral D function.
+ * @set_deglitch: enable/disable the deglitch feature.
+ * @set_debounce: enable/disable the debounce feature.
+ * @set_pulldown: enable/disable the pulldown feature.
+ * @disable_schmitt_trig: disable schmitt trigger
+ */
+struct at91_pinctrl_mux_ops {
+ void (*mux_A_periph)(struct at91_port *pio, u32 mask);
+ void (*mux_B_periph)(struct at91_port *pio, u32 mask);
+ void (*mux_C_periph)(struct at91_port *pio, u32 mask);
+ void (*mux_D_periph)(struct at91_port *pio, u32 mask);
+ void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
+ void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
+ u32 div);
+ void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
+ void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
+ void (*set_drivestrength)(struct at91_port *pio, u32 pin,
+ u32 strength);
+};
+
+static u32 two_bit_pin_value_shift_amount(u32 pin)
+{
+ /* return the shift value for a pin for "two bit" per pin registers,
+ * i.e. drive strength */
+ return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
+ ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
+}
+
+static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
+{
+ writel(mask, &pio->idr);
+}
+
+static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
+{
+ if (on)
+ writel(mask, &pio->mux.pio3.ppddr);
+
+ writel(mask, (on ? &pio->puer : &pio->pudr));
+}
+
+static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
+ bool is_on, bool val)
+{
+ writel(mask, (val ? &pio->sodr : &pio->codr));
+ writel(mask, (is_on ? &pio->oer : &pio->odr));
+}
+
+static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
+{
+ writel(mask, (on ? &pio->mder : &pio->mddr));
+}
+
+static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
+{
+ writel(mask, &pio->mux.pio2.asr);
+}
+
+static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
+{
+ writel(mask, &pio->mux.pio2.bsr);
+}
+
+static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
+{
+ writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
+ writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
+}
+
+static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
+{
+ writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
+ writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
+}
+
+static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
+{
+ writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
+ writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
+}
+
+static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
+{
+ writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
+ writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
+}
+
+static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
+{
+ writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
+}
+
+static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
+ u32 mask, bool is_on)
+{
+ if (is_on)
+ writel(mask, &pio->mux.pio3.ifscdr);
+ at91_mux_set_deglitch(pio, mask, is_on);
+}
+
+static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
+ bool is_on, u32 div)
+{
+ if (is_on) {
+ writel(mask, &pio->mux.pio3.ifscer);
+ writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
+ writel(mask, &pio->ifer);
+ } else {
+ writel(mask, &pio->mux.pio3.ifscdr);
+ }
+}
+
+static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
+ u32 mask, bool is_on)
+{
+ if (is_on)
+ writel(mask, &pio->pudr);
+
+ writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
+}
+
+static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
+ u32 mask)
+{
+ writel(readl(&pio->schmitt) | mask, &pio->schmitt);
+}
+
+static void set_drive_strength(void *reg, u32 pin, u32 strength)
+{
+ u32 shift = two_bit_pin_value_shift_amount(pin);
+
+ clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
+}
+
+static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
+ u32 pin, u32 setting)
+{
+ void *reg;
+
+ reg = &pio->driver12;
+ if (pin >= MAX_NB_GPIO_PER_BANK / 2)
+ reg = &pio->driver2;
+
+ /* do nothing if setting is zero */
+ if (!setting)
+ return;
+
+ /* strength is 1 to 1 with setting for SAMA5 */
+ set_drive_strength(reg, pin, setting);
+}
+
+static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
+ u32 pin, u32 setting)
+{
+ void *reg;
+
+ reg = &pio->driver1;
+ if (pin >= MAX_NB_GPIO_PER_BANK / 2)
+ reg = &pio->driver12;
+
+ /* do nothing if setting is zero */
+ if (!setting)
+ return;
+
+ /* strength is inverse on SAM9x5s with our defines
+ * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
+ setting = DRIVE_STRENGTH_HI - setting;
+
+ set_drive_strength(reg, pin, setting);
+}
+
+static struct at91_pinctrl_mux_ops at91rm9200_ops = {
+ .mux_A_periph = at91_mux_set_A_periph,
+ .mux_B_periph = at91_mux_set_B_periph,
+ .set_deglitch = at91_mux_set_deglitch,
+};
+
+static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
+};
+
+static struct at91_pinctrl_mux_ops sama5d3_ops = {
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
+};
+
+static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
+{
+ writel(mask, &pio->pdr);
+}
+
+static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
+{
+ writel(mask, &pio->per);
+ writel(mask, (input ? &pio->odr : &pio->oer));
+}
+
+static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
+ struct at91_port *pio, u32 mask, enum at91_mux mux)
+{
+ at91_mux_disable_interrupt(pio, mask);
+ switch (mux) {
+ case AT91_MUX_GPIO:
+ at91_mux_gpio_enable(pio, mask, 1);
+ break;
+ case AT91_MUX_PERIPH_A:
+ ops->mux_A_periph(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_B:
+ ops->mux_B_periph(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_C:
+ if (!ops->mux_C_periph)
+ return -EINVAL;
+ ops->mux_C_periph(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_D:
+ if (!ops->mux_D_periph)
+ return -EINVAL;
+ ops->mux_D_periph(pio, mask);
+ break;
+ }
+ if (mux)
+ at91_mux_gpio_disable(pio, mask);
+
+ return 0;
+}
+
+static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
+ struct at91_port *pio, u32 pin, u32 config)
+{
+ u32 mask = BIT(pin);
+
+ if ((config & PULL_UP) && (config & PULL_DOWN))
+ return -EINVAL;
+
+ at91_mux_set_output(pio, mask, config & OUTPUT,
+ (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
+ at91_mux_set_pullup(pio, mask, config & PULL_UP);
+ at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
+ if (ops->set_deglitch)
+ ops->set_deglitch(pio, mask, config & DEGLITCH);
+ if (ops->set_debounce)
+ ops->set_debounce(pio, mask, config & DEBOUNCE,
+ (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
+ if (ops->set_pulldown)
+ ops->set_pulldown(pio, mask, config & PULL_DOWN);
+ if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
+ ops->disable_schmitt_trig(pio, mask);
+ if (ops->set_drivestrength)
+ ops->set_drivestrength(pio, pin,
+ (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
+
+ return 0;
+}
+
+static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
+{
+ struct at91_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (bank >= priv->nbanks) {
+ debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
+ return -EINVAL;
+ }
+
+ if (pin >= MAX_NB_GPIO_PER_BANK) {
+ debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ struct at91_pinctrl_priv *priv = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int node = config->of_offset;
+ u32 cells[MAX_PINMUX_ENTRIES];
+ const u32 *list = cells;
+ u32 bank, pin;
+ u32 conf, mask, count, i;
+ int size;
+ int ret;
+ enum at91_mux mux;
+ struct at91_port *pio;
+ struct at91_pinctrl_mux_ops *ops =
+ (struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
+
+ /*
+ * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
+ * do sanity check and calculate pins number
+ */
+ size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
+ cells, ARRAY_SIZE(cells));
+
+ /* we do not check return since it's safe node passed down */
+ count = size >> 2;
+ if (!count)
+ return -EINVAL;
+
+ for (i = 0; i < count; i++) {
+ bank = *list++;
+ pin = *list++;
+ mux = *list++;
+ conf = *list++;
+
+ ret = at91_pin_check_config(dev, bank, pin);
+ if (ret)
+ return ret;
+
+ pio = priv->reg_base[bank];
+ mask = BIT(pin);
+
+ ret = at91_pmx_set(ops, pio, mask, mux);
+ if (ret)
+ return ret;
+
+ ret = at91_pinconf_set(ops, pio, pin, conf);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+const struct pinctrl_ops at91_pinctrl_ops = {
+ .set_state = at91_pinctrl_set_state,
+};
+
+static int at91_pinctrl_probe(struct udevice *dev)
+{
+ struct at91_pinctrl_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr_base;
+ int index;
+
+ for (index = 0; index < MAX_GPIO_BANKS; index++) {
+ addr_base = dev_get_addr_index(dev, index);
+ if (addr_base == FDT_ADDR_T_NONE)
+ break;
+
+ priv->reg_base[index] = (struct at91_port *)addr_base;
+ }
+
+ priv->nbanks = index;
+
+ return 0;
+}
+
+static const struct udevice_id at91_pinctrl_match[] = {
+ { .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
+ { .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
+ { .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
+ {}
+};
+
+U_BOOT_DRIVER(at91_pinctrl) = {
+ .name = "pinctrl_at91",
+ .id = UCLASS_PINCTRL,
+ .of_match = at91_pinctrl_match,
+ .probe = at91_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
+ .ops = &at91_pinctrl_ops,
+};
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index bbca3d0389..2732d6c0fb 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -15,6 +15,8 @@
#define AT91_PINCTRL_DEGLITCH (1 << 2)
#define AT91_PINCTRL_PULL_DOWN (1 << 3)
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
+#define AT91_PINCTRL_OUTPUT (1 << 7)
+#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v8 1/2] gpio: at91_gpio: remove CPU_HAS_PIO3 macro
2017-03-23 4:44 ` [U-Boot] [PATCH v8 1/2] gpio: at91_gpio: remove CPU_HAS_PIO3 macro Wenyou Yang
@ 2017-04-01 4:21 ` Simon Glass
2017-04-13 21:16 ` Simon Glass
0 siblings, 1 reply; 6+ messages in thread
From: Simon Glass @ 2017-04-01 4:21 UTC (permalink / raw)
To: u-boot
On 22 March 2017 at 22:44, Wenyou Yang <wenyou.yang@atmel.com> wrote:
> The intention of the removal is the preparation to introduce the
> new AT91 PIO pinctrl driver.
>
> Use the union to make the PIO3 and PIO2's registers be together
> and make their offset aligned.
>
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
>
> Changes in v8: None
> Changes in v7:
> - Fix the missing conversion for the at91_emac driver when building
> the at91rm9200 devices.
>
> Changes in v6:
> - Move PIO_SCDR_DIV define from mach/<soc.h> to mach/at91_pio.h
> to fix the build error.
>
> Changes in v5: None
> Changes in v4:
> - Fix the incomplete conversion of the peripheral configurations on
> the sama5d3, sam9x5, and sam9n12.
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 106 ++++++------
> arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 112 ++++++-------
> arch/arm/mach-at91/armv7/sama5d3_devices.c | 140 ++++++++--------
> arch/arm/mach-at91/include/mach/at91_pio.h | 63 ++++----
> arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 -
> arch/arm/mach-at91/include/mach/sama5d3.h | 2 -
> arch/arm/mach-at91/include/mach/sama5d4.h | 2 -
> board/atmel/at91sam9n12ek/at91sam9n12ek.c | 10 +-
> board/atmel/at91sam9x5ek/at91sam9x5ek.c | 90 +++++------
> board/atmel/sama5d3xek/sama5d3xek.c | 64 ++++----
> board/atmel/sama5d4_xplained/sama5d4_xplained.c | 148 ++++++++---------
> board/atmel/sama5d4ek/sama5d4ek.c | 136 ++++++++--------
> board/denx/ma5d4evk/ma5d4evk.c | 178 ++++++++++-----------
> board/l+g/vinco/vinco.c | 70 ++++----
> drivers/gpio/at91_gpio.c | 142 ++++++++++------
> drivers/net/at91_emac.c | 4 +-
> 16 files changed, 660 insertions(+), 609 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v8 1/2] gpio: at91_gpio: remove CPU_HAS_PIO3 macro
2017-04-01 4:21 ` Simon Glass
@ 2017-04-13 21:16 ` Simon Glass
0 siblings, 0 replies; 6+ messages in thread
From: Simon Glass @ 2017-04-13 21:16 UTC (permalink / raw)
To: u-boot
On 31 March 2017 at 22:21, Simon Glass <sjg@chromium.org> wrote:
> On 22 March 2017 at 22:44, Wenyou Yang <wenyou.yang@atmel.com> wrote:
>> The intention of the removal is the preparation to introduce the
>> new AT91 PIO pinctrl driver.
>>
>> Use the union to make the PIO3 and PIO2's registers be together
>> and make their offset aligned.
>>
>> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
>> ---
>>
>> Changes in v8: None
>> Changes in v7:
>> - Fix the missing conversion for the at91_emac driver when building
>> the at91rm9200 devices.
>>
>> Changes in v6:
>> - Move PIO_SCDR_DIV define from mach/<soc.h> to mach/at91_pio.h
>> to fix the build error.
>>
>> Changes in v5: None
>> Changes in v4:
>> - Fix the incomplete conversion of the peripheral configurations on
>> the sama5d3, sam9x5, and sam9n12.
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>> arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 106 ++++++------
>> arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 112 ++++++-------
>> arch/arm/mach-at91/armv7/sama5d3_devices.c | 140 ++++++++--------
>> arch/arm/mach-at91/include/mach/at91_pio.h | 63 ++++----
>> arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 -
>> arch/arm/mach-at91/include/mach/sama5d3.h | 2 -
>> arch/arm/mach-at91/include/mach/sama5d4.h | 2 -
>> board/atmel/at91sam9n12ek/at91sam9n12ek.c | 10 +-
>> board/atmel/at91sam9x5ek/at91sam9x5ek.c | 90 +++++------
>> board/atmel/sama5d3xek/sama5d3xek.c | 64 ++++----
>> board/atmel/sama5d4_xplained/sama5d4_xplained.c | 148 ++++++++---------
>> board/atmel/sama5d4ek/sama5d4ek.c | 136 ++++++++--------
>> board/denx/ma5d4evk/ma5d4evk.c | 178 ++++++++++-----------
>> board/l+g/vinco/vinco.c | 70 ++++----
>> drivers/gpio/at91_gpio.c | 142 ++++++++++------
>> drivers/net/at91_emac.c | 4 +-
>> 16 files changed, 660 insertions(+), 609 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot-dm, thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v8 2/2] pinctrl: at91: add pinctrl driver
2017-03-23 4:44 ` [U-Boot] [PATCH v8 2/2] pinctrl: at91: add pinctrl driver Wenyou Yang
@ 2017-04-13 21:16 ` Simon Glass
0 siblings, 0 replies; 6+ messages in thread
From: Simon Glass @ 2017-04-13 21:16 UTC (permalink / raw)
To: u-boot
On 22 March 2017 at 22:44, Wenyou Yang <wenyou.yang@atmel.com> wrote:
> AT91 PIO controller is a combined gpio-controller, pin-mux and
> pin-config module. The peripheral's pins are assigned through
> per-pin based muxing logic.
>
> Each SoC will have to describe the its limitation and pin
> configuration via device tree. This will allow to do not need
> to touch the C code when adding new SoC if the IP version is
> supported.
>
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v8:
> - Rebase on v2017.03.
>
> Changes in v7: None
> Changes in v6: None
> Changes in v5:
> - Rebase on the master branch on git://git.denx.de/u-boot-atmel.git
> commit: 0ff27d4a94637d4b1937c625d33212375bd118d9
>
> Changes in v4: None
> Changes in v3:
> - Add support for OUTPUT config
>
> Changes in v2:
> - Add more information for the PINCTRL_AT91 option's help.
> - Add more comments for the callback of struct at91_pinctrl_mux_ops.
> - Use clrsetbits_le32() in set_drive_strength().
> - Add the brackets for readability.
> - Use debug() to print the message to debug, instead of printf().
> - Remove not veryuseful at91_bank_base().
> - Add Reviewed-by tag.
>
> arch/arm/mach-at91/include/mach/at91_pio.h | 6 +-
> drivers/pinctrl/Kconfig | 14 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-at91.c | 453 +++++++++++++++++++++++++++++
> include/dt-bindings/pinctrl/at91.h | 2 +
> 5 files changed, 475 insertions(+), 1 deletion(-)
> create mode 100644 drivers/pinctrl/pinctrl-at91.c
Applied to u-boot-dm, thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-04-13 21:16 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-23 4:44 [U-Boot] [PATCH v8 0/2] pinctrl: at91: Add pinctrl driver Wenyou Yang
2017-03-23 4:44 ` [U-Boot] [PATCH v8 1/2] gpio: at91_gpio: remove CPU_HAS_PIO3 macro Wenyou Yang
2017-04-01 4:21 ` Simon Glass
2017-04-13 21:16 ` Simon Glass
2017-03-23 4:44 ` [U-Boot] [PATCH v8 2/2] pinctrl: at91: add pinctrl driver Wenyou Yang
2017-04-13 21:16 ` Simon Glass
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