* [U-Boot] [PATCHv3 02/15] dm: pci: return the real controller in pci_bus_to_hose()
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-18 1:14 ` Simon Glass
2016-11-16 9:48 ` [U-Boot] [PATCHv3 03/15] dm: pci: remove pci_bus_to_hose(0) calling Zhiqiang Hou
` (12 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
for the legacy PCI driver, the function pci_bus_to_hose() returns
the real PCIe controller. To keep consistency, this function is
changed to return the PCIe controller pointer of the root bus
instead of the current PCIe bus.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
drivers/pci/pci_compat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c
index ddaf358..25bc095 100644
--- a/drivers/pci/pci_compat.c
+++ b/drivers/pci/pci_compat.c
@@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum)
return NULL;
}
- return dev_get_uclass_priv(bus);
+ return dev_get_uclass_priv(pci_get_controller(bus));
}
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 02/15] dm: pci: return the real controller in pci_bus_to_hose()
2016-11-16 9:48 ` [U-Boot] [PATCHv3 02/15] dm: pci: return the real controller in pci_bus_to_hose() Zhiqiang Hou
@ 2016-11-18 1:14 ` Simon Glass
2016-11-21 6:13 ` Z.Q. Hou
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2016-11-18 1:14 UTC (permalink / raw)
To: u-boot
On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com> wrote:
> From: Minghuan Lian <Minghuan.Lian@nxp.com>
>
> for the legacy PCI driver, the function pci_bus_to_hose() returns
> the real PCIe controller. To keep consistency, this function is
> changed to return the PCIe controller pointer of the root bus
> instead of the current PCIe bus.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V3:
> - No change
>
> drivers/pci/pci_compat.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCHv3 02/15] dm: pci: return the real controller in pci_bus_to_hose()
2016-11-18 1:14 ` Simon Glass
@ 2016-11-21 6:13 ` Z.Q. Hou
0 siblings, 0 replies; 31+ messages in thread
From: Z.Q. Hou @ 2016-11-21 6:13 UTC (permalink / raw)
To: u-boot
Hi Simon,
Thanks for your review!
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: 2016?11?18? 9:15
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [PATCHv3 02/15] dm: pci: return the real controller in
> pci_bus_to_hose()
>
> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> wrote:
> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
> >
> > for the legacy PCI driver, the function pci_bus_to_hose() returns the
> > real PCIe controller. To keep consistency, this function is changed to
> > return the PCIe controller pointer of the root bus instead of the
> > current PCIe bus.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V3:
> > - No change
> >
> > drivers/pci/pci_compat.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>[]
Regards,
Zhiqiang
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCHv3 03/15] dm: pci: remove pci_bus_to_hose(0) calling
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 02/15] dm: pci: return the real controller in pci_bus_to_hose() Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-18 1:14 ` Simon Glass
2016-11-16 9:48 ` [U-Boot] [PATCHv3 04/15] arm: ls1021a: add PCIe dts node Zhiqiang Hou
` (11 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
There may be multiple PCIe controllers in a SoC.
It is not correct that always calling pci_bus_to_hose(0) to get
the first PCIe controller for the PCIe device connected other
controllers. We just remove this calling because hose always point
the correct PCIe controller.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- Comment func pci_hose_phys_to_bus() that @hose must be the root PCI controller
drivers/pci/pci_common.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index 1755914..9e09acd 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
return phys_addr;
}
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- hose = pci_bus_to_hose(0);
-#endif
-
/*
* if PCI_REGION_MEM is set we do a two pass search with preference
* on matches that don't have PCI_REGION_SYS_MEMORY set
@@ -236,6 +231,13 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
return 1;
}
+/*
+ * pci_hose_phys_to_bus(): Convert physical address to bus address
+ * @hose: PCI hose of the root PCI controller
+ * @phys_addr: physical address to convert
+ * @flags: flags of pci regions
+ *
+ */
pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags)
@@ -248,11 +250,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
return bus_addr;
}
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- hose = pci_bus_to_hose(0);
-#endif
-
/*
* if PCI_REGION_MEM is set we do a two pass search with preference
* on matches that don't have PCI_REGION_SYS_MEMORY set
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 03/15] dm: pci: remove pci_bus_to_hose(0) calling
2016-11-16 9:48 ` [U-Boot] [PATCHv3 03/15] dm: pci: remove pci_bus_to_hose(0) calling Zhiqiang Hou
@ 2016-11-18 1:14 ` Simon Glass
2016-11-21 6:11 ` Z.Q. Hou
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2016-11-18 1:14 UTC (permalink / raw)
To: u-boot
On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com> wrote:
> From: Minghuan Lian <Minghuan.Lian@nxp.com>
>
> There may be multiple PCIe controllers in a SoC.
> It is not correct that always calling pci_bus_to_hose(0) to get
> the first PCIe controller for the PCIe device connected other
> controllers. We just remove this calling because hose always point
> the correct PCIe controller.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V3:
> - Comment func pci_hose_phys_to_bus() that @hose must be the root PCI controller
>
> drivers/pci/pci_common.c | 17 +++++++----------
> 1 file changed, 7 insertions(+), 10 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
But please see below
>
> diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
> index 1755914..9e09acd 100644
> --- a/drivers/pci/pci_common.c
> +++ b/drivers/pci/pci_common.c
> @@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
> return phys_addr;
> }
>
> -#ifdef CONFIG_DM_PCI
> - /* The root controller has the region information */
> - hose = pci_bus_to_hose(0);
> -#endif
> -
> /*
> * if PCI_REGION_MEM is set we do a two pass search with preference
> * on matches that don't have PCI_REGION_SYS_MEMORY set
> @@ -236,6 +231,13 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
> return 1;
> }
>
> +/*
> + * pci_hose_phys_to_bus(): Convert physical address to bus address
> + * @hose: PCI hose of the root PCI controller
> + * @phys_addr: physical address to convert
> + * @flags: flags of pci regions
@return ....
> + *
> + */
> pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
> phys_addr_t phys_addr,
> unsigned long flags)
> @@ -248,11 +250,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
> return bus_addr;
> }
>
> -#ifdef CONFIG_DM_PCI
> - /* The root controller has the region information */
> - hose = pci_bus_to_hose(0);
> -#endif
> -
> /*
> * if PCI_REGION_MEM is set we do a two pass search with preference
> * on matches that don't have PCI_REGION_SYS_MEMORY set
> --
> 2.1.0.27.g96db324
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCHv3 03/15] dm: pci: remove pci_bus_to_hose(0) calling
2016-11-18 1:14 ` Simon Glass
@ 2016-11-21 6:11 ` Z.Q. Hou
0 siblings, 0 replies; 31+ messages in thread
From: Z.Q. Hou @ 2016-11-21 6:11 UTC (permalink / raw)
To: u-boot
Hi Simon,
Thanks for your comments!
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: 2016?11?18? 9:15
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [PATCHv3 03/15] dm: pci: remove pci_bus_to_hose(0) calling
>
> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> wrote:
> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
> >
> > There may be multiple PCIe controllers in a SoC.
> > It is not correct that always calling pci_bus_to_hose(0) to get the
> > first PCIe controller for the PCIe device connected other controllers.
> > We just remove this calling because hose always point the correct PCIe
> > controller.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V3:
> > - Comment func pci_hose_phys_to_bus() that @hose must be the root PCI
> > controller
> >
> > drivers/pci/pci_common.c | 17 +++++++----------
> > 1 file changed, 7 insertions(+), 10 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> But please see below
>
> >
> > diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index
> > 1755914..9e09acd 100644
> > --- a/drivers/pci/pci_common.c
> > +++ b/drivers/pci/pci_common.c
> > @@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct
> pci_controller *hose,
> > return phys_addr;
> > }
> >
> > -#ifdef CONFIG_DM_PCI
> > - /* The root controller has the region information */
> > - hose = pci_bus_to_hose(0);
> > -#endif
> > -
> > /*
> > * if PCI_REGION_MEM is set we do a two pass search with
> preference
> > * on matches that don't have PCI_REGION_SYS_MEMORY set
> @@
> > -236,6 +231,13 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
> > return 1;
> > }
> >
> > +/*
> > + * pci_hose_phys_to_bus(): Convert physical address to bus address
> > + * @hose: PCI hose of the root PCI controller
> > + * @phys_addr: physical address to convert
> > + * @flags: flags of pci regions
>
> @return ....
>
Will add the description of return.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCHv3 04/15] arm: ls1021a: add PCIe dts node
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 02/15] dm: pci: return the real controller in pci_bus_to_hose() Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 03/15] dm: pci: remove pci_bus_to_hose(0) calling Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 05/15] arm: ls1012a: " Zhiqiang Hou
` (10 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
arch/arm/dts/ls1021a.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 119b1af..e06cf60 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -373,5 +373,36 @@
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x03400000 0x20000 /* dbi registers */
+ 0x01570000 0x10000 /* pf controls registers */
+ 0x24000000 0x20000>; /* configuration space */
+ reg-names = "dbi", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x03500000 0x10000 /* dbi registers */
+ 0x01570000 0x10000 /* pf controls registers */
+ 0x34000000 0x20000>; /* configuration space */
+ reg-names = "dbi", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
+ };
};
};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 05/15] arm: ls1012a: add PCIe dts node
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (2 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 04/15] arm: ls1021a: add PCIe dts node Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 06/15] armv8: ls1043a: " Zhiqiang Hou
` (9 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
arch/arm/dts/fsl-ls1012a.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 024527e..c4ca9c1 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -103,5 +103,20 @@
status = "disabled";
};
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03480000 0x0 0x40000 /* lut registers */
+ 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
+ 0x40 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 06/15] armv8: ls1043a: add PCIe dts node
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (3 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 05/15] arm: ls1012a: " Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 07/15] armv8: ls1046a: " Zhiqiang Hou
` (8 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
arch/arm/dts/fsl-ls1043a.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f038f96..fe6698f 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -236,5 +236,51 @@
interrupts = <0 63 0x4>;
dr_mode = "host";
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
+ 0x00 0x03410000 0x0 0x10000 /* lut registers */
+ 0x40 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
+ 0x00 0x03510000 0x0 0x10000 /* lut registers */
+ 0x48 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
+ 0x00 0x03610000 0x0 0x10000 /* lut registers */
+ 0x50 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 07/15] armv8: ls1046a: add PCIe dts node
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (4 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 06/15] armv8: ls1043a: " Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 08/15] armv8: ls2080a: " Zhiqiang Hou
` (7 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
arch/arm/dts/fsl-ls1046a.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 87dd997..5d30112 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -162,5 +162,54 @@
big-endian;
status = "disabled";
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03480000 0x0 0x40000 /* lut registers */
+ 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
+ 0x40 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03580000 0x0 0x40000 /* lut registers */
+ 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
+ 0x48 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03680000 0x0 0x40000 /* lut registers */
+ 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
+ 0x50 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 08/15] armv8: ls2080a: add PCIe dts node
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (5 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 07/15] armv8: ls1046a: " Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM Zhiqiang Hou
` (6 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
arch/arm/dts/fsl-ls2080a.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index f76e981..79047d5 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -89,4 +89,64 @@
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03480000 0x0 0x80000 /* lut registers */
+ 0x10 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03580000 0x0 0x80000 /* lut registers */
+ 0x12 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03680000 0x0 0x80000 /* lut registers */
+ 0x14 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3700000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03780000 0x0 0x80000 /* lut registers */
+ 0x16 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (6 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 08/15] armv8: ls2080a: " Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-18 1:14 ` Simon Glass
2016-11-16 9:48 ` [U-Boot] [PATCHv3 10/15] arm: ls1021a: Enable PCIe in defconfigs Zhiqiang Hou
` (5 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
There are more than five kinds of Layerscape SoCs. unfortunately,
PCIe controller of each SoC is a little bit different. In order
to avoid too many macro definitions, the patch addes a new
implementation of PCIe driver based on DM. PCIe dts node is
used to describe the difference.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
drivers/pci/Kconfig | 8 +
drivers/pci/pcie_layerscape.c | 761 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 769 insertions(+)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b8376b4..07d21ea 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -61,4 +61,12 @@ config PCI_XILINX
Enable support for the Xilinx AXI bridge for PCI express, an IP block
which can be used on some generations of Xilinx FPGAs.
+config PCIE_LAYERSCAPE
+ bool "Layerscape PCIe support"
+ depends on DM_PCI
+ help
+ Support Layerscape PCIe. The Layerscape SoC may have one or several
+ PCIe controllers. The PCIe may works in RC or EP mode according to
+ RCW setting.
+
endif
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 2e6b986..f107d1c 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -11,11 +11,14 @@
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
+#include <dm.h>
#ifndef CONFIG_LS102XA
#include <asm/arch/fdt.h>
#include <asm/arch/soc.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
#endif
@@ -40,6 +43,7 @@
#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
+#define PCIE_ATU_REGION_NUM 6
#define PCIE_ATU_CR1 0x904
#define PCIE_ATU_TYPE_MEM (0x0 << 0)
#define PCIE_ATU_TYPE_IO (0x2 << 0)
@@ -58,6 +62,9 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+/* DBI registers */
+#define PCIE_SRIOV 0x178
+#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
#define PCIE_DBI_RO_WR_EN 0x8bc
#define PCIE_LINK_CAP 0x7c
@@ -88,6 +95,8 @@
#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
+#ifndef CONFIG_DM_PCI
+
struct ls_pcie {
int idx;
void __iomem *dbi;
@@ -814,3 +823,755 @@ void ft_pci_setup(void *blob, bd_t *bd)
{
}
#endif
+
+#else
+
+/* LUT registers */
+#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE (1 << 31)
+#define PCIE_LUT_ENTRY_COUNT 32
+
+/* PF Controll registers */
+#define PCIE_PF_VF_CTRL 0x7F8
+#define PCIE_PF_DBG 0x7FC
+
+#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
+#define PCIE_SYS_BASE_ADDR 0x3400000
+#define PCIE_CCSR_SIZE 0x0100000
+
+/* CS2 */
+#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */
+
+#ifdef CONFIG_LS102XA
+/* LS1021a PCIE space */
+#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
+#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL
+
+/* LS1021a PEX1/2 Misc Ports Status Register */
+#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
+#define LS1021_LTSSM_STATE_SHIFT 20
+#endif
+
+struct ls_pcie {
+ int idx;
+ struct list_head list;
+ struct udevice *bus;
+ struct fdt_resource dbi_res;
+ struct fdt_resource lut_res;
+ struct fdt_resource ctrl_res;
+ struct fdt_resource cfg_res;
+ void __iomem *dbi;
+ void __iomem *lut;
+ void __iomem *ctrl;
+ void __iomem *cfg0;
+ void __iomem *cfg1;
+ bool big_endian;
+ bool enabled;
+ int next_lut_index;
+ struct pci_controller hose;
+};
+
+static LIST_HEAD(ls_pcie_list);
+
+static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
+{
+ return in_le32(pcie->dbi + offset);
+}
+
+static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
+ unsigned int offset)
+{
+ out_le32(pcie->dbi + offset, value);
+}
+
+#ifdef CONFIG_FSL_LSCH3
+static void lut_writel(struct ls_pcie *pcie, unsigned int value,
+ unsigned int offset)
+{
+ if (pcie->big_endian)
+ out_be32(pcie->lut + offset, value);
+ else
+ out_le32(pcie->lut + offset, value);
+}
+#endif
+
+static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
+{
+ if (pcie->big_endian)
+ return in_be32(pcie->ctrl + offset);
+ else
+ return in_le32(pcie->ctrl + offset);
+}
+
+static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
+ unsigned int offset)
+{
+ if (pcie->big_endian)
+ out_be32(pcie->ctrl + offset, value);
+ else
+ out_le32(pcie->ctrl + offset, value);
+}
+
+#ifdef CONFIG_LS102XA
+static int ls_pcie_ltssm(struct ls_pcie *pcie)
+{
+ u32 state;
+
+ state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
+ state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
+
+ return state;
+}
+#else
+static int ls_pcie_ltssm(struct ls_pcie *pcie)
+{
+ return ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
+}
+#endif
+
+static int ls_pcie_link_up(struct ls_pcie *pcie)
+{
+ int ltssm;
+
+ ltssm = ls_pcie_ltssm(pcie);
+ if (ltssm < LTSSM_PCIE_L0)
+ return 0;
+
+ return 1;
+}
+
+static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
+{
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
+{
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+ u64 phys, u64 bus_addr, pci_size_t size)
+{
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
+ dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
+ dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
+ dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
+ dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
+ dbi_writel(pcie, type, PCIE_ATU_CR1);
+ dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+}
+
+/* Use bar match mode and MEM type as default */
+static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
+ int bar, u64 phys)
+{
+ dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
+ dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
+ dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+ dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
+ PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
+}
+
+static void ls_pcie_dump_atu(struct ls_pcie *pcie)
+{
+ int i;
+
+ for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
+ PCIE_ATU_VIEWPORT);
+ debug("iATU%d:\n", i);
+ debug("\tLOWER PHYS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
+ debug("\tUPPER PHYS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
+ debug("\tLOWER BUS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
+ debug("\tUPPER BUS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
+ debug("\tLIMIT 0x%08x\n",
+ readl(pcie->dbi + PCIE_ATU_LIMIT));
+ debug("\tCR1 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_CR1));
+ debug("\tCR2 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_CR2));
+ }
+}
+
+static void ls_pcie_setup_atu(struct ls_pcie *pcie)
+{
+ struct pci_region *io, *mem, *pref;
+ unsigned long long offset = 0;
+ int idx = 0;
+
+#ifdef CONFIG_LS102XA
+ offset = LS1021_PCIE_SPACE_OFFSET + LS1021_PCIE_SPACE_SIZE * pcie->idx;
+#endif
+
+ /* ATU 0 : OUTBOUND : CFG0 */
+ ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_CFG0,
+ pcie->cfg_res.start + offset,
+ 0,
+ fdt_resource_size(&pcie->cfg_res) / 2);
+ /* ATU 1 : OUTBOUND : CFG1 */
+ ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_CFG1,
+ pcie->cfg_res.start + offset +
+ fdt_resource_size(&pcie->cfg_res) / 2,
+ 0,
+ fdt_resource_size(&pcie->cfg_res) / 2);
+
+ pci_get_regions(pcie->bus, &io, &mem, &pref);
+ idx = PCIE_ATU_REGION_INDEX1 + 1;
+
+ if (io)
+ /* ATU : OUTBOUND : IO */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_IO,
+ io->phys_start + offset,
+ io->bus_start,
+ io->size);
+
+ if (mem)
+ /* ATU : OUTBOUND : MEM */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_MEM,
+ mem->phys_start + offset,
+ mem->bus_start,
+ mem->size);
+
+ if (pref)
+ /* ATU : OUTBOUND : pref */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_MEM,
+ pref->phys_start + offset,
+ pref->bus_start,
+ pref->size);
+
+ ls_pcie_dump_atu(pcie);
+}
+
+static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
+{
+ struct udevice *bus = pcie->bus;
+
+ if (!pcie->enabled)
+ return -ENODEV;
+
+ if (PCI_BUS(bdf) < bus->seq)
+ return -EINVAL;
+
+ if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
+ return -EINVAL;
+
+ if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
+ return -EINVAL;
+
+ return 0;
+}
+
+void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
+ int offset)
+{
+ struct udevice *bus = pcie->bus;
+ u32 busdev;
+
+ if (PCI_BUS(bdf) == bus->seq)
+ return pcie->dbi + offset;
+
+ busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
+ PCIE_ATU_DEV(PCI_DEV(bdf)) |
+ PCIE_ATU_FUNC(PCI_FUNC(bdf));
+
+ if (PCI_BUS(bdf) == bus->seq + 1) {
+ ls_pcie_cfg0_set_busdev(pcie, busdev);
+ return pcie->cfg0 + offset;
+ } else {
+ ls_pcie_cfg1_set_busdev(pcie, busdev);
+ return pcie->cfg1 + offset;
+ }
+}
+
+static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct ls_pcie *pcie = dev_get_priv(bus);
+ void *address;
+
+ if (ls_pcie_addr_valid(pcie, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ address = ls_pcie_conf_address(pcie, bdf, offset);
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = readb(address);
+ return 0;
+ case PCI_SIZE_16:
+ *valuep = readw(address);
+ return 0;
+ case PCI_SIZE_32:
+ *valuep = readl(address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct ls_pcie *pcie = dev_get_priv(bus);
+ void *address;
+
+ if (ls_pcie_addr_valid(pcie, bdf))
+ return 0;
+
+ address = ls_pcie_conf_address(pcie, bdf, offset);
+
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(value, address);
+ return 0;
+ case PCI_SIZE_16:
+ writew(value, address);
+ return 0;
+ case PCI_SIZE_32:
+ writel(value, address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+/* Clear multi-function bit */
+static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
+{
+ writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
+}
+
+/* Fix class value */
+static void ls_pcie_fix_class(struct ls_pcie *pcie)
+{
+ writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
+}
+
+/* Drop MSG TLP except for Vendor MSG */
+static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
+{
+ u32 val;
+
+ val = dbi_readl(pcie, PCIE_STRFMR1);
+ val &= 0xDFFFFFFF;
+ dbi_writel(pcie, val, PCIE_STRFMR1);
+}
+
+/* Disable all bars in RC mode */
+static void ls_pcie_disable_bars(struct ls_pcie *pcie)
+{
+ u32 sriov;
+
+ sriov = in_le32(pcie->dbi + PCIE_SRIOV);
+
+ if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
+ return;
+
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
+}
+
+static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
+{
+ ls_pcie_setup_atu(pcie);
+
+ dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
+ ls_pcie_fix_class(pcie);
+ ls_pcie_clear_multifunction(pcie);
+ ls_pcie_drop_msg_tlp(pcie);
+ dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
+
+ ls_pcie_disable_bars(pcie);
+}
+
+static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
+{
+ u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
+
+ /* ATU 0 : INBOUND : map BAR0 */
+ ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
+ /* ATU 1 : INBOUND : map BAR1 */
+ phys += PCIE_BAR1_SIZE;
+ ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
+ /* ATU 2 : INBOUND : map BAR2 */
+ phys += PCIE_BAR2_SIZE;
+ ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
+ /* ATU 3 : INBOUND : map BAR4 */
+ phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
+ ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
+
+ /* ATU 0 : OUTBOUND : map MEM */
+ ls_pcie_atu_outbound_set(pcie, 0,
+ PCIE_ATU_TYPE_MEM,
+ pcie->cfg_res.start,
+ 0,
+ CONFIG_SYS_PCI_MEMORY_SIZE);
+}
+
+/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
+static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
+{
+ if (size < 4 * 1024)
+ return;
+
+ switch (bar) {
+ case 0:
+ writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
+ break;
+ case 1:
+ writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
+ break;
+ case 2:
+ writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
+ writel(0, bar_base + PCI_BASE_ADDRESS_3);
+ break;
+ case 4:
+ writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
+ writel(0, bar_base + PCI_BASE_ADDRESS_5);
+ break;
+ default:
+ break;
+ }
+}
+
+static void ls_pcie_ep_setup_bars(void *bar_base)
+{
+ /* BAR0 - 32bit - 4K configuration */
+ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
+ /* BAR1 - 32bit - 8K MSIX*/
+ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
+ /* BAR2 - 64bit - 4K MEM desciptor */
+ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
+ /* BAR4 - 64bit - 1M MEM*/
+ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
+}
+
+static void ls_pcie_setup_ep(struct ls_pcie *pcie)
+{
+ u32 sriov;
+
+ sriov = readl(pcie->dbi + PCIE_SRIOV);
+ if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
+ int pf, vf;
+
+ for (pf = 0; pf < PCIE_PF_NUM; pf++) {
+ for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+ ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
+ PCIE_PF_VF_CTRL);
+
+ ls_pcie_ep_setup_bars(pcie->dbi);
+ ls_pcie_ep_setup_atu(pcie);
+ }
+ }
+ /* Disable CFG2 */
+ ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
+ } else {
+ ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
+ ls_pcie_ep_setup_atu(pcie);
+ }
+}
+
+#ifdef CONFIG_FSL_LSCH3
+/*
+ * Return next available LUT index.
+ */
+static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
+{
+ if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+ return pcie->next_lut_index++;
+ else
+ return -1; /* LUT is full */
+}
+
+/*
+ * Program a single LUT entry
+ */
+static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
+ u32 streamid)
+{
+ /* leave mask as all zeroes, want to match all bits */
+ lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
+ lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
+}
+
+/* returns the next available streamid */
+static u32 ls_pcie_next_streamid(void)
+{
+ static int next_stream_id = FSL_PEX_STREAM_ID_START;
+
+ if (next_stream_id > FSL_PEX_STREAM_ID_END)
+ return 0xffffffff;
+
+ return next_stream_id++;
+}
+
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 phandle;
+ int nodeoffset;
+
+ /* find pci controller node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+ pcie->dbi_res.start);
+ if (nodeoffset < 0) {
+ #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob,
+ FSL_PCIE_COMPAT,
+ pcie->dbi_res.start);
+ if (nodeoffset < 0)
+ return;
+ #else
+ return;
+ #endif
+ }
+
+ /* get phandle to MSI controller */
+ prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
+ if (prop == NULL) {
+ printf("\n%s: ERROR: missing msi-parent: PCIe%d\n",
+ __func__, pcie->idx);
+ return;
+ }
+ phandle = be32_to_cpu(*prop);
+
+ /* set one msi-map row */
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
+}
+
+static void fdt_fixup_pcie(void *blob)
+{
+ struct udevice *dev, *bus;
+ struct ls_pcie *pcie;
+ u32 streamid;
+ int index;
+ pci_dev_t bdf;
+
+ /* Scan all known buses */
+ for (pci_find_first_device(&dev);
+ dev;
+ pci_find_next_device(&dev)) {
+ for (bus = dev; device_is_on_pci_bus(bus);)
+ bus = bus->parent;
+ pcie = dev_get_priv(bus);
+
+ streamid = ls_pcie_next_streamid();
+ if (streamid == 0xffffffff) {
+ printf("ERROR: no stream ids free\n");
+ continue;
+ }
+
+ index = ls_pcie_next_lut_index(pcie);
+ if (index < 0) {
+ printf("ERROR: no LUT indexes free\n");
+ continue;
+ }
+
+ /* the DT fixup must be relative to the hose first_busno */
+ bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
+ streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
+ streamid);
+ }
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <libfdt.h>
+#include <fdt_support.h>
+
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+{
+ int off;
+
+ off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+ pcie->dbi_res.start);
+ if (off < 0) {
+ #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+ off = fdt_node_offset_by_compat_reg(blob,
+ FSL_PCIE_COMPAT,
+ pcie->dbi_res.start);
+ if (off < 0)
+ return;
+ #else
+ return;
+ #endif
+ }
+
+ if (pcie->enabled)
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ else
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+ struct ls_pcie *pcie;
+
+ list_for_each_entry(pcie, &ls_pcie_list, list)
+ ft_pcie_ls_setup(blob, pcie);
+
+ #ifdef CONFIG_FSL_LSCH3
+ fdt_fixup_pcie(blob);
+ #endif
+}
+
+#else
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+}
+#endif
+
+static int ls_pcie_probe(struct udevice *dev)
+{
+ struct ls_pcie *pcie = dev_get_priv(dev);
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ u8 header_type;
+ u16 link_sta;
+ bool ep_mode;
+ int ret;
+
+ pcie->bus = dev;
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "dbi", &pcie->dbi_res);
+ if (ret) {
+ printf("ls-pcie: resource \"dbi\" not found\n");
+ return ret;
+ }
+
+ pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
+
+ list_add(&pcie->list, &ls_pcie_list);
+
+ pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
+ if (!pcie->enabled) {
+ printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ return 0;
+ }
+
+ pcie->dbi = map_physmem(pcie->dbi_res.start,
+ fdt_resource_size(&pcie->dbi_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "lut", &pcie->lut_res);
+ if (!ret)
+ pcie->lut = map_physmem(pcie->lut_res.start,
+ fdt_resource_size(&pcie->lut_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "ctrl", &pcie->ctrl_res);
+ if (!ret)
+ pcie->ctrl = map_physmem(pcie->ctrl_res.start,
+ fdt_resource_size(&pcie->ctrl_res),
+ MAP_NOCACHE);
+ if (!pcie->ctrl)
+ pcie->ctrl = pcie->lut;
+
+ if (!pcie->ctrl) {
+ printf("%s: NOT find CTRL\n", dev->name);
+ return 0;
+ }
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "config", &pcie->cfg_res);
+ if (ret) {
+ printf("%s: resource \"config\" not found\n", dev->name);
+ return 0;
+ }
+
+ pcie->cfg0 = map_physmem(pcie->cfg_res.start,
+ fdt_resource_size(&pcie->cfg_res),
+ MAP_NOCACHE);
+ pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
+
+ pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+
+ debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
+ dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
+ (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
+ pcie->big_endian);
+
+ header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
+ ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
+ printf("PCIe%u: %s %s", pcie->idx, dev->name,
+ ep_mode ? "Endpoint" : "Root Complex");
+
+ if (ep_mode)
+ ls_pcie_setup_ep(pcie);
+ else
+ ls_pcie_setup_ctrl(pcie);
+
+ if (!ls_pcie_link_up(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+ }
+
+ /* Print the negotiated PCIe link width */
+ link_sta = readw(pcie->dbi + PCIE_LINK_STA);
+ printf(": x%d gen%d\n", (link_sta & 0x3f0) >> 4, link_sta & 0xf);
+
+ return 0;
+}
+
+static const struct dm_pci_ops ls_pcie_ops = {
+ .read_config = ls_pcie_read_config,
+ .write_config = ls_pcie_write_config,
+};
+
+static const struct udevice_id ls_pcie_ids[] = {
+ { .compatible = "fsl,ls-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_layerscape) = {
+ .name = "pci_layerscape",
+ .id = UCLASS_PCI,
+ .of_match = ls_pcie_ids,
+ .ops = &ls_pcie_ops,
+ .probe = ls_pcie_probe,
+ .priv_auto_alloc_size = sizeof(struct ls_pcie),
+};
+
+#endif /* CONFIG_DM_PCI */
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-16 9:48 ` [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM Zhiqiang Hou
@ 2016-11-18 1:14 ` Simon Glass
2016-11-22 9:25 ` Z.Q. Hou
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2016-11-18 1:14 UTC (permalink / raw)
To: u-boot
Hi,
On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com> wrote:
> From: Minghuan Lian <Minghuan.Lian@nxp.com>
>
> There are more than five kinds of Layerscape SoCs. unfortunately,
> PCIe controller of each SoC is a little bit different. In order
> to avoid too many macro definitions, the patch addes a new
> implementation of PCIe driver based on DM. PCIe dts node is
> used to describe the difference.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V3:
> - No change
>
> drivers/pci/Kconfig | 8 +
> drivers/pci/pcie_layerscape.c | 761 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 769 insertions(+)
>
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index b8376b4..07d21ea 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -61,4 +61,12 @@ config PCI_XILINX
> Enable support for the Xilinx AXI bridge for PCI express, an IP block
> which can be used on some generations of Xilinx FPGAs.
>
> +config PCIE_LAYERSCAPE
> + bool "Layerscape PCIe support"
> + depends on DM_PCI
> + help
> + Support Layerscape PCIe. The Layerscape SoC may have one or several
> + PCIe controllers. The PCIe may works in RC or EP mode according to
> + RCW setting.
Can you please write out RC, EP, RCW in full since this is help?
> +
> endif
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index 2e6b986..f107d1c 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -11,11 +11,14 @@
> #include <asm/io.h>
> #include <errno.h>
> #include <malloc.h>
> +#include <dm.h>
> #ifndef CONFIG_LS102XA
> #include <asm/arch/fdt.h>
> #include <asm/arch/soc.h>
> #endif
This is odd - drivers should not have board-specific code in them.
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> #ifndef CONFIG_SYS_PCI_MEMORY_BUS
> #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
> #endif
> @@ -40,6 +43,7 @@
> #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
> #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
> #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
> +#define PCIE_ATU_REGION_NUM 6
> #define PCIE_ATU_CR1 0x904
> #define PCIE_ATU_TYPE_MEM (0x0 << 0)
> #define PCIE_ATU_TYPE_IO (0x2 << 0)
> @@ -58,6 +62,9 @@
> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> #define PCIE_ATU_UPPER_TARGET 0x91C
>
> +/* DBI registers */
> +#define PCIE_SRIOV 0x178
> +#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
> #define PCIE_DBI_RO_WR_EN 0x8bc
>
> #define PCIE_LINK_CAP 0x7c
> @@ -88,6 +95,8 @@
> #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
> #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
>
> +#ifndef CONFIG_DM_PCI
> +
> struct ls_pcie {
> int idx;
> void __iomem *dbi;
> @@ -814,3 +823,755 @@ void ft_pci_setup(void *blob, bd_t *bd)
> {
> }
> #endif
> +
> +#else
> +
> +/* LUT registers */
> +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> +#define PCIE_LUT_ENABLE (1 << 31)
> +#define PCIE_LUT_ENTRY_COUNT 32
> +
> +/* PF Controll registers */
> +#define PCIE_PF_VF_CTRL 0x7F8
> +#define PCIE_PF_DBG 0x7FC
> +
> +#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
> +#define PCIE_SYS_BASE_ADDR 0x3400000
> +#define PCIE_CCSR_SIZE 0x0100000
> +
> +/* CS2 */
> +#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */
> +
> +#ifdef CONFIG_LS102XA
> +/* LS1021a PCIE space */
> +#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
> +#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL
> +
> +/* LS1021a PEX1/2 Misc Ports Status Register */
> +#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
> +#define LS1021_LTSSM_STATE_SHIFT 20
> +#endif
> +
> +struct ls_pcie {
> + int idx;
> + struct list_head list;
> + struct udevice *bus;
> + struct fdt_resource dbi_res;
> + struct fdt_resource lut_res;
> + struct fdt_resource ctrl_res;
> + struct fdt_resource cfg_res;
> + void __iomem *dbi;
> + void __iomem *lut;
> + void __iomem *ctrl;
> + void __iomem *cfg0;
> + void __iomem *cfg1;
> + bool big_endian;
> + bool enabled;
> + int next_lut_index;
> + struct pci_controller hose;
> +};
> +
> +static LIST_HEAD(ls_pcie_list);
> +
> +static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
> +{
> + return in_le32(pcie->dbi + offset);
> +}
> +
> +static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
> + unsigned int offset)
> +{
> + out_le32(pcie->dbi + offset, value);
> +}
> +
> +#ifdef CONFIG_FSL_LSCH3
> +static void lut_writel(struct ls_pcie *pcie, unsigned int value,
> + unsigned int offset)
> +{
> + if (pcie->big_endian)
> + out_be32(pcie->lut + offset, value);
> + else
> + out_le32(pcie->lut + offset, value);
> +}
> +#endif
> +
> +static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
> +{
> + if (pcie->big_endian)
> + return in_be32(pcie->ctrl + offset);
> + else
> + return in_le32(pcie->ctrl + offset);
> +}
> +
> +static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
> + unsigned int offset)
> +{
> + if (pcie->big_endian)
> + out_be32(pcie->ctrl + offset, value);
> + else
> + out_le32(pcie->ctrl + offset, value);
> +}
> +
> +#ifdef CONFIG_LS102XA
Ick, should not have board-specific code here. Perhaps add a private
run-time value indicating whether to do this or not.
> +static int ls_pcie_ltssm(struct ls_pcie *pcie)
> +{
> + u32 state;
> +
> + state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
> + state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
> +
> + return state;
> +}
> +#else
> +static int ls_pcie_ltssm(struct ls_pcie *pcie)
> +{
> + return ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
> +}
> +#endif
> +
> +static int ls_pcie_link_up(struct ls_pcie *pcie)
> +{
> + int ltssm;
> +
> + ltssm = ls_pcie_ltssm(pcie);
> + if (ltssm < LTSSM_PCIE_L0)
> + return 0;
> +
> + return 1;
> +}
> +
> +static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
> +{
> + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
> + PCIE_ATU_VIEWPORT);
> + dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
> +}
> +
> +static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
> +{
> + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
> + PCIE_ATU_VIEWPORT);
> + dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
> +}
> +
> +static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
> + u64 phys, u64 bus_addr, pci_size_t size)
> +{
> + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
> + dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
> + dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
> + dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
> + dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
> + dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
> + dbi_writel(pcie, type, PCIE_ATU_CR1);
> + dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
> +}
> +
> +/* Use bar match mode and MEM type as default */
> +static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
> + int bar, u64 phys)
> +{
> + dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
> + dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
> + dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
> + dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
> + dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
> + PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
> +}
> +
> +static void ls_pcie_dump_atu(struct ls_pcie *pcie)
> +{
> + int i;
> +
> + for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
> + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
> + PCIE_ATU_VIEWPORT);
> + debug("iATU%d:\n", i);
> + debug("\tLOWER PHYS 0x%08x\n",
> + dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
> + debug("\tUPPER PHYS 0x%08x\n",
> + dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
> + debug("\tLOWER BUS 0x%08x\n",
> + dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
> + debug("\tUPPER BUS 0x%08x\n",
> + dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
> + debug("\tLIMIT 0x%08x\n",
> + readl(pcie->dbi + PCIE_ATU_LIMIT));
> + debug("\tCR1 0x%08x\n",
> + dbi_readl(pcie, PCIE_ATU_CR1));
> + debug("\tCR2 0x%08x\n",
> + dbi_readl(pcie, PCIE_ATU_CR2));
> + }
> +}
> +
> +static void ls_pcie_setup_atu(struct ls_pcie *pcie)
> +{
> + struct pci_region *io, *mem, *pref;
> + unsigned long long offset = 0;
> + int idx = 0;
> +
> +#ifdef CONFIG_LS102XA
> + offset = LS1021_PCIE_SPACE_OFFSET + LS1021_PCIE_SPACE_SIZE * pcie->idx;
> +#endif
Here also
> +
> + /* ATU 0 : OUTBOUND : CFG0 */
> + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
> + PCIE_ATU_TYPE_CFG0,
> + pcie->cfg_res.start + offset,
> + 0,
> + fdt_resource_size(&pcie->cfg_res) / 2);
> + /* ATU 1 : OUTBOUND : CFG1 */
> + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
> + PCIE_ATU_TYPE_CFG1,
> + pcie->cfg_res.start + offset +
> + fdt_resource_size(&pcie->cfg_res) / 2,
> + 0,
> + fdt_resource_size(&pcie->cfg_res) / 2);
> +
> + pci_get_regions(pcie->bus, &io, &mem, &pref);
> + idx = PCIE_ATU_REGION_INDEX1 + 1;
> +
> + if (io)
> + /* ATU : OUTBOUND : IO */
> + ls_pcie_atu_outbound_set(pcie, idx++,
> + PCIE_ATU_TYPE_IO,
> + io->phys_start + offset,
> + io->bus_start,
> + io->size);
> +
> + if (mem)
> + /* ATU : OUTBOUND : MEM */
> + ls_pcie_atu_outbound_set(pcie, idx++,
> + PCIE_ATU_TYPE_MEM,
> + mem->phys_start + offset,
> + mem->bus_start,
> + mem->size);
> +
> + if (pref)
> + /* ATU : OUTBOUND : pref */
> + ls_pcie_atu_outbound_set(pcie, idx++,
> + PCIE_ATU_TYPE_MEM,
> + pref->phys_start + offset,
> + pref->bus_start,
> + pref->size);
> +
> + ls_pcie_dump_atu(pcie);
> +}
> +
> +static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
Function comment, in particular the return value.
> +{
> + struct udevice *bus = pcie->bus;
> +
> + if (!pcie->enabled)
> + return -ENODEV;
That means there is no device. Can it use -ENXIO instead since we
should not be in the driver if there is no devices?
> +
> + if (PCI_BUS(bdf) < bus->seq)
> + return -EINVAL;
> +
> + if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
> + return -EINVAL;
> +
> + if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
> + int offset)
> +{
> + struct udevice *bus = pcie->bus;
> + u32 busdev;
> +
> + if (PCI_BUS(bdf) == bus->seq)
> + return pcie->dbi + offset;
> +
> + busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
> + PCIE_ATU_DEV(PCI_DEV(bdf)) |
> + PCIE_ATU_FUNC(PCI_FUNC(bdf));
> +
> + if (PCI_BUS(bdf) == bus->seq + 1) {
> + ls_pcie_cfg0_set_busdev(pcie, busdev);
> + return pcie->cfg0 + offset;
> + } else {
> + ls_pcie_cfg1_set_busdev(pcie, busdev);
> + return pcie->cfg1 + offset;
> + }
> +}
> +
> +static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
> + uint offset, ulong *valuep,
> + enum pci_size_t size)
> +{
> + struct ls_pcie *pcie = dev_get_priv(bus);
> + void *address;
> +
> + if (ls_pcie_addr_valid(pcie, bdf)) {
> + *valuep = pci_get_ff(size);
> + return 0;
> + }
> +
> + address = ls_pcie_conf_address(pcie, bdf, offset);
> +
> + switch (size) {
> + case PCI_SIZE_8:
> + *valuep = readb(address);
> + return 0;
> + case PCI_SIZE_16:
> + *valuep = readw(address);
> + return 0;
> + case PCI_SIZE_32:
> + *valuep = readl(address);
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
> + uint offset, ulong value,
> + enum pci_size_t size)
> +{
> + struct ls_pcie *pcie = dev_get_priv(bus);
> + void *address;
> +
> + if (ls_pcie_addr_valid(pcie, bdf))
> + return 0;
> +
> + address = ls_pcie_conf_address(pcie, bdf, offset);
> +
> + switch (size) {
> + case PCI_SIZE_8:
> + writeb(value, address);
> + return 0;
> + case PCI_SIZE_16:
> + writew(value, address);
> + return 0;
> + case PCI_SIZE_32:
> + writel(value, address);
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +/* Clear multi-function bit */
> +static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
> +{
> + writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
> +}
> +
> +/* Fix class value */
> +static void ls_pcie_fix_class(struct ls_pcie *pcie)
> +{
> + writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
> +}
> +
> +/* Drop MSG TLP except for Vendor MSG */
> +static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
> +{
> + u32 val;
> +
> + val = dbi_readl(pcie, PCIE_STRFMR1);
> + val &= 0xDFFFFFFF;
> + dbi_writel(pcie, val, PCIE_STRFMR1);
> +}
> +
> +/* Disable all bars in RC mode */
> +static void ls_pcie_disable_bars(struct ls_pcie *pcie)
> +{
> + u32 sriov;
> +
> + sriov = in_le32(pcie->dbi + PCIE_SRIOV);
> +
> + if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
> + return;
Comment this?
> +
> + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
> + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
> + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
> +}
> +
> +static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
> +{
> + ls_pcie_setup_atu(pcie);
> +
> + dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
> + ls_pcie_fix_class(pcie);
> + ls_pcie_clear_multifunction(pcie);
> + ls_pcie_drop_msg_tlp(pcie);
> + dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
> +
> + ls_pcie_disable_bars(pcie);
> +}
> +
> +static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
> +{
> + u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
> +
> + /* ATU 0 : INBOUND : map BAR0 */
> + ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
> + /* ATU 1 : INBOUND : map BAR1 */
> + phys += PCIE_BAR1_SIZE;
> + ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
> + /* ATU 2 : INBOUND : map BAR2 */
> + phys += PCIE_BAR2_SIZE;
> + ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
> + /* ATU 3 : INBOUND : map BAR4 */
> + phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
> + ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
> +
> + /* ATU 0 : OUTBOUND : map MEM */
> + ls_pcie_atu_outbound_set(pcie, 0,
> + PCIE_ATU_TYPE_MEM,
> + pcie->cfg_res.start,
> + 0,
> + CONFIG_SYS_PCI_MEMORY_SIZE);
> +}
> +
> +/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
> +static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
> +{
> + if (size < 4 * 1024)
> + return;
Why? Comment?
> +
> + switch (bar) {
> + case 0:
> + writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
> + break;
> + case 1:
> + writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
> + break;
> + case 2:
> + writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
> + writel(0, bar_base + PCI_BASE_ADDRESS_3);
> + break;
> + case 4:
> + writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
> + writel(0, bar_base + PCI_BASE_ADDRESS_5);
> + break;
> + default:
> + break;
> + }
> +}
> +
> +static void ls_pcie_ep_setup_bars(void *bar_base)
> +{
> + /* BAR0 - 32bit - 4K configuration */
> + ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
> + /* BAR1 - 32bit - 8K MSIX*/
> + ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
> + /* BAR2 - 64bit - 4K MEM desciptor */
> + ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
> + /* BAR4 - 64bit - 1M MEM*/
> + ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
> +}
> +
> +static void ls_pcie_setup_ep(struct ls_pcie *pcie)
> +{
> + u32 sriov;
> +
> + sriov = readl(pcie->dbi + PCIE_SRIOV);
> + if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
> + int pf, vf;
> +
> + for (pf = 0; pf < PCIE_PF_NUM; pf++) {
> + for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
> + ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
> + PCIE_PF_VF_CTRL);
> +
> + ls_pcie_ep_setup_bars(pcie->dbi);
> + ls_pcie_ep_setup_atu(pcie);
> + }
> + }
> + /* Disable CFG2 */
> + ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
> + } else {
> + ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
> + ls_pcie_ep_setup_atu(pcie);
> + }
> +}
> +
> +#ifdef CONFIG_FSL_LSCH3
Can this be a run-time check?
> +/*
> + * Return next available LUT index.
> + */
> +static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
> +{
> + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> + return pcie->next_lut_index++;
> + else
> + return -1; /* LUT is full */
-ENOSPC?
> +}
> +
> +/*
> + * Program a single LUT entry
> + */
> +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
> + u32 streamid)
> +{
> + /* leave mask as all zeroes, want to match all bits */
> + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
> + lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
> +}
> +
> +/* returns the next available streamid */
> +static u32 ls_pcie_next_streamid(void)
> +{
> + static int next_stream_id = FSL_PEX_STREAM_ID_START;
> +
> + if (next_stream_id > FSL_PEX_STREAM_ID_END)
> + return 0xffffffff;
Is FSL_PEX_STREAM_ID_END the maximum value, or the number of values?
> +
> + return next_stream_id++;
> +}
> +
> +/*
> + * An msi-map is a property to be added to the pci controller
> + * node. It is a table, where each entry consists of 4 fields
> + * e.g.:
> + *
> + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
> + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
> + */
> +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
> + u32 devid, u32 streamid)
> +{
> + u32 *prop;
> + u32 phandle;
> + int nodeoffset;
> +
> + /* find pci controller node */
> + nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
> + pcie->dbi_res.start);
At this point I'm a bit lost, but if this is using driver model, you
can use dev->of_offset
> + if (nodeoffset < 0) {
> + #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
Eek! Can't you detect this at run-time?
> + nodeoffset = fdt_node_offset_by_compat_reg(blob,
> + FSL_PCIE_COMPAT,
> + pcie->dbi_res.start);
> + if (nodeoffset < 0)
> + return;
> + #else
> + return;
> + #endif
> + }
> +
> + /* get phandle to MSI controller */
> + prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
fdtdec_getint()
> + if (prop == NULL) {
> + printf("\n%s: ERROR: missing msi-parent: PCIe%d\n",
> + __func__, pcie->idx);
> + return;
Return an error error and check it.
> + }
> + phandle = be32_to_cpu(*prop);
fdt32_to_cpu()
> +
> + /* set one msi-map row */
> + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
> + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
> + fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
> + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
> +}
> +
> +static void fdt_fixup_pcie(void *blob)
This is a pretty horrible function. What is it for?
> +{
> + struct udevice *dev, *bus;
> + struct ls_pcie *pcie;
> + u32 streamid;
> + int index;
> + pci_dev_t bdf;
> +
> + /* Scan all known buses */
> + for (pci_find_first_device(&dev);
> + dev;
> + pci_find_next_device(&dev)) {
> + for (bus = dev; device_is_on_pci_bus(bus);)
> + bus = bus->parent;
> + pcie = dev_get_priv(bus);
> +
> + streamid = ls_pcie_next_streamid();
> + if (streamid == 0xffffffff) {
> + printf("ERROR: no stream ids free\n");
> + continue;
> + }
> +
> + index = ls_pcie_next_lut_index(pcie);
> + if (index < 0) {
> + printf("ERROR: no LUT indexes free\n");
> + continue;
> + }
> +
> + /* the DT fixup must be relative to the hose first_busno */
> + bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
> + /* map PCI b.d.f to streamID in LUT */
> + ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
> + streamid);
> + /* update msi-map in device tree */
> + fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
> + streamid);
> + }
> +}
> +#endif
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +
> +static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
> +{
> + int off;
> +
> + off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
> + pcie->dbi_res.start);
> + if (off < 0) {
> + #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
Run-time check?
> + off = fdt_node_offset_by_compat_reg(blob,
> + FSL_PCIE_COMPAT,
> + pcie->dbi_res.start);
> + if (off < 0)
> + return;
> + #else
> + return;
> + #endif
> + }
> +
> + if (pcie->enabled)
> + fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
> + else
> + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
> +}
> +
> +void ft_pci_setup(void *blob, bd_t *bd)
> +{
> + struct ls_pcie *pcie;
> +
> + list_for_each_entry(pcie, &ls_pcie_list, list)
> + ft_pcie_ls_setup(blob, pcie);
> +
> + #ifdef CONFIG_FSL_LSCH3
# in column one, but as mentioned, this should be a run-time check.
> + fdt_fixup_pcie(blob);
> + #endif
> +}
> +
> +#else
> +void ft_pci_setup(void *blob, bd_t *bd)
> +{
> +}
> +#endif
> +
> +static int ls_pcie_probe(struct udevice *dev)
> +{
> + struct ls_pcie *pcie = dev_get_priv(dev);
> + void *fdt = (void *)gd->fdt_blob;
const void *fdt, then you don't need the cast.
> + int node = dev->of_offset;
> + u8 header_type;
> + u16 link_sta;
> + bool ep_mode;
> + int ret;
> +
> + pcie->bus = dev;
> +
> + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
> + "dbi", &pcie->dbi_res);
> + if (ret) {
> + printf("ls-pcie: resource \"dbi\" not found\n");
> + return ret;
> + }
> +
> + pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
> +
> + list_add(&pcie->list, &ls_pcie_list);
> +
> + pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
> + if (!pcie->enabled) {
> + printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
> + return 0;
> + }
> +
> + pcie->dbi = map_physmem(pcie->dbi_res.start,
> + fdt_resource_size(&pcie->dbi_res),
> + MAP_NOCACHE);
> +
> + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
> + "lut", &pcie->lut_res);
> + if (!ret)
> + pcie->lut = map_physmem(pcie->lut_res.start,
> + fdt_resource_size(&pcie->lut_res),
> + MAP_NOCACHE);
> +
> + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
> + "ctrl", &pcie->ctrl_res);
> + if (!ret)
> + pcie->ctrl = map_physmem(pcie->ctrl_res.start,
> + fdt_resource_size(&pcie->ctrl_res),
> + MAP_NOCACHE);
> + if (!pcie->ctrl)
> + pcie->ctrl = pcie->lut;
> +
> + if (!pcie->ctrl) {
> + printf("%s: NOT find CTRL\n", dev->name);
> + return 0;
Return error?
> + }
> +
> + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
> + "config", &pcie->cfg_res);
> + if (ret) {
> + printf("%s: resource \"config\" not found\n", dev->name);
> + return 0;
Return error?
> + }
> +
> + pcie->cfg0 = map_physmem(pcie->cfg_res.start,
> + fdt_resource_size(&pcie->cfg_res),
> + MAP_NOCACHE);
> + pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
> +
> + pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
> +
> + debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
> + dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
> + (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
> + pcie->big_endian);
> +
> + header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
> + ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
> + printf("PCIe%u: %s %s", pcie->idx, dev->name,
> + ep_mode ? "Endpoint" : "Root Complex");
> +
> + if (ep_mode)
> + ls_pcie_setup_ep(pcie);
> + else
> + ls_pcie_setup_ctrl(pcie);
> +
> + if (!ls_pcie_link_up(pcie)) {
> + /* Let the user know there's no PCIe link */
> + printf(": no link\n");
> + return 0;
Return error?
> + }
> +
> + /* Print the negotiated PCIe link width */
> + link_sta = readw(pcie->dbi + PCIE_LINK_STA);
> + printf(": x%d gen%d\n", (link_sta & 0x3f0) >> 4, link_sta & 0xf);
> +
> + return 0;
> +}
> +
> +static const struct dm_pci_ops ls_pcie_ops = {
> + .read_config = ls_pcie_read_config,
> + .write_config = ls_pcie_write_config,
> +};
> +
> +static const struct udevice_id ls_pcie_ids[] = {
> + { .compatible = "fsl,ls-pcie" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pci_layerscape) = {
> + .name = "pci_layerscape",
> + .id = UCLASS_PCI,
> + .of_match = ls_pcie_ids,
> + .ops = &ls_pcie_ops,
> + .probe = ls_pcie_probe,
> + .priv_auto_alloc_size = sizeof(struct ls_pcie),
> +};
> +
> +#endif /* CONFIG_DM_PCI */
> --
> 2.1.0.27.g96db324
>
Regards,
Simon
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-18 1:14 ` Simon Glass
@ 2016-11-22 9:25 ` Z.Q. Hou
2016-11-24 2:20 ` Simon Glass
0 siblings, 1 reply; 31+ messages in thread
From: Z.Q. Hou @ 2016-11-22 9:25 UTC (permalink / raw)
To: u-boot
Hi Simon,
Sorry for my delay respond due to out of the office several days, and thanks a lot for your comments!
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: 2016?11?18? 9:15
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>
> Hi,
>
> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> wrote:
> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
> >
> > There are more than five kinds of Layerscape SoCs. unfortunately, PCIe
> > controller of each SoC is a little bit different. In order to avoid
> > too many macro definitions, the patch addes a new implementation of
> > PCIe driver based on DM. PCIe dts node is used to describe the
> > difference.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V3:
> > - No change
> >
> > drivers/pci/Kconfig | 8 +
> > drivers/pci/pcie_layerscape.c | 761
> > ++++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 769 insertions(+)
> >
> > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index
> > b8376b4..07d21ea 100644
> > --- a/drivers/pci/Kconfig
> > +++ b/drivers/pci/Kconfig
> > @@ -61,4 +61,12 @@ config PCI_XILINX
> > Enable support for the Xilinx AXI bridge for PCI express, an IP
> block
> > which can be used on some generations of Xilinx FPGAs.
> >
> > +config PCIE_LAYERSCAPE
> > + bool "Layerscape PCIe support"
> > + depends on DM_PCI
> > + help
> > + Support Layerscape PCIe. The Layerscape SoC may have one or
> several
> > + PCIe controllers. The PCIe may works in RC or EP mode
> according to
> > + RCW setting.
>
> Can you please write out RC, EP, RCW in full since this is help?
>
Yes, will add the field of RCW to set the mode of PCIE.
> > +
> > endif
> > diff --git a/drivers/pci/pcie_layerscape.c
> > b/drivers/pci/pcie_layerscape.c index 2e6b986..f107d1c 100644
> > --- a/drivers/pci/pcie_layerscape.c
> > +++ b/drivers/pci/pcie_layerscape.c
> > @@ -11,11 +11,14 @@
> > #include <asm/io.h>
> > #include <errno.h>
> > #include <malloc.h>
> > +#include <dm.h>
> > #ifndef CONFIG_LS102XA
> > #include <asm/arch/fdt.h>
> > #include <asm/arch/soc.h>
> > #endif
>
> This is odd - drivers should not have board-specific code in them.
>
This 2 header files are unused for now, so will remove them.
> >
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > #ifndef CONFIG_SYS_PCI_MEMORY_BUS
> > #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
> #endif @@
> > -40,6 +43,7 @@
> > #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
> > #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
> > #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
> > +#define PCIE_ATU_REGION_NUM 6
> > #define PCIE_ATU_CR1 0x904
> > #define PCIE_ATU_TYPE_MEM (0x0 << 0)
> > #define PCIE_ATU_TYPE_IO (0x2 << 0)
> > @@ -58,6 +62,9 @@
> > #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> > #define PCIE_ATU_UPPER_TARGET 0x91C
> >
> > +/* DBI registers */
> > +#define PCIE_SRIOV 0x178
> > +#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask
> Register1 */
> > #define PCIE_DBI_RO_WR_EN 0x8bc
> >
> > #define PCIE_LINK_CAP 0x7c
> > @@ -88,6 +95,8 @@
> > #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
> > #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
> >
> > +#ifndef CONFIG_DM_PCI
> > +
> > struct ls_pcie {
> > int idx;
> > void __iomem *dbi;
> > @@ -814,3 +823,755 @@ void ft_pci_setup(void *blob, bd_t *bd) { }
> > #endif
> > +
> > +#else
> > +
> > +/* LUT registers */
> > +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> > +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> > +#define PCIE_LUT_ENABLE (1 << 31)
> > +#define PCIE_LUT_ENTRY_COUNT 32
> > +
> > +/* PF Controll registers */
> > +#define PCIE_PF_VF_CTRL 0x7F8
> > +#define PCIE_PF_DBG 0x7FC
> > +
> > +#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
> > +#define PCIE_SYS_BASE_ADDR 0x3400000
> > +#define PCIE_CCSR_SIZE 0x0100000
> > +
> > +/* CS2 */
> > +#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without
> SR-IOV */
> > +
> > +#ifdef CONFIG_LS102XA
> > +/* LS1021a PCIE space */
> > +#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
> > +#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL
> > +
> > +/* LS1021a PEX1/2 Misc Ports Status Register */
> > +#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
> > +#define LS1021_LTSSM_STATE_SHIFT 20
> > +#endif
> > +
> > +struct ls_pcie {
> > + int idx;
> > + struct list_head list;
> > + struct udevice *bus;
> > + struct fdt_resource dbi_res;
> > + struct fdt_resource lut_res;
> > + struct fdt_resource ctrl_res;
> > + struct fdt_resource cfg_res;
> > + void __iomem *dbi;
> > + void __iomem *lut;
> > + void __iomem *ctrl;
> > + void __iomem *cfg0;
> > + void __iomem *cfg1;
> > + bool big_endian;
> > + bool enabled;
> > + int next_lut_index;
> > + struct pci_controller hose;
> > +};
> > +
> > +static LIST_HEAD(ls_pcie_list);
> > +
> > +static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int
> > +offset) {
> > + return in_le32(pcie->dbi + offset); }
> > +
> > +static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
> > + unsigned int offset) {
> > + out_le32(pcie->dbi + offset, value); }
> > +
> > +#ifdef CONFIG_FSL_LSCH3
> > +static void lut_writel(struct ls_pcie *pcie, unsigned int value,
> > + unsigned int offset) {
> > + if (pcie->big_endian)
> > + out_be32(pcie->lut + offset, value);
> > + else
> > + out_le32(pcie->lut + offset, value); } #endif
> > +
> > +static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int
> > +offset) {
> > + if (pcie->big_endian)
> > + return in_be32(pcie->ctrl + offset);
> > + else
> > + return in_le32(pcie->ctrl + offset); }
> > +
> > +static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
> > + unsigned int offset) {
> > + if (pcie->big_endian)
> > + out_be32(pcie->ctrl + offset, value);
> > + else
> > + out_le32(pcie->ctrl + offset, value); }
> > +
> > +#ifdef CONFIG_LS102XA
>
> Ick, should not have board-specific code here. Perhaps add a private run-time
> value indicating whether to do this or not.
Yes, totally agree, will consolidate this function.
>
> > +static int ls_pcie_ltssm(struct ls_pcie *pcie) {
> > + u32 state;
> > +
> > + state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
> > + state = (state >> LS1021_LTSSM_STATE_SHIFT) &
> > + LTSSM_STATE_MASK;
> > +
> > + return state;
> > +}
> > +#else
> > +static int ls_pcie_ltssm(struct ls_pcie *pcie) {
> > + return ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK; }
> > +#endif
> > +
> > +static int ls_pcie_link_up(struct ls_pcie *pcie) {
> > + int ltssm;
> > +
> > + ltssm = ls_pcie_ltssm(pcie);
> > + if (ltssm < LTSSM_PCIE_L0)
> > + return 0;
> > +
> > + return 1;
> > +}
> > +
> > +static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
> > +{
> > + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND |
> PCIE_ATU_REGION_INDEX0,
> > + PCIE_ATU_VIEWPORT);
> > + dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); }
> > +
> > +static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
> > +{
> > + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND |
> PCIE_ATU_REGION_INDEX1,
> > + PCIE_ATU_VIEWPORT);
> > + dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); }
> > +
> > +static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
> > + u64 phys, u64 bus_addr,
> > +pci_size_t size) {
> > + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx,
> PCIE_ATU_VIEWPORT);
> > + dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
> > + dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
> > + dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
> > + dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
> > + dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
> > + dbi_writel(pcie, type, PCIE_ATU_CR1);
> > + dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2); }
> > +
> > +/* Use bar match mode and MEM type as default */ static void
> > +ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
> > + int bar, u64 phys) {
> > + dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx,
> PCIE_ATU_VIEWPORT);
> > + dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
> > + dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
> > + dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
> > + dbi_writel(pcie, PCIE_ATU_ENABLE |
> PCIE_ATU_BAR_MODE_ENABLE |
> > + PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2); }
> > +
> > +static void ls_pcie_dump_atu(struct ls_pcie *pcie) {
> > + int i;
> > +
> > + for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
> > + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
> > + PCIE_ATU_VIEWPORT);
> > + debug("iATU%d:\n", i);
> > + debug("\tLOWER PHYS 0x%08x\n",
> > + dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
> > + debug("\tUPPER PHYS 0x%08x\n",
> > + dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
> > + debug("\tLOWER BUS 0x%08x\n",
> > + dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
> > + debug("\tUPPER BUS 0x%08x\n",
> > + dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
> > + debug("\tLIMIT 0x%08x\n",
> > + readl(pcie->dbi + PCIE_ATU_LIMIT));
> > + debug("\tCR1 0x%08x\n",
> > + dbi_readl(pcie, PCIE_ATU_CR1));
> > + debug("\tCR2 0x%08x\n",
> > + dbi_readl(pcie, PCIE_ATU_CR2));
> > + }
> > +}
> > +
> > +static void ls_pcie_setup_atu(struct ls_pcie *pcie) {
> > + struct pci_region *io, *mem, *pref;
> > + unsigned long long offset = 0;
> > + int idx = 0;
> > +
> > +#ifdef CONFIG_LS102XA
> > + offset = LS1021_PCIE_SPACE_OFFSET + LS1021_PCIE_SPACE_SIZE *
> > +pcie->idx; #endif
>
> Here also
>
Yes
> > +
> > + /* ATU 0 : OUTBOUND : CFG0 */
> > + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
> > + PCIE_ATU_TYPE_CFG0,
> > + pcie->cfg_res.start + offset,
> > + 0,
> > + fdt_resource_size(&pcie->cfg_res) /
> 2);
> > + /* ATU 1 : OUTBOUND : CFG1 */
> > + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
> > + PCIE_ATU_TYPE_CFG1,
> > + pcie->cfg_res.start + offset +
> > + fdt_resource_size(&pcie->cfg_res) /
> 2,
> > + 0,
> > + fdt_resource_size(&pcie->cfg_res) /
> > + 2);
> > +
> > + pci_get_regions(pcie->bus, &io, &mem, &pref);
> > + idx = PCIE_ATU_REGION_INDEX1 + 1;
> > +
> > + if (io)
> > + /* ATU : OUTBOUND : IO */
> > + ls_pcie_atu_outbound_set(pcie, idx++,
> > + PCIE_ATU_TYPE_IO,
> > + io->phys_start + offset,
> > + io->bus_start,
> > + io->size);
> > +
> > + if (mem)
> > + /* ATU : OUTBOUND : MEM */
> > + ls_pcie_atu_outbound_set(pcie, idx++,
> > + PCIE_ATU_TYPE_MEM,
> > + mem->phys_start + offset,
> > + mem->bus_start,
> > + mem->size);
> > +
> > + if (pref)
> > + /* ATU : OUTBOUND : pref */
> > + ls_pcie_atu_outbound_set(pcie, idx++,
> > + PCIE_ATU_TYPE_MEM,
> > + pref->phys_start + offset,
> > + pref->bus_start,
> > + pref->size);
> > +
> > + ls_pcie_dump_atu(pcie);
> > +}
> > +
> > +static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
>
> Function comment, in particular the return value.
>
Yes, will add comments for this function.
> > +{
> > + struct udevice *bus = pcie->bus;
> > +
> > + if (!pcie->enabled)
> > + return -ENODEV;
>
> That means there is no device. Can it use -ENXIO instead since we should not
> be in the driver if there is no devices?
>
Yes, agree with you and will fix in next version.
> > +
> > + if (PCI_BUS(bdf) < bus->seq)
> > + return -EINVAL;
> > +
> > + if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
> > + return -EINVAL;
> > +
> > + if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
> > +void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
> > + int offset) {
> > + struct udevice *bus = pcie->bus;
> > + u32 busdev;
> > +
> > + if (PCI_BUS(bdf) == bus->seq)
> > + return pcie->dbi + offset;
> > +
> > + busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
> > + PCIE_ATU_DEV(PCI_DEV(bdf)) |
> > + PCIE_ATU_FUNC(PCI_FUNC(bdf));
> > +
> > + if (PCI_BUS(bdf) == bus->seq + 1) {
> > + ls_pcie_cfg0_set_busdev(pcie, busdev);
> > + return pcie->cfg0 + offset;
> > + } else {
> > + ls_pcie_cfg1_set_busdev(pcie, busdev);
> > + return pcie->cfg1 + offset;
> > + }
> > +}
> > +
> > +static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
> > + uint offset, ulong *valuep,
> > + enum pci_size_t size) {
> > + struct ls_pcie *pcie = dev_get_priv(bus);
> > + void *address;
> > +
> > + if (ls_pcie_addr_valid(pcie, bdf)) {
> > + *valuep = pci_get_ff(size);
> > + return 0;
> > + }
> > +
> > + address = ls_pcie_conf_address(pcie, bdf, offset);
> > +
> > + switch (size) {
> > + case PCI_SIZE_8:
> > + *valuep = readb(address);
> > + return 0;
> > + case PCI_SIZE_16:
> > + *valuep = readw(address);
> > + return 0;
> > + case PCI_SIZE_32:
> > + *valuep = readl(address);
> > + return 0;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
> > + uint offset, ulong value,
> > + enum pci_size_t size) {
> > + struct ls_pcie *pcie = dev_get_priv(bus);
> > + void *address;
> > +
> > + if (ls_pcie_addr_valid(pcie, bdf))
> > + return 0;
> > +
> > + address = ls_pcie_conf_address(pcie, bdf, offset);
> > +
> > + switch (size) {
> > + case PCI_SIZE_8:
> > + writeb(value, address);
> > + return 0;
> > + case PCI_SIZE_16:
> > + writew(value, address);
> > + return 0;
> > + case PCI_SIZE_32:
> > + writel(value, address);
> > + return 0;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +/* Clear multi-function bit */
> > +static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) {
> > + writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi +
> PCI_HEADER_TYPE); }
> > +
> > +/* Fix class value */
> > +static void ls_pcie_fix_class(struct ls_pcie *pcie) {
> > + writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); }
> > +
> > +/* Drop MSG TLP except for Vendor MSG */ static void
> > +ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) {
> > + u32 val;
> > +
> > + val = dbi_readl(pcie, PCIE_STRFMR1);
> > + val &= 0xDFFFFFFF;
> > + dbi_writel(pcie, val, PCIE_STRFMR1); }
> > +
> > +/* Disable all bars in RC mode */
> > +static void ls_pcie_disable_bars(struct ls_pcie *pcie) {
> > + u32 sriov;
> > +
> > + sriov = in_le32(pcie->dbi + PCIE_SRIOV);
> > +
> > + if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
> > + return;
>
> Comment this?
>
Will add comments for this condition.
> > +
> > + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
> > + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
> > + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1); }
> > +
> > +static void ls_pcie_setup_ctrl(struct ls_pcie *pcie) {
> > + ls_pcie_setup_atu(pcie);
> > +
> > + dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
> > + ls_pcie_fix_class(pcie);
> > + ls_pcie_clear_multifunction(pcie);
> > + ls_pcie_drop_msg_tlp(pcie);
> > + dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
> > +
> > + ls_pcie_disable_bars(pcie);
> > +}
> > +
> > +static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie) {
> > + u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
> > +
> > + /* ATU 0 : INBOUND : map BAR0 */
> > + ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
> > + /* ATU 1 : INBOUND : map BAR1 */
> > + phys += PCIE_BAR1_SIZE;
> > + ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
> > + /* ATU 2 : INBOUND : map BAR2 */
> > + phys += PCIE_BAR2_SIZE;
> > + ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
> > + /* ATU 3 : INBOUND : map BAR4 */
> > + phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
> > + ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
> > +
> > + /* ATU 0 : OUTBOUND : map MEM */
> > + ls_pcie_atu_outbound_set(pcie, 0,
> > + PCIE_ATU_TYPE_MEM,
> > + pcie->cfg_res.start,
> > + 0,
> > + CONFIG_SYS_PCI_MEMORY_SIZE); }
> > +
> > +/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ static void
> > +ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) {
> > + if (size < 4 * 1024)
> > + return;
>
> Why? Comment?
Layerscape PCIe controller limited the least inbound window is 4KiB, and will add comments for this condition.
> > +
> > + switch (bar) {
> > + case 0:
> > + writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
> > + break;
> > + case 1:
> > + writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
> > + break;
> > + case 2:
> > + writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
> > + writel(0, bar_base + PCI_BASE_ADDRESS_3);
> > + break;
> > + case 4:
> > + writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
> > + writel(0, bar_base + PCI_BASE_ADDRESS_5);
> > + break;
> > + default:
> > + break;
> > + }
> > +}
> > +
> > +static void ls_pcie_ep_setup_bars(void *bar_base) {
> > + /* BAR0 - 32bit - 4K configuration */
> > + ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
> > + /* BAR1 - 32bit - 8K MSIX*/
> > + ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
> > + /* BAR2 - 64bit - 4K MEM desciptor */
> > + ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
> > + /* BAR4 - 64bit - 1M MEM*/
> > + ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); }
> > +
> > +static void ls_pcie_setup_ep(struct ls_pcie *pcie) {
> > + u32 sriov;
> > +
> > + sriov = readl(pcie->dbi + PCIE_SRIOV);
> > + if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
> > + int pf, vf;
> > +
> > + for (pf = 0; pf < PCIE_PF_NUM; pf++) {
> > + for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
> > + ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf,
> vf),
> > + PCIE_PF_VF_CTRL);
> > +
> > + ls_pcie_ep_setup_bars(pcie->dbi);
> > + ls_pcie_ep_setup_atu(pcie);
> > + }
> > + }
> > + /* Disable CFG2 */
> > + ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
> > + } else {
> > + ls_pcie_ep_setup_bars(pcie->dbi +
> PCIE_NO_SRIOV_BAR_BASE);
> > + ls_pcie_ep_setup_atu(pcie);
> > + }
> > +}
> > +
> > +#ifdef CONFIG_FSL_LSCH3
>
> Can this be a run-time check?
No, it is for Linux DT fixup and these functions is needed only by FSL_LSCH3 SoCs.
>
> > +/*
> > + * Return next available LUT index.
> > + */
> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> > + return pcie->next_lut_index++;
> > + else
> > + return -1; /* LUT is full */
>
> -ENOSPC?
Yes, ENOSPC is more reasonable.
>
> > +}
> > +
> > +/*
> > + * Program a single LUT entry
> > + */
> > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32
> devid,
> > + u32 streamid) {
> > + /* leave mask as all zeroes, want to match all bits */
> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
> > +PCIE_LUT_LDR(index)); }
> > +
> > +/* returns the next available streamid */ static u32
> > +ls_pcie_next_streamid(void) {
> > + static int next_stream_id = FSL_PEX_STREAM_ID_START;
> > +
> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
> > + return 0xffffffff;
>
> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of values?
The maximum value for PCIe.
> > +
> > + return next_stream_id++;
> > +}
> > +
> > +/*
> > + * An msi-map is a property to be added to the pci controller
> > + * node. It is a table, where each entry consists of 4 fields
> > + * e.g.:
> > + *
> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
> > + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
> > + */
> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
> > + u32 devid, u32 streamid) {
> > + u32 *prop;
> > + u32 phandle;
> > + int nodeoffset;
> > +
> > + /* find pci controller node */
> > + nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
> > +
> > + pcie->dbi_res.start);
>
> At this point I'm a bit lost, but if this is using driver model, you can use
> dev->of_offset
This function is used to fixup Linux Kernel DT instead of u-boot DT.
>
> > + if (nodeoffset < 0) {
> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts
> > + node */
>
> Eek! Can't you detect this at run-time?
>
No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe Linux driver using the compatible "fsl,ls-pcie",
but for now the macro FSL_PCIE_COMPAT must be defined to fixup Linux DT.
> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
> > +
> FSL_PCIE_COMPAT,
> > +
> pcie->dbi_res.start);
> > + if (nodeoffset < 0)
> > + return;
> > + #else
> > + return;
> > + #endif
> > + }
> > +
> > + /* get phandle to MSI controller */
> > + prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
>
> fdtdec_getint()
The fdtdec_get_int() is not suit for this case, because the value of "msi-parent" is an index of gic-its, so there isn't a default value.
>
> > + if (prop == NULL) {
> > + printf("\n%s: ERROR: missing msi-parent: PCIe%d\n",
> > + __func__, pcie->idx);
> > + return;
>
> Return an error error and check it.
This function is used to fixup Linux DT, so this error won't block the u-boot process, and I think an error message is enough.
> > + }
> > + phandle = be32_to_cpu(*prop);
>
> fdt32_to_cpu()
>
Yes, better to use fdt32_to_cpu.
> > +
> > + /* set one msi-map row */
> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
> > +
> > +static void fdt_fixup_pcie(void *blob)
>
> This is a pretty horrible function. What is it for?
Kernel DT fixup.
> > +{
> > + struct udevice *dev, *bus;
> > + struct ls_pcie *pcie;
> > + u32 streamid;
> > + int index;
> > + pci_dev_t bdf;
> > +
> > + /* Scan all known buses */
> > + for (pci_find_first_device(&dev);
> > + dev;
> > + pci_find_next_device(&dev)) {
> > + for (bus = dev; device_is_on_pci_bus(bus);)
> > + bus = bus->parent;
> > + pcie = dev_get_priv(bus);
> > +
> > + streamid = ls_pcie_next_streamid();
> > + if (streamid == 0xffffffff) {
> > + printf("ERROR: no stream ids free\n");
> > + continue;
> > + }
> > +
> > + index = ls_pcie_next_lut_index(pcie);
> > + if (index < 0) {
> > + printf("ERROR: no LUT indexes free\n");
> > + continue;
> > + }
> > +
> > + /* the DT fixup must be relative to the hose first_busno
> */
> > + bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
> > + /* map PCI b.d.f to streamID in LUT */
> > + ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
> > + streamid);
> > + /* update msi-map in device tree */
> > + fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
> > + streamid);
> > + }
> > +}
> > +#endif
> > +
> > +#ifdef CONFIG_OF_BOARD_SETUP
> > +#include <libfdt.h>
> > +#include <fdt_support.h>
> > +
> > +static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) {
> > + int off;
> > +
> > + off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
> > + pcie->dbi_res.start);
> > + if (off < 0) {
> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts
> > + node */
>
> Run-time check?
No, it is still Kernel DT fixup.
> > + off = fdt_node_offset_by_compat_reg(blob,
> > +
> FSL_PCIE_COMPAT,
> > +
> pcie->dbi_res.start);
> > + if (off < 0)
> > + return;
> > + #else
> > + return;
> > + #endif
> > + }
> > +
> > + if (pcie->enabled)
> > + fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
> > + else
> > + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED,
> > +0); }
> > +
> > +void ft_pci_setup(void *blob, bd_t *bd) {
> > + struct ls_pcie *pcie;
> > +
> > + list_for_each_entry(pcie, &ls_pcie_list, list)
> > + ft_pcie_ls_setup(blob, pcie);
> > +
> > + #ifdef CONFIG_FSL_LSCH3
>
> # in column one, but as mentioned, this should be a run-time check.
>
Yes, will correct the indent of #.
> > + fdt_fixup_pcie(blob);
> > + #endif
> > +}
> > +
> > +#else
> > +void ft_pci_setup(void *blob, bd_t *bd) { } #endif
> > +
> > +static int ls_pcie_probe(struct udevice *dev) {
> > + struct ls_pcie *pcie = dev_get_priv(dev);
> > + void *fdt = (void *)gd->fdt_blob;
>
> const void *fdt, then you don't need the cast.
>
Yes, will fix next version.
> > + int node = dev->of_offset;
> > + u8 header_type;
> > + u16 link_sta;
> > + bool ep_mode;
> > + int ret;
> > +
> > + pcie->bus = dev;
> > +
> > + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
> > + "dbi", &pcie->dbi_res);
> > + if (ret) {
> > + printf("ls-pcie: resource \"dbi\" not found\n");
> > + return ret;
> > + }
> > +
> > + pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) /
> > + PCIE_CCSR_SIZE;
> > +
> > + list_add(&pcie->list, &ls_pcie_list);
> > +
> > + pcie->enabled =
> is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
> > + if (!pcie->enabled) {
> > + printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
> > + return 0;
> > + }
> > +
> > + pcie->dbi = map_physmem(pcie->dbi_res.start,
> > + fdt_resource_size(&pcie->dbi_res),
> > + MAP_NOCACHE);
> > +
> > + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
> > + "lut", &pcie->lut_res);
> > + if (!ret)
> > + pcie->lut = map_physmem(pcie->lut_res.start,
> > +
> fdt_resource_size(&pcie->lut_res),
> > + MAP_NOCACHE);
> > +
> > + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
> > + "ctrl", &pcie->ctrl_res);
> > + if (!ret)
> > + pcie->ctrl = map_physmem(pcie->ctrl_res.start,
> > +
> fdt_resource_size(&pcie->ctrl_res),
> > + MAP_NOCACHE);
> > + if (!pcie->ctrl)
> > + pcie->ctrl = pcie->lut;
> > +
> > + if (!pcie->ctrl) {
> > + printf("%s: NOT find CTRL\n", dev->name);
> > + return 0;
>
> Return error?
Yes, it should return error.
> > + }
> > +
> > + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
> > + "config", &pcie->cfg_res);
> > + if (ret) {
> > + printf("%s: resource \"config\" not found\n",
> dev->name);
> > + return 0;
>
> Return error?
Yes, will return error.
> > + }
> > +
> > + pcie->cfg0 = map_physmem(pcie->cfg_res.start,
> > + fdt_resource_size(&pcie->cfg_res),
> > + MAP_NOCACHE);
> > + pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) /
> > + 2;
> > +
> > + pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
> > +
> > + debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
> > + dev->name, (unsigned long)pcie->dbi, (unsigned
> long)pcie->lut,
> > + (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
> > + pcie->big_endian);
> > +
> > + header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
> > + ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
> > + printf("PCIe%u: %s %s", pcie->idx, dev->name,
> > + ep_mode ? "Endpoint" : "Root Complex");
> > +
> > + if (ep_mode)
> > + ls_pcie_setup_ep(pcie);
> > + else
> > + ls_pcie_setup_ctrl(pcie);
> > +
> > + if (!ls_pcie_link_up(pcie)) {
> > + /* Let the user know there's no PCIe link */
> > + printf(": no link\n");
> > + return 0;
>
> Return error?
>
The no link condition is not an error, it is a info.
> > + }
> > +
> > + /* Print the negotiated PCIe link width */
> > + link_sta = readw(pcie->dbi + PCIE_LINK_STA);
> > + printf(": x%d gen%d\n", (link_sta & 0x3f0) >> 4, link_sta &
> > + 0xf);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct dm_pci_ops ls_pcie_ops = {
> > + .read_config = ls_pcie_read_config,
> > + .write_config = ls_pcie_write_config,
> > +};
> > +
> > +static const struct udevice_id ls_pcie_ids[] = {
> > + { .compatible = "fsl,ls-pcie" },
> > + { }
> > +};
> > +
> > +U_BOOT_DRIVER(pci_layerscape) = {
> > + .name = "pci_layerscape",
> > + .id = UCLASS_PCI,
> > + .of_match = ls_pcie_ids,
> > + .ops = &ls_pcie_ops,
> > + .probe = ls_pcie_probe,
> > + .priv_auto_alloc_size = sizeof(struct ls_pcie), };
> > +
> > +#endif /* CONFIG_DM_PCI */
> > --
> > 2.1.0.27.g96db324
> >
>
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-22 9:25 ` Z.Q. Hou
@ 2016-11-24 2:20 ` Simon Glass
2016-11-24 9:28 ` Z.Q. Hou
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2016-11-24 2:20 UTC (permalink / raw)
To: u-boot
Hi,
On 22 November 2016 at 02:25, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> Hi Simon,
>
> Sorry for my delay respond due to out of the office several days, and thanks a lot for your comments!
>
>> -----Original Message-----
>> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
>> Sent: 2016?11?18? 9:15
>> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
>> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
>> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
>> <mingkai.hu@nxp.com>
>> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>>
>> Hi,
>>
>> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
>> wrote:
>> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
>> >
>> > There are more than five kinds of Layerscape SoCs. unfortunately, PCIe
>> > controller of each SoC is a little bit different. In order to avoid
>> > too many macro definitions, the patch addes a new implementation of
>> > PCIe driver based on DM. PCIe dts node is used to describe the
>> > difference.
>> >
>> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>> > ---
>> > V3:
>> > - No change
>> >
>> > drivers/pci/Kconfig | 8 +
>> > drivers/pci/pcie_layerscape.c | 761
>> > ++++++++++++++++++++++++++++++++++++++++++
>> > 2 files changed, 769 insertions(+)
>> >
>> > +#ifdef CONFIG_FSL_LSCH3
>>
>> Can this be a run-time check?
>
> No, it is for Linux DT fixup and these functions is needed only by FSL_LSCH3 SoCs.
I mean that you cannot have an #ifdef in a driver - it should be done
at run-time by looking at the compatible strings.
>
>>
>> > +/*
>> > + * Return next available LUT index.
>> > + */
>> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
>> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
>> > + return pcie->next_lut_index++;
>> > + else
>> > + return -1; /* LUT is full */
>>
>> -ENOSPC?
>
> Yes, ENOSPC is more reasonable.
>
>>
>> > +}
>> > +
>> > +/*
>> > + * Program a single LUT entry
>> > + */
>> > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32
>> devid,
>> > + u32 streamid) {
>> > + /* leave mask as all zeroes, want to match all bits */
>> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
>> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
>> > +PCIE_LUT_LDR(index)); }
>> > +
>> > +/* returns the next available streamid */ static u32
>> > +ls_pcie_next_streamid(void) {
>> > + static int next_stream_id = FSL_PEX_STREAM_ID_START;
>> > +
>> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
>> > + return 0xffffffff;
>>
>> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of values?
>
> The maximum value for PCIe.
>
>> > +
>> > + return next_stream_id++;
>> > +}
>> > +
>> > +/*
>> > + * An msi-map is a property to be added to the pci controller
>> > + * node. It is a table, where each entry consists of 4 fields
>> > + * e.g.:
>> > + *
>> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
>> > + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
>> > + */
>> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
>> > + u32 devid, u32 streamid) {
>> > + u32 *prop;
>> > + u32 phandle;
>> > + int nodeoffset;
>> > +
>> > + /* find pci controller node */
>> > + nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
>> > +
>> > + pcie->dbi_res.start);
>>
>> At this point I'm a bit lost, but if this is using driver model, you can use
>> dev->of_offset
>
> This function is used to fixup Linux Kernel DT instead of u-boot DT.
They should use the same DT.
>
>>
>> > + if (nodeoffset < 0) {
>> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts
>> > + node */
>>
>> Eek! Can't you detect this at run-time?
>>
>
> No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe Linux driver using the compatible "fsl,ls-pcie",
> but for now the macro FSL_PCIE_COMPAT must be defined to fixup Linux DT.
I'm still confused by this. I don't see it defined anywhere and it is
not a CONFIG. Can you not detect at run-time when you need to do the
fix-up?
>
>> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
>> > +
>> FSL_PCIE_COMPAT,
>> > +
>> pcie->dbi_res.start);
>> > + if (nodeoffset < 0)
>> > + return;
>> > + #else
>> > + return;
>> > + #endif
>> > + }
>> > +
>> > + /* get phandle to MSI controller */
>> > + prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
>>
>> fdtdec_getint()
>
> The fdtdec_get_int() is not suit for this case, because the value of "msi-parent" is an index of gic-its, so there isn't a default value.
Try:
val = fdtdec_get_int(blob, nodeoffset, "msi-parent", -1)
if (val == -1) {
debug(...);
return -EINVAL;
}
>
>>
>> > + if (prop == NULL) {
>> > + printf("\n%s: ERROR: missing msi-parent: PCIe%d\n",
>> > + __func__, pcie->idx);
>> > + return;
>>
>> Return an error error and check it.
>
> This function is used to fixup Linux DT, so this error won't block the u-boot process, and I think an error message is enough.
If it is an error it should return an error. If it is just a warning
it should say so, ideally using debug(). As it is, it is very
confusing for the user to get this message.
>
>> > + }
>> > + phandle = be32_to_cpu(*prop);
>>
>> fdt32_to_cpu()
>>
>
> Yes, better to use fdt32_to_cpu.
But where do you use that value? Also. consider fdtdec_lookup_phandle().
>
>> > +
>> > + /* set one msi-map row */
>> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
>> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
>> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
>> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
>> > +
>> > +static void fdt_fixup_pcie(void *blob)
>>
>> This is a pretty horrible function. What is it for?
>
> Kernel DT fixup.
OK, well please add some comments!
[...]
Regards,
Simon
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-24 2:20 ` Simon Glass
@ 2016-11-24 9:28 ` Z.Q. Hou
2016-11-27 17:02 ` Simon Glass
0 siblings, 1 reply; 31+ messages in thread
From: Z.Q. Hou @ 2016-11-24 9:28 UTC (permalink / raw)
To: u-boot
Hi Simon,
Thanks for your comments!
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: 2016?11?24? 10:21
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>
> Hi,
>
> On 22 November 2016 at 02:25, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> > Hi Simon,
> >
> > Sorry for my delay respond due to out of the office several days, and thanks
> a lot for your comments!
> >
> >> -----Original Message-----
> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> >> Sent: 2016?11?18? 9:15
> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> Ruchika
> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H.
> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> Mingkai
> >> Hu <mingkai.hu@nxp.com>
> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on
> >> DM
> >>
> >> Hi,
> >>
> >> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> >> wrote:
> >> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
> >> >
> >> > There are more than five kinds of Layerscape SoCs. unfortunately,
> >> > PCIe controller of each SoC is a little bit different. In order to
> >> > avoid too many macro definitions, the patch addes a new
> >> > implementation of PCIe driver based on DM. PCIe dts node is used to
> >> > describe the difference.
> >> >
> >> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> >> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >> > ---
> >> > V3:
> >> > - No change
> >> >
> >> > drivers/pci/Kconfig | 8 +
> >> > drivers/pci/pcie_layerscape.c | 761
> >> > ++++++++++++++++++++++++++++++++++++++++++
> >> > 2 files changed, 769 insertions(+)
> >> >
>
> >> > +#ifdef CONFIG_FSL_LSCH3
> >>
> >> Can this be a run-time check?
> >
> > No, it is for Linux DT fixup and these functions is needed only by FSL_LSCH3
> SoCs.
>
> I mean that you cannot have an #ifdef in a driver - it should be done at
> run-time by looking at the compatible strings.
This driver work for many platforms, but this fixup is only used by FSL_LSCH3 SoCs,
if check the compatible string at run-time, the fixup will be still compiled for the platform which doesn't need it.
Why compile it into the binary for the platform which doesn't need it?
> >
> >>
> >> > +/*
> >> > + * Return next available LUT index.
> >> > + */
> >> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
> >> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> >> > + return pcie->next_lut_index++;
> >> > + else
> >> > + return -1; /* LUT is full */
> >>
> >> -ENOSPC?
> >
> > Yes, ENOSPC is more reasonable.
> >
> >>
> >> > +}
> >> > +
> >> > +/*
> >> > + * Program a single LUT entry
> >> > + */
> >> > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int
> >> > +index, u32
> >> devid,
> >> > + u32 streamid) {
> >> > + /* leave mask as all zeroes, want to match all bits */
> >> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
> >> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
> >> > +PCIE_LUT_LDR(index)); }
> >> > +
> >> > +/* returns the next available streamid */ static u32
> >> > +ls_pcie_next_streamid(void) {
> >> > + static int next_stream_id = FSL_PEX_STREAM_ID_START;
> >> > +
> >> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
> >> > + return 0xffffffff;
> >>
> >> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of values?
> >
> > The maximum value for PCIe.
> >
> >> > +
> >> > + return next_stream_id++;
> >> > +}
> >> > +
> >> > +/*
> >> > + * An msi-map is a property to be added to the pci controller
> >> > + * node. It is a table, where each entry consists of 4 fields
> >> > + * e.g.:
> >> > + *
> >> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
> >> > + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
> >> > + */
> >> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
> >> > + u32 devid, u32 streamid) {
> >> > + u32 *prop;
> >> > + u32 phandle;
> >> > + int nodeoffset;
> >> > +
> >> > + /* find pci controller node */
> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
> >> > + "fsl,ls-pcie",
> >> > +
> >> > + pcie->dbi_res.start);
> >>
> >> At this point I'm a bit lost, but if this is using driver model, you
> >> can use
> >> dev->of_offset
> >
> > This function is used to fixup Linux Kernel DT instead of u-boot DT.
>
> They should use the same DT.
Yes, Ideally they should, but up to now actually Kernel does not use the one u-boot
used, so we cannot make sure the offset of the nodes are the same.
So to ensure the fixup work, get the node offset from kernel DT.
>
> >
> >>
> >> > + if (nodeoffset < 0) {
> >> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older version of
> >> > + dts node */
> >>
> >> Eek! Can't you detect this at run-time?
> >>
> >
> > No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe Linux
> > driver using the compatible "fsl,ls-pcie", but for now the macro
> FSL_PCIE_COMPAT must be defined to fixup Linux DT.
>
> I'm still confused by this. I don't see it defined anywhere and it is not a CONFIG.
> Can you not detect at run-time when you need to do the fix-up?
Ok, the process is find the node offset by "fsl,ls-pcie" first, if failed, find it again by FSL_PCIE_COMPAT.
But in the current kernel DT the name of PCIe controller node is NOT the "fsl,ls-pcie" which we will
refactor layerscape pcie kernel driver to use, so far it is the FSL_PCIE_COMPAT which is defined
according to the current kernel DT in header file include/configs/ls*.h.
So it is unable to be detected at run-time, but it will be removed when the kernel driver refactored.
>
> >
> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
> >> > +
> >> FSL_PCIE_COMPAT,
> >> > +
> >> pcie->dbi_res.start);
> >> > + if (nodeoffset < 0)
> >> > + return;
> >> > + #else
> >> > + return;
> >> > + #endif
> >> > + }
> >> > +
> >> > + /* get phandle to MSI controller */
> >> > + prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent",
> >> > + 0);
> >>
> >> fdtdec_getint()
> >
> > The fdtdec_get_int() is not suit for this case, because the value of
> "msi-parent" is an index of gic-its, so there isn't a default value.
>
> Try:
>
> val = fdtdec_get_int(blob, nodeoffset, "msi-parent", -1)
> if (val == -1) {
> debug(...);
> return -EINVAL;
> }
>
Any benefit compared with fdt_getprop? I'm confused by this function, what if the correct value equal to the given default value?
> >
> >>
> >> > + if (prop == NULL) {
> >> > + printf("\n%s: ERROR: missing msi-parent: PCIe%d\n",
> >> > + __func__, pcie->idx);
> >> > + return;
> >>
> >> Return an error error and check it.
> >
> > This function is used to fixup Linux DT, so this error won't block the u-boot
> process, and I think an error message is enough.
>
> If it is an error it should return an error. If it is just a warning it should say so,
> ideally using debug(). As it is, it is very confusing for the user to get this
> message.
Will replace with debug().
> >
> >> > + }
> >> > + phandle = be32_to_cpu(*prop);
> >>
> >> fdt32_to_cpu()
> >>
> >
> > Yes, better to use fdt32_to_cpu.
>
> But where do you use that value? Also. consider fdtdec_lookup_phandle().
Thanks for your tip, just the value of this phandle is used, see the lines below.
> >
> >> > +
> >> > + /* set one msi-map row */
> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
> >> > +
> >> > +static void fdt_fixup_pcie(void *blob)
> >>
> >> This is a pretty horrible function. What is it for?
> >
> > Kernel DT fixup.
>
> OK, well please add some comments!
Will comment it.
> [...]
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-24 9:28 ` Z.Q. Hou
@ 2016-11-27 17:02 ` Simon Glass
2016-11-28 5:59 ` Z.Q. Hou
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2016-11-27 17:02 UTC (permalink / raw)
To: u-boot
Hi,
On 24 November 2016 at 02:28, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> Hi Simon,
>
> Thanks for your comments!
>
>> -----Original Message-----
>> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
>> Sent: 2016?11?24? 10:21
>> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
>> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
>> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
>> <mingkai.hu@nxp.com>
>> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>>
>> Hi,
>>
>> On 22 November 2016 at 02:25, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
>> > Hi Simon,
>> >
>> > Sorry for my delay respond due to out of the office several days, and thanks
>> a lot for your comments!
>> >
>> >> -----Original Message-----
>> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
>> >> Sent: 2016?11?18? 9:15
>> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
>> Ruchika
>> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H.
>> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
>> Mingkai
>> >> Hu <mingkai.hu@nxp.com>
>> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on
>> >> DM
>> >>
>> >> Hi,
>> >>
>> >> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
>> >> wrote:
>> >> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
>> >> >
>> >> > There are more than five kinds of Layerscape SoCs. unfortunately,
>> >> > PCIe controller of each SoC is a little bit different. In order to
>> >> > avoid too many macro definitions, the patch addes a new
>> >> > implementation of PCIe driver based on DM. PCIe dts node is used to
>> >> > describe the difference.
>> >> >
>> >> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>> >> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>> >> > ---
>> >> > V3:
>> >> > - No change
>> >> >
>> >> > drivers/pci/Kconfig | 8 +
>> >> > drivers/pci/pcie_layerscape.c | 761
>> >> > ++++++++++++++++++++++++++++++++++++++++++
>> >> > 2 files changed, 769 insertions(+)
>> >> >
>>
>> >> > +#ifdef CONFIG_FSL_LSCH3
>> >>
>> >> Can this be a run-time check?
>> >
>> > No, it is for Linux DT fixup and these functions is needed only by FSL_LSCH3
>> SoCs.
>>
>> I mean that you cannot have an #ifdef in a driver - it should be done at
>> run-time by looking at the compatible strings.
>
> This driver work for many platforms, but this fixup is only used by FSL_LSCH3 SoCs,
> if check the compatible string at run-time, the fixup will be still compiled for the platform which doesn't need it.
> Why compile it into the binary for the platform which doesn't need it?
Because that's how it works. Drivers are drivers for their hardware.
We cannot compile them differently depending on who might use them...
If this is a big problem you could split the driver into multiple
parts perhaps. But what exactly is the problem here?
>
>> >
>> >>
>> >> > +/*
>> >> > + * Return next available LUT index.
>> >> > + */
>> >> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
>> >> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
>> >> > + return pcie->next_lut_index++;
>> >> > + else
>> >> > + return -1; /* LUT is full */
>> >>
>> >> -ENOSPC?
>> >
>> > Yes, ENOSPC is more reasonable.
>> >
>> >>
>> >> > +}
>> >> > +
>> >> > +/*
>> >> > + * Program a single LUT entry
>> >> > + */
>> >> > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int
>> >> > +index, u32
>> >> devid,
>> >> > + u32 streamid) {
>> >> > + /* leave mask as all zeroes, want to match all bits */
>> >> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
>> >> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
>> >> > +PCIE_LUT_LDR(index)); }
>> >> > +
>> >> > +/* returns the next available streamid */ static u32
>> >> > +ls_pcie_next_streamid(void) {
>> >> > + static int next_stream_id = FSL_PEX_STREAM_ID_START;
>> >> > +
>> >> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
>> >> > + return 0xffffffff;
>> >>
>> >> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of values?
>> >
>> > The maximum value for PCIe.
>> >
>> >> > +
>> >> > + return next_stream_id++;
>> >> > +}
>> >> > +
>> >> > +/*
>> >> > + * An msi-map is a property to be added to the pci controller
>> >> > + * node. It is a table, where each entry consists of 4 fields
>> >> > + * e.g.:
>> >> > + *
>> >> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
>> >> > + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
>> >> > + */
>> >> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
>> >> > + u32 devid, u32 streamid) {
>> >> > + u32 *prop;
>> >> > + u32 phandle;
>> >> > + int nodeoffset;
>> >> > +
>> >> > + /* find pci controller node */
>> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
>> >> > + "fsl,ls-pcie",
>> >> > +
>> >> > + pcie->dbi_res.start);
>> >>
>> >> At this point I'm a bit lost, but if this is using driver model, you
>> >> can use
>> >> dev->of_offset
>> >
>> > This function is used to fixup Linux Kernel DT instead of u-boot DT.
>>
>> They should use the same DT.
>
> Yes, Ideally they should, but up to now actually Kernel does not use the one u-boot
> used, so we cannot make sure the offset of the nodes are the same.
> So to ensure the fixup work, get the node offset from kernel DT.
Is it not possible to change U-Boot to use the kernel DT? It might be less work.
>
>>
>> >
>> >>
>> >> > + if (nodeoffset < 0) {
>> >> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older version of
>> >> > + dts node */
>> >>
>> >> Eek! Can't you detect this at run-time?
>> >>
>> >
>> > No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe Linux
>> > driver using the compatible "fsl,ls-pcie", but for now the macro
>> FSL_PCIE_COMPAT must be defined to fixup Linux DT.
>>
>> I'm still confused by this. I don't see it defined anywhere and it is not a CONFIG.
>> Can you not detect at run-time when you need to do the fix-up?
>
> Ok, the process is find the node offset by "fsl,ls-pcie" first, if failed, find it again by FSL_PCIE_COMPAT.
> But in the current kernel DT the name of PCIe controller node is NOT the "fsl,ls-pcie" which we will
> refactor layerscape pcie kernel driver to use, so far it is the FSL_PCIE_COMPAT which is defined
> according to the current kernel DT in header file include/configs/ls*.h.
> So it is unable to be detected at run-time, but it will be removed when the kernel driver refactored.
OK, so how about making this a new CONFIG which you can turn on/off?
>
>>
>> >
>> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
>> >> > +
>> >> FSL_PCIE_COMPAT,
>> >> > +
>> >> pcie->dbi_res.start);
>> >> > + if (nodeoffset < 0)
>> >> > + return;
>> >> > + #else
>> >> > + return;
>> >> > + #endif
>> >> > + }
>> >> > +
>> >> > + /* get phandle to MSI controller */
>> >> > + prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent",
>> >> > + 0);
>> >>
>> >> fdtdec_getint()
>> >
>> > The fdtdec_get_int() is not suit for this case, because the value of
>> "msi-parent" is an index of gic-its, so there isn't a default value.
>>
>> Try:
>>
>> val = fdtdec_get_int(blob, nodeoffset, "msi-parent", -1)
>> if (val == -1) {
>> debug(...);
>> return -EINVAL;
>> }
>>
>
> Any benefit compared with fdt_getprop? I'm confused by this function, what if the correct value equal to the given default value?
You choose an invalid default. If there isn't one then you cannot use
this function. The benefit is that it avoids the be32_to_cpu().
>
>> >
>> >>
>> >> > + if (prop == NULL) {
>> >> > + printf("\n%s: ERROR: missing msi-parent: PCIe%d\n",
>> >> > + __func__, pcie->idx);
>> >> > + return;
>> >>
>> >> Return an error error and check it.
>> >
>> > This function is used to fixup Linux DT, so this error won't block the u-boot
>> process, and I think an error message is enough.
>>
>> If it is an error it should return an error. If it is just a warning it should say so,
>> ideally using debug(). As it is, it is very confusing for the user to get this
>> message.
>
> Will replace with debug().
>
>> >
>> >> > + }
>> >> > + phandle = be32_to_cpu(*prop);
>> >>
>> >> fdt32_to_cpu()
>> >>
>> >
>> > Yes, better to use fdt32_to_cpu.
>>
>> But where do you use that value? Also. consider fdtdec_lookup_phandle().
>
> Thanks for your tip, just the value of this phandle is used, see the lines below.
OK I see.
>
>> >
>> >> > +
>> >> > + /* set one msi-map row */
>> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
>> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
>> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
>> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
>> >> > +
>> >> > +static void fdt_fixup_pcie(void *blob)
>> >>
>> >> This is a pretty horrible function. What is it for?
>> >
>> > Kernel DT fixup.
>>
>> OK, well please add some comments!
>
> Will comment it.
Regards,
Simon
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-27 17:02 ` Simon Glass
@ 2016-11-28 5:59 ` Z.Q. Hou
2016-11-29 21:40 ` Simon Glass
0 siblings, 1 reply; 31+ messages in thread
From: Z.Q. Hou @ 2016-11-28 5:59 UTC (permalink / raw)
To: u-boot
Hi Simon,
Thanks for your comments!
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: 2016?11?28? 1:02
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>
> Hi,
>
> On 24 November 2016 at 02:28, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> > Hi Simon,
> >
> > Thanks for your comments!
> >
> >> -----Original Message-----
> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> >> Sent: 2016?11?24? 10:21
> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> Ruchika
> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H.
> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> Mingkai
> >> Hu <mingkai.hu@nxp.com>
> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on
> >> DM
> >>
> >> Hi,
> >>
> >> On 22 November 2016 at 02:25, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> >> > Hi Simon,
> >> >
> >> > Sorry for my delay respond due to out of the office several days,
> >> > and thanks
> >> a lot for your comments!
> >> >
> >> >> -----Original Message-----
> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon
> >> >> Glass
> >> >> Sent: 2016?11?18? 9:15
> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> >> Ruchika
> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>;
> M.H.
> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> >> Mingkai
> >> >> Hu <mingkai.hu@nxp.com>
> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based
> >> >> on DM
> >> >>
> >> >> Hi,
> >> >>
> >> >> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> >> >> wrote:
> >> >> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
> >> >> >
> >> >> > There are more than five kinds of Layerscape SoCs.
> >> >> > unfortunately, PCIe controller of each SoC is a little bit
> >> >> > different. In order to avoid too many macro definitions, the
> >> >> > patch addes a new implementation of PCIe driver based on DM.
> >> >> > PCIe dts node is used to describe the difference.
> >> >> >
> >> >> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> >> >> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >> >> > ---
> >> >> > V3:
> >> >> > - No change
> >> >> >
> >> >> > drivers/pci/Kconfig | 8 +
> >> >> > drivers/pci/pcie_layerscape.c | 761
> >> >> > ++++++++++++++++++++++++++++++++++++++++++
> >> >> > 2 files changed, 769 insertions(+)
> >> >> >
> >>
> >> >> > +#ifdef CONFIG_FSL_LSCH3
> >> >>
> >> >> Can this be a run-time check?
> >> >
> >> > No, it is for Linux DT fixup and these functions is needed only by
> >> > FSL_LSCH3
> >> SoCs.
> >>
> >> I mean that you cannot have an #ifdef in a driver - it should be done
> >> at run-time by looking at the compatible strings.
> >
> > This driver work for many platforms, but this fixup is only used by
> > FSL_LSCH3 SoCs, if check the compatible string at run-time, the fixup will be
> still compiled for the platform which doesn't need it.
> > Why compile it into the binary for the platform which doesn't need it?
>
> Because that's how it works. Drivers are drivers for their hardware.
> We cannot compile them differently depending on who might use them...
>
> If this is a big problem you could split the driver into multiple parts perhaps. But
> what exactly is the problem here?
It isn't a big problem, actually it is just kernel DT fixup function, and it doesn't affect the u-boot pcie driver.
But the fixup is LSCH3 SoC special, and some macros are only defined in header file of LSCH3, e.g. FSL_PEX_STREAM_ID_*.
So cannot removed the #ifdef CONFIG_FSL_LSCH3.
>
> >
> >> >
> >> >>
> >> >> > +/*
> >> >> > + * Return next available LUT index.
> >> >> > + */
> >> >> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
> >> >> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> >> >> > + return pcie->next_lut_index++;
> >> >> > + else
> >> >> > + return -1; /* LUT is full */
> >> >>
> >> >> -ENOSPC?
> >> >
> >> > Yes, ENOSPC is more reasonable.
> >> >
> >> >>
> >> >> > +}
> >> >> > +
> >> >> > +/*
> >> >> > + * Program a single LUT entry
> >> >> > + */
> >> >> > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int
> >> >> > +index, u32
> >> >> devid,
> >> >> > + u32 streamid) {
> >> >> > + /* leave mask as all zeroes, want to match all bits */
> >> >> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
> >> >> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
> >> >> > +PCIE_LUT_LDR(index)); }
> >> >> > +
> >> >> > +/* returns the next available streamid */ static u32
> >> >> > +ls_pcie_next_streamid(void) {
> >> >> > + static int next_stream_id = FSL_PEX_STREAM_ID_START;
> >> >> > +
> >> >> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
> >> >> > + return 0xffffffff;
> >> >>
> >> >> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of
> values?
> >> >
> >> > The maximum value for PCIe.
> >> >
> >> >> > +
> >> >> > + return next_stream_id++; }
> >> >> > +
> >> >> > +/*
> >> >> > + * An msi-map is a property to be added to the pci controller
> >> >> > + * node. It is a table, where each entry consists of 4 fields
> >> >> > + * e.g.:
> >> >> > + *
> >> >> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
> >> >> > + * [devid] [phandle-to-msi-ctrl] [stream-id]
> [count]>;
> >> >> > + */
> >> >> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie
> *pcie,
> >> >> > + u32 devid, u32
> streamid) {
> >> >> > + u32 *prop;
> >> >> > + u32 phandle;
> >> >> > + int nodeoffset;
> >> >> > +
> >> >> > + /* find pci controller node */
> >> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
> >> >> > + "fsl,ls-pcie",
> >> >> > +
> >> >> > + pcie->dbi_res.start);
> >> >>
> >> >> At this point I'm a bit lost, but if this is using driver model,
> >> >> you can use
> >> >> dev->of_offset
> >> >
> >> > This function is used to fixup Linux Kernel DT instead of u-boot DT.
> >>
> >> They should use the same DT.
> >
> > Yes, Ideally they should, but up to now actually Kernel does not use
> > the one u-boot used, so we cannot make sure the offset of the nodes are the
> same.
> > So to ensure the fixup work, get the node offset from kernel DT.
>
> Is it not possible to change U-Boot to use the kernel DT? It might be less work.
Since this is used to fixup Kernel DT, and u-boot and Kernel use two copies of DT, until the u-boot and kernel use one copy of DT, we must fixup the one works for Kernel.
>
> >
> >>
> >> >
> >> >>
> >> >> > + if (nodeoffset < 0) {
> >> >> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older version
> >> >> > + of dts node */
> >> >>
> >> >> Eek! Can't you detect this at run-time?
> >> >>
> >> >
> >> > No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe Linux
> >> > driver using the compatible "fsl,ls-pcie", but for now the macro
> >> FSL_PCIE_COMPAT must be defined to fixup Linux DT.
> >>
> >> I'm still confused by this. I don't see it defined anywhere and it is not a
> CONFIG.
> >> Can you not detect at run-time when you need to do the fix-up?
> >
> > Ok, the process is find the node offset by "fsl,ls-pcie" first, if failed, find it
> again by FSL_PCIE_COMPAT.
> > But in the current kernel DT the name of PCIe controller node is NOT
> > the "fsl,ls-pcie" which we will refactor layerscape pcie kernel driver
> > to use, so far it is the FSL_PCIE_COMPAT which is defined according to the
> current kernel DT in header file include/configs/ls*.h.
> > So it is unable to be detected at run-time, but it will be removed when the
> kernel driver refactored.
>
> OK, so how about making this a new CONFIG which you can turn on/off?
Yes, will move it to CONFIG_ FSL_PCIE_COMPAT.
> >
> >>
> >> >
> >> >> > + nodeoffset =
> fdt_node_offset_by_compat_reg(blob,
> >> >> > +
> >> >> FSL_PCIE_COMPAT,
> >> >> > +
> >> >> pcie->dbi_res.start);
> >> >> > + if (nodeoffset < 0)
> >> >> > + return;
> >> >> > + #else
> >> >> > + return;
> >> >> > + #endif
> >> >> > + }
> >> >> > +
> >> >> > + /* get phandle to MSI controller */
> >> >> > + prop = (u32 *)fdt_getprop(blob, nodeoffset,
> >> >> > + "msi-parent", 0);
> >> >>
> >> >> fdtdec_getint()
> >> >
> >> > The fdtdec_get_int() is not suit for this case, because the value
> >> > of
> >> "msi-parent" is an index of gic-its, so there isn't a default value.
> >>
> >> Try:
> >>
> >> val = fdtdec_get_int(blob, nodeoffset, "msi-parent", -1)
> >> if (val == -1) {
> >> debug(...);
> >> return -EINVAL;
> >> }
> >>
> >
> > Any benefit compared with fdt_getprop? I'm confused by this function, what
> if the correct value equal to the given default value?
>
> You choose an invalid default. If there isn't one then you cannot use this
> function. The benefit is that it avoids the be32_to_cpu().
The value of this property is a reference of other node and don't know which is the invalid value.
Do you have any suggestion about this case?
> >
> >> >
> >> >>
> >> >> > + if (prop == NULL) {
> >> >> > + printf("\n%s: ERROR: missing msi-parent:
> PCIe%d\n",
> >> >> > + __func__, pcie->idx);
> >> >> > + return;
> >> >>
> >> >> Return an error error and check it.
> >> >
> >> > This function is used to fixup Linux DT, so this error won't block
> >> > the u-boot
> >> process, and I think an error message is enough.
> >>
> >> If it is an error it should return an error. If it is just a warning
> >> it should say so, ideally using debug(). As it is, it is very
> >> confusing for the user to get this message.
> >
> > Will replace with debug().
> >
> >> >
> >> >> > + }
> >> >> > + phandle = be32_to_cpu(*prop);
> >> >>
> >> >> fdt32_to_cpu()
> >> >>
> >> >
> >> > Yes, better to use fdt32_to_cpu.
> >>
> >> But where do you use that value? Also. consider fdtdec_lookup_phandle().
> >
> > Thanks for your tip, just the value of this phandle is used, see the lines below.
>
> OK I see.
>
> >
> >> >
> >> >> > +
> >> >> > + /* set one msi-map row */
> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
> streamid);
> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
> >> >> > +
> >> >> > +static void fdt_fixup_pcie(void *blob)
> >> >>
> >> >> This is a pretty horrible function. What is it for?
> >> >
> >> > Kernel DT fixup.
> >>
> >> OK, well please add some comments!
> >
> > Will comment it.
Regards,
Zhiqiang
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-28 5:59 ` Z.Q. Hou
@ 2016-11-29 21:40 ` Simon Glass
2016-11-30 8:14 ` Z.Q. Hou
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2016-11-29 21:40 UTC (permalink / raw)
To: u-boot
Hi,
On 27 November 2016 at 22:59, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> Hi Simon,
>
> Thanks for your comments!
>
>> -----Original Message-----
>> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
>> Sent: 2016?11?28? 1:02
>> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
>> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
>> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
>> <mingkai.hu@nxp.com>
>> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>>
>> Hi,
>>
>> On 24 November 2016 at 02:28, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
>> > Hi Simon,
>> >
>> > Thanks for your comments!
>> >
>> >> -----Original Message-----
>> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
>> >> Sent: 2016?11?24? 10:21
>> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
>> Ruchika
>> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H.
>> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
>> Mingkai
>> >> Hu <mingkai.hu@nxp.com>
>> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on
>> >> DM
>> >>
>> >> Hi,
>> >>
>> >> On 22 November 2016 at 02:25, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
>> >> > Hi Simon,
>> >> >
>> >> > Sorry for my delay respond due to out of the office several days,
>> >> > and thanks
>> >> a lot for your comments!
>> >> >
>> >> >> -----Original Message-----
>> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon
>> >> >> Glass
>> >> >> Sent: 2016?11?18? 9:15
>> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> >> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> >> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
>> >> Ruchika
>> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> >> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>;
>> M.H.
>> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
>> >> Mingkai
>> >> >> Hu <mingkai.hu@nxp.com>
>> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based
>> >> >> on DM
>> >> >>
>> >> >> Hi,
>> >> >>
>> >> >> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
>> >> >> wrote:
>> >> >> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
>> >> >> >
>> >> >> > There are more than five kinds of Layerscape SoCs.
>> >> >> > unfortunately, PCIe controller of each SoC is a little bit
>> >> >> > different. In order to avoid too many macro definitions, the
>> >> >> > patch addes a new implementation of PCIe driver based on DM.
>> >> >> > PCIe dts node is used to describe the difference.
>> >> >> >
>> >> >> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>> >> >> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>> >> >> > ---
>> >> >> > V3:
>> >> >> > - No change
>> >> >> >
>> >> >> > drivers/pci/Kconfig | 8 +
>> >> >> > drivers/pci/pcie_layerscape.c | 761
>> >> >> > ++++++++++++++++++++++++++++++++++++++++++
>> >> >> > 2 files changed, 769 insertions(+)
>> >> >> >
>> >>
>> >> >> > +#ifdef CONFIG_FSL_LSCH3
>> >> >>
>> >> >> Can this be a run-time check?
>> >> >
>> >> > No, it is for Linux DT fixup and these functions is needed only by
>> >> > FSL_LSCH3
>> >> SoCs.
>> >>
>> >> I mean that you cannot have an #ifdef in a driver - it should be done
>> >> at run-time by looking at the compatible strings.
>> >
>> > This driver work for many platforms, but this fixup is only used by
>> > FSL_LSCH3 SoCs, if check the compatible string at run-time, the fixup will be
>> still compiled for the platform which doesn't need it.
>> > Why compile it into the binary for the platform which doesn't need it?
>>
>> Because that's how it works. Drivers are drivers for their hardware.
>> We cannot compile them differently depending on who might use them...
>>
>> If this is a big problem you could split the driver into multiple parts perhaps. But
>> what exactly is the problem here?
>
> It isn't a big problem, actually it is just kernel DT fixup function, and it doesn't affect the u-boot pcie driver.
> But the fixup is LSCH3 SoC special, and some macros are only defined in header file of LSCH3, e.g. FSL_PEX_STREAM_ID_*.
> So cannot removed the #ifdef CONFIG_FSL_LSCH3.
Really there should be two separate drivers, with a shared common file
for common code.
Failing that, is it really impossible to include the extra macros regardless?
If we start putting board-specific #ifdefs in drivers, we have lost
the DM battle.
>
>>
>> >
>> >> >
>> >> >>
>> >> >> > +/*
>> >> >> > + * Return next available LUT index.
>> >> >> > + */
>> >> >> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
>> >> >> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
>> >> >> > + return pcie->next_lut_index++;
>> >> >> > + else
>> >> >> > + return -1; /* LUT is full */
>> >> >>
>> >> >> -ENOSPC?
>> >> >
>> >> > Yes, ENOSPC is more reasonable.
>> >> >
>> >> >>
>> >> >> > +}
>> >> >> > +
>> >> >> > +/*
>> >> >> > + * Program a single LUT entry
>> >> >> > + */
>> >> >> > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int
>> >> >> > +index, u32
>> >> >> devid,
>> >> >> > + u32 streamid) {
>> >> >> > + /* leave mask as all zeroes, want to match all bits */
>> >> >> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
>> >> >> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
>> >> >> > +PCIE_LUT_LDR(index)); }
>> >> >> > +
>> >> >> > +/* returns the next available streamid */ static u32
>> >> >> > +ls_pcie_next_streamid(void) {
>> >> >> > + static int next_stream_id = FSL_PEX_STREAM_ID_START;
>> >> >> > +
>> >> >> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
>> >> >> > + return 0xffffffff;
>> >> >>
>> >> >> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of
>> values?
>> >> >
>> >> > The maximum value for PCIe.
>> >> >
>> >> >> > +
>> >> >> > + return next_stream_id++; }
>> >> >> > +
>> >> >> > +/*
>> >> >> > + * An msi-map is a property to be added to the pci controller
>> >> >> > + * node. It is a table, where each entry consists of 4 fields
>> >> >> > + * e.g.:
>> >> >> > + *
>> >> >> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
>> >> >> > + * [devid] [phandle-to-msi-ctrl] [stream-id]
>> [count]>;
>> >> >> > + */
>> >> >> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie
>> *pcie,
>> >> >> > + u32 devid, u32
>> streamid) {
>> >> >> > + u32 *prop;
>> >> >> > + u32 phandle;
>> >> >> > + int nodeoffset;
>> >> >> > +
>> >> >> > + /* find pci controller node */
>> >> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
>> >> >> > + "fsl,ls-pcie",
>> >> >> > +
>> >> >> > + pcie->dbi_res.start);
>> >> >>
>> >> >> At this point I'm a bit lost, but if this is using driver model,
>> >> >> you can use
>> >> >> dev->of_offset
>> >> >
>> >> > This function is used to fixup Linux Kernel DT instead of u-boot DT.
>> >>
>> >> They should use the same DT.
>> >
>> > Yes, Ideally they should, but up to now actually Kernel does not use
>> > the one u-boot used, so we cannot make sure the offset of the nodes are the
>> same.
>> > So to ensure the fixup work, get the node offset from kernel DT.
>>
>> Is it not possible to change U-Boot to use the kernel DT? It might be less work.
>
> Since this is used to fixup Kernel DT, and u-boot and Kernel use two copies of DT, until the u-boot and kernel use one copy of DT, we must fixup the one works for Kernel.
OK. Please add a TODO(email) prominently.
>
>>
>> >
>> >>
>> >> >
>> >> >>
>> >> >> > + if (nodeoffset < 0) {
>> >> >> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older version
>> >> >> > + of dts node */
>> >> >>
>> >> >> Eek! Can't you detect this at run-time?
>> >> >>
>> >> >
>> >> > No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe Linux
>> >> > driver using the compatible "fsl,ls-pcie", but for now the macro
>> >> FSL_PCIE_COMPAT must be defined to fixup Linux DT.
>> >>
>> >> I'm still confused by this. I don't see it defined anywhere and it is not a
>> CONFIG.
>> >> Can you not detect at run-time when you need to do the fix-up?
>> >
>> > Ok, the process is find the node offset by "fsl,ls-pcie" first, if failed, find it
>> again by FSL_PCIE_COMPAT.
>> > But in the current kernel DT the name of PCIe controller node is NOT
>> > the "fsl,ls-pcie" which we will refactor layerscape pcie kernel driver
>> > to use, so far it is the FSL_PCIE_COMPAT which is defined according to the
>> current kernel DT in header file include/configs/ls*.h.
>> > So it is unable to be detected at run-time, but it will be removed when the
>> kernel driver refactored.
>>
>> OK, so how about making this a new CONFIG which you can turn on/off?
>
> Yes, will move it to CONFIG_ FSL_PCIE_COMPAT.
>
>> >
>> >>
>> >> >
>> >> >> > + nodeoffset =
>> fdt_node_offset_by_compat_reg(blob,
>> >> >> > +
>> >> >> FSL_PCIE_COMPAT,
>> >> >> > +
>> >> >> pcie->dbi_res.start);
>> >> >> > + if (nodeoffset < 0)
>> >> >> > + return;
>> >> >> > + #else
>> >> >> > + return;
>> >> >> > + #endif
>> >> >> > + }
>> >> >> > +
>> >> >> > + /* get phandle to MSI controller */
>> >> >> > + prop = (u32 *)fdt_getprop(blob, nodeoffset,
>> >> >> > + "msi-parent", 0);
>> >> >>
>> >> >> fdtdec_getint()
>> >> >
>> >> > The fdtdec_get_int() is not suit for this case, because the value
>> >> > of
>> >> "msi-parent" is an index of gic-its, so there isn't a default value.
>> >>
>> >> Try:
>> >>
>> >> val = fdtdec_get_int(blob, nodeoffset, "msi-parent", -1)
>> >> if (val == -1) {
>> >> debug(...);
>> >> return -EINVAL;
>> >> }
>> >>
>> >
>> > Any benefit compared with fdt_getprop? I'm confused by this function, what
>> if the correct value equal to the given default value?
>>
>> You choose an invalid default. If there isn't one then you cannot use this
>> function. The benefit is that it avoids the be32_to_cpu().
>
> The value of this property is a reference of other node and don't know which is the invalid value.
> Do you have any suggestion about this case?
Well, phandles cannot be < 0, so how about -1?
>
>> >
>> >> >
>> >> >>
>> >> >> > + if (prop == NULL) {
>> >> >> > + printf("\n%s: ERROR: missing msi-parent:
>> PCIe%d\n",
>> >> >> > + __func__, pcie->idx);
>> >> >> > + return;
>> >> >>
>> >> >> Return an error error and check it.
>> >> >
>> >> > This function is used to fixup Linux DT, so this error won't block
>> >> > the u-boot
>> >> process, and I think an error message is enough.
>> >>
>> >> If it is an error it should return an error. If it is just a warning
>> >> it should say so, ideally using debug(). As it is, it is very
>> >> confusing for the user to get this message.
>> >
>> > Will replace with debug().
>> >
>> >> >
>> >> >> > + }
>> >> >> > + phandle = be32_to_cpu(*prop);
>> >> >>
>> >> >> fdt32_to_cpu()
>> >> >>
>> >> >
>> >> > Yes, better to use fdt32_to_cpu.
>> >>
>> >> But where do you use that value? Also. consider fdtdec_lookup_phandle().
>> >
>> > Thanks for your tip, just the value of this phandle is used, see the lines below.
>>
>> OK I see.
>>
>> >
>> >> >
>> >> >> > +
>> >> >> > + /* set one msi-map row */
>> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
>> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
>> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
>> streamid);
>> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
>> >> >> > +
>> >> >> > +static void fdt_fixup_pcie(void *blob)
>> >> >>
>> >> >> This is a pretty horrible function. What is it for?
>> >> >
>> >> > Kernel DT fixup.
>> >>
>> >> OK, well please add some comments!
>> >
>> > Will comment it.
>
> Regards,
> Zhiqiang
Regards,
Simon
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-29 21:40 ` Simon Glass
@ 2016-11-30 8:14 ` Z.Q. Hou
2016-12-01 2:19 ` Simon Glass
0 siblings, 1 reply; 31+ messages in thread
From: Z.Q. Hou @ 2016-11-30 8:14 UTC (permalink / raw)
To: u-boot
Hi Simon,
Thanks for your comments!
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: 2016?11?30? 5:41
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>
> Hi,
>
> On 27 November 2016 at 22:59, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> > Hi Simon,
> >
> > Thanks for your comments!
> >
> >> -----Original Message-----
> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> >> Sent: 2016?11?28? 1:02
> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> Ruchika
> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H.
> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> Mingkai
> >> Hu <mingkai.hu@nxp.com>
> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on
> >> DM
> >>
> >> Hi,
> >>
> >> On 24 November 2016 at 02:28, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> >> > Hi Simon,
> >> >
> >> > Thanks for your comments!
> >> >
> >> >> -----Original Message-----
> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon
> >> >> Glass
> >> >> Sent: 2016?11?24? 10:21
> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> >> Ruchika
> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>;
> M.H.
> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> >> Mingkai
> >> >> Hu <mingkai.hu@nxp.com>
> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based
> >> >> on DM
> >> >>
> >> >> Hi,
> >> >>
> >> >> On 22 November 2016 at 02:25, Z.Q. Hou <zhiqiang.hou@nxp.com>
> wrote:
> >> >> > Hi Simon,
> >> >> >
> >> >> > Sorry for my delay respond due to out of the office several
> >> >> > days, and thanks
> >> >> a lot for your comments!
> >> >> >
> >> >> >> -----Original Message-----
> >> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon
> >> >> >> Glass
> >> >> >> Sent: 2016?11?18? 9:15
> >> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> >> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> >> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> >> >> Ruchika
> >> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> >> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>;
> >> M.H.
> >> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> >> >> Mingkai
> >> >> >> Hu <mingkai.hu@nxp.com>
> >> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver
> >> >> >> based on DM
> >> >> >>
> >> >> >> Hi,
> >> >> >>
> >> >> >> On 16 November 2016 at 02:48, Zhiqiang Hou
> >> >> >> <Zhiqiang.Hou@nxp.com>
> >> >> >> wrote:
> >> >> >> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
> >> >> >> >
> >> >> >> > There are more than five kinds of Layerscape SoCs.
> >> >> >> > unfortunately, PCIe controller of each SoC is a little bit
> >> >> >> > different. In order to avoid too many macro definitions, the
> >> >> >> > patch addes a new implementation of PCIe driver based on DM.
> >> >> >> > PCIe dts node is used to describe the difference.
> >> >> >> >
> >> >> >> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> >> >> >> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >> >> >> > ---
> >> >> >> > V3:
> >> >> >> > - No change
> >> >> >> >
> >> >> >> > drivers/pci/Kconfig | 8 +
> >> >> >> > drivers/pci/pcie_layerscape.c | 761
> >> >> >> > ++++++++++++++++++++++++++++++++++++++++++
> >> >> >> > 2 files changed, 769 insertions(+)
> >> >> >> >
> >> >>
> >> >> >> > +#ifdef CONFIG_FSL_LSCH3
> >> >> >>
> >> >> >> Can this be a run-time check?
> >> >> >
> >> >> > No, it is for Linux DT fixup and these functions is needed only
> >> >> > by
> >> >> > FSL_LSCH3
> >> >> SoCs.
> >> >>
> >> >> I mean that you cannot have an #ifdef in a driver - it should be
> >> >> done at run-time by looking at the compatible strings.
> >> >
> >> > This driver work for many platforms, but this fixup is only used by
> >> > FSL_LSCH3 SoCs, if check the compatible string at run-time, the
> >> > fixup will be
> >> still compiled for the platform which doesn't need it.
> >> > Why compile it into the binary for the platform which doesn't need it?
> >>
> >> Because that's how it works. Drivers are drivers for their hardware.
> >> We cannot compile them differently depending on who might use them...
> >>
> >> If this is a big problem you could split the driver into multiple
> >> parts perhaps. But what exactly is the problem here?
> >
> > It isn't a big problem, actually it is just kernel DT fixup function, and it doesn't
> affect the u-boot pcie driver.
> > But the fixup is LSCH3 SoC special, and some macros are only defined in
> header file of LSCH3, e.g. FSL_PEX_STREAM_ID_*.
> > So cannot removed the #ifdef CONFIG_FSL_LSCH3.
>
> Really there should be two separate drivers, with a shared common file for
> common code.
>
> Failing that, is it really impossible to include the extra macros regardless?
>
> If we start putting board-specific #ifdefs in drivers, we have lost the DM battle.
Is it necessary to separate two drivers just for a fixup function?
The fixup is functionally independent with pcie driver, and it works for kernel pcie driver, if removed the fixup, u-boot pcie driver is still unabridged and works well but kernel pcie driver won't.
The #ifdefs isn't introduced by Minghuan's refactor based on DM, actually this refactor removed many #ifdefs. So we do not lost the DM battle.
> >
> >>
> >> >
> >> >> >
> >> >> >>
> >> >> >> > +/*
> >> >> >> > + * Return next available LUT index.
> >> >> >> > + */
> >> >> >> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
> >> >> >> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> >> >> >> > + return pcie->next_lut_index++;
> >> >> >> > + else
> >> >> >> > + return -1; /* LUT is full */
> >> >> >>
> >> >> >> -ENOSPC?
> >> >> >
> >> >> > Yes, ENOSPC is more reasonable.
> >> >> >
> >> >> >>
> >> >> >> > +}
> >> >> >> > +
> >> >> >> > +/*
> >> >> >> > + * Program a single LUT entry */ static void
> >> >> >> > +ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32
> >> >> >> devid,
> >> >> >> > + u32 streamid) {
> >> >> >> > + /* leave mask as all zeroes, want to match all bits */
> >> >> >> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
> >> >> >> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
> >> >> >> > +PCIE_LUT_LDR(index)); }
> >> >> >> > +
> >> >> >> > +/* returns the next available streamid */ static u32
> >> >> >> > +ls_pcie_next_streamid(void) {
> >> >> >> > + static int next_stream_id = FSL_PEX_STREAM_ID_START;
> >> >> >> > +
> >> >> >> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
> >> >> >> > + return 0xffffffff;
> >> >> >>
> >> >> >> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of
> >> values?
> >> >> >
> >> >> > The maximum value for PCIe.
> >> >> >
> >> >> >> > +
> >> >> >> > + return next_stream_id++; }
> >> >> >> > +
> >> >> >> > +/*
> >> >> >> > + * An msi-map is a property to be added to the pci
> >> >> >> > +controller
> >> >> >> > + * node. It is a table, where each entry consists of 4
> >> >> >> > +fields
> >> >> >> > + * e.g.:
> >> >> >> > + *
> >> >> >> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id]
> [count]
> >> >> >> > + * [devid] [phandle-to-msi-ctrl] [stream-id]
> >> [count]>;
> >> >> >> > + */
> >> >> >> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct
> >> >> >> > +ls_pcie
> >> *pcie,
> >> >> >> > + u32 devid, u32
> >> streamid) {
> >> >> >> > + u32 *prop;
> >> >> >> > + u32 phandle;
> >> >> >> > + int nodeoffset;
> >> >> >> > +
> >> >> >> > + /* find pci controller node */
> >> >> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
> >> >> >> > + "fsl,ls-pcie",
> >> >> >> > +
> >> >> >> > + pcie->dbi_res.start);
> >> >> >>
> >> >> >> At this point I'm a bit lost, but if this is using driver
> >> >> >> model, you can use
> >> >> >> dev->of_offset
> >> >> >
> >> >> > This function is used to fixup Linux Kernel DT instead of u-boot DT.
> >> >>
> >> >> They should use the same DT.
> >> >
> >> > Yes, Ideally they should, but up to now actually Kernel does not
> >> > use the one u-boot used, so we cannot make sure the offset of the
> >> > nodes are the
> >> same.
> >> > So to ensure the fixup work, get the node offset from kernel DT.
> >>
> >> Is it not possible to change U-Boot to use the kernel DT? It might be less
> work.
> >
> > Since this is used to fixup Kernel DT, and u-boot and Kernel use two copies of
> DT, until the u-boot and kernel use one copy of DT, we must fixup the one
> works for Kernel.
>
> OK. Please add a TODO(email) prominently.
I'm afraid you're confused.
U-boot and kernel use two copies of DT whether they are the same or not, they locate in different addresses, and let's name the u-boot used A and kernel used B.
This function is used to fixup B, so the node-offset must be get from B instead of A. Because we cannot ensure A and B always are the same.
> >
> >>
> >> >
> >> >>
> >> >> >
> >> >> >>
> >> >> >> > + if (nodeoffset < 0) {
> >> >> >> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older
> >> >> >> > + version of dts node */
> >> >> >>
> >> >> >> Eek! Can't you detect this at run-time?
> >> >> >>
> >> >> >
> >> >> > No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe
> >> >> > Linux driver using the compatible "fsl,ls-pcie", but for now the
> >> >> > macro
> >> >> FSL_PCIE_COMPAT must be defined to fixup Linux DT.
> >> >>
> >> >> I'm still confused by this. I don't see it defined anywhere and it
> >> >> is not a
> >> CONFIG.
> >> >> Can you not detect at run-time when you need to do the fix-up?
> >> >
> >> > Ok, the process is find the node offset by "fsl,ls-pcie" first, if
> >> > failed, find it
> >> again by FSL_PCIE_COMPAT.
> >> > But in the current kernel DT the name of PCIe controller node is
> >> > NOT the "fsl,ls-pcie" which we will refactor layerscape pcie kernel
> >> > driver to use, so far it is the FSL_PCIE_COMPAT which is defined
> >> > according to the
> >> current kernel DT in header file include/configs/ls*.h.
> >> > So it is unable to be detected at run-time, but it will be removed
> >> > when the
> >> kernel driver refactored.
> >>
> >> OK, so how about making this a new CONFIG which you can turn on/off?
> >
> > Yes, will move it to CONFIG_ FSL_PCIE_COMPAT.
> >
> >> >
> >> >>
> >> >> >
> >> >> >> > + nodeoffset =
> >> fdt_node_offset_by_compat_reg(blob,
> >> >> >> > +
> >> >> >> FSL_PCIE_COMPAT,
> >> >> >> > +
> >> >> >> pcie->dbi_res.start);
> >> >> >> > + if (nodeoffset < 0)
> >> >> >> > + return;
> >> >> >> > + #else
> >> >> >> > + return;
> >> >> >> > + #endif
> >> >> >> > + }
> >> >> >> > +
> >> >> >> > + /* get phandle to MSI controller */
> >> >> >> > + prop = (u32 *)fdt_getprop(blob, nodeoffset,
> >> >> >> > + "msi-parent", 0);
> >> >> >>
> >> >> >> fdtdec_getint()
> >> >> >
> >> >> > The fdtdec_get_int() is not suit for this case, because the
> >> >> > value of
> >> >> "msi-parent" is an index of gic-its, so there isn't a default value.
> >> >>
> >> >> Try:
> >> >>
> >> >> val = fdtdec_get_int(blob, nodeoffset, "msi-parent", -1)
> >> >> if (val == -1) {
> >> >> debug(...);
> >> >> return -EINVAL;
> >> >> }
> >> >>
> >> >
> >> > Any benefit compared with fdt_getprop? I'm confused by this
> >> > function, what
> >> if the correct value equal to the given default value?
> >>
> >> You choose an invalid default. If there isn't one then you cannot use
> >> this function. The benefit is that it avoids the be32_to_cpu().
> >
> > The value of this property is a reference of other node and don't know which
> is the invalid value.
> > Do you have any suggestion about this case?
>
> Well, phandles cannot be < 0, so how about -1?
No, it can be < 0.
Made an experiment that added "test = <0xffffffff>;" to DT then the fdtdec_get_int() return -1.
So, avoid to use it when didn't know an invalid value.
> >
> >> >
> >> >> >
> >> >> >>
> >> >> >> > + if (prop == NULL) {
> >> >> >> > + printf("\n%s: ERROR: missing msi-parent:
> >> PCIe%d\n",
> >> >> >> > + __func__, pcie->idx);
> >> >> >> > + return;
> >> >> >>
> >> >> >> Return an error error and check it.
> >> >> >
> >> >> > This function is used to fixup Linux DT, so this error won't
> >> >> > block the u-boot
> >> >> process, and I think an error message is enough.
> >> >>
> >> >> If it is an error it should return an error. If it is just a
> >> >> warning it should say so, ideally using debug(). As it is, it is
> >> >> very confusing for the user to get this message.
> >> >
> >> > Will replace with debug().
> >> >
> >> >> >
> >> >> >> > + }
> >> >> >> > + phandle = be32_to_cpu(*prop);
> >> >> >>
> >> >> >> fdt32_to_cpu()
> >> >> >>
> >> >> >
> >> >> > Yes, better to use fdt32_to_cpu.
> >> >>
> >> >> But where do you use that value? Also. consider
> fdtdec_lookup_phandle().
> >> >
> >> > Thanks for your tip, just the value of this phandle is used, see the lines
> below.
> >>
> >> OK I see.
> >>
> >> >
> >> >> >
> >> >> >> > +
> >> >> >> > + /* set one msi-map row */
> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
> phandle);
> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
> >> streamid);
> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
> >> >> >> > +
> >> >> >> > +static void fdt_fixup_pcie(void *blob)
> >> >> >>
> >> >> >> This is a pretty horrible function. What is it for?
> >> >> >
> >> >> > Kernel DT fixup.
> >> >>
> >> >> OK, well please add some comments!
> >> >
> >> > Will comment it.
> >
Regards,
Zhiqiang
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-11-30 8:14 ` Z.Q. Hou
@ 2016-12-01 2:19 ` Simon Glass
2016-12-01 10:48 ` Z.Q. Hou
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2016-12-01 2:19 UTC (permalink / raw)
To: u-boot
Hi,
On 30 November 2016 at 01:14, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> Hi Simon,
>
> Thanks for your comments!
>
>> -----Original Message-----
>> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
>> Sent: 2016?11?30? 5:41
>> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
>> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
>> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
>> <mingkai.hu@nxp.com>
>> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>>
>> Hi,
>>
>> On 27 November 2016 at 22:59, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
>> > Hi Simon,
>> >
>> > Thanks for your comments!
>> >
>> >> -----Original Message-----
>> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
>> >> Sent: 2016?11?28? 1:02
>> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
>> Ruchika
>> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H.
>> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
>> Mingkai
>> >> Hu <mingkai.hu@nxp.com>
>> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on
>> >> DM
>> >>
>> >> Hi,
>> >>
>> >> On 24 November 2016 at 02:28, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
>> >> > Hi Simon,
>> >> >
>> >> > Thanks for your comments!
>> >> >
>> >> >> -----Original Message-----
>> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon
>> >> >> Glass
>> >> >> Sent: 2016?11?24? 10:21
>> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> >> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> >> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
>> >> Ruchika
>> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> >> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>;
>> M.H.
>> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
>> >> Mingkai
>> >> >> Hu <mingkai.hu@nxp.com>
>> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based
>> >> >> on DM
>> >> >>
>> >> >> Hi,
>> >> >>
>> >> >> On 22 November 2016 at 02:25, Z.Q. Hou <zhiqiang.hou@nxp.com>
>> wrote:
>> >> >> > Hi Simon,
>> >> >> >
>> >> >> > Sorry for my delay respond due to out of the office several
>> >> >> > days, and thanks
>> >> >> a lot for your comments!
>> >> >> >
>> >> >> >> -----Original Message-----
>> >> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon
>> >> >> >> Glass
>> >> >> >> Sent: 2016?11?18? 9:15
>> >> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
>> >> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
>> >> >> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
>> >> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
>> >> >> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
>> >> >> Ruchika
>> >> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
>> >> >> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>;
>> >> M.H.
>> >> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
>> >> >> Mingkai
>> >> >> >> Hu <mingkai.hu@nxp.com>
>> >> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver
>> >> >> >> based on DM
>> >> >> >>
>> >> >> >> Hi,
>> >> >> >>
>> >> >> >> On 16 November 2016 at 02:48, Zhiqiang Hou
>> >> >> >> <Zhiqiang.Hou@nxp.com>
>> >> >> >> wrote:
>> >> >> >> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
>> >> >> >> >
>> >> >> >> > There are more than five kinds of Layerscape SoCs.
>> >> >> >> > unfortunately, PCIe controller of each SoC is a little bit
>> >> >> >> > different. In order to avoid too many macro definitions, the
>> >> >> >> > patch addes a new implementation of PCIe driver based on DM.
>> >> >> >> > PCIe dts node is used to describe the difference.
>> >> >> >> >
>> >> >> >> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>> >> >> >> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>> >> >> >> > ---
>> >> >> >> > V3:
>> >> >> >> > - No change
>> >> >> >> >
>> >> >> >> > drivers/pci/Kconfig | 8 +
>> >> >> >> > drivers/pci/pcie_layerscape.c | 761
>> >> >> >> > ++++++++++++++++++++++++++++++++++++++++++
>> >> >> >> > 2 files changed, 769 insertions(+)
>> >> >> >> >
>> >> >>
>> >> >> >> > +#ifdef CONFIG_FSL_LSCH3
>> >> >> >>
>> >> >> >> Can this be a run-time check?
>> >> >> >
>> >> >> > No, it is for Linux DT fixup and these functions is needed only
>> >> >> > by
>> >> >> > FSL_LSCH3
>> >> >> SoCs.
>> >> >>
>> >> >> I mean that you cannot have an #ifdef in a driver - it should be
>> >> >> done at run-time by looking at the compatible strings.
>> >> >
>> >> > This driver work for many platforms, but this fixup is only used by
>> >> > FSL_LSCH3 SoCs, if check the compatible string at run-time, the
>> >> > fixup will be
>> >> still compiled for the platform which doesn't need it.
>> >> > Why compile it into the binary for the platform which doesn't need it?
>> >>
>> >> Because that's how it works. Drivers are drivers for their hardware.
>> >> We cannot compile them differently depending on who might use them...
>> >>
>> >> If this is a big problem you could split the driver into multiple
>> >> parts perhaps. But what exactly is the problem here?
>> >
>> > It isn't a big problem, actually it is just kernel DT fixup function, and it doesn't
>> affect the u-boot pcie driver.
>> > But the fixup is LSCH3 SoC special, and some macros are only defined in
>> header file of LSCH3, e.g. FSL_PEX_STREAM_ID_*.
>> > So cannot removed the #ifdef CONFIG_FSL_LSCH3.
>>
>> Really there should be two separate drivers, with a shared common file for
>> common code.
>>
>> Failing that, is it really impossible to include the extra macros regardless?
>>
>> If we start putting board-specific #ifdefs in drivers, we have lost the DM battle.
>
> Is it necessary to separate two drivers just for a fixup function?
> The fixup is functionally independent with pcie driver, and it works for kernel pcie driver, if removed the fixup, u-boot pcie driver is still unabridged and works well but kernel pcie driver won't.
> The #ifdefs isn't introduced by Minghuan's refactor based on DM, actually this refactor removed many #ifdefs. So we do not lost the DM battle.
OK so the #ifdef is only used for the fix-up function? In that case
can we move this into a separate file like pcie_layerscape_fixup.c?
Then we don't have #ifdef CONFIGs in the driver. Would that work?
>
>> >
>> >>
>> >> >
>> >> >> >
>> >> >> >>
>> >> >> >> > +/*
>> >> >> >> > + * Return next available LUT index.
>> >> >> >> > + */
>> >> >> >> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
>> >> >> >> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
>> >> >> >> > + return pcie->next_lut_index++;
>> >> >> >> > + else
>> >> >> >> > + return -1; /* LUT is full */
>> >> >> >>
>> >> >> >> -ENOSPC?
>> >> >> >
>> >> >> > Yes, ENOSPC is more reasonable.
>> >> >> >
>> >> >> >>
>> >> >> >> > +}
>> >> >> >> > +
>> >> >> >> > +/*
>> >> >> >> > + * Program a single LUT entry */ static void
>> >> >> >> > +ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32
>> >> >> >> devid,
>> >> >> >> > + u32 streamid) {
>> >> >> >> > + /* leave mask as all zeroes, want to match all bits */
>> >> >> >> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
>> >> >> >> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
>> >> >> >> > +PCIE_LUT_LDR(index)); }
>> >> >> >> > +
>> >> >> >> > +/* returns the next available streamid */ static u32
>> >> >> >> > +ls_pcie_next_streamid(void) {
>> >> >> >> > + static int next_stream_id = FSL_PEX_STREAM_ID_START;
>> >> >> >> > +
>> >> >> >> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
>> >> >> >> > + return 0xffffffff;
>> >> >> >>
>> >> >> >> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of
>> >> values?
>> >> >> >
>> >> >> > The maximum value for PCIe.
>> >> >> >
>> >> >> >> > +
>> >> >> >> > + return next_stream_id++; }
>> >> >> >> > +
>> >> >> >> > +/*
>> >> >> >> > + * An msi-map is a property to be added to the pci
>> >> >> >> > +controller
>> >> >> >> > + * node. It is a table, where each entry consists of 4
>> >> >> >> > +fields
>> >> >> >> > + * e.g.:
>> >> >> >> > + *
>> >> >> >> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id]
>> [count]
>> >> >> >> > + * [devid] [phandle-to-msi-ctrl] [stream-id]
>> >> [count]>;
>> >> >> >> > + */
>> >> >> >> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct
>> >> >> >> > +ls_pcie
>> >> *pcie,
>> >> >> >> > + u32 devid, u32
>> >> streamid) {
>> >> >> >> > + u32 *prop;
>> >> >> >> > + u32 phandle;
>> >> >> >> > + int nodeoffset;
>> >> >> >> > +
>> >> >> >> > + /* find pci controller node */
>> >> >> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
>> >> >> >> > + "fsl,ls-pcie",
>> >> >> >> > +
>> >> >> >> > + pcie->dbi_res.start);
>> >> >> >>
>> >> >> >> At this point I'm a bit lost, but if this is using driver
>> >> >> >> model, you can use
>> >> >> >> dev->of_offset
>> >> >> >
>> >> >> > This function is used to fixup Linux Kernel DT instead of u-boot DT.
>> >> >>
>> >> >> They should use the same DT.
>> >> >
>> >> > Yes, Ideally they should, but up to now actually Kernel does not
>> >> > use the one u-boot used, so we cannot make sure the offset of the
>> >> > nodes are the
>> >> same.
>> >> > So to ensure the fixup work, get the node offset from kernel DT.
>> >>
>> >> Is it not possible to change U-Boot to use the kernel DT? It might be less
>> work.
>> >
>> > Since this is used to fixup Kernel DT, and u-boot and Kernel use two copies of
>> DT, until the u-boot and kernel use one copy of DT, we must fixup the one
>> works for Kernel.
>>
>> OK. Please add a TODO(email) prominently.
>
> I'm afraid you're confused.
> U-boot and kernel use two copies of DT whether they are the same or not, they locate in different addresses, and let's name the u-boot used A and kernel used B.
> This function is used to fixup B, so the node-offset must be get from B instead of A. Because we cannot ensure A and B always are the same.
OK I think I am slowly understanding this. So you have a kernel DT
fix-up function that you are putting in this driver. The only calls
into drivers should be via driver model. As above I suggest putting
this in its own file.
>
>> >
>> >>
>> >> >
>> >> >>
>> >> >> >
>> >> >> >>
>> >> >> >> > + if (nodeoffset < 0) {
>> >> >> >> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older
>> >> >> >> > + version of dts node */
>> >> >> >>
>> >> >> >> Eek! Can't you detect this at run-time?
>> >> >> >>
>> >> >> >
>> >> >> > No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe
>> >> >> > Linux driver using the compatible "fsl,ls-pcie", but for now the
>> >> >> > macro
>> >> >> FSL_PCIE_COMPAT must be defined to fixup Linux DT.
>> >> >>
>> >> >> I'm still confused by this. I don't see it defined anywhere and it
>> >> >> is not a
>> >> CONFIG.
>> >> >> Can you not detect at run-time when you need to do the fix-up?
>> >> >
>> >> > Ok, the process is find the node offset by "fsl,ls-pcie" first, if
>> >> > failed, find it
>> >> again by FSL_PCIE_COMPAT.
>> >> > But in the current kernel DT the name of PCIe controller node is
>> >> > NOT the "fsl,ls-pcie" which we will refactor layerscape pcie kernel
>> >> > driver to use, so far it is the FSL_PCIE_COMPAT which is defined
>> >> > according to the
>> >> current kernel DT in header file include/configs/ls*.h.
>> >> > So it is unable to be detected at run-time, but it will be removed
>> >> > when the
>> >> kernel driver refactored.
>> >>
>> >> OK, so how about making this a new CONFIG which you can turn on/off?
>> >
>> > Yes, will move it to CONFIG_ FSL_PCIE_COMPAT.
>> >
>> >> >
>> >> >>
>> >> >> >
>> >> >> >> > + nodeoffset =
>> >> fdt_node_offset_by_compat_reg(blob,
>> >> >> >> > +
>> >> >> >> FSL_PCIE_COMPAT,
>> >> >> >> > +
>> >> >> >> pcie->dbi_res.start);
>> >> >> >> > + if (nodeoffset < 0)
>> >> >> >> > + return;
>> >> >> >> > + #else
>> >> >> >> > + return;
>> >> >> >> > + #endif
>> >> >> >> > + }
>> >> >> >> > +
>> >> >> >> > + /* get phandle to MSI controller */
>> >> >> >> > + prop = (u32 *)fdt_getprop(blob, nodeoffset,
>> >> >> >> > + "msi-parent", 0);
>> >> >> >>
>> >> >> >> fdtdec_getint()
>> >> >> >
>> >> >> > The fdtdec_get_int() is not suit for this case, because the
>> >> >> > value of
>> >> >> "msi-parent" is an index of gic-its, so there isn't a default value.
>> >> >>
>> >> >> Try:
>> >> >>
>> >> >> val = fdtdec_get_int(blob, nodeoffset, "msi-parent", -1)
>> >> >> if (val == -1) {
>> >> >> debug(...);
>> >> >> return -EINVAL;
>> >> >> }
>> >> >>
>> >> >
>> >> > Any benefit compared with fdt_getprop? I'm confused by this
>> >> > function, what
>> >> if the correct value equal to the given default value?
>> >>
>> >> You choose an invalid default. If there isn't one then you cannot use
>> >> this function. The benefit is that it avoids the be32_to_cpu().
>> >
>> > The value of this property is a reference of other node and don't know which
>> is the invalid value.
>> > Do you have any suggestion about this case?
>>
>> Well, phandles cannot be < 0, so how about -1?
>
> No, it can be < 0.
> Made an experiment that added "test = <0xffffffff>;" to DT then the fdtdec_get_int() return -1.
> So, avoid to use it when didn't know an invalid value.
Yes but a phandle will never be -1. My point is that if the phandle is
missing, the function will return -1, so you can detect that case. All
valid phandles are >= 0. Anyway if you like the code as is, it's fine
with me. It just seems unnecessarily complicated.
>
>> >
>> >> >
>> >> >> >
>> >> >> >>
>> >> >> >> > + if (prop == NULL) {
>> >> >> >> > + printf("\n%s: ERROR: missing msi-parent:
>> >> PCIe%d\n",
>> >> >> >> > + __func__, pcie->idx);
>> >> >> >> > + return;
>> >> >> >>
>> >> >> >> Return an error error and check it.
>> >> >> >
>> >> >> > This function is used to fixup Linux DT, so this error won't
>> >> >> > block the u-boot
>> >> >> process, and I think an error message is enough.
>> >> >>
>> >> >> If it is an error it should return an error. If it is just a
>> >> >> warning it should say so, ideally using debug(). As it is, it is
>> >> >> very confusing for the user to get this message.
>> >> >
>> >> > Will replace with debug().
>> >> >
>> >> >> >
>> >> >> >> > + }
>> >> >> >> > + phandle = be32_to_cpu(*prop);
>> >> >> >>
>> >> >> >> fdt32_to_cpu()
>> >> >> >>
>> >> >> >
>> >> >> > Yes, better to use fdt32_to_cpu.
>> >> >>
>> >> >> But where do you use that value? Also. consider
>> fdtdec_lookup_phandle().
>> >> >
>> >> > Thanks for your tip, just the value of this phandle is used, see the lines
>> below.
>> >>
>> >> OK I see.
>> >>
>> >> >
>> >> >> >
>> >> >> >> > +
>> >> >> >> > + /* set one msi-map row */
>> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
>> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
>> phandle);
>> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
>> >> streamid);
>> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); }
>> >> >> >> > +
>> >> >> >> > +static void fdt_fixup_pcie(void *blob)
>> >> >> >>
>> >> >> >> This is a pretty horrible function. What is it for?
>> >> >> >
>> >> >> > Kernel DT fixup.
>> >> >>
>> >> >> OK, well please add some comments!
>> >> >
>> >> > Will comment it.
>> >
>
> Regards,
> Zhiqiang
^ permalink raw reply [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
2016-12-01 2:19 ` Simon Glass
@ 2016-12-01 10:48 ` Z.Q. Hou
0 siblings, 0 replies; 31+ messages in thread
From: Z.Q. Hou @ 2016-12-01 10:48 UTC (permalink / raw)
To: u-boot
Hi Simon,
Thanks for your comments!
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: 2016?12?1? 10:20
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>
> Hi,
>
> On 30 November 2016 at 01:14, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> > Hi Simon,
> >
> > Thanks for your comments!
> >
> >> -----Original Message-----
> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> >> Sent: 2016?11?30? 5:41
> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> Ruchika
> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H.
> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> Mingkai
> >> Hu <mingkai.hu@nxp.com>
> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on
> >> DM
> >>
> >> Hi,
> >>
> >> On 27 November 2016 at 22:59, Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> >> > Hi Simon,
> >> >
> >> > Thanks for your comments!
> >> >
> >> >> -----Original Message-----
> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon
> >> >> Glass
> >> >> Sent: 2016?11?28? 1:02
> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> >> Ruchika
> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>;
> M.H.
> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> >> Mingkai
> >> >> Hu <mingkai.hu@nxp.com>
> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based
> >> >> on DM
> >> >>
> >> >> Hi,
> >> >>
> >> >> On 24 November 2016 at 02:28, Z.Q. Hou <zhiqiang.hou@nxp.com>
> wrote:
> >> >> > Hi Simon,
> >> >> >
> >> >> > Thanks for your comments!
> >> >> >
> >> >> >> -----Original Message-----
> >> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon
> >> >> >> Glass
> >> >> >> Sent: 2016?11?24? 10:21
> >> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> >> >> >> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> >> >> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>;
> >> >> Ruchika
> >> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> >> >> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>;
> >> M.H.
> >> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>;
> >> >> Mingkai
> >> >> >> Hu <mingkai.hu@nxp.com>
> >> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver
> >> >> >> based on DM
> >> >> >>
> >> >> >> Hi,
> >> >> >>
> >> >> >> On 22 November 2016 at 02:25, Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> wrote:
> >> >> >> > Hi Simon,
> >> >> >> >
> >> >> >> > Sorry for my delay respond due to out of the office several
> >> >> >> > days, and thanks
> >> >> >> a lot for your comments!
> >> >> >> >
> >> >> >> >> -----Original Message-----
> >> >> >> >> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of
> >> >> >> >> Simon Glass
> >> >> >> >> Sent: 2016?11?18? 9:15
> >> >> >> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> >> >> >> >> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert
> >> >> >> >> ARIBAUD <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> >> >> >> >> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> >> >> >> >> <alison.wang@freescale.com>; Sumit Garg
> >> >> >> >> <sumit.garg@nxp.com>;
> >> >> >> Ruchika
> >> >> >> >> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> >> >> >> >> <saksham.jain@nxp.freescale.com>; york sun
> >> >> >> >> <york.sun@nxp.com>;
> >> >> M.H.
> >> >> >> >> Lian <minghuan.lian@nxp.com>; Bin Meng
> <bmeng.cn@gmail.com>;
> >> >> >> Mingkai
> >> >> >> >> Hu <mingkai.hu@nxp.com>
> >> >> >> >> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver
> >> >> >> >> based on DM
> >> >> >> >>
> >> >> >> >> Hi,
> >> >> >> >>
> >> >> >> >> On 16 November 2016 at 02:48, Zhiqiang Hou
> >> >> >> >> <Zhiqiang.Hou@nxp.com>
> >> >> >> >> wrote:
> >> >> >> >> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
> >> >> >> >> >
> >> >> >> >> > There are more than five kinds of Layerscape SoCs.
> >> >> >> >> > unfortunately, PCIe controller of each SoC is a little bit
> >> >> >> >> > different. In order to avoid too many macro definitions,
> >> >> >> >> > the patch addes a new implementation of PCIe driver based on
> DM.
> >> >> >> >> > PCIe dts node is used to describe the difference.
> >> >> >> >> >
> >> >> >> >> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> >> >> >> >> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >> >> >> >> > ---
> >> >> >> >> > V3:
> >> >> >> >> > - No change
> >> >> >> >> >
> >> >> >> >> > drivers/pci/Kconfig | 8 +
> >> >> >> >> > drivers/pci/pcie_layerscape.c | 761
> >> >> >> >> > ++++++++++++++++++++++++++++++++++++++++++
> >> >> >> >> > 2 files changed, 769 insertions(+)
> >> >> >> >> >
> >> >> >>
> >> >> >> >> > +#ifdef CONFIG_FSL_LSCH3
> >> >> >> >>
> >> >> >> >> Can this be a run-time check?
> >> >> >> >
> >> >> >> > No, it is for Linux DT fixup and these functions is needed
> >> >> >> > only by
> >> >> >> > FSL_LSCH3
> >> >> >> SoCs.
> >> >> >>
> >> >> >> I mean that you cannot have an #ifdef in a driver - it should
> >> >> >> be done at run-time by looking at the compatible strings.
> >> >> >
> >> >> > This driver work for many platforms, but this fixup is only used
> >> >> > by
> >> >> > FSL_LSCH3 SoCs, if check the compatible string at run-time, the
> >> >> > fixup will be
> >> >> still compiled for the platform which doesn't need it.
> >> >> > Why compile it into the binary for the platform which doesn't need it?
> >> >>
> >> >> Because that's how it works. Drivers are drivers for their hardware.
> >> >> We cannot compile them differently depending on who might use
> them...
> >> >>
> >> >> If this is a big problem you could split the driver into multiple
> >> >> parts perhaps. But what exactly is the problem here?
> >> >
> >> > It isn't a big problem, actually it is just kernel DT fixup
> >> > function, and it doesn't
> >> affect the u-boot pcie driver.
> >> > But the fixup is LSCH3 SoC special, and some macros are only
> >> > defined in
> >> header file of LSCH3, e.g. FSL_PEX_STREAM_ID_*.
> >> > So cannot removed the #ifdef CONFIG_FSL_LSCH3.
> >>
> >> Really there should be two separate drivers, with a shared common
> >> file for common code.
> >>
> >> Failing that, is it really impossible to include the extra macros regardless?
> >>
> >> If we start putting board-specific #ifdefs in drivers, we have lost the DM
> battle.
> >
> > Is it necessary to separate two drivers just for a fixup function?
> > The fixup is functionally independent with pcie driver, and it works for kernel
> pcie driver, if removed the fixup, u-boot pcie driver is still unabridged and
> works well but kernel pcie driver won't.
> > The #ifdefs isn't introduced by Minghuan's refactor based on DM, actually
> this refactor removed many #ifdefs. So we do not lost the DM battle.
>
> OK so the #ifdef is only used for the fix-up function? In that case can we move
> this into a separate file like pcie_layerscape_fixup.c?
> Then we don't have #ifdef CONFIGs in the driver. Would that work?
Ok, will add a new file for fixup.
>
> >
> >> >
> >> >>
> >> >> >
> >> >> >> >
> >> >> >> >>
> >> >> >> >> > +/*
> >> >> >> >> > + * Return next available LUT index.
> >> >> >> >> > + */
> >> >> >> >> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
> >> >> >> >> > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> >> >> >> >> > + return pcie->next_lut_index++;
> >> >> >> >> > + else
> >> >> >> >> > + return -1; /* LUT is full */
> >> >> >> >>
> >> >> >> >> -ENOSPC?
> >> >> >> >
> >> >> >> > Yes, ENOSPC is more reasonable.
> >> >> >> >
> >> >> >> >>
> >> >> >> >> > +}
> >> >> >> >> > +
> >> >> >> >> > +/*
> >> >> >> >> > + * Program a single LUT entry */ static void
> >> >> >> >> > +ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index,
> >> >> >> >> > +u32
> >> >> >> >> devid,
> >> >> >> >> > + u32 streamid) {
> >> >> >> >> > + /* leave mask as all zeroes, want to match all bits */
> >> >> >> >> > + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
> >> >> >> >> > + lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
> >> >> >> >> > +PCIE_LUT_LDR(index)); }
> >> >> >> >> > +
> >> >> >> >> > +/* returns the next available streamid */ static u32
> >> >> >> >> > +ls_pcie_next_streamid(void) {
> >> >> >> >> > + static int next_stream_id =
> >> >> >> >> > +FSL_PEX_STREAM_ID_START;
> >> >> >> >> > +
> >> >> >> >> > + if (next_stream_id > FSL_PEX_STREAM_ID_END)
> >> >> >> >> > + return 0xffffffff;
> >> >> >> >>
> >> >> >> >> Is FSL_PEX_STREAM_ID_END the maximum value, or the number
> of
> >> >> values?
> >> >> >> >
> >> >> >> > The maximum value for PCIe.
> >> >> >> >
> >> >> >> >> > +
> >> >> >> >> > + return next_stream_id++; }
> >> >> >> >> > +
> >> >> >> >> > +/*
> >> >> >> >> > + * An msi-map is a property to be added to the pci
> >> >> >> >> > +controller
> >> >> >> >> > + * node. It is a table, where each entry consists of 4
> >> >> >> >> > +fields
> >> >> >> >> > + * e.g.:
> >> >> >> >> > + *
> >> >> >> >> > + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id]
> >> [count]
> >> >> >> >> > + * [devid] [phandle-to-msi-ctrl] [stream-id]
> >> >> [count]>;
> >> >> >> >> > + */
> >> >> >> >> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct
> >> >> >> >> > +ls_pcie
> >> >> *pcie,
> >> >> >> >> > + u32 devid, u32
> >> >> streamid) {
> >> >> >> >> > + u32 *prop;
> >> >> >> >> > + u32 phandle;
> >> >> >> >> > + int nodeoffset;
> >> >> >> >> > +
> >> >> >> >> > + /* find pci controller node */
> >> >> >> >> > + nodeoffset = fdt_node_offset_by_compat_reg(blob,
> >> >> >> >> > + "fsl,ls-pcie",
> >> >> >> >> > +
> >> >> >> >> > + pcie->dbi_res.start);
> >> >> >> >>
> >> >> >> >> At this point I'm a bit lost, but if this is using driver
> >> >> >> >> model, you can use
> >> >> >> >> dev->of_offset
> >> >> >> >
> >> >> >> > This function is used to fixup Linux Kernel DT instead of u-boot DT.
> >> >> >>
> >> >> >> They should use the same DT.
> >> >> >
> >> >> > Yes, Ideally they should, but up to now actually Kernel does not
> >> >> > use the one u-boot used, so we cannot make sure the offset of
> >> >> > the nodes are the
> >> >> same.
> >> >> > So to ensure the fixup work, get the node offset from kernel DT.
> >> >>
> >> >> Is it not possible to change U-Boot to use the kernel DT? It might
> >> >> be less
> >> work.
> >> >
> >> > Since this is used to fixup Kernel DT, and u-boot and Kernel use
> >> > two copies of
> >> DT, until the u-boot and kernel use one copy of DT, we must fixup the
> >> one works for Kernel.
> >>
> >> OK. Please add a TODO(email) prominently.
> >
> > I'm afraid you're confused.
> > U-boot and kernel use two copies of DT whether they are the same or not,
> they locate in different addresses, and let's name the u-boot used A and kernel
> used B.
> > This function is used to fixup B, so the node-offset must be get from B
> instead of A. Because we cannot ensure A and B always are the same.
>
> OK I think I am slowly understanding this. So you have a kernel DT fix-up
> function that you are putting in this driver. The only calls into drivers should be
> via driver model. As above I suggest putting this in its own file.
>
> >
> >> >
> >> >>
> >> >> >
> >> >> >>
> >> >> >> >
> >> >> >> >>
> >> >> >> >> > + if (nodeoffset < 0) {
> >> >> >> >> > + #ifdef FSL_PCIE_COMPAT /* Compatible with older
> >> >> >> >> > + version of dts node */
> >> >> >> >>
> >> >> >> >> Eek! Can't you detect this at run-time?
> >> >> >> >>
> >> >> >> >
> >> >> >> > No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe
> >> >> >> > Linux driver using the compatible "fsl,ls-pcie", but for now
> >> >> >> > the macro
> >> >> >> FSL_PCIE_COMPAT must be defined to fixup Linux DT.
> >> >> >>
> >> >> >> I'm still confused by this. I don't see it defined anywhere and
> >> >> >> it is not a
> >> >> CONFIG.
> >> >> >> Can you not detect at run-time when you need to do the fix-up?
> >> >> >
> >> >> > Ok, the process is find the node offset by "fsl,ls-pcie" first,
> >> >> > if failed, find it
> >> >> again by FSL_PCIE_COMPAT.
> >> >> > But in the current kernel DT the name of PCIe controller node is
> >> >> > NOT the "fsl,ls-pcie" which we will refactor layerscape pcie
> >> >> > kernel driver to use, so far it is the FSL_PCIE_COMPAT which is
> >> >> > defined according to the
> >> >> current kernel DT in header file include/configs/ls*.h.
> >> >> > So it is unable to be detected at run-time, but it will be
> >> >> > removed when the
> >> >> kernel driver refactored.
> >> >>
> >> >> OK, so how about making this a new CONFIG which you can turn on/off?
> >> >
> >> > Yes, will move it to CONFIG_ FSL_PCIE_COMPAT.
> >> >
> >> >> >
> >> >> >>
> >> >> >> >
> >> >> >> >> > + nodeoffset =
> >> >> fdt_node_offset_by_compat_reg(blob,
> >> >> >> >> > +
> >> >> >> >> FSL_PCIE_COMPAT,
> >> >> >> >> > +
> >> >> >> >> pcie->dbi_res.start);
> >> >> >> >> > + if (nodeoffset < 0)
> >> >> >> >> > + return;
> >> >> >> >> > + #else
> >> >> >> >> > + return;
> >> >> >> >> > + #endif
> >> >> >> >> > + }
> >> >> >> >> > +
> >> >> >> >> > + /* get phandle to MSI controller */
> >> >> >> >> > + prop = (u32 *)fdt_getprop(blob, nodeoffset,
> >> >> >> >> > + "msi-parent", 0);
> >> >> >> >>
> >> >> >> >> fdtdec_getint()
> >> >> >> >
> >> >> >> > The fdtdec_get_int() is not suit for this case, because the
> >> >> >> > value of
> >> >> >> "msi-parent" is an index of gic-its, so there isn't a default value.
> >> >> >>
> >> >> >> Try:
> >> >> >>
> >> >> >> val = fdtdec_get_int(blob, nodeoffset, "msi-parent", -1)
> >> >> >> if (val == -1) {
> >> >> >> debug(...);
> >> >> >> return -EINVAL;
> >> >> >> }
> >> >> >>
> >> >> >
> >> >> > Any benefit compared with fdt_getprop? I'm confused by this
> >> >> > function, what
> >> >> if the correct value equal to the given default value?
> >> >>
> >> >> You choose an invalid default. If there isn't one then you cannot
> >> >> use this function. The benefit is that it avoids the be32_to_cpu().
> >> >
> >> > The value of this property is a reference of other node and don't
> >> > know which
> >> is the invalid value.
> >> > Do you have any suggestion about this case?
> >>
> >> Well, phandles cannot be < 0, so how about -1?
> >
> > No, it can be < 0.
> > Made an experiment that added "test = <0xffffffff>;" to DT then the
> fdtdec_get_int() return -1.
> > So, avoid to use it when didn't know an invalid value.
>
> Yes but a phandle will never be -1. My point is that if the phandle is missing, the
> function will return -1, so you can detect that case. All valid phandles are >= 0.
> Anyway if you like the code as is, it's fine with me. It just seems unnecessarily
> complicated.
Ok, thanks for your tips.
>
> >
> >> >
> >> >> >
> >> >> >> >
> >> >> >> >>
> >> >> >> >> > + if (prop == NULL) {
> >> >> >> >> > + printf("\n%s: ERROR: missing msi-parent:
> >> >> PCIe%d\n",
> >> >> >> >> > + __func__, pcie->idx);
> >> >> >> >> > + return;
> >> >> >> >>
> >> >> >> >> Return an error error and check it.
> >> >> >> >
> >> >> >> > This function is used to fixup Linux DT, so this error won't
> >> >> >> > block the u-boot
> >> >> >> process, and I think an error message is enough.
> >> >> >>
> >> >> >> If it is an error it should return an error. If it is just a
> >> >> >> warning it should say so, ideally using debug(). As it is, it
> >> >> >> is very confusing for the user to get this message.
> >> >> >
> >> >> > Will replace with debug().
> >> >> >
> >> >> >> >
> >> >> >> >> > + }
> >> >> >> >> > + phandle = be32_to_cpu(*prop);
> >> >> >> >>
> >> >> >> >> fdt32_to_cpu()
> >> >> >> >>
> >> >> >> >
> >> >> >> > Yes, better to use fdt32_to_cpu.
> >> >> >>
> >> >> >> But where do you use that value? Also. consider
> >> fdtdec_lookup_phandle().
> >> >> >
> >> >> > Thanks for your tip, just the value of this phandle is used, see
> >> >> > the lines
> >> below.
> >> >>
> >> >> OK I see.
> >> >>
> >> >> >
> >> >> >> >
> >> >> >> >> > +
> >> >> >> >> > + /* set one msi-map row */
> >> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
> devid);
> >> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
> >> phandle);
> >> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
> >> >> streamid);
> >> >> >> >> > + fdt_appendprop_u32(blob, nodeoffset, "msi-map",
> >> >> >> >> > + 1); }
> >> >> >> >> > +
> >> >> >> >> > +static void fdt_fixup_pcie(void *blob)
> >> >> >> >>
> >> >> >> >> This is a pretty horrible function. What is it for?
> >> >> >> >
> >> >> >> > Kernel DT fixup.
> >> >> >>
> >> >> >> OK, well please add some comments!
> >> >> >
> >> >> > Will comment it.
> >> >
> >
Regards,
Zhiqiang
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCHv3 10/15] arm: ls1021a: Enable PCIe in defconfigs
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (7 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 11/15] arm: ls1012a: Enable PCIe and E1000 " Zhiqiang Hou
` (4 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
The patch enables PCIe in ls1021a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
configs/ls1021aqds_ddr4_nor_defconfig | 5 ++++-
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 5 ++++-
configs/ls1021aqds_nand_defconfig | 5 ++++-
configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 5 ++++-
configs/ls1021aqds_nor_defconfig | 5 ++++-
configs/ls1021aqds_nor_lpuart_defconfig | 5 ++++-
configs/ls1021aqds_qspi_defconfig | 5 ++++-
configs/ls1021aqds_sdcard_ifc_defconfig | 5 ++++-
configs/ls1021aqds_sdcard_qspi_defconfig | 5 ++++-
configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 5 ++++-
configs/ls1021atwr_nor_defconfig | 5 ++++-
configs/ls1021atwr_nor_lpuart_defconfig | 5 ++++-
configs/ls1021atwr_qspi_defconfig | 5 ++++-
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 5 ++++-
configs/ls1021atwr_sdcard_ifc_defconfig | 5 ++++-
configs/ls1021atwr_sdcard_qspi_defconfig | 5 ++++-
include/configs/ls1021aqds.h | 16 ----------------
include/configs/ls1021atwr.h | 16 ----------------
18 files changed, 64 insertions(+), 48 deletions(-)
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 95930f3..64ca746 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
@@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 27ef79d..4f1b0d1 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -30,7 +30,6 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
@@ -39,3 +38,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 63f455c..cd0c12d 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -41,7 +41,6 @@ CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -49,3 +48,7 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index d9f3503..38b727f 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -31,7 +31,6 @@ CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -41,3 +40,7 @@ CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 12205ea..a4534f3 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
@@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 4d910cd..6cecc04 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -30,7 +30,6 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
@@ -39,3 +38,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 79eb9fe..8a7f145 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -35,7 +35,6 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -45,3 +44,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 402cce7..b5027d0 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -39,10 +39,13 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 6f3588e..374352f 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -43,7 +43,6 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -53,3 +52,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 5899dee..0c8c4aa 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -30,7 +30,6 @@ CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -40,3 +39,7 @@ CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 2b351aa..98d7a5d 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -28,7 +28,6 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
@@ -36,3 +35,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index daede61..9443598 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
@@ -37,3 +36,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 05793e9..ec35138 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -35,7 +35,6 @@ CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -45,3 +44,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 29f0c8e..099c125 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -41,7 +41,6 @@ CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -51,3 +50,7 @@ CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index fd5c6e5..7fa3345 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -38,7 +38,6 @@ CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -46,3 +45,7 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 3f6fb17..19fd1e2 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -43,7 +43,6 @@ CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -53,3 +52,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 53f0368..e26e751 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -503,24 +503,8 @@ unsigned long get_board_ddr_clk(void);
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 4a579b1..32e18ef 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -376,24 +376,8 @@
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 11/15] arm: ls1012a: Enable PCIe and E1000 in defconfigs
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (8 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 10/15] arm: ls1021a: Enable PCIe in defconfigs Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 12/15] armv8: ls1043a: " Zhiqiang Hou
` (3 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
The patch enables PCIe and E1000 in ls1012a defconfigs and
removes unused PCIe related macro defines
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
configs/ls1012afrdm_qspi_defconfig | 5 +++++
configs/ls1012aqds_qspi_defconfig | 5 ++++-
configs/ls1012ardb_qspi_defconfig | 5 ++++-
include/configs/ls1012aqds.h | 16 ----------------
include/configs/ls1012ardb.h | 16 ----------------
5 files changed, 13 insertions(+), 34 deletions(-)
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1f3d487..0c862b6 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -28,9 +28,14 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
+CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index c0514ae..0e54d5a 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -30,7 +30,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -38,3 +37,7 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 13c9f21..9f5c82b 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -30,7 +30,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -38,3 +37,7 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 0cc1791..0e4f6e3 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -155,24 +155,8 @@
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
-
#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 15410dd..d5573ba 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -68,24 +68,8 @@
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
-
#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 12/15] armv8: ls1043a: Enable PCIe and E1000 in defconfigs
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (9 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 11/15] arm: ls1012a: Enable PCIe and E1000 " Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 13/15] armv8: ls1046a: " Zhiqiang Hou
` (2 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
The patch enables PCIe and E1000 in ls1043a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
configs/ls1043aqds_defconfig | 7 ++++++-
configs/ls1043aqds_lpuart_defconfig | 7 ++++++-
configs/ls1043aqds_nand_defconfig | 7 ++++++-
configs/ls1043aqds_nor_ddr3_defconfig | 7 ++++++-
configs/ls1043aqds_qspi_defconfig | 7 ++++++-
configs/ls1043aqds_sdcard_ifc_defconfig | 7 ++++++-
configs/ls1043aqds_sdcard_qspi_defconfig | 7 ++++++-
configs/ls1043ardb_SECURE_BOOT_defconfig | 7 ++++++-
configs/ls1043ardb_defconfig | 7 ++++++-
configs/ls1043ardb_nand_defconfig | 7 ++++++-
configs/ls1043ardb_sdcard_defconfig | 7 ++++++-
include/configs/ls1043a_common.h | 17 -----------------
12 files changed, 66 insertions(+), 28 deletions(-)
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 7ca27d7..b085a23 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -24,7 +24,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -32,3 +31,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index f6efe46..40d8224 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -25,7 +25,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_SPI=y
@@ -34,3 +33,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index dbdb416..f7da0eb 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -44,3 +43,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 1f33c88..88b3bb8 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -24,7 +24,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -32,3 +31,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 38abeaf..bc2f2c0 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -27,7 +27,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -35,3 +34,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 24220ed..0878337 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -44,3 +43,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index fdcbf8a..2819f2b 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -37,7 +37,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -45,3 +44,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 6ee0ad0..2c69ea8 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -21,7 +21,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -31,3 +30,9 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 79a4eb2..2627c14 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -20,7 +20,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -28,3 +27,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index b21f47e..5da5009 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -40,3 +39,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 12ac648..618746d 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
@@ -40,3 +39,9 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 64682b1..84f7748 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -120,27 +120,10 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
-
#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
-#define CONFIG_E1000
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 13/15] armv8: ls1046a: Enable PCIe and E1000 in defconfigs
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (10 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 12/15] armv8: ls1043a: " Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 14/15] armv8: ls2080a: Enable PCIe " Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 15/15] pci: layerscape: remove unnecessary legacy code Zhiqiang Hou
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
The patch enables PCIe and E1000 in ls1046a related defconfigs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
configs/ls1046aqds_defconfig | 6 ++++++
configs/ls1046aqds_nand_defconfig | 6 ++++++
configs/ls1046aqds_qspi_defconfig | 6 ++++++
configs/ls1046aqds_sdcard_ifc_defconfig | 6 ++++++
configs/ls1046aqds_sdcard_qspi_defconfig | 6 ++++++
configs/ls1046ardb_emmc_defconfig | 6 ++++++
configs/ls1046ardb_qspi_defconfig | 6 ++++++
configs/ls1046ardb_sdcard_defconfig | 6 ++++++
8 files changed, 48 insertions(+)
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 2cc1a0b..e80cc4d 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -26,3 +26,9 @@ CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index 01140b9..57c6e61 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -28,3 +28,9 @@ CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index c8a68fa..b1ef63b 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -29,3 +29,9 @@ CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index e6eeadd..52a9435 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -28,3 +28,9 @@ CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 8a14862..b241d47 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -30,3 +30,9 @@ CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index ba28047..1d974c6 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -25,3 +25,9 @@ CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 8508c09..583f190 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -24,3 +24,9 @@ CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 01e6397..e355c3a 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -25,3 +25,9 @@ CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 14/15] armv8: ls2080a: Enable PCIe in defconfigs
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (11 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 13/15] armv8: ls1046a: " Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-16 9:48 ` [U-Boot] [PATCHv3 15/15] pci: layerscape: remove unnecessary legacy code Zhiqiang Hou
13 siblings, 0 replies; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 --------
configs/ls2080aqds_SECURE_BOOT_defconfig | 5 ++++-
configs/ls2080aqds_defconfig | 5 ++++-
configs/ls2080aqds_nand_defconfig | 5 ++++-
configs/ls2080aqds_qspi_defconfig | 5 ++++-
configs/ls2080ardb_SECURE_BOOT_defconfig | 5 ++++-
configs/ls2080ardb_defconfig | 5 ++++-
configs/ls2080ardb_nand_defconfig | 5 ++++-
include/configs/ls2080a_common.h | 22 ----------------------
include/configs/ls2080aqds.h | 1 -
include/configs/ls2080ardb.h | 1 -
11 files changed, 28 insertions(+), 39 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7acba27..bd07808 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -104,14 +104,6 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
-/* LUT registers */
-#define PCIE_LUT_BASE 0x80000
-#define PCIE_LUT_LCTRL0 0x7F8
-#define PCIE_LUT_DBG 0x7FC
-#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
-#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
-#define PCIE_LUT_ENABLE (1 << 31)
-#define PCIE_LUT_ENTRY_COUNT 32
/* Device Configuration */
#define DCFG_BASE 0x01e00000
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index e5ad80d..3147cb2 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -27,7 +27,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -39,3 +38,7 @@ CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index e8fa1bd..5361503 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -27,7 +27,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -37,3 +36,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 2161815..db8b8ef 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -36,7 +36,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
@@ -46,3 +45,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 7c84eba..cbde0e9 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -28,7 +28,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
@@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index c2e613e..b7bde56 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -27,7 +27,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -39,3 +38,7 @@ CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 1a5d83a..3c09b23 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -27,7 +27,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -37,3 +36,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index e40152e..551d7ed 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -33,7 +33,6 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
@@ -41,3 +40,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2cae966..805457d 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -171,29 +171,7 @@ unsigned long long get_qixis_addr(void);
#endif
/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-#ifdef CONFIG_LS2080A
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
-#endif
-
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
/* Command line configuration */
#define CONFIG_CMD_ENV
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 838568f..e96994e 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -347,7 +347,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b9cb6d3..f207a86 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -290,7 +290,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 15/15] pci: layerscape: remove unnecessary legacy code
2016-11-16 9:48 [U-Boot] [PATCHv3 01/15] configs: ls1021a: enable DT and DM support Zhiqiang Hou
` (12 preceding siblings ...)
2016-11-16 9:48 ` [U-Boot] [PATCHv3 14/15] armv8: ls2080a: Enable PCIe " Zhiqiang Hou
@ 2016-11-16 9:48 ` Zhiqiang Hou
2016-11-18 1:14 ` Simon Glass
13 siblings, 1 reply; 31+ messages in thread
From: Zhiqiang Hou @ 2016-11-16 9:48 UTC (permalink / raw)
To: u-boot
From: Minghuan Lian <Minghuan.Lian@nxp.com>
All Layerscape SoCs have supported new PCIe driver based on DM.
The lagecy PCIe driver code is unused and can be removed.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
drivers/pci/pcie_layerscape.c | 733 ------------------------------------------
1 file changed, 733 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index f107d1c..31a485e 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -95,737 +95,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
-#ifndef CONFIG_DM_PCI
-
-struct ls_pcie {
- int idx;
- void __iomem *dbi;
- void __iomem *va_cfg0;
- void __iomem *va_cfg1;
- int next_lut_index;
- struct pci_controller hose;
-};
-
-struct ls_pcie_info {
- unsigned long regs;
- int pci_num;
- u64 phys_base;
- u64 cfg0_phys;
- u64 cfg0_size;
- u64 cfg1_phys;
- u64 cfg1_size;
- u64 mem_bus;
- u64 mem_phys;
- u64 mem_size;
- u64 io_bus;
- u64 io_phys;
- u64 io_size;
-};
-
-#define SET_LS_PCIE_INFO(x, num) \
-{ \
- x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
- x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
- CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
- x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
- CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
- x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
- x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
- CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
- x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
- x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
- CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
- x.pci_num = num; \
-}
-
-#ifdef CONFIG_LS102XA
-#include <asm/arch/immap_ls102xa.h>
-
-/* PEX1/2 Misc Ports Status Register */
-#define LTSSM_STATE_SHIFT 20
-
-static int ls_pcie_link_state(struct ls_pcie *pcie)
-{
- u32 state;
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
- state = in_be32(&scfg->pexmscportsr[pcie->idx]);
- state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
- if (state < LTSSM_PCIE_L0) {
- debug("....PCIe link error. LTSSM=0x%02x.\n", state);
- return 0;
- }
-
- return 1;
-}
-#else
-static int ls_pcie_link_state(struct ls_pcie *pcie)
-{
- u32 state;
-
- state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
- LTSSM_STATE_MASK;
- if (state < LTSSM_PCIE_L0) {
- debug("....PCIe link error. LTSSM=0x%02x.\n", state);
- return 0;
- }
-
- return 1;
-}
-#endif
-
-static int ls_pcie_link_up(struct ls_pcie *pcie)
-{
- int state;
- u32 cap;
-
- state = ls_pcie_link_state(pcie);
- if (state)
- return state;
-
- /* Try to download speed to gen1 */
- cap = readl(pcie->dbi + PCIE_LINK_CAP);
- writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
- /*
- * Notice: the following delay has critical impact on link training
- * if too short (<30ms) the link doesn't get up.
- */
- mdelay(100);
- state = ls_pcie_link_state(pcie);
- if (state)
- return state;
-
- writel(cap, pcie->dbi + PCIE_LINK_CAP);
-
- return 0;
-}
-
-static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
- writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
- pcie->dbi + PCIE_ATU_VIEWPORT);
- writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
- writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
- pcie->dbi + PCIE_ATU_VIEWPORT);
- writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size)
-{
- writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
- writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
- writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
- writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
- writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
- writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
- writel(type, pcie->dbi + PCIE_ATU_CR1);
- writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
-}
-
-/* Use bar match mode and MEM type as default */
-static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
- int bar, u64 phys)
-{
- writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
- writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
- writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
- writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
- writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
- PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
-}
-
-static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
-{
-#ifdef DEBUG
- int i;
-#endif
-
- /* ATU 0 : OUTBOUND : CFG0 */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_CFG0,
- info->cfg0_phys,
- 0,
- info->cfg0_size);
- /* ATU 1 : OUTBOUND : CFG1 */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_CFG1,
- info->cfg1_phys,
- 0,
- info->cfg1_size);
- /* ATU 2 : OUTBOUND : MEM */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
- PCIE_ATU_TYPE_MEM,
- info->mem_phys,
- info->mem_bus,
- info->mem_size);
- /* ATU 3 : OUTBOUND : IO */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
- PCIE_ATU_TYPE_IO,
- info->io_phys,
- info->io_bus,
- info->io_size);
-
-#ifdef DEBUG
- for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
- writel(PCIE_ATU_REGION_OUTBOUND | i,
- pcie->dbi + PCIE_ATU_VIEWPORT);
- debug("iATU%d:\n", i);
- debug("\tLOWER PHYS 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
- debug("\tUPPER PHYS 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
- debug("\tLOWER BUS 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
- debug("\tUPPER BUS 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
- debug("\tLIMIT 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_LIMIT));
- debug("\tCR1 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_CR1));
- debug("\tCR2 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_CR2));
- }
-#endif
-}
-
-int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
-{
- /* Do not skip controller */
- return 0;
-}
-
-static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
-{
- if (PCI_DEV(d) > 0)
- return -EINVAL;
-
- /* Controller does not support multi-function in RC mode */
- if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
- return -EINVAL;
-
- return 0;
-}
-
-static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
- int where, u32 *val)
-{
- struct ls_pcie *pcie = hose->priv_data;
- u32 busdev, *addr;
-
- if (ls_pcie_addr_valid(hose, d)) {
- *val = 0xffffffff;
- return 0;
- }
-
- if (PCI_BUS(d) == hose->first_busno) {
- addr = pcie->dbi + (where & ~0x3);
- } else {
- busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
- PCIE_ATU_DEV(PCI_DEV(d)) |
- PCIE_ATU_FUNC(PCI_FUNC(d));
-
- if (PCI_BUS(d) == hose->first_busno + 1) {
- ls_pcie_cfg0_set_busdev(pcie, busdev);
- addr = pcie->va_cfg0 + (where & ~0x3);
- } else {
- ls_pcie_cfg1_set_busdev(pcie, busdev);
- addr = pcie->va_cfg1 + (where & ~0x3);
- }
- }
-
- *val = readl(addr);
-
- return 0;
-}
-
-static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
- int where, u32 val)
-{
- struct ls_pcie *pcie = hose->priv_data;
- u32 busdev, *addr;
-
- if (ls_pcie_addr_valid(hose, d))
- return -EINVAL;
-
- if (PCI_BUS(d) == hose->first_busno) {
- addr = pcie->dbi + (where & ~0x3);
- } else {
- busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
- PCIE_ATU_DEV(PCI_DEV(d)) |
- PCIE_ATU_FUNC(PCI_FUNC(d));
-
- if (PCI_BUS(d) == hose->first_busno + 1) {
- ls_pcie_cfg0_set_busdev(pcie, busdev);
- addr = pcie->va_cfg0 + (where & ~0x3);
- } else {
- ls_pcie_cfg1_set_busdev(pcie, busdev);
- addr = pcie->va_cfg1 + (where & ~0x3);
- }
- }
-
- writel(val, addr);
-
- return 0;
-}
-
-static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
- struct ls_pcie_info *info)
-{
- struct pci_controller *hose = &pcie->hose;
- pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
-
- ls_pcie_setup_atu(pcie, info);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
-
- /* program correct class for RC */
- writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
- pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
- PCI_CLASS_BRIDGE_PCI);
-#ifndef CONFIG_LS102XA
- writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
-#endif
-}
-
-static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie,
- struct ls_pcie_info *info)
-{
- u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
-
- /* ATU 0 : INBOUND : map BAR0 */
- ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys);
- /* ATU 1 : INBOUND : map BAR1 */
- phys += PCIE_BAR1_SIZE;
- ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys);
- /* ATU 2 : INBOUND : map BAR2 */
- phys += PCIE_BAR2_SIZE;
- ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys);
- /* ATU 3 : INBOUND : map BAR4 */
- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
- ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys);
-
- /* ATU 0 : OUTBOUND : map 4G MEM */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_MEM,
- info->phys_base,
- 0,
- 4 * 1024 * 1024 * 1024ULL);
-}
-
-/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
-static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
-{
- if (size < 4 * 1024)
- return;
-
- switch (bar) {
- case 0:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
- break;
- case 1:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
- break;
- case 2:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
- writel(0, bar_base + PCI_BASE_ADDRESS_3);
- break;
- case 4:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
- writel(0, bar_base + PCI_BASE_ADDRESS_5);
- break;
- default:
- break;
- }
-}
-
-static void ls_pcie_ep_setup_bars(void *bar_base)
-{
- /* BAR0 - 32bit - 4K configuration */
- ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
- /* BAR1 - 32bit - 8K MSIX*/
- ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
- /* BAR2 - 64bit - 4K MEM desciptor */
- ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
- /* BAR4 - 64bit - 1M MEM*/
- ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
-}
-
-static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
-{
- struct pci_controller *hose = &pcie->hose;
- pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
- int sriov;
-
- sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV);
- if (sriov) {
- int pf, vf;
-
- for (pf = 0; pf < PCIE_PF_NUM; pf++) {
- for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
-#ifndef CONFIG_LS102XA
- writel(PCIE_LCTRL0_VAL(pf, vf),
- pcie->dbi + PCIE_LUT_BASE +
- PCIE_LUT_LCTRL0);
-#endif
- ls_pcie_ep_setup_bars(pcie->dbi);
- ls_pcie_ep_setup_atu(pcie, info);
- }
- }
-
- /* Disable CFG2 */
-#ifndef CONFIG_LS102XA
- writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
-#endif
- } else {
- ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
- ls_pcie_ep_setup_atu(pcie, info);
- }
-}
-
-#ifdef CONFIG_FSL_LSCH3
-/*
- * Return next available LUT index.
- */
-static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
-{
- if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
- return pcie->next_lut_index++;
- else
- return -1; /* LUT is full */
-}
-
-/*
- * Program a single LUT entry
- */
-static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
- u32 streamid)
-{
- void __iomem *lut;
-
- lut = pcie->dbi + PCIE_LUT_BASE;
-
- /* leave mask as all zeroes, want to match all bits */
- writel((devid << 16), lut + PCIE_LUT_UDR(index));
- writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
-}
-
-/* returns the next available streamid */
-static u32 ls_pcie_next_streamid(void)
-{
- static int next_stream_id = FSL_PEX_STREAM_ID_START;
-
- if (next_stream_id > FSL_PEX_STREAM_ID_END)
- return 0xffffffff;
-
- return next_stream_id++;
-}
-
-/*
- * An msi-map is a property to be added to the pci controller
- * node. It is a table, where each entry consists of 4 fields
- * e.g.:
- *
- * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
- * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
- */
-static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
- u32 devid, u32 streamid)
-{
- char pcie_path[19];
- u32 *prop;
- u32 phandle;
- int nodeoffset;
-
- /* find pci controller node */
- snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
- (u64)pcie->dbi);
- nodeoffset = fdt_path_offset(blob, pcie_path);
- if (nodeoffset < 0) {
- printf("\n%s: ERROR: unable to update PCIe node: %s\n",
- __func__, pcie_path);
- return;
- }
-
- /* get phandle to MSI controller */
- prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
- if (prop == NULL) {
- printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
- pcie_path);
- return;
- }
- phandle = be32_to_cpu(*prop);
-
- /* set one msi-map row */
- fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
- fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
- fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
- fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
-}
-
-static void fdt_fixup_pcie(void *blob)
-{
- unsigned int found_multi = 0;
- unsigned char header_type;
- int index;
- u32 streamid;
- pci_dev_t dev, bdf;
- int bus;
- unsigned short id;
- struct pci_controller *hose;
- struct ls_pcie *pcie;
- int i;
-
- for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
- pcie = hose->priv_data;
- for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
-
- for (dev = PCI_BDF(bus, 0, 0);
- dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
- PCI_MAX_PCI_FUNCTIONS - 1);
- dev += PCI_BDF(0, 0, 1)) {
-
- if (PCI_FUNC(dev) && !found_multi)
- continue;
-
- pci_read_config_word(dev, PCI_VENDOR_ID, &id);
-
- pci_read_config_byte(dev, PCI_HEADER_TYPE,
- &header_type);
-
- if ((id == 0xFFFF) || (id == 0x0000))
- continue;
-
- if (!PCI_FUNC(dev))
- found_multi = header_type & 0x80;
-
- streamid = ls_pcie_next_streamid();
- if (streamid == 0xffffffff) {
- printf("ERROR: no stream ids free\n");
- continue;
- }
-
- index = ls_pcie_next_lut_index(pcie);
- if (index < 0) {
- printf("ERROR: no LUT indexes free\n");
- continue;
- }
-
- /* the DT fixup must be relative to the hose first_busno */
- bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
-
- /* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
- streamid);
-
- /* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
- streamid);
- }
- }
- }
-}
-#endif
-
-int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
-{
- struct ls_pcie *pcie;
- struct pci_controller *hose;
- int num = dev - PCIE1;
- pci_dev_t pdev = PCI_BDF(busno, 0, 0);
- int i, linkup, ep_mode;
- u8 header_type;
- u16 temp16;
-
- if (!is_serdes_configured(dev)) {
- printf("PCIe%d: disabled\n", num + 1);
- return busno;
- }
-
- pcie = malloc(sizeof(*pcie));
- if (!pcie)
- return busno;
- memset(pcie, 0, sizeof(*pcie));
-
- hose = &pcie->hose;
- hose->priv_data = pcie;
- hose->first_busno = busno;
- pcie->idx = num;
- pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
- pcie->va_cfg0 = map_physmem(info->cfg0_phys,
- info->cfg0_size,
- MAP_NOCACHE);
- pcie->va_cfg1 = map_physmem(info->cfg1_phys,
- info->cfg1_size,
- MAP_NOCACHE);
- pcie->next_lut_index = 0;
-
- /* outbound memory */
- pci_set_region(&hose->regions[0],
- (pci_size_t)info->mem_bus,
- (phys_size_t)info->mem_phys,
- (pci_size_t)info->mem_size,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(&hose->regions[1],
- (pci_size_t)info->io_bus,
- (phys_size_t)info->io_phys,
- (pci_size_t)info->io_size,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(&hose->regions[2],
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 3;
-
- for (i = 0; i < hose->region_count; i++)
- debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
- i,
- (u64)hose->regions[i].phys_start,
- (u64)hose->regions[i].bus_start,
- (u64)hose->regions[i].size,
- hose->regions[i].flags);
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- ls_pcie_read_config,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- ls_pcie_write_config);
-
- pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
- ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
- printf("PCIe%u: %s ", info->pci_num,
- ep_mode ? "Endpoint" : "Root Complex");
-
- if (ep_mode)
- ls_pcie_setup_ep(pcie, info);
- else
- ls_pcie_setup_ctrl(pcie, info);
-
- linkup = ls_pcie_link_up(pcie);
-
- if (!linkup) {
- /* Let the user know there's no PCIe link */
- printf("no link, regs @ 0x%lx\n", info->regs);
- hose->last_busno = hose->first_busno;
- return busno;
- }
-
- /* Print the negotiated PCIe link width */
- pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
- printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
- (temp16 & 0xf), info->regs);
-
- if (ep_mode)
- return busno;
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-
- printf("PCIe%x: Bus %02x - %02x\n",
- info->pci_num, hose->first_busno, hose->last_busno);
-
- return hose->last_busno + 1;
-}
-
-int ls_pcie_init_board(int busno)
-{
- struct ls_pcie_info info;
-
-#ifdef CONFIG_PCIE1
- SET_LS_PCIE_INFO(info, 1);
- busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
-#endif
-
-#ifdef CONFIG_PCIE2
- SET_LS_PCIE_INFO(info, 2);
- busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
-#endif
-
-#ifdef CONFIG_PCIE3
- SET_LS_PCIE_INFO(info, 3);
- busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
-#endif
-
-#ifdef CONFIG_PCIE4
- SET_LS_PCIE_INFO(info, 4);
- busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
-#endif
-
- return busno;
-}
-
-void pci_init_board(void)
-{
- ls_pcie_init_board(0);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#include <libfdt.h>
-#include <fdt_support.h>
-
-static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
- unsigned long ctrl_addr, enum srds_prtcl dev)
-{
- int off;
-
- off = fdt_node_offset_by_compat_reg(blob, pci_compat,
- (phys_addr_t)ctrl_addr);
- if (off < 0)
- return;
-
- if (!is_serdes_configured(dev))
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
-}
-
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- #ifdef CONFIG_PCIE1
- ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
- #endif
-
- #ifdef CONFIG_PCIE2
- ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
- #endif
-
- #ifdef CONFIG_PCIE3
- ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
- #endif
-
- #ifdef CONFIG_PCIE4
- ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
- #endif
-
- #ifdef CONFIG_FSL_LSCH3
- fdt_fixup_pcie(blob);
- #endif
-}
-
-#else
-void ft_pci_setup(void *blob, bd_t *bd)
-{
-}
-#endif
-
-#else
-
/* LUT registers */
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
@@ -1573,5 +842,3 @@ U_BOOT_DRIVER(pci_layerscape) = {
.probe = ls_pcie_probe,
.priv_auto_alloc_size = sizeof(struct ls_pcie),
};
-
-#endif /* CONFIG_DM_PCI */
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 31+ messages in thread* [U-Boot] [PATCHv3 15/15] pci: layerscape: remove unnecessary legacy code
2016-11-16 9:48 ` [U-Boot] [PATCHv3 15/15] pci: layerscape: remove unnecessary legacy code Zhiqiang Hou
@ 2016-11-18 1:14 ` Simon Glass
2016-11-22 9:26 ` Z.Q. Hou
0 siblings, 1 reply; 31+ messages in thread
From: Simon Glass @ 2016-11-18 1:14 UTC (permalink / raw)
To: u-boot
On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com> wrote:
> From: Minghuan Lian <Minghuan.Lian@nxp.com>
>
> All Layerscape SoCs have supported new PCIe driver based on DM.
> The lagecy PCIe driver code is unused and can be removed.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V3:
> - No change
>
> drivers/pci/pcie_layerscape.c | 733 ------------------------------------------
> 1 file changed, 733 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCHv3 15/15] pci: layerscape: remove unnecessary legacy code
2016-11-18 1:14 ` Simon Glass
@ 2016-11-22 9:26 ` Z.Q. Hou
0 siblings, 0 replies; 31+ messages in thread
From: Z.Q. Hou @ 2016-11-22 9:26 UTC (permalink / raw)
To: u-boot
Hi Simon,
Thanks for your review!
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: 2016?11?18? 9:15
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.boot@aribaud.net>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Huan Wang-B18965
> <alison.wang@freescale.com>; Sumit Garg <sumit.garg@nxp.com>; Ruchika
> Gupta <ruchika.gupta@nxp.com>; Saksham Jain
> <saksham.jain@nxp.freescale.com>; york sun <york.sun@nxp.com>; M.H. Lian
> <minghuan.lian@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [PATCHv3 15/15] pci: layerscape: remove unnecessary legacy
> code
>
> On 16 November 2016 at 02:48, Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
> wrote:
> > From: Minghuan Lian <Minghuan.Lian@nxp.com>
> >
> > All Layerscape SoCs have supported new PCIe driver based on DM.
> > The lagecy PCIe driver code is unused and can be removed.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V3:
> > - No change
> >
> > drivers/pci/pcie_layerscape.c | 733 ------------------------------------------
> > 1 file changed, 733 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Regards,
Zhiqiang
^ permalink raw reply [flat|nested] 31+ messages in thread