* [PATCH] x86: use "R" constraint for fxsaveq/fxrstorq enforcement
@ 2013-08-13 15:43 Jan Beulich
2013-08-13 17:02 ` Andrew Cooper
2013-08-13 17:34 ` Keir Fraser
0 siblings, 2 replies; 3+ messages in thread
From: Jan Beulich @ 2013-08-13 15:43 UTC (permalink / raw)
To: xen-devel; +Cc: Keir Fraser
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I became aware of this constraint's (referring to all legacy registers
in one go) existence by (accidentally) noticing Linux commit 82024135
("x86-64, fpu: Simplify constraints for fxsave/fxtstor").
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/i387.c
+++ b/xen/arch/x86/i387.c
@@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vc
".previous \n"
_ASM_EXTABLE(1b, 2b)
:
- : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4),
- "cdaSDb" (fpu_ctxt) );
+ : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) );
break;
case 4: case 2:
asm volatile (
@@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcp
* addressing mode that doesn't require extended registers.
*/
asm volatile ( REX64_PREFIX "fxsave (%1)"
- : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) );
+ : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) );
/*
* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
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x86: use "R" constraint for fxsaveq/fxrstorq enforcement
I became aware of this constraint's (referring to all legacy registers
in one go) existence by (accidentally) noticing Linux commit 82024135
("x86-64, fpu: Simplify constraints for fxsave/fxtstor").
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/i387.c
+++ b/xen/arch/x86/i387.c
@@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vc
".previous \n"
_ASM_EXTABLE(1b, 2b)
:
- : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4),
- "cdaSDb" (fpu_ctxt) );
+ : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) );
break;
case 4: case 2:
asm volatile (
@@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcp
* addressing mode that doesn't require extended registers.
*/
asm volatile ( REX64_PREFIX "fxsave (%1)"
- : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) );
+ : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) );
/*
* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
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Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] x86: use "R" constraint for fxsaveq/fxrstorq enforcement
2013-08-13 15:43 [PATCH] x86: use "R" constraint for fxsaveq/fxrstorq enforcement Jan Beulich
@ 2013-08-13 17:02 ` Andrew Cooper
2013-08-13 17:34 ` Keir Fraser
1 sibling, 0 replies; 3+ messages in thread
From: Andrew Cooper @ 2013-08-13 17:02 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel, Keir Fraser
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On 13/08/13 16:43, Jan Beulich wrote:
> I became aware of this constraint's (referring to all legacy registers
> in one go) existence by (accidentally) noticing Linux commit 82024135
> ("x86-64, fpu: Simplify constraints for fxsave/fxtstor").
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
>
> --- a/xen/arch/x86/i387.c
> +++ b/xen/arch/x86/i387.c
> @@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vc
> ".previous \n"
> _ASM_EXTABLE(1b, 2b)
> :
> - : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4),
> - "cdaSDb" (fpu_ctxt) );
> + : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) );
> break;
> case 4: case 2:
> asm volatile (
> @@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcp
> * addressing mode that doesn't require extended registers.
> */
> asm volatile ( REX64_PREFIX "fxsave (%1)"
> - : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) );
> + : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) );
>
> /*
> * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
>
>
>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel
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_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] x86: use "R" constraint for fxsaveq/fxrstorq enforcement
2013-08-13 15:43 [PATCH] x86: use "R" constraint for fxsaveq/fxrstorq enforcement Jan Beulich
2013-08-13 17:02 ` Andrew Cooper
@ 2013-08-13 17:34 ` Keir Fraser
1 sibling, 0 replies; 3+ messages in thread
From: Keir Fraser @ 2013-08-13 17:34 UTC (permalink / raw)
To: Jan Beulich, xen-devel
On 13/08/2013 16:43, "Jan Beulich" <JBeulich@suse.com> wrote:
> I became aware of this constraint's (referring to all legacy registers
> in one go) existence by (accidentally) noticing Linux commit 82024135
> ("x86-64, fpu: Simplify constraints for fxsave/fxtstor").
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Assuming it is available on all our supported versions of gcc:
Acked-by: Keir Fraser <keir@xen.org>
> --- a/xen/arch/x86/i387.c
> +++ b/xen/arch/x86/i387.c
> @@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vc
> ".previous \n"
> _ASM_EXTABLE(1b, 2b)
> :
> - : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4),
> - "cdaSDb" (fpu_ctxt) );
> + : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) );
> break;
> case 4: case 2:
> asm volatile (
> @@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcp
> * addressing mode that doesn't require extended registers.
> */
> asm volatile ( REX64_PREFIX "fxsave (%1)"
> - : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) );
> + : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) );
>
> /*
> * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2013-08-13 15:43 [PATCH] x86: use "R" constraint for fxsaveq/fxrstorq enforcement Jan Beulich
2013-08-13 17:02 ` Andrew Cooper
2013-08-13 17:34 ` Keir Fraser
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