* [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode @ 2021-08-04 7:50 Jiawei Gu 2021-08-04 8:07 ` Gu, JiaWei (Will) 0 siblings, 1 reply; 7+ messages in thread From: Jiawei Gu @ 2021-08-04 7:50 UTC (permalink / raw) To: amd-gfx; +Cc: david.nieto, emily.deng, Jiawei Gu Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under SRIOV 1-VF scenario. Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 769f58d5ae1a..04c7d82f8b89 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2005,10 +2005,10 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ static struct amdgpu_device_attr amdgpu_device_attrs[] = { AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), - AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC), + AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode 2021-08-04 7:50 [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode Jiawei Gu @ 2021-08-04 8:07 ` Gu, JiaWei (Will) 2021-08-05 6:31 ` Gu, JiaWei (Will) 0 siblings, 1 reply; 7+ messages in thread From: Gu, JiaWei (Will) @ 2021-08-04 8:07 UTC (permalink / raw) To: Gu, JiaWei (Will), amd-gfx Cc: Nieto, David M, Deng, Emily, Deucher, Alexander [AMD Official Use Only] Add Alex. -----Original Message----- From: Jiawei Gu <Jiawei.Gu@amd.com> Sent: Wednesday, August 4, 2021 3:50 PM To: amd-gfx@lists.freedesktop.org Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Gu, JiaWei (Will) <JiaWei.Gu@amd.com> Subject: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under SRIOV 1-VF scenario. Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 769f58d5ae1a..04c7d82f8b89 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2005,10 +2005,10 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ static struct amdgpu_device_attr amdgpu_device_attrs[] = { AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), - AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC), + AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode 2021-08-04 8:07 ` Gu, JiaWei (Will) @ 2021-08-05 6:31 ` Gu, JiaWei (Will) 2021-08-05 8:37 ` Deng, Emily 2021-08-05 9:07 ` Lazar, Lijo 0 siblings, 2 replies; 7+ messages in thread From: Gu, JiaWei (Will) @ 2021-08-05 6:31 UTC (permalink / raw) To: amd-gfx; +Cc: Nieto, David M, Deng, Emily, Deucher, Alexander [AMD Official Use Only] Ping. -----Original Message----- From: Gu, JiaWei (Will) <JiaWei.Gu@amd.com> Sent: Wednesday, August 4, 2021 4:08 PM To: Gu, JiaWei (Will) <JiaWei.Gu@amd.com>; amd-gfx@lists.freedesktop.org Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com> Subject: RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode [AMD Official Use Only] Add Alex. -----Original Message----- From: Jiawei Gu <Jiawei.Gu@amd.com> Sent: Wednesday, August 4, 2021 3:50 PM To: amd-gfx@lists.freedesktop.org Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Gu, JiaWei (Will) <JiaWei.Gu@amd.com> Subject: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under SRIOV 1-VF scenario. Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 769f58d5ae1a..04c7d82f8b89 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2005,10 +2005,10 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ static struct amdgpu_device_attr amdgpu_device_attrs[] = { AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), - AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), - AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC), + AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode 2021-08-05 6:31 ` Gu, JiaWei (Will) @ 2021-08-05 8:37 ` Deng, Emily 2021-08-05 9:07 ` Lazar, Lijo 1 sibling, 0 replies; 7+ messages in thread From: Deng, Emily @ 2021-08-05 8:37 UTC (permalink / raw) To: Gu, JiaWei (Will), amd-gfx; +Cc: Nieto, David M, Deucher, Alexander Acked-by: Emily.Deng <Emily.Deng@amd.com> >-----Original Message----- >From: Gu, JiaWei (Will) <JiaWei.Gu@amd.com> >Sent: Thursday, August 5, 2021 2:32 PM >To: amd-gfx@lists.freedesktop.org >Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily ><Emily.Deng@amd.com>; Deucher, Alexander ><Alexander.Deucher@amd.com> >Subject: RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF >mode > >[AMD Official Use Only] > >Ping. > >-----Original Message----- >From: Gu, JiaWei (Will) <JiaWei.Gu@amd.com> >Sent: Wednesday, August 4, 2021 4:08 PM >To: Gu, JiaWei (Will) <JiaWei.Gu@amd.com>; amd-gfx@lists.freedesktop.org >Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily ><Emily.Deng@amd.com>; Deucher, Alexander ><Alexander.Deucher@amd.com> >Subject: RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF >mode > >[AMD Official Use Only] > >Add Alex. > >-----Original Message----- >From: Jiawei Gu <Jiawei.Gu@amd.com> >Sent: Wednesday, August 4, 2021 3:50 PM >To: amd-gfx@lists.freedesktop.org >Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily ><Emily.Deng@amd.com>; Gu, JiaWei (Will) <JiaWei.Gu@amd.com> >Subject: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF >mode > >Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under >SRIOV 1-VF scenario. > >Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> >--- > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > >diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c >b/drivers/gpu/drm/amd/pm/amdgpu_pm.c >index 769f58d5ae1a..04c7d82f8b89 100644 >--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c >+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c >@@ -2005,10 +2005,10 @@ static int ss_bias_attr_update(struct >amdgpu_device *adev, struct amdgpu_device_ static struct >amdgpu_device_attr amdgpu_device_attrs[] = { > AMDGPU_DEVICE_ATTR_RW(power_dpm_state, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >- AMDGPU_DEVICE_ATTR_RO(pp_num_states, > ATTR_FLAG_BASIC), >- AMDGPU_DEVICE_ATTR_RO(pp_cur_state, > ATTR_FLAG_BASIC), >- AMDGPU_DEVICE_ATTR_RW(pp_force_state, > ATTR_FLAG_BASIC), >- AMDGPU_DEVICE_ATTR_RW(pp_table, > ATTR_FLAG_BASIC), >+ AMDGPU_DEVICE_ATTR_RO(pp_num_states, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >+ AMDGPU_DEVICE_ATTR_RO(pp_cur_state, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >+ AMDGPU_DEVICE_ATTR_RW(pp_force_state, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >+ AMDGPU_DEVICE_ATTR_RW(pp_table, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >-- >2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode 2021-08-05 6:31 ` Gu, JiaWei (Will) 2021-08-05 8:37 ` Deng, Emily @ 2021-08-05 9:07 ` Lazar, Lijo 2021-08-05 9:18 ` Gu, JiaWei (Will) 1 sibling, 1 reply; 7+ messages in thread From: Lazar, Lijo @ 2021-08-05 9:07 UTC (permalink / raw) To: Gu, JiaWei (Will), amd-gfx Cc: Nieto, David M, Deng, Emily, Deucher, Alexander On 8/5/2021 12:01 PM, Gu, JiaWei (Will) wrote: > [AMD Official Use Only] > > Ping. > > -----Original Message----- > From: Gu, JiaWei (Will) <JiaWei.Gu@amd.com> > Sent: Wednesday, August 4, 2021 4:08 PM > To: Gu, JiaWei (Will) <JiaWei.Gu@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com> > Subject: RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode > > [AMD Official Use Only] > > Add Alex. > > -----Original Message----- > From: Jiawei Gu <Jiawei.Gu@amd.com> > Sent: Wednesday, August 4, 2021 3:50 PM > To: amd-gfx@lists.freedesktop.org > Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Gu, JiaWei (Will) <JiaWei.Gu@amd.com> > Subject: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode > > Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under SRIOV 1-VF scenario. > > Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> > --- > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > index 769f58d5ae1a..04c7d82f8b89 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > @@ -2005,10 +2005,10 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ static struct amdgpu_device_attr amdgpu_device_attrs[] = { > AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > - AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), > - AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), > - AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), > - AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC), > + AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > + AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > + AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), Which ASIC is this for? As far as I see from the current implementation, power state is not supported in swsmu projects. Thanks, Lijo > + AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF) > AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode 2021-08-05 9:07 ` Lazar, Lijo @ 2021-08-05 9:18 ` Gu, JiaWei (Will) 2021-08-05 9:32 ` Lazar, Lijo 0 siblings, 1 reply; 7+ messages in thread From: Gu, JiaWei (Will) @ 2021-08-05 9:18 UTC (permalink / raw) To: Lazar, Lijo, amd-gfx; +Cc: Nieto, David M, Deng, Emily, Deucher, Alexander [AMD Official Use Only] Hi Lijo, It's for Navi12 asic as far as I know. Best regards, Jiawei -----Original Message----- From: Lazar, Lijo <Lijo.Lazar@amd.com> Sent: Thursday, August 5, 2021 5:08 PM To: Gu, JiaWei (Will) <JiaWei.Gu@amd.com>; amd-gfx@lists.freedesktop.org Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com> Subject: Re: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode On 8/5/2021 12:01 PM, Gu, JiaWei (Will) wrote: > [AMD Official Use Only] > > Ping. > > -----Original Message----- > From: Gu, JiaWei (Will) <JiaWei.Gu@amd.com> > Sent: Wednesday, August 4, 2021 4:08 PM > To: Gu, JiaWei (Will) <JiaWei.Gu@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily > <Emily.Deng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com> > Subject: RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF > mode > > [AMD Official Use Only] > > Add Alex. > > -----Original Message----- > From: Jiawei Gu <Jiawei.Gu@amd.com> > Sent: Wednesday, August 4, 2021 3:50 PM > To: amd-gfx@lists.freedesktop.org > Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily > <Emily.Deng@amd.com>; Gu, JiaWei (Will) <JiaWei.Gu@amd.com> > Subject: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF > mode > > Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under SRIOV 1-VF scenario. > > Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> > --- > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > index 769f58d5ae1a..04c7d82f8b89 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > @@ -2005,10 +2005,10 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ static struct amdgpu_device_attr amdgpu_device_attrs[] = { > AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > - AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), > - AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), > - AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), > - AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC), > + AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > + AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > + AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), Which ASIC is this for? As far as I see from the current implementation, power state is not supported in swsmu projects. Thanks, Lijo > + AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF) > AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode 2021-08-05 9:18 ` Gu, JiaWei (Will) @ 2021-08-05 9:32 ` Lazar, Lijo 0 siblings, 0 replies; 7+ messages in thread From: Lazar, Lijo @ 2021-08-05 9:32 UTC (permalink / raw) To: Gu, JiaWei (Will), amd-gfx Cc: Nieto, David M, Deng, Emily, Deucher, Alexander Navi12 is swsmu based. Suggest you to check the implementation of below sys nodes and decide what you want to do. Not able to figure out how it worked for you, did you really try this on any 1VF system? + AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), + AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), Thanks, Lijo On 8/5/2021 2:48 PM, Gu, JiaWei (Will) wrote: > [AMD Official Use Only] > > Hi Lijo, > > It's for Navi12 asic as far as I know. > > Best regards, > Jiawei > > -----Original Message----- > From: Lazar, Lijo <Lijo.Lazar@amd.com> > Sent: Thursday, August 5, 2021 5:08 PM > To: Gu, JiaWei (Will) <JiaWei.Gu@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com> > Subject: Re: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode > > > > On 8/5/2021 12:01 PM, Gu, JiaWei (Will) wrote: >> [AMD Official Use Only] >> >> Ping. >> >> -----Original Message----- >> From: Gu, JiaWei (Will) <JiaWei.Gu@amd.com> >> Sent: Wednesday, August 4, 2021 4:08 PM >> To: Gu, JiaWei (Will) <JiaWei.Gu@amd.com>; >> amd-gfx@lists.freedesktop.org >> Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily >> <Emily.Deng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com> >> Subject: RE: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF >> mode >> >> [AMD Official Use Only] >> >> Add Alex. >> >> -----Original Message----- >> From: Jiawei Gu <Jiawei.Gu@amd.com> >> Sent: Wednesday, August 4, 2021 3:50 PM >> To: amd-gfx@lists.freedesktop.org >> Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily >> <Emily.Deng@amd.com>; Gu, JiaWei (Will) <JiaWei.Gu@amd.com> >> Subject: [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF >> mode >> >> Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under SRIOV 1-VF scenario. >> >> Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> >> --- >> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c >> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c >> index 769f58d5ae1a..04c7d82f8b89 100644 >> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c >> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c >> @@ -2005,10 +2005,10 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ static struct amdgpu_device_attr amdgpu_device_attrs[] = { >> AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >> AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >> - AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), >> - AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), >> - AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), >> - AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC), > >> + AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >> + AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >> + AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), > > Which ASIC is this for? As far as I see from the current implementation, power state is not supported in swsmu projects. > > Thanks, > Lijo > >> + AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF) > AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, > ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >> AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >> AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), >> -- >> 2.17.1 >> ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-08-05 9:33 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-08-04 7:50 [PATCH] drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode Jiawei Gu 2021-08-04 8:07 ` Gu, JiaWei (Will) 2021-08-05 6:31 ` Gu, JiaWei (Will) 2021-08-05 8:37 ` Deng, Emily 2021-08-05 9:07 ` Lazar, Lijo 2021-08-05 9:18 ` Gu, JiaWei (Will) 2021-08-05 9:32 ` Lazar, Lijo
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