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* [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2
@ 2020-01-07 21:13 Alex Deucher
  2020-01-07 21:13 ` [PATCH 2/2] drm/amdgpu: enable S/G display for renoir Alex Deucher
  2020-01-08 10:19 ` [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2 Christian König
  0 siblings, 2 replies; 8+ messages in thread
From: Alex Deucher @ 2020-01-07 21:13 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

It should work on all Raven variants, but some users have
reported issues with original Raven with IOMMU enabled.
So far there have been no issues observed with PCO or RV2.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 22 ++++++++++++++-----
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ++++++++++-----
 2 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 4e699071d144..6d520a3eec40 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -513,13 +513,23 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 	 * will not allow USWC mappings.
 	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
 	 */
-	if (adev->asic_type >= CHIP_CARRIZO &&
-	    adev->asic_type < CHIP_RAVEN &&
-	    (adev->flags & AMD_IS_APU) &&
-	    (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
+	if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 	    amdgpu_bo_support_uswc(bo_flags) &&
-	    amdgpu_device_asic_has_dc_support(adev->asic_type))
-		domain |= AMDGPU_GEM_DOMAIN_GTT;
+	    amdgpu_device_asic_has_dc_support(adev->asic_type)) {
+		switch (adev->asic_type) {
+		case CHIP_CARRIZO:
+		case CHIP_STONEY:
+			domain |= AMDGPU_GEM_DOMAIN_GTT;
+			break;
+		case CHIP_RAVEN:
+			/* enable S/G on PCO and RV2 */
+			if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
+				domain |= AMDGPU_GEM_DOMAIN_GTT;
+			break;
+		default:
+			break;
+		}
+	}
 #endif
 
 	return domain;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b998b0382477..05118c8860f9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -906,13 +906,19 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 
 	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 
-	/*
-	 * TODO debug why this doesn't work on Raven
-	 */
-	if (adev->flags & AMD_IS_APU &&
-	    adev->asic_type >= CHIP_CARRIZO &&
-	    adev->asic_type < CHIP_RAVEN)
+	switch (adev->asic_type) {
+	case CHIP_CARRIZO:
+	case CHIP_STONEY:
 		init_data.flags.gpu_vm_support = true;
+		break;
+	case CHIP_RAVEN:
+		/* enable S/G on PCO and RV2 */
+		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
+			init_data.flags.gpu_vm_support = true;
+		break;
+	default:
+		break;
+	}
 
 	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
 		init_data.flags.fbc_support = true;
-- 
2.24.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
  2020-01-07 21:13 [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2 Alex Deucher
@ 2020-01-07 21:13 ` Alex Deucher
  2020-01-08  2:48   ` Liu, Aaron
  2020-01-08 15:27   ` Harry Wentland
  2020-01-08 10:19 ` [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2 Christian König
  1 sibling, 2 replies; 8+ messages in thread
From: Alex Deucher @ 2020-01-07 21:13 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

Everything is in place so go ahead and enable this for
renoir.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

I don't have a renoir board handy.  Can someone test this?

 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 6d520a3eec40..318605ca9bc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -519,6 +519,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 		switch (adev->asic_type) {
 		case CHIP_CARRIZO:
 		case CHIP_STONEY:
+		case CHIP_RENOIR:
 			domain |= AMDGPU_GEM_DOMAIN_GTT;
 			break;
 		case CHIP_RAVEN:
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 05118c8860f9..3be7ab0ce9e3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -909,6 +909,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
+	case CHIP_RENOIR:
 		init_data.flags.gpu_vm_support = true;
 		break;
 	case CHIP_RAVEN:
-- 
2.24.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
  2020-01-07 21:13 ` [PATCH 2/2] drm/amdgpu: enable S/G display for renoir Alex Deucher
@ 2020-01-08  2:48   ` Liu, Aaron
  2020-01-08  3:05     ` Deucher, Alexander
  2020-01-08 15:27   ` Harry Wentland
  1 sibling, 1 reply; 8+ messages in thread
From: Liu, Aaron @ 2020-01-08  2:48 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx; +Cc: Deucher, Alexander

Reviewed & Tested-by: Aaron Liu <aaron.liu@amd.com>

BR,
Aaron Liu

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Wednesday, January 8, 2020 5:13 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> 
> Everything is in place so go ahead and enable this for renoir.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> 
> I don't have a renoir board handy.  Can someone test this?
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 1 +
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 6d520a3eec40..318605ca9bc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -519,6 +519,7 @@ uint32_t amdgpu_display_supported_domains(struct
> amdgpu_device *adev,
>  		switch (adev->asic_type) {
>  		case CHIP_CARRIZO:
>  		case CHIP_STONEY:
> +		case CHIP_RENOIR:
>  			domain |= AMDGPU_GEM_DOMAIN_GTT;
>  			break;
>  		case CHIP_RAVEN:
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 05118c8860f9..3be7ab0ce9e3 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -909,6 +909,7 @@ static int amdgpu_dm_init(struct amdgpu_device
> *adev)
>  	switch (adev->asic_type) {
>  	case CHIP_CARRIZO:
>  	case CHIP_STONEY:
> +	case CHIP_RENOIR:
>  		init_data.flags.gpu_vm_support = true;
>  		break;
>  	case CHIP_RAVEN:
> --
> 2.24.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.f
> reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&amp;data=02%7C01%7Caaron.liu%40amd.com%7Cd9cdd08e60a942e97c
> 6a08d793b67ea1%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> 37140284454500549&amp;sdata=TGuS5qqX8siW1sxWUZtQggnk4P2RPjxUiLk
> dvS1Fcog%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 8+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
  2020-01-08  2:48   ` Liu, Aaron
@ 2020-01-08  3:05     ` Deucher, Alexander
  2020-01-08  5:42       ` Liu, Aaron
  0 siblings, 1 reply; 8+ messages in thread
From: Deucher, Alexander @ 2020-01-08  3:05 UTC (permalink / raw)
  To: Liu, Aaron, Alex Deucher, amd-gfx

[AMD Official Use Only - Internal Distribution Only]

> -----Original Message-----
> From: Liu, Aaron <Aaron.Liu@amd.com>
> Sent: Tuesday, January 7, 2020 9:48 PM
> To: Alex Deucher <alexdeucher@gmail.com>; amd-
> gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> 
> Reviewed & Tested-by: Aaron Liu <aaron.liu@amd.com>
> 

Did you test with limited vram?  E.g, set the carve out to 32 or 64 MB so the driver actually uses gart for display?

Thanks,

Alex

> BR,
> Aaron Liu
> 
> > -----Original Message-----
> > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Alex Deucher
> > Sent: Wednesday, January 8, 2020 5:13 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> > Subject: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> >
> > Everything is in place so go ahead and enable this for renoir.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >
> > I don't have a renoir board handy.  Can someone test this?
> >
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 1 +
> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
> >  2 files changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index 6d520a3eec40..318605ca9bc3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -519,6 +519,7 @@ uint32_t
> amdgpu_display_supported_domains(struct
> > amdgpu_device *adev,
> >  		switch (adev->asic_type) {
> >  		case CHIP_CARRIZO:
> >  		case CHIP_STONEY:
> > +		case CHIP_RENOIR:
> >  			domain |= AMDGPU_GEM_DOMAIN_GTT;
> >  			break;
> >  		case CHIP_RAVEN:
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 05118c8860f9..3be7ab0ce9e3 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -909,6 +909,7 @@ static int amdgpu_dm_init(struct amdgpu_device
> > *adev)
> >  	switch (adev->asic_type) {
> >  	case CHIP_CARRIZO:
> >  	case CHIP_STONEY:
> > +	case CHIP_RENOIR:
> >  		init_data.flags.gpu_vm_support = true;
> >  		break;
> >  	case CHIP_RAVEN:
> > --
> > 2.24.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.f
> > reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> >
> gfx&amp;data=02%7C01%7Caaron.liu%40amd.com%7Cd9cdd08e60a942e97c
> > 6a08d793b67ea1%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> >
> 37140284454500549&amp;sdata=TGuS5qqX8siW1sxWUZtQggnk4P2RPjxUiLk
> > dvS1Fcog%3D&amp;reserved=0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 8+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
  2020-01-08  3:05     ` Deucher, Alexander
@ 2020-01-08  5:42       ` Liu, Aaron
  0 siblings, 0 replies; 8+ messages in thread
From: Liu, Aaron @ 2020-01-08  5:42 UTC (permalink / raw)
  To: Deucher, Alexander, Alex Deucher, amd-gfx

> -----Original Message-----
> From: Deucher, Alexander <Alexander.Deucher@amd.com>
> Sent: Wednesday, January 8, 2020 11:05 AM
> To: Liu, Aaron <Aaron.Liu@amd.com>; Alex Deucher
> <alexdeucher@gmail.com>; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> 
> [AMD Official Use Only - Internal Distribution Only]
> 
> > -----Original Message-----
> > From: Liu, Aaron <Aaron.Liu@amd.com>
> > Sent: Tuesday, January 7, 2020 9:48 PM
> > To: Alex Deucher <alexdeucher@gmail.com>; amd-
> > gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> > Subject: RE: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> >
> > Reviewed & Tested-by: Aaron Liu <aaron.liu@amd.com>
> >
> 
> Did you test with limited vram?  E.g, set the carve out to 32 or 64 MB so the
> driver actually uses gart for display?
> 
Hi Alex,
If I lower the UMA size to 64M.(UMA default is 512M)
For Renoir and with [PATCH 2/2], white screen appears and ubuntu desktop cannot boot up successfully.
For Raven, no matter with or without [PATCH 1/2], the system can bootup normally.

> Thanks,
> 
> Alex
> 
> > BR,
> > Aaron Liu
> >
> > > -----Original Message-----
> > > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > > Alex Deucher
> > > Sent: Wednesday, January 8, 2020 5:13 AM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> > > Subject: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
> > >
> > > Everything is in place so go ahead and enable this for renoir.
> > >
> > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > ---
> > >
> > > I don't have a renoir board handy.  Can someone test this?
> > >
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 1 +
> > >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
> > >  2 files changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > index 6d520a3eec40..318605ca9bc3 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > @@ -519,6 +519,7 @@ uint32_t
> > amdgpu_display_supported_domains(struct
> > > amdgpu_device *adev,
> > >  		switch (adev->asic_type) {
> > >  		case CHIP_CARRIZO:
> > >  		case CHIP_STONEY:
> > > +		case CHIP_RENOIR:
> > >  			domain |= AMDGPU_GEM_DOMAIN_GTT;
> > >  			break;
> > >  		case CHIP_RAVEN:
> > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > index 05118c8860f9..3be7ab0ce9e3 100644
> > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > @@ -909,6 +909,7 @@ static int amdgpu_dm_init(struct amdgpu_device
> > > *adev)
> > >  	switch (adev->asic_type) {
> > >  	case CHIP_CARRIZO:
> > >  	case CHIP_STONEY:
> > > +	case CHIP_RENOIR:
> > >  		init_data.flags.gpu_vm_support = true;
> > >  		break;
> > >  	case CHIP_RAVEN:
> > > --
> > > 2.24.1
> > >
> > > _______________________________________________
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > > st
> > > s.f
> > > reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> > >
> >
> gfx&amp;data=02%7C01%7Caaron.liu%40amd.com%7Cd9cdd08e60a942e97c
> > >
> 6a08d793b67ea1%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> > >
> >
> 37140284454500549&amp;sdata=TGuS5qqX8siW1sxWUZtQggnk4P2RPjxUiLk
> > > dvS1Fcog%3D&amp;reserved=0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2
  2020-01-07 21:13 [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2 Alex Deucher
  2020-01-07 21:13 ` [PATCH 2/2] drm/amdgpu: enable S/G display for renoir Alex Deucher
@ 2020-01-08 10:19 ` Christian König
  2020-01-08 22:22   ` Alex Deucher
  1 sibling, 1 reply; 8+ messages in thread
From: Christian König @ 2020-01-08 10:19 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx; +Cc: Alex Deucher

Am 07.01.20 um 22:13 schrieb Alex Deucher:
> It should work on all Raven variants, but some users have
> reported issues with original Raven with IOMMU enabled.
> So far there have been no issues observed with PCO or RV2.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 22 ++++++++++++++-----
>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ++++++++++-----
>   2 files changed, 28 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 4e699071d144..6d520a3eec40 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -513,13 +513,23 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
>   	 * will not allow USWC mappings.
>   	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
>   	 */
> -	if (adev->asic_type >= CHIP_CARRIZO &&
> -	    adev->asic_type < CHIP_RAVEN &&
> -	    (adev->flags & AMD_IS_APU) &&
> -	    (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
> +	if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
>   	    amdgpu_bo_support_uswc(bo_flags) &&
> -	    amdgpu_device_asic_has_dc_support(adev->asic_type))
> -		domain |= AMDGPU_GEM_DOMAIN_GTT;
> +	    amdgpu_device_asic_has_dc_support(adev->asic_type)) {
> +		switch (adev->asic_type) {
> +		case CHIP_CARRIZO:
> +		case CHIP_STONEY:
> +			domain |= AMDGPU_GEM_DOMAIN_GTT;
> +			break;
> +		case CHIP_RAVEN:
> +			/* enable S/G on PCO and RV2 */
> +			if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
> +				domain |= AMDGPU_GEM_DOMAIN_GTT;
> +			break;
> +		default:
> +			break;
> +		}
> +	}
>   #endif
>   
>   	return domain;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index b998b0382477..05118c8860f9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -906,13 +906,19 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>   
>   	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
>   
> -	/*
> -	 * TODO debug why this doesn't work on Raven
> -	 */
> -	if (adev->flags & AMD_IS_APU &&
> -	    adev->asic_type >= CHIP_CARRIZO &&
> -	    adev->asic_type < CHIP_RAVEN)
> +	switch (adev->asic_type) {
> +	case CHIP_CARRIZO:
> +	case CHIP_STONEY:
>   		init_data.flags.gpu_vm_support = true;
> +		break;
> +	case CHIP_RAVEN:
> +		/* enable S/G on PCO and RV2 */
> +		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
> +			init_data.flags.gpu_vm_support = true;
> +		break;
> +	default:
> +		break;
> +	}

It might be a good idea to enable gpu_vm_support independent anyway.

Might be even a good idea to do this in a separate patch.

But either way I'm not an expert on how the hardware works in this area, 
so Acked-by: Christian König <christian.koenig@amd.com> for this series 
either way.

Regards,
Christian.

>   
>   	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
>   		init_data.flags.fbc_support = true;

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^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: enable S/G display for renoir
  2020-01-07 21:13 ` [PATCH 2/2] drm/amdgpu: enable S/G display for renoir Alex Deucher
  2020-01-08  2:48   ` Liu, Aaron
@ 2020-01-08 15:27   ` Harry Wentland
  1 sibling, 0 replies; 8+ messages in thread
From: Harry Wentland @ 2020-01-08 15:27 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx; +Cc: Alex Deucher

Series is
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

On 2020-01-07 4:13 p.m., Alex Deucher wrote:
> Everything is in place so go ahead and enable this for
> renoir.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> 
> I don't have a renoir board handy.  Can someone test this?
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 1 +
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 6d520a3eec40..318605ca9bc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -519,6 +519,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
>  		switch (adev->asic_type) {
>  		case CHIP_CARRIZO:
>  		case CHIP_STONEY:
> +		case CHIP_RENOIR:
>  			domain |= AMDGPU_GEM_DOMAIN_GTT;
>  			break;
>  		case CHIP_RAVEN:
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 05118c8860f9..3be7ab0ce9e3 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -909,6 +909,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>  	switch (adev->asic_type) {
>  	case CHIP_CARRIZO:
>  	case CHIP_STONEY:
> +	case CHIP_RENOIR:
>  		init_data.flags.gpu_vm_support = true;
>  		break;
>  	case CHIP_RAVEN:
> 
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^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2
  2020-01-08 10:19 ` [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2 Christian König
@ 2020-01-08 22:22   ` Alex Deucher
  0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2020-01-08 22:22 UTC (permalink / raw)
  To: Christian Koenig; +Cc: Alex Deucher, amd-gfx list

On Wed, Jan 8, 2020 at 5:19 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 07.01.20 um 22:13 schrieb Alex Deucher:
> > It should work on all Raven variants, but some users have
> > reported issues with original Raven with IOMMU enabled.
> > So far there have been no issues observed with PCO or RV2.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 22 ++++++++++++++-----
> >   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ++++++++++-----
> >   2 files changed, 28 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index 4e699071d144..6d520a3eec40 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -513,13 +513,23 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
> >        * will not allow USWC mappings.
> >        * Also, don't allow GTT domain if the BO doens't have USWC falg set.
> >        */
> > -     if (adev->asic_type >= CHIP_CARRIZO &&
> > -         adev->asic_type < CHIP_RAVEN &&
> > -         (adev->flags & AMD_IS_APU) &&
> > -         (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
> > +     if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
> >           amdgpu_bo_support_uswc(bo_flags) &&
> > -         amdgpu_device_asic_has_dc_support(adev->asic_type))
> > -             domain |= AMDGPU_GEM_DOMAIN_GTT;
> > +         amdgpu_device_asic_has_dc_support(adev->asic_type)) {
> > +             switch (adev->asic_type) {
> > +             case CHIP_CARRIZO:
> > +             case CHIP_STONEY:
> > +                     domain |= AMDGPU_GEM_DOMAIN_GTT;
> > +                     break;
> > +             case CHIP_RAVEN:
> > +                     /* enable S/G on PCO and RV2 */
> > +                     if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
> > +                             domain |= AMDGPU_GEM_DOMAIN_GTT;
> > +                     break;
> > +             default:
> > +                     break;
> > +             }
> > +     }
> >   #endif
> >
> >       return domain;
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index b998b0382477..05118c8860f9 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -906,13 +906,19 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> >
> >       init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
> >
> > -     /*
> > -      * TODO debug why this doesn't work on Raven
> > -      */
> > -     if (adev->flags & AMD_IS_APU &&
> > -         adev->asic_type >= CHIP_CARRIZO &&
> > -         adev->asic_type < CHIP_RAVEN)
> > +     switch (adev->asic_type) {
> > +     case CHIP_CARRIZO:
> > +     case CHIP_STONEY:
> >               init_data.flags.gpu_vm_support = true;
> > +             break;
> > +     case CHIP_RAVEN:
> > +             /* enable S/G on PCO and RV2 */
> > +             if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
> > +                     init_data.flags.gpu_vm_support = true;
> > +             break;
> > +     default:
> > +             break;
> > +     }
>
> It might be a good idea to enable gpu_vm_support independent anyway.
>
> Might be even a good idea to do this in a separate patch.
>
> But either way I'm not an expert on how the hardware works in this area,
> so Acked-by: Christian König <christian.koenig@amd.com> for this series
> either way.
>

Yeah, we can probably just always set the .gpu_vm_support flag if the
asic supports it.  It won't get enabled unless we add GTT as a valid
domain.

Alex


> Regards,
> Christian.
>
> >
> >       if (amdgpu_dc_feature_mask & DC_FBC_MASK)
> >               init_data.flags.fbc_support = true;
>
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^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-01-08 22:23 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-07 21:13 [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2 Alex Deucher
2020-01-07 21:13 ` [PATCH 2/2] drm/amdgpu: enable S/G display for renoir Alex Deucher
2020-01-08  2:48   ` Liu, Aaron
2020-01-08  3:05     ` Deucher, Alexander
2020-01-08  5:42       ` Liu, Aaron
2020-01-08 15:27   ` Harry Wentland
2020-01-08 10:19 ` [PATCH 1/2] drm/amdgpu: enable S/G display on PCO and RV2 Christian König
2020-01-08 22:22   ` Alex Deucher

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