* [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements
@ 2021-07-23 7:05 Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
` (14 more replies)
0 siblings, 15 replies; 27+ messages in thread
From: Lee Shawn C @ 2021-07-23 7:05 UTC (permalink / raw)
To: intel-gfx; +Cc: cooper.chiou, william.tseng, jani.nikula
v2:
- Check for dsc enable and slice count ==1 then allow to
double confirm min cdclk value.
v3:
- Add two patches that fix MIPI DCS backlight control.
Lee Shawn C (7):
drm/i915/dsi: send correct gpio_number on gen11 platform
drm/i915/jsl: program DSI panel GPIOs
drm/i915/dsi: wait for header and payload credit available
drm/i915/dsi: refine send MIPI DCS command sequence
drm/i915: Get proper min cdclk if vDSC enabled
drm/i915/dsi: Retrieve max brightness level from VBT.
drm/i915/dsi: Send proper brightness value via MIPI DCS command
drivers/gpu/drm/i915/display/icl_dsi.c | 50 +++++++++----------
drivers/gpu/drm/i915/display/intel_bios.c | 3 ++
drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++
.../i915/display/intel_dsi_dcs_backlight.c | 15 ++++--
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 46 ++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10 ++++
7 files changed, 102 insertions(+), 33 deletions(-)
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [V3 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
@ 2021-07-23 7:05 ` Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs Lee Shawn C
` (13 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Lee Shawn C @ 2021-07-23 7:05 UTC (permalink / raw)
To: intel-gfx; +Cc: cooper.chiou, william.tseng, jani.nikula
Transfer "gpio_nunmber" instead of "gpio_index" while doing
gpio configuration in icl_exec_gpio().
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index c2a2cd1f84dc..cc93e045a425 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -381,7 +381,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
value = *data++ & 1;
if (DISPLAY_VER(dev_priv) >= 11)
- icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+ icl_exec_gpio(dev_priv, gpio_source, gpio_number, value);
else if (IS_VALLEYVIEW(dev_priv))
vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(dev_priv))
--
2.17.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
@ 2021-07-23 7:05 ` Lee Shawn C
2021-08-10 9:31 ` Jani Nikula
2021-07-23 7:05 ` [Intel-gfx] [V3 3/7] drm/i915/dsi: wait for header and payload credit available Lee Shawn C
` (12 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: Lee Shawn C @ 2021-07-23 7:05 UTC (permalink / raw)
To: intel-gfx; +Cc: cooper.chiou, william.tseng, jani.nikula
DSI driver should have its own implementation to toggle
gpio pins based on GPIO info coming from VBT sequences.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 10 +++++
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index cc93e045a425..dd03e5629ba6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -43,6 +43,7 @@
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_sideband.h"
+#include "intel_de.h"
#define MIPI_TRANSFER_MODE_SHIFT 0
#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
@@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
static void icl_exec_gpio(struct drm_i915_private *dev_priv,
u8 gpio_source, u8 gpio_index, bool value)
{
- drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
+ u32 val;
+
+ switch (gpio_index) {
+ case ICL_GPIO_L_VDDEN_1:
+ val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
+ if (value)
+ val |= PWR_STATE_TARGET;
+ else
+ val &= ~PWR_STATE_TARGET;
+ intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
+ break;
+ case ICL_GPIO_L_BKLTEN_1:
+ val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
+ if (value)
+ val |= BACKLIGHT_ENABLE;
+ else
+ val &= ~BACKLIGHT_ENABLE;
+ intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
+ break;
+ case ICL_GPIO_DDPA_CTRLCLK_1:
+ val = intel_de_read(dev_priv, GPIO(1));
+ if (value)
+ val |= GPIO_CLOCK_VAL_OUT;
+ else
+ val &= ~GPIO_CLOCK_VAL_OUT;
+ val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
+ intel_de_write(dev_priv, GPIO(1), val);
+ break;
+ case ICL_GPIO_DDPA_CTRLDATA_1:
+ val = intel_de_read(dev_priv, GPIO(1));
+ if (value)
+ val |= GPIO_DATA_VAL_OUT;
+ else
+ val &= ~GPIO_DATA_VAL_OUT;
+ val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
+ intel_de_write(dev_priv, GPIO(1), val);
+ break;
+ default:
+ /* TODO: Add support for remaining GPIOs */
+ DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
+ break;
+ }
}
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 943fe485c662..b725234e0e9c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5143,6 +5143,16 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
#define PP_ON REG_BIT(31)
+
+#define _PP_CONTROL_1 0xc7204
+#define _PP_CONTROL_2 0xc7304
+#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+ _PP_CONTROL_2)
+#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
+#define VDD_OVERRIDE_FORCE REG_BIT(3)
+#define BACKLIGHT_ENABLE REG_BIT(2)
+#define PWR_DOWN_ON_RESET REG_BIT(1)
+#define PWR_STATE_TARGET REG_BIT(0)
/*
* Indicates that all dependencies of the panel are on:
*
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [V3 3/7] drm/i915/dsi: wait for header and payload credit available
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs Lee Shawn C
@ 2021-07-23 7:05 ` Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 4/7] drm/i915/dsi: refine send MIPI DCS command sequence Lee Shawn C
` (11 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Lee Shawn C @ 2021-07-23 7:05 UTC (permalink / raw)
To: intel-gfx; +Cc: cooper.chiou, william.tseng, jani.nikula
Driver should wait for free header or payload buffer in FIFO.
It would be good to wait a while for HW to release credit before
give it up to write to HW. Without sending initailize command
sets completely. It would caused MIPI display can't light up properly.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 40 ++++++++++++--------------
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 43ec7fcd3f5d..1780830d9909 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -54,20 +54,28 @@ static int payload_credits_available(struct drm_i915_private *dev_priv,
>> FREE_PLOAD_CREDIT_SHIFT;
}
-static void wait_for_header_credits(struct drm_i915_private *dev_priv,
- enum transcoder dsi_trans)
+static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans, int hdr_credit)
{
if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
- MAX_HEADER_CREDIT, 100))
+ hdr_credit, 100)) {
drm_err(&dev_priv->drm, "DSI header credits not released\n");
+ return false;
+ }
+
+ return true;
}
-static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
- enum transcoder dsi_trans)
+static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans, int payld_credit)
{
if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
- MAX_PLOAD_CREDIT, 100))
+ payld_credit, 100)) {
drm_err(&dev_priv->drm, "DSI payload credits not released\n");
+ return false;
+ }
+
+ return true;
}
static enum transcoder dsi_port_to_transcoder(enum port port)
@@ -90,8 +98,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
/* wait for header/payload credits to be released */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- wait_for_header_credits(dev_priv, dsi_trans);
- wait_for_payload_credits(dev_priv, dsi_trans);
+ wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
+ wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
}
/* send nop DCS command */
@@ -108,7 +116,7 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
/* wait for header credits to be released */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- wait_for_header_credits(dev_priv, dsi_trans);
+ wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
}
/* wait for LP TX in progress bit to be cleared */
@@ -126,18 +134,13 @@ static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
struct intel_dsi *intel_dsi = host->intel_dsi;
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
- int free_credits;
int i, j;
for (i = 0; i < len; i += 4) {
u32 tmp = 0;
- free_credits = payload_credits_available(dev_priv, dsi_trans);
- if (free_credits < 1) {
- drm_err(&dev_priv->drm,
- "Payload credit not available\n");
+ if (!wait_for_payload_credits(dev_priv, dsi_trans, 1))
return false;
- }
for (j = 0; j < min_t(u32, len - i, 4); j++)
tmp |= *data++ << 8 * j;
@@ -155,15 +158,10 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
u32 tmp;
- int free_credits;
/* check if header credit available */
- free_credits = header_credits_available(dev_priv, dsi_trans);
- if (free_credits < 1) {
- drm_err(&dev_priv->drm,
- "send pkt header failed, not enough hdr credits\n");
+ if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
return -1;
- }
tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
--
2.17.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [V3 4/7] drm/i915/dsi: refine send MIPI DCS command sequence
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (2 preceding siblings ...)
2021-07-23 7:05 ` [Intel-gfx] [V3 3/7] drm/i915/dsi: wait for header and payload credit available Lee Shawn C
@ 2021-07-23 7:05 ` Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled Lee Shawn C
` (10 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Lee Shawn C @ 2021-07-23 7:05 UTC (permalink / raw)
To: intel-gfx; +Cc: cooper.chiou, william.tseng, jani.nikula
According to chapter "Sending Commands to the Panel" in bspec #29738
and #49188. If driver try to send DCS long pakcet, we have to program
TX payload register at first. And configure TX header HW register later.
DSC long packet would not be sent properly if we don't follow this
sequence.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 1780830d9909..60413bbf565f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1807,11 +1807,6 @@ static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
if (msg->flags & MIPI_DSI_MSG_USE_LPM)
enable_lpdt = true;
- /* send packet header */
- ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
- if (ret < 0)
- return ret;
-
/* only long packet contains payload */
if (mipi_dsi_packet_format_is_long(msg->type)) {
ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
@@ -1819,6 +1814,11 @@ static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
return ret;
}
+ /* send packet header */
+ ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
+ if (ret < 0)
+ return ret;
+
//TODO: add payload receive code if needed
ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
--
2.17.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (3 preceding siblings ...)
2021-07-23 7:05 ` [Intel-gfx] [V3 4/7] drm/i915/dsi: refine send MIPI DCS command sequence Lee Shawn C
@ 2021-07-23 7:05 ` Lee Shawn C
2021-07-23 7:06 ` Kulkarni, Vandita
2021-07-23 7:05 ` [Intel-gfx] [V3 6/7] drm/i915/dsi: Retrieve max brightness level from VBT Lee Shawn C
` (9 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: Lee Shawn C @ 2021-07-23 7:05 UTC (permalink / raw)
To: intel-gfx; +Cc: cooper.chiou, william.tseng, jani.nikula
VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.
v2:
- Check for dsc enable and slice count ==1 then allow to
double confirm min cdclk value.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 71067a62264d..3e09f6370d27 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2159,6 +2159,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
+ /*
+ * VDSC engine can process only 1 pixel per Cd clock.
+ * In case VDSC is used and max slice count == 1,
+ * max supported pixel clock should be 100% of CD clock.
+ * Then do min_cdclk and pixel clock comparison to get cdclk.
+ */
+ if (crtc_state->dsc.compression_enable &&
+ crtc_state->dsc.slice_count == 1)
+ min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
/*
* HACK. Currently for TGL platforms we calculate
* min_cdclk initially based on pixel_rate divided
--
2.17.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [V3 6/7] drm/i915/dsi: Retrieve max brightness level from VBT.
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (4 preceding siblings ...)
2021-07-23 7:05 ` [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled Lee Shawn C
@ 2021-07-23 7:05 ` Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command Lee Shawn C
` (8 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Lee Shawn C @ 2021-07-23 7:05 UTC (permalink / raw)
To: intel-gfx; +Cc: cooper.chiou, william.tseng, jani.nikula
So far, DCS backlight driver hardcode (0xFF) for max brightness level.
MIPI DCS spec allow max 0xFFFF for set_display_brightness (51h) command.
And VBT brightness precision bits can support 8 ~ 16 bits.
We should set correct precision bits in VBT that meet panel's request.
Driver can refer to this setting then configure max brightness level
in DCS backlight driver properly.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 +++
.../gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 12 +++++++++---
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 5b6922e28ef2..a43cbf35a01d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -483,6 +483,9 @@ parse_lfp_backlight(struct drm_i915_private *i915,
level = 255;
}
i915->vbt.backlight.min_brightness = min_level;
+
+ i915->vbt.backlight.max_brightness_level =
+ (1 << backlight_data->brightness_precision_bits[panel_type]) - 1;
} else {
level = backlight_data->level[panel_type];
i915->vbt.backlight.min_brightness = entry->min_brightness;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 584c14c4cbd0..cd85520d36e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -41,7 +41,7 @@
#define POWER_SAVE_HIGH (3 << 0)
#define POWER_SAVE_OUTDOOR_MODE (4 << 0)
-#define PANEL_PWM_MAX_VALUE 0xFF
+#define PANEL_PWM_MAX_VALUE 0xFFFF
static u32 dcs_get_backlight(struct intel_connector *connector, enum pipe unused)
{
@@ -147,10 +147,16 @@ static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state,
static int dcs_setup_backlight(struct intel_connector *connector,
enum pipe unused)
{
+ struct drm_device *dev = connector->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_panel *panel = &connector->panel;
- panel->backlight.max = PANEL_PWM_MAX_VALUE;
- panel->backlight.level = PANEL_PWM_MAX_VALUE;
+ panel->backlight.max = dev_priv->vbt.backlight.max_brightness_level \
+ ? dev_priv->vbt.backlight.max_brightness_level \
+ : PANEL_PWM_MAX_VALUE;
+ panel->backlight.level = dev_priv->vbt.backlight.max_brightness_level \
+ ? dev_priv->vbt.backlight.max_brightness_level \
+ : PANEL_PWM_MAX_VALUE;
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f99b6c0dd068..210eef301ba6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -712,6 +712,7 @@ struct intel_vbt_data {
struct {
u16 pwm_freq_hz;
+ u16 max_brightness_level;
bool present;
bool active_low_pwm;
u8 min_brightness; /* min_brightness/255 of max */
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (5 preceding siblings ...)
2021-07-23 7:05 ` [Intel-gfx] [V3 6/7] drm/i915/dsi: Retrieve max brightness level from VBT Lee Shawn C
@ 2021-07-23 7:05 ` Lee Shawn C
2021-07-23 11:14 ` kernel test robot
2021-07-26 6:54 ` [Intel-gfx] [v2] " Lee Shawn C
2021-07-23 7:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev3) Patchwork
` (7 subsequent siblings)
14 siblings, 2 replies; 27+ messages in thread
From: Lee Shawn C @ 2021-07-23 7:05 UTC (permalink / raw)
To: intel-gfx; +Cc: cooper.chiou, william.tseng, jani.nikula
Driver has to swap the endian before send brightness level value
to tcon.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index cd85520d36e2..47c1cd704915 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -66,10 +66,9 @@ static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
struct mipi_dsi_device *dsi_device;
- u8 data = level;
+ u16 data = cpu_to_be16(level);
enum port port;
- /* FIXME: Need to take care of 16 bit brightness level */
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
mipi_dsi_dcs_write(dsi_device, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled
2021-07-23 7:05 ` [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled Lee Shawn C
@ 2021-07-23 7:06 ` Kulkarni, Vandita
0 siblings, 0 replies; 27+ messages in thread
From: Kulkarni, Vandita @ 2021-07-23 7:06 UTC (permalink / raw)
To: Lee, Shawn C, intel-gfx; +Cc: Nikula, Jani, Chiou, Cooper, Tseng, William
> -----Original Message-----
> From: Lee, Shawn C <shawn.c.lee@intel.com>
> Sent: Friday, July 23, 2021 12:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; Chiou, Cooper
> <cooper.chiou@intel.com>; Tseng, William <william.tseng@intel.com>; Lee,
> Shawn C <shawn.c.lee@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>
> Subject: [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled
>
> VDSC engine can process only 1 pixel per Cd clock. In case VDSC is used and
> max slice count == 1, max supported pixel clock should be 100% of CD clock.
> Then do min_cdclk and pixel clock comparison to get proper min cdclk.
>
> v2:
> - Check for dsc enable and slice count ==1 then allow to
> double confirm min cdclk value.
LGTM,
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: William Tseng <william.tseng@intel.com>
> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 71067a62264d..3e09f6370d27 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2159,6 +2159,16 @@ int intel_crtc_compute_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> /* Account for additional needs from the planes */
> min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>
> + /*
> + * VDSC engine can process only 1 pixel per Cd clock.
> + * In case VDSC is used and max slice count == 1,
> + * max supported pixel clock should be 100% of CD clock.
> + * Then do min_cdclk and pixel clock comparison to get cdclk.
> + */
> + if (crtc_state->dsc.compression_enable &&
> + crtc_state->dsc.slice_count == 1)
> + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
> +
> /*
> * HACK. Currently for TGL platforms we calculate
> * min_cdclk initially based on pixel_rate divided
> --
> 2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev3)
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (6 preceding siblings ...)
2021-07-23 7:05 ` [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command Lee Shawn C
@ 2021-07-23 7:39 ` Patchwork
2021-07-23 7:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-07-23 7:39 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: MIPI DSI driver enhancements (rev3)
URL : https://patchwork.freedesktop.org/series/92695/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d7af033a52e3 drm/i915/dsi: send correct gpio_number on gen11 platform
0071f18cf3f3 drm/i915/jsl: program DSI panel GPIOs
57d3de727a89 drm/i915/dsi: wait for header and payload credit available
72480625ce94 drm/i915/dsi: refine send MIPI DCS command sequence
0df46fa4d7cc drm/i915: Get proper min cdclk if vDSC enabled
20289018e0a5 drm/i915/dsi: Retrieve max brightness level from VBT.
-:58: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#58: FILE: drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:154:
+ panel->backlight.max = dev_priv->vbt.backlight.max_brightness_level \
-:61: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#61: FILE: drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:157:
+ panel->backlight.level = dev_priv->vbt.backlight.max_brightness_level \
total: 0 errors, 2 warnings, 0 checks, 42 lines checked
86a133132144 drm/i915/dsi: Send proper brightness value via MIPI DCS command
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for MIPI DSI driver enhancements (rev3)
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (7 preceding siblings ...)
2021-07-23 7:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev3) Patchwork
@ 2021-07-23 7:40 ` Patchwork
2021-07-23 8:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-07-23 7:40 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: MIPI DSI driver enhancements (rev3)
URL : https://patchwork.freedesktop.org/series/92695/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: expected unsigned short [usertype] data
+drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: got restricted __be16 [usertype]
+drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: warning: incorrect type in initializer (different base types)
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: expected struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: got struct i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for MIPI DSI driver enhancements (rev3)
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (8 preceding siblings ...)
2021-07-23 7:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-07-23 8:09 ` Patchwork
2021-07-23 12:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-07-23 8:09 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 1909 bytes --]
== Series Details ==
Series: MIPI DSI driver enhancements (rev3)
URL : https://patchwork.freedesktop.org/series/92695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10376 -> Patchwork_20689
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/index.html
Known issues
------------
Here are the changes found in Patchwork_20689 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
Participating hosts (41 -> 35)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u bat-adlp-4 bat-adls-4 bat-adls-3 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10376 -> Patchwork_20689
CI-20190529: 20190529
CI_DRM_10376: 299bd09eafa6bf94ac922867ee0c797f8e569d3b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6147: f3994c2cd99a1acfe991a8cc838a387dcb36598a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20689: 86a133132144cac513321a5e8f05bf48fa3e1c17 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
86a133132144 drm/i915/dsi: Send proper brightness value via MIPI DCS command
20289018e0a5 drm/i915/dsi: Retrieve max brightness level from VBT.
0df46fa4d7cc drm/i915: Get proper min cdclk if vDSC enabled
72480625ce94 drm/i915/dsi: refine send MIPI DCS command sequence
57d3de727a89 drm/i915/dsi: wait for header and payload credit available
0071f18cf3f3 drm/i915/jsl: program DSI panel GPIOs
d7af033a52e3 drm/i915/dsi: send correct gpio_number on gen11 platform
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command
2021-07-23 7:05 ` [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command Lee Shawn C
@ 2021-07-23 11:14 ` kernel test robot
2021-07-26 6:54 ` [Intel-gfx] [v2] " Lee Shawn C
1 sibling, 0 replies; 27+ messages in thread
From: kernel test robot @ 2021-07-23 11:14 UTC (permalink / raw)
To: Lee Shawn C, intel-gfx
Cc: jani.nikula, cooper.chiou, kbuild-all, william.tseng
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Hi Lee,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip v5.14-rc2 next-20210723]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Lee-Shawn-C/MIPI-DSI-driver-enhancements/20210723-150019
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s031-20210723 (attached as .config)
compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/3c3b297d0e553591be7fb6d5b66bb41cf23bff42
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Lee-Shawn-C/MIPI-DSI-driver-enhancements/20210723-150019
git checkout 3c3b297d0e553591be7fb6d5b66bb41cf23bff42
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned short [usertype] data @@ got restricted __be16 [usertype] @@
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: sparse: expected unsigned short [usertype] data
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: sparse: got restricted __be16 [usertype]
vim +69 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
64
65 static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32 level)
66 {
67 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
68 struct mipi_dsi_device *dsi_device;
> 69 u16 data = cpu_to_be16(level);
70 enum port port;
71
72 for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
73 dsi_device = intel_dsi->dsi_hosts[port]->device;
74 mipi_dsi_dcs_write(dsi_device, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
75 &data, sizeof(data));
76 }
77 }
78
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command
@ 2021-07-23 11:14 ` kernel test robot
0 siblings, 0 replies; 27+ messages in thread
From: kernel test robot @ 2021-07-23 11:14 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2639 bytes --]
Hi Lee,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip v5.14-rc2 next-20210723]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Lee-Shawn-C/MIPI-DSI-driver-enhancements/20210723-150019
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s031-20210723 (attached as .config)
compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/3c3b297d0e553591be7fb6d5b66bb41cf23bff42
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Lee-Shawn-C/MIPI-DSI-driver-enhancements/20210723-150019
git checkout 3c3b297d0e553591be7fb6d5b66bb41cf23bff42
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned short [usertype] data @@ got restricted __be16 [usertype] @@
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: sparse: expected unsigned short [usertype] data
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:69:20: sparse: got restricted __be16 [usertype]
vim +69 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
64
65 static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32 level)
66 {
67 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
68 struct mipi_dsi_device *dsi_device;
> 69 u16 data = cpu_to_be16(level);
70 enum port port;
71
72 for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
73 dsi_device = intel_dsi->dsi_hosts[port]->device;
74 mipi_dsi_dcs_write(dsi_device, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
75 &data, sizeof(data));
76 }
77 }
78
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for MIPI DSI driver enhancements (rev3)
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (9 preceding siblings ...)
2021-07-23 8:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-07-23 12:57 ` Patchwork
2021-07-26 6:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev4) Patchwork
` (3 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-07-23 12:57 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30258 bytes --]
== Series Details ==
Series: MIPI DSI driver enhancements (rev3)
URL : https://patchwork.freedesktop.org/series/92695/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10376_full -> Patchwork_20689_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20689_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20689_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20689_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_dc@dc5-dpms:
- shard-kbl: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl1/igt@i915_pm_dc@dc5-dpms.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-skl: [PASS][2] -> [FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s3:
- {shard-rkl}: NOTRUN -> [DMESG-WARN][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- {shard-rkl}: NOTRUN -> [SKIP][5] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-2/igt@i915_pm_rpm@debugfs-forcewake-user.html
* {igt@kms_dsc@basic-dsc-enable}:
- shard-iclb: NOTRUN -> [SKIP][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb3/igt@kms_dsc@basic-dsc-enable.html
Known issues
------------
Here are the changes found in Patchwork_20689_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_import_export@flink:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#750])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-tglb2/igt@drm_import_export@flink.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-tglb2/igt@drm_import_export@flink.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-snb7/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [PASS][10] -> [INCOMPLETE][11] ([i915#155])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-kbl1/igt@gem_eio@in-flight-suspend.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl3/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-glk3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: NOTRUN -> [FAIL][14] ([i915#2842]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][19] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][20] -> [SKIP][21] ([fdo#109271])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2842])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-iclb3/igt@gem_exec_fair@basic-pace@vecs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-iclb: [PASS][24] -> [FAIL][25] ([i915#307])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb6/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][26] ([i915#2658])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3323])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl3/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][28] ([i915#3002]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl7/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][29] ([i915#2724])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-snb7/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@basic-offset:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271]) +267 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl7/igt@gen7_exec_parse@basic-offset.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#1937])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][32] -> [INCOMPLETE][33] ([i915#2782])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-snb6/igt@i915_selftest@live@hangcheck.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][34] -> [FAIL][35] ([i915#2521])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3777])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][39] ([fdo#109271]) +308 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-snb7/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3689])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-tglb5/igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-snb: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +15 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-snb5/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +16 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl8/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +22 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl1/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][45] ([i915#2105])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl7/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271]) +54 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([i915#180]) +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271]) +154 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-snb: [PASS][50] -> [SKIP][51] ([fdo#109271])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-snb5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-snb7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#2346])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#533]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl3/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: NOTRUN -> [INCOMPLETE][55] ([i915#180])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][56] -> [FAIL][57] ([i915#2122])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][58] -> [FAIL][59] ([i915#79])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][60] -> [DMESG-WARN][61] ([i915#180]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][62] ([fdo#111825])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-tglb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#1188])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: NOTRUN -> [DMESG-WARN][66] ([i915#180]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][67] ([i915#265])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][71] -> [FAIL][72] ([fdo#108145] / [i915#265]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl8/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#658]) +5 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][76] -> [SKIP][77] ([fdo#109642] / [fdo#111068] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-iclb2/igt@kms_psr2_su@page_flip.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb8/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][78] -> [SKIP][79] ([fdo#109441]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2437]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl1/igt@kms_writeback@writeback-check-output.html
* igt@sysfs_clients@fair-0:
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl7/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@fair-7:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2994]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl2/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@split-50:
- shard-skl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2994])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl8/igt@sysfs_clients@split-50.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [PASS][84] -> [FAIL][85] ([i915#1731])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl4/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl6/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Possible fixes ####
* igt@drm_import_export@prime:
- shard-kbl: [INCOMPLETE][86] ([i915#2944]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-kbl3/igt@drm_import_export@prime.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl7/igt@drm_import_export@prime.html
* igt@feature_discovery@psr2:
- {shard-rkl}: [SKIP][88] ([i915#658]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@feature_discovery@psr2.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@feature_discovery@psr2.html
* igt@gem_ctx_persistence@engines-hostile@rcs0:
- {shard-rkl}: [FAIL][90] ([i915#2410]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-2/igt@gem_ctx_persistence@engines-hostile@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-1/igt@gem_ctx_persistence@engines-hostile@rcs0.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [FAIL][92] ([i915#2410]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@unwedge-stress:
- {shard-rkl}: [TIMEOUT][94] ([i915#3063]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@gem_eio@unwedge-stress.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_schedule@u-independent@vcs1:
- shard-tglb: [FAIL][96] ([i915#3795]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-tglb7/igt@gem_exec_schedule@u-independent@vcs1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-tglb7/igt@gem_exec_schedule@u-independent@vcs1.html
* igt@gem_exec_suspend@basic-s4-devices:
- {shard-rkl}: [INCOMPLETE][98] ([i915#3810]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-2/igt@gem_exec_suspend@basic-s4-devices.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-1/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [DMESG-WARN][100] ([i915#118] / [i915#95]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-glk2/igt@gem_exec_whisper@basic-queues-all.html
* igt@gem_mmap_gtt@basic-wc:
- {shard-rkl}: [FAIL][102] ([i915#3830]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-2/igt@gem_mmap_gtt@basic-wc.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-1/igt@gem_mmap_gtt@basic-wc.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][104] ([i915#1436] / [i915#716]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl5/igt@gen9_exec_parse@allowed-single.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl10/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][106] ([i915#454]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live@execlists:
- {shard-rkl}: [DMESG-FAIL][108] -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@i915_selftest@live@execlists.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-5/igt@i915_selftest@live@execlists.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- {shard-rkl}: [SKIP][110] ([i915#3721]) -> [PASS][111] +4 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs:
- {shard-rkl}: [FAIL][112] ([i915#3678]) -> [PASS][113] +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [DMESG-WARN][114] ([i915#1982]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl9/igt@kms_color@pipe-a-ctm-0-5.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl2/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_color@pipe-c-ctm-max:
- {shard-rkl}: [SKIP][116] ([i915#1149] / [i915#1849]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-5/igt@kms_color@pipe-c-ctm-max.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@kms_color@pipe-c-ctm-max.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
- shard-skl: [FAIL][118] ([i915#3444]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-onscreen:
- {shard-rkl}: [SKIP][120] ([fdo#112022]) -> [PASS][121] +5 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html
* igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
- {shard-rkl}: [SKIP][122] ([fdo#111825]) -> [PASS][123] +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
* igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
- shard-skl: [FAIL][124] ([i915#3451]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl8/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl9/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
- {shard-rkl}: [SKIP][126] ([fdo#111314]) -> [PASS][127] +2 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][128] ([i915#180]) -> [PASS][129] +6 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
- shard-apl: [DMESG-WARN][130] ([i915#180]) -> [PASS][131] +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- {shard-rkl}: [SKIP][132] ([i915#1849]) -> [PASS][133] +17 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: [FAIL][134] ([i915#53]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant:
- shard-iclb: [SKIP][136] ([fdo#109278]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-iclb2/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb8/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][138] ([fdo#108145] / [i915#265]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- {shard-rkl}: [SKIP][140] ([i915#3558]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-rkl-1/igt@kms_plane_multiple@atomic-pipe-a-tiling-x.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-a-tiling-x.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][142] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10376/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20689/index.html
[-- Attachment #1.2: Type: text/html, Size: 33387 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [v2] drm/i915/dsi: Send proper brightness value via MIPI DCS command
2021-07-23 7:05 ` [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command Lee Shawn C
2021-07-23 11:14 ` kernel test robot
@ 2021-07-26 6:54 ` Lee Shawn C
1 sibling, 0 replies; 27+ messages in thread
From: Lee Shawn C @ 2021-07-26 6:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Cooper Chiou, William Tseng
Driver has to swap the endian before send brightness level value
to tcon.
v2: Use __be16 instead of u16 to fix sparse warning.
Reported-by: kernel test robot <lkp@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index cd85520d36e2..71c2adfa8931 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -66,10 +66,9 @@ static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
struct mipi_dsi_device *dsi_device;
- u8 data = level;
+ __be16 data = cpu_to_be16(level);
enum port port;
- /* FIXME: Need to take care of 16 bit brightness level */
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
mipi_dsi_dcs_write(dsi_device, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev4)
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (10 preceding siblings ...)
2021-07-23 12:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-07-26 6:56 ` Patchwork
2021-07-26 6:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-07-26 6:56 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: MIPI DSI driver enhancements (rev4)
URL : https://patchwork.freedesktop.org/series/92695/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
77529e9e348e drm/i915/dsi: send correct gpio_number on gen11 platform
1994193a9893 drm/i915/jsl: program DSI panel GPIOs
4a2d5040a99d drm/i915/dsi: wait for header and payload credit available
cb2493d12c0d drm/i915/dsi: refine send MIPI DCS command sequence
fef2d31a1c41 drm/i915: Get proper min cdclk if vDSC enabled
b62bfc065334 drm/i915/dsi: Retrieve max brightness level from VBT.
-:58: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#58: FILE: drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:154:
+ panel->backlight.max = dev_priv->vbt.backlight.max_brightness_level \
-:61: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#61: FILE: drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:157:
+ panel->backlight.level = dev_priv->vbt.backlight.max_brightness_level \
total: 0 errors, 2 warnings, 0 checks, 42 lines checked
4956eeca561c drm/i915/dsi: Send proper brightness value via MIPI DCS command
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for MIPI DSI driver enhancements (rev4)
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (11 preceding siblings ...)
2021-07-26 6:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev4) Patchwork
@ 2021-07-26 6:57 ` Patchwork
2021-07-26 7:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-26 9:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-07-26 6:57 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: MIPI DSI driver enhancements (rev4)
URL : https://patchwork.freedesktop.org/series/92695/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1900:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1900:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1900:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: expected struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: got struct i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1402:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write8' - different lock contexts for basic block
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for MIPI DSI driver enhancements (rev4)
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (12 preceding siblings ...)
2021-07-26 6:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-07-26 7:27 ` Patchwork
2021-07-26 9:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-07-26 7:27 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3872 bytes --]
== Series Details ==
Series: MIPI DSI driver enhancements (rev4)
URL : https://patchwork.freedesktop.org/series/92695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10392 -> Patchwork_20703
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/index.html
Known issues
------------
Here are the changes found in Patchwork_20703 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-apl-guc/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@i915_hangman@error-state-basic:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][2] ([i915#1610])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-apl-guc/igt@i915_hangman@error-state-basic.html
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> [FAIL][3] ([i915#2426] / [i915#3363])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-apl-guc/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@gtt:
- {fi-tgl-dsi}: [DMESG-FAIL][4] ([i915#2927]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/fi-tgl-dsi/igt@i915_selftest@live@gtt.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-tgl-dsi/igt@i915_selftest@live@gtt.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-FAIL][6] ([i915#165]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (40 -> 35)
------------------------------
Additional (1): fi-apl-guc
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adls-4 bat-adls-3 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10392 -> Patchwork_20703
CI-20190529: 20190529
CI_DRM_10392: 5ed997f5d0de6cbd2379499e7c132410df93922d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6149: 34ff2cf2bc352dce691593db803389fe0eb2be03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20703: 4956eeca561c8f9feffd3ed5bd56d4037e4ab432 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4956eeca561c drm/i915/dsi: Send proper brightness value via MIPI DCS command
b62bfc065334 drm/i915/dsi: Retrieve max brightness level from VBT.
fef2d31a1c41 drm/i915: Get proper min cdclk if vDSC enabled
cb2493d12c0d drm/i915/dsi: refine send MIPI DCS command sequence
4a2d5040a99d drm/i915/dsi: wait for header and payload credit available
1994193a9893 drm/i915/jsl: program DSI panel GPIOs
77529e9e348e drm/i915/dsi: send correct gpio_number on gen11 platform
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/index.html
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_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for MIPI DSI driver enhancements (rev4)
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
` (13 preceding siblings ...)
2021-07-26 7:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-07-26 9:24 ` Patchwork
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-07-26 9:24 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
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== Series Details ==
Series: MIPI DSI driver enhancements (rev4)
URL : https://patchwork.freedesktop.org/series/92695/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10392_full -> Patchwork_20703_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20703_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20703_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20703_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf_pmu@multi-client@vcs0:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl9/igt@perf_pmu@multi-client@vcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl3/igt@perf_pmu@multi-client@vcs0.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane@pixel-format-source-clamping@pipe-a-planes:
- {shard-rkl}: [SKIP][3] ([i915#3558]) -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-5/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
* igt@runner@aborted:
- {shard-rkl}: ([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8]) ([i915#3002] / [i915#3728] / [i915#3811]) -> ([FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12]) ([i915#3002] / [i915#3811])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-1/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-2/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-2/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-6/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-2/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-2/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-5/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_20703_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-snb2/igt@gem_ctx_persistence@engines-hostile-preempt.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2846])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-glk5/igt@gem_exec_fair@basic-deadline.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-glk6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-glk5/igt@gem_exec_fair@basic-none-solo@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-glk3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2842])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][21] -> [SKIP][22] ([i915#2190])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-tglb2/igt@gem_huc_copy@huc-copy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-skl: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl10/igt@gem_pread@exhaustion.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271]) +218 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl1/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271]) +25 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl7/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][26] ([i915#3002])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl7/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][27] ([i915#2724])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-snb7/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][28] -> [DMESG-WARN][29] ([i915#1436] / [i915#716])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@drm-resources-equal:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#579])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb6/igt@i915_pm_rpm@drm-resources-equal.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: NOTRUN -> [INCOMPLETE][31] ([i915#2782])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][32] -> [DMESG-WARN][33] ([i915#180]) +4 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-apl3/igt@i915_suspend@sysfs-reader.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl1/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][34] ([i915#3722])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][36] ([i915#3763])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][37] ([fdo#111615])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb6/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271]) +102 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl7/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3689])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb2/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-snb: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +23 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl4/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +7 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl10/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +15 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl7/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][45] ([i915#1319])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl1/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][46] ([i915#2105])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl2/igt@kms_content_protection@uevent.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][47] ([fdo#109271]) +407 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-snb7/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
- shard-skl: [PASS][48] -> [FAIL][49] ([i915#2122])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#111825]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl7/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][53] ([i915#265])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][54] -> [FAIL][55] ([fdo#108145] / [i915#265]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant:
- shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#109278])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-iclb8/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb2/igt@kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][58] ([fdo#108145] / [i915#265])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +4 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl10/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_su@page_flip:
- shard-kbl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl7/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][63] -> [SKIP][64] ([fdo#109441]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb5/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][65] -> [FAIL][66] ([i915#1542])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-glk6/igt@perf@polling-parameterized.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-glk9/igt@perf@polling-parameterized.html
- shard-skl: [PASS][67] -> [FAIL][68] ([i915#1542])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl7/igt@perf@polling-parameterized.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl2/igt@perf@polling-parameterized.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2994]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl2/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@split-25:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2994])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl10/igt@sysfs_clients@split-25.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-skl: NOTRUN -> [FAIL][71] ([i915#1731]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl7/igt@sysfs_heartbeat_interval@mixed@vcs0.html
#### Possible fixes ####
* igt@gem_ctx_persistence@engines-hang@bcs0:
- {shard-rkl}: [FAIL][72] ([i915#2410]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-1/igt@gem_ctx_persistence@engines-hang@bcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [TIMEOUT][74] ([i915#3063]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@unwedge-stress:
- {shard-rkl}: [TIMEOUT][76] ([i915#3063]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-6/igt@gem_eio@unwedge-stress.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][78] ([i915#2846]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][80] ([i915#2842]) -> [PASS][81] +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][82] ([i915#2842] / [i915#3468]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][84] ([i915#2842]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- {shard-rkl}: [FAIL][86] ([i915#2842]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-1/igt@gem_exec_fair@basic-pace@vcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-5/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [SKIP][88] ([fdo#109271]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][90] ([i915#2842]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-iclb: [FAIL][92] ([i915#2849]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-independent@vecs0:
- {shard-rkl}: [FAIL][94] ([i915#3795]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-2/igt@gem_exec_schedule@u-independent@vecs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-2/igt@gem_exec_schedule@u-independent@vecs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: [WARN][96] ([i915#2681]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-tglb7/igt@i915_pm_rc6_residency@rc6-fence.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- {shard-rkl}: [SKIP][98] ([i915#3638]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-5/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs:
- {shard-rkl}: [FAIL][100] ([i915#3678]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-5/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs.html
* igt@kms_color@pipe-b-ctm-blue-to-red:
- shard-skl: [DMESG-WARN][102] ([i915#1982]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl1/igt@kms_color@pipe-b-ctm-blue-to-red.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl6/igt@kms_color@pipe-b-ctm-blue-to-red.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][104] ([i915#180]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@d-edp1:
- shard-tglb: [FAIL][106] ([i915#79]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank@d-edp1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank@d-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl: [INCOMPLETE][108] ([i915#198]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-kbl: [INCOMPLETE][110] ([i915#155]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-kbl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][112] ([i915#2122]) -> [PASS][113] +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
- {shard-rkl}: [SKIP][114] ([i915#3558]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-5/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant:
- shard-iclb: [SKIP][116] ([fdo#109278]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-iclb2/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb5/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_cursor@pipe-a-overlay-size-256:
- {shard-rkl}: [SKIP][120] ([i915#1845]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-5/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][122] ([fdo#109441]) -> [PASS][123] +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][124] ([i915#588]) -> [SKIP][125] ([i915#658])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: [FAIL][126] ([i915#3722]) -> [FAIL][127] ([i915#1888] / [i915#3722])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-iclb: [SKIP][128] ([i915#658]) -> [SKIP][129] ([i915#2920]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-iclb4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-iclb: [SKIP][130] ([i915#2920]) -> [SKIP][131] ([i915#658]) +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@runner@aborted:
- shard-apl: ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140]) ([i915#180] / [i915#3002] / [i915#3363])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-apl6/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-apl7/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-apl6/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-apl8/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl7/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl3/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl6/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl1/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-apl8/igt@runner@aborted.html
- shard-skl: [FAIL][141] ([i915#3002] / [i915#3363]) -> ([FAIL][142], [FAIL][143], [FAIL][144]) ([i915#1436] / [i915#3002] / [i915#3363])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl10/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl2/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl7/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
2021-07-23 7:05 ` [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs Lee Shawn C
@ 2021-08-10 9:31 ` Jani Nikula
2021-08-10 10:04 ` Lee, Shawn C
0 siblings, 1 reply; 27+ messages in thread
From: Jani Nikula @ 2021-08-10 9:31 UTC (permalink / raw)
To: Lee Shawn C, intel-gfx
Cc: ville.syrjala, vandita.kulkarni, cooper.chiou, william.tseng,
Lee Shawn C
On Fri, 23 Jul 2021, Lee Shawn C <shawn.c.lee@intel.com> wrote:
> DSI driver should have its own implementation to toggle
> gpio pins based on GPIO info coming from VBT sequences.
Why?
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: William Tseng <william.tseng@intel.com>
> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++
> 2 files changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> index cc93e045a425..dd03e5629ba6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> @@ -43,6 +43,7 @@
> #include "intel_display_types.h"
> #include "intel_dsi.h"
> #include "intel_sideband.h"
> +#include "intel_de.h"
>
> #define MIPI_TRANSFER_MODE_SHIFT 0
> #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
> @@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
> static void icl_exec_gpio(struct drm_i915_private *dev_priv,
> u8 gpio_source, u8 gpio_index, bool value)
> {
> - drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
> + u32 val;
> +
> + switch (gpio_index) {
> + case ICL_GPIO_L_VDDEN_1:
> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
> + if (value)
> + val |= PWR_STATE_TARGET;
> + else
> + val &= ~PWR_STATE_TARGET;
> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
All the PPS access should be in intel_pps.[ch] and protected with the
pps mutex.
> + break;
> + case ICL_GPIO_L_BKLTEN_1:
> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
> + if (value)
> + val |= BACKLIGHT_ENABLE;
> + else
> + val &= ~BACKLIGHT_ENABLE;
> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
> + break;
> + case ICL_GPIO_DDPA_CTRLCLK_1:
> + val = intel_de_read(dev_priv, GPIO(1));
> + if (value)
> + val |= GPIO_CLOCK_VAL_OUT;
> + else
> + val &= ~GPIO_CLOCK_VAL_OUT;
> + val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
> + intel_de_write(dev_priv, GPIO(1), val);
> + break;
> + case ICL_GPIO_DDPA_CTRLDATA_1:
> + val = intel_de_read(dev_priv, GPIO(1));
> + if (value)
> + val |= GPIO_DATA_VAL_OUT;
> + else
> + val &= ~GPIO_DATA_VAL_OUT;
> + val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
> + intel_de_write(dev_priv, GPIO(1), val);
> + break;
> + default:
> + /* TODO: Add support for remaining GPIOs */
> + DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
> + break;
> + }
> }
>
> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 943fe485c662..b725234e0e9c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5143,6 +5143,16 @@ enum {
> #define _PP_STATUS 0x61200
> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
> #define PP_ON REG_BIT(31)
> +
> +#define _PP_CONTROL_1 0xc7204
> +#define _PP_CONTROL_2 0xc7304
> +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
> + _PP_CONTROL_2)
> +#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
> +#define VDD_OVERRIDE_FORCE REG_BIT(3)
> +#define BACKLIGHT_ENABLE REG_BIT(2)
> +#define PWR_DOWN_ON_RESET REG_BIT(1)
> +#define PWR_STATE_TARGET REG_BIT(0)
These are all duplicate defines for existing PP_CONTROL() registers and
macros.
> /*
> * Indicates that all dependencies of the panel are on:
> *
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
2021-08-10 9:31 ` Jani Nikula
@ 2021-08-10 10:04 ` Lee, Shawn C
2021-08-10 11:53 ` Jani Nikula
2021-08-11 1:50 ` Lee, Shawn C
0 siblings, 2 replies; 27+ messages in thread
From: Lee, Shawn C @ 2021-08-10 10:04 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
Cc: ville.syrjala, Kulkarni, Vandita, Chiou, Cooper, Tseng, William
On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>On Fri, 23 Jul 2021, Lee Shawn C <shawn.c.lee@intel.com> wrote:
>> DSI driver should have its own implementation to toggle gpio pins
>> based on GPIO info coming from VBT sequences.
>
>Why?
>
Without this change, we are not able to control gpio signal output to
meet MIPI panel's requirement for power on/off sequence.
>>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Cc: Cooper Chiou <cooper.chiou@intel.com>
>> Cc: William Tseng <william.tseng@intel.com>
>> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
>> drivers/gpu/drm/i915/i915_reg.h | 10 +++++
>> 2 files changed, 53 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>> index cc93e045a425..dd03e5629ba6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>> @@ -43,6 +43,7 @@
>> #include "intel_display_types.h"
>> #include "intel_dsi.h"
>> #include "intel_sideband.h"
>> +#include "intel_de.h"
>>
>> #define MIPI_TRANSFER_MODE_SHIFT 0
>> #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
>> @@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private
>> *dev_priv, static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>> u8 gpio_source, u8 gpio_index, bool value) {
>> - drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
>> + u32 val;
>> +
>> + switch (gpio_index) {
>> + case ICL_GPIO_L_VDDEN_1:
>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>> + if (value)
>> + val |= PWR_STATE_TARGET;
>> + else
>> + val &= ~PWR_STATE_TARGET;
>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>
>All the PPS access should be in intel_pps.[ch] and protected with the pps mutex.
>
OK! We will move icl_exec_gpio() into intel_pps.c and use pps mutex to protect it.
>> + break;
>> + case ICL_GPIO_L_BKLTEN_1:
>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>> + if (value)
>> + val |= BACKLIGHT_ENABLE;
>> + else
>> + val &= ~BACKLIGHT_ENABLE;
>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>> + break;
>> + case ICL_GPIO_DDPA_CTRLCLK_1:
>> + val = intel_de_read(dev_priv, GPIO(1));
>> + if (value)
>> + val |= GPIO_CLOCK_VAL_OUT;
>> + else
>> + val &= ~GPIO_CLOCK_VAL_OUT;
>> + val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
>> + intel_de_write(dev_priv, GPIO(1), val);
>> + break;
>> + case ICL_GPIO_DDPA_CTRLDATA_1:
>> + val = intel_de_read(dev_priv, GPIO(1));
>> + if (value)
>> + val |= GPIO_DATA_VAL_OUT;
>> + else
>> + val &= ~GPIO_DATA_VAL_OUT;
>> + val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
>> + intel_de_write(dev_priv, GPIO(1), val);
>> + break;
>> + default:
>> + /* TODO: Add support for remaining GPIOs */
>> + DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
>> + break;
>> + }
>> }
>>
>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8
>> *data) diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 943fe485c662..b725234e0e9c
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5143,6 +5143,16 @@ enum {
>> #define _PP_STATUS 0x61200
>> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
>> #define PP_ON REG_BIT(31)
>> +
>> +#define _PP_CONTROL_1 0xc7204
>> +#define _PP_CONTROL_2 0xc7304
>> +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
>> + _PP_CONTROL_2)
>> +#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
>> +#define VDD_OVERRIDE_FORCE REG_BIT(3)
>> +#define BACKLIGHT_ENABLE REG_BIT(2)
>> +#define PWR_DOWN_ON_RESET REG_BIT(1)
>> +#define PWR_STATE_TARGET REG_BIT(0)
>
>These are all duplicate defines for existing PP_CONTROL() registers and macros.
I found this patch on drm-tip branch and removed PP_CONTRL() defines.
https://patchwork.freedesktop.org/patch/291095/
Best regards,
Shawn
>
>> /*
>> * Indicates that all dependencies of the panel are on:
>> *
>
>--
>Jani Nikula, Intel Open Source Graphics Center
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
2021-08-10 10:04 ` Lee, Shawn C
@ 2021-08-10 11:53 ` Jani Nikula
2021-08-11 1:50 ` Lee, Shawn C
1 sibling, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2021-08-10 11:53 UTC (permalink / raw)
To: 20210723070548.29315-3-shawn.c.lee, intel-gfx
Cc: ville.syrjala, Kulkarni, Vandita, Chiou, Cooper, Tseng, William
On Tue, 10 Aug 2021, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
> On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>On Fri, 23 Jul 2021, Lee Shawn C <shawn.c.lee@intel.com> wrote:
>>> DSI driver should have its own implementation to toggle gpio pins
>>> based on GPIO info coming from VBT sequences.
>>
>>Why?
>>
>
> Without this change, we are not able to control gpio signal output to
> meet MIPI panel's requirement for power on/off sequence.
>
>>>
>>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>>> Cc: Cooper Chiou <cooper.chiou@intel.com>
>>> Cc: William Tseng <william.tseng@intel.com>
>>> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
>>> drivers/gpu/drm/i915/i915_reg.h | 10 +++++
>>> 2 files changed, 53 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>> index cc93e045a425..dd03e5629ba6 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>> @@ -43,6 +43,7 @@
>>> #include "intel_display_types.h"
>>> #include "intel_dsi.h"
>>> #include "intel_sideband.h"
>>> +#include "intel_de.h"
>>>
>>> #define MIPI_TRANSFER_MODE_SHIFT 0
>>> #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
>>> @@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private
>>> *dev_priv, static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>>> u8 gpio_source, u8 gpio_index, bool value) {
>>> - drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
>>> + u32 val;
>>> +
>>> + switch (gpio_index) {
>>> + case ICL_GPIO_L_VDDEN_1:
>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>> + if (value)
>>> + val |= PWR_STATE_TARGET;
>>> + else
>>> + val &= ~PWR_STATE_TARGET;
>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>
>>All the PPS access should be in intel_pps.[ch] and protected with the pps mutex.
>>
>
> OK! We will move icl_exec_gpio() into intel_pps.c and use pps mutex to protect it.
>
>>> + break;
>>> + case ICL_GPIO_L_BKLTEN_1:
>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>> + if (value)
>>> + val |= BACKLIGHT_ENABLE;
>>> + else
>>> + val &= ~BACKLIGHT_ENABLE;
>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>> + break;
>>> + case ICL_GPIO_DDPA_CTRLCLK_1:
>>> + val = intel_de_read(dev_priv, GPIO(1));
>>> + if (value)
>>> + val |= GPIO_CLOCK_VAL_OUT;
>>> + else
>>> + val &= ~GPIO_CLOCK_VAL_OUT;
>>> + val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
>>> + intel_de_write(dev_priv, GPIO(1), val);
>>> + break;
>>> + case ICL_GPIO_DDPA_CTRLDATA_1:
>>> + val = intel_de_read(dev_priv, GPIO(1));
>>> + if (value)
>>> + val |= GPIO_DATA_VAL_OUT;
>>> + else
>>> + val &= ~GPIO_DATA_VAL_OUT;
>>> + val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
>>> + intel_de_write(dev_priv, GPIO(1), val);
>>> + break;
>>> + default:
>>> + /* TODO: Add support for remaining GPIOs */
>>> + DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
>>> + break;
>>> + }
>>> }
>>>
>>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8
>>> *data) diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h index 943fe485c662..b725234e0e9c
>>> 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -5143,6 +5143,16 @@ enum {
>>> #define _PP_STATUS 0x61200
>>> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
>>> #define PP_ON REG_BIT(31)
>>> +
>>> +#define _PP_CONTROL_1 0xc7204
>>> +#define _PP_CONTROL_2 0xc7304
>>> +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
>>> + _PP_CONTROL_2)
>>> +#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
>>> +#define VDD_OVERRIDE_FORCE REG_BIT(3)
>>> +#define BACKLIGHT_ENABLE REG_BIT(2)
>>> +#define PWR_DOWN_ON_RESET REG_BIT(1)
>>> +#define PWR_STATE_TARGET REG_BIT(0)
>>
>>These are all duplicate defines for existing PP_CONTROL() registers and macros.
>
> I found this patch on drm-tip branch and removed PP_CONTRL() defines.
> https://patchwork.freedesktop.org/patch/291095/
Look for PP_CONTROL(), not ICL_PP_CONTROL().
>
> Best regards,
> Shawn
>
>>
>>> /*
>>> * Indicates that all dependencies of the panel are on:
>>> *
>>
>>--
>>Jani Nikula, Intel Open Source Graphics Center
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
2021-08-10 10:04 ` Lee, Shawn C
2021-08-10 11:53 ` Jani Nikula
@ 2021-08-11 1:50 ` Lee, Shawn C
2021-08-11 14:10 ` Lee, Shawn C
2021-08-12 12:22 ` Jani Nikula
1 sibling, 2 replies; 27+ messages in thread
From: Lee, Shawn C @ 2021-08-11 1:50 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
Cc: ville.syrjala, Kulkarni, Vandita, Chiou, Cooper, Tseng, William
On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>On Tue, 10 Aug 2021, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
>> On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>On Fri, 23 Jul 2021, Lee Shawn C <shawn.c.lee@intel.com> wrote:
>>>> DSI driver should have its own implementation to toggle gpio pins
>>>> based on GPIO info coming from VBT sequences.
>>>
>>>Why?
>>>
>>
>> Without this change, we are not able to control gpio signal output to
>> meet MIPI panel's requirement for power on/off sequence.
>>
>>>>
>>>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>>>> Cc: Cooper Chiou <cooper.chiou@intel.com>
>>>> Cc: William Tseng <william.tseng@intel.com>
>>>> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
>>>> drivers/gpu/drm/i915/i915_reg.h | 10 +++++
>>>> 2 files changed, 53 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>> index cc93e045a425..dd03e5629ba6 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>> @@ -43,6 +43,7 @@
>>>> #include "intel_display_types.h"
>>>> #include "intel_dsi.h"
>>>> #include "intel_sideband.h"
>>>> +#include "intel_de.h"
>>>>
>>>> #define MIPI_TRANSFER_MODE_SHIFT 0
>>>> #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
>>>> @@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private
>>>> *dev_priv, static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>>>> u8 gpio_source, u8 gpio_index, bool value) {
>>>> - drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
>>>> + u32 val;
>>>> +
>>>> + switch (gpio_index) {
>>>> + case ICL_GPIO_L_VDDEN_1:
>>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>>> + if (value)
>>>> + val |= PWR_STATE_TARGET;
>>>> + else
>>>> + val &= ~PWR_STATE_TARGET;
>>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>>
>>>All the PPS access should be in intel_pps.[ch] and protected with the pps mutex.
>>>
>>
>> OK! We will move icl_exec_gpio() into intel_pps.c and use pps mutex to protect it.
>>
>>>> + break;
>>>> + case ICL_GPIO_L_BKLTEN_1:
>>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>>> + if (value)
>>>> + val |= BACKLIGHT_ENABLE;
>>>> + else
>>>> + val &= ~BACKLIGHT_ENABLE;
>>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>>> + break;
>>>> + case ICL_GPIO_DDPA_CTRLCLK_1:
>>>> + val = intel_de_read(dev_priv, GPIO(1));
>>>> + if (value)
>>>> + val |= GPIO_CLOCK_VAL_OUT;
>>>> + else
>>>> + val &= ~GPIO_CLOCK_VAL_OUT;
>>>> + val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
>>>> + intel_de_write(dev_priv, GPIO(1), val);
>>>> + break;
>>>> + case ICL_GPIO_DDPA_CTRLDATA_1:
>>>> + val = intel_de_read(dev_priv, GPIO(1));
>>>> + if (value)
>>>> + val |= GPIO_DATA_VAL_OUT;
>>>> + else
>>>> + val &= ~GPIO_DATA_VAL_OUT;
>>>> + val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
>>>> + intel_de_write(dev_priv, GPIO(1), val);
>>>> + break;
>>>> + default:
>>>> + /* TODO: Add support for remaining GPIOs */
>>>> + DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
>>>> + break;
>>>> + }
>>>> }
>>>>
>>>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8
>>>> *data) diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>>> b/drivers/gpu/drm/i915/i915_reg.h index 943fe485c662..b725234e0e9c
>>>> 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -5143,6 +5143,16 @@ enum {
>>>> #define _PP_STATUS 0x61200
>>>> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
>>>> #define PP_ON REG_BIT(31)
>>>> +
>>>> +#define _PP_CONTROL_1 0xc7204
>>>> +#define _PP_CONTROL_2 0xc7304
>>>> +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
>>>> + _PP_CONTROL_2)
>>>> +#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
>>>> +#define VDD_OVERRIDE_FORCE REG_BIT(3)
>>>> +#define BACKLIGHT_ENABLE REG_BIT(2)
>>>> +#define PWR_DOWN_ON_RESET REG_BIT(1)
>>>> +#define PWR_STATE_TARGET REG_BIT(0)
>>>
>>>These are all duplicate defines for existing PP_CONTROL() registers and macros.
>>
>> I found this patch on drm-tip branch and removed PP_CONTRL() defines.
>> https://patchwork.freedesktop.org/patch/291095/
>
>Look for PP_CONTROL(), not ICL_PP_CONTROL().
>
PP_CONTROL() mapped to PPS_BASE (0x61200) register. It looks to me driver may need
a new define like _MMIO_PPS that map to PCH_PPS_BASE (0xC7200). What do you think?
>
>>
>> Best regards,
>> Shawn
>>
>>>
>>>> /*
>>>> * Indicates that all dependencies of the panel are on:
>>>> *
>>>
>>>--
>>>Jani Nikula, Intel Open Source Graphics Center
>>>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
2021-08-11 1:50 ` Lee, Shawn C
@ 2021-08-11 14:10 ` Lee, Shawn C
2021-08-12 14:52 ` Lee, Shawn C
2021-08-12 12:22 ` Jani Nikula
1 sibling, 1 reply; 27+ messages in thread
From: Lee, Shawn C @ 2021-08-11 14:10 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
Cc: ville.syrjala, Kulkarni, Vandita, Chiou, Cooper, Tseng, William
On Tue, 11 Aug 2021, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
>On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>On Tue, 10 Aug 2021, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
>>> On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>>On Fri, 23 Jul 2021, Lee Shawn C <shawn.c.lee@intel.com> wrote:
>>>>> DSI driver should have its own implementation to toggle gpio pins
>>>>> based on GPIO info coming from VBT sequences.
>>>>
>>>>Why?
>>>>
>>>
>>> Without this change, we are not able to control gpio signal output to
>>> meet MIPI panel's requirement for power on/off sequence.
>>>
>>>>>
>>>>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>>>>> Cc: Cooper Chiou <cooper.chiou@intel.com>
>>>>> Cc: William Tseng <william.tseng@intel.com>
>>>>> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
>>>>> drivers/gpu/drm/i915/i915_reg.h | 10 +++++
>>>>> 2 files changed, 53 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>> index cc93e045a425..dd03e5629ba6 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>> @@ -43,6 +43,7 @@
>>>>> #include "intel_display_types.h"
>>>>> #include "intel_dsi.h"
>>>>> #include "intel_sideband.h"
>>>>> +#include "intel_de.h"
>>>>>
>>>>> #define MIPI_TRANSFER_MODE_SHIFT 0
>>>>> #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 @@ -354,7 +355,48 @@ static
>>>>> void bxt_exec_gpio(struct drm_i915_private *dev_priv, static void
>>>>> icl_exec_gpio(struct drm_i915_private *dev_priv,
>>>>> u8 gpio_source, u8 gpio_index, bool value) {
>>>>> - drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
>>>>> + u32 val;
>>>>> +
>>>>> + switch (gpio_index) {
>>>>> + case ICL_GPIO_L_VDDEN_1:
>>>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>>>> + if (value)
>>>>> + val |= PWR_STATE_TARGET;
>>>>> + else
>>>>> + val &= ~PWR_STATE_TARGET;
>>>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>>>
>>>>All the PPS access should be in intel_pps.[ch] and protected with the pps mutex.
>>>>
>>>
>>> OK! We will move icl_exec_gpio() into intel_pps.c and use pps mutex to protect it.
>>>
Just my two cents. All the MIPI DSI sequences are about panel power on, off and initialize.
Refer to intel_dp_aux_xfer(). How about to add intel_pps_lock/unlock in intel_dsi_vbt_exec_sequence()
to protect every MIPI sequence? And we can keep these code in this file for MIPI DSI only.
Best regards,
Shawn
>>>>> + break;
>>>>> + case ICL_GPIO_L_BKLTEN_1:
>>>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>>>> + if (value)
>>>>> + val |= BACKLIGHT_ENABLE;
>>>>> + else
>>>>> + val &= ~BACKLIGHT_ENABLE;
>>>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>>>> + break;
>>>>> + case ICL_GPIO_DDPA_CTRLCLK_1:
>>>>> + val = intel_de_read(dev_priv, GPIO(1));
>>>>> + if (value)
>>>>> + val |= GPIO_CLOCK_VAL_OUT;
>>>>> + else
>>>>> + val &= ~GPIO_CLOCK_VAL_OUT;
>>>>> + val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
>>>>> + intel_de_write(dev_priv, GPIO(1), val);
>>>>> + break;
>>>>> + case ICL_GPIO_DDPA_CTRLDATA_1:
>>>>> + val = intel_de_read(dev_priv, GPIO(1));
>>>>> + if (value)
>>>>> + val |= GPIO_DATA_VAL_OUT;
>>>>> + else
>>>>> + val &= ~GPIO_DATA_VAL_OUT;
>>>>> + val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
>>>>> + intel_de_write(dev_priv, GPIO(1), val);
>>>>> + break;
>>>>> + default:
>>>>> + /* TODO: Add support for remaining GPIOs */
>>>>> + DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
>>>>> + break;
>>>>> + }
>>>>> }
>>>>>
>>>>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const
>>>>> u8
>>>>> *data) diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>>>> b/drivers/gpu/drm/i915/i915_reg.h index 943fe485c662..b725234e0e9c
>>>>> 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>> @@ -5143,6 +5143,16 @@ enum {
>>>>> #define _PP_STATUS 0x61200
>>>>> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
>>>>> #define PP_ON REG_BIT(31)
>>>>> +
>>>>> +#define _PP_CONTROL_1 0xc7204
>>>>> +#define _PP_CONTROL_2 0xc7304
>>>>> +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
>>>>> + _PP_CONTROL_2)
>>>>> +#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
>>>>> +#define VDD_OVERRIDE_FORCE REG_BIT(3)
>>>>> +#define BACKLIGHT_ENABLE REG_BIT(2)
>>>>> +#define PWR_DOWN_ON_RESET REG_BIT(1)
>>>>> +#define PWR_STATE_TARGET REG_BIT(0)
>>>>
>>>>These are all duplicate defines for existing PP_CONTROL() registers and macros.
>>>
>>> I found this patch on drm-tip branch and removed PP_CONTRL() defines.
>>> https://patchwork.freedesktop.org/patch/291095/
>>
>>Look for PP_CONTROL(), not ICL_PP_CONTROL().
>>
>
>PP_CONTROL() mapped to PPS_BASE (0x61200) register. It looks to me driver may need a new define like _MMIO_PPS that map to PCH_PPS_BASE (0xC7200). What do you think?
>
>>
>>>
>>> Best regards,
>>> Shawn
>>>
>>>>
>>>>> /*
>>>>> * Indicates that all dependencies of the panel are on:
>>>>> *
>>>>
>>>>--
>>>>Jani Nikula, Intel Open Source Graphics Center
>>>>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
2021-08-11 1:50 ` Lee, Shawn C
2021-08-11 14:10 ` Lee, Shawn C
@ 2021-08-12 12:22 ` Jani Nikula
1 sibling, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2021-08-12 12:22 UTC (permalink / raw)
To: 20210723070548.29315-3-shawn.c.lee, intel-gfx
Cc: ville.syrjala, Kulkarni, Vandita, Chiou, Cooper, Tseng, William
On Wed, 11 Aug 2021, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
> On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>On Tue, 10 Aug 2021, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
>>> On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>>On Fri, 23 Jul 2021, Lee Shawn C <shawn.c.lee@intel.com> wrote:
>>>>> DSI driver should have its own implementation to toggle gpio pins
>>>>> based on GPIO info coming from VBT sequences.
>>>>
>>>>Why?
>>>>
>>>
>>> Without this change, we are not able to control gpio signal output to
>>> meet MIPI panel's requirement for power on/off sequence.
>>>
>>>>>
>>>>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>>>>> Cc: Cooper Chiou <cooper.chiou@intel.com>
>>>>> Cc: William Tseng <william.tseng@intel.com>
>>>>> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
>>>>> drivers/gpu/drm/i915/i915_reg.h | 10 +++++
>>>>> 2 files changed, 53 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>> index cc93e045a425..dd03e5629ba6 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>> @@ -43,6 +43,7 @@
>>>>> #include "intel_display_types.h"
>>>>> #include "intel_dsi.h"
>>>>> #include "intel_sideband.h"
>>>>> +#include "intel_de.h"
>>>>>
>>>>> #define MIPI_TRANSFER_MODE_SHIFT 0
>>>>> #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
>>>>> @@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private
>>>>> *dev_priv, static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>>>>> u8 gpio_source, u8 gpio_index, bool value) {
>>>>> - drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
>>>>> + u32 val;
>>>>> +
>>>>> + switch (gpio_index) {
>>>>> + case ICL_GPIO_L_VDDEN_1:
>>>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>>>> + if (value)
>>>>> + val |= PWR_STATE_TARGET;
>>>>> + else
>>>>> + val &= ~PWR_STATE_TARGET;
>>>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>>>
>>>>All the PPS access should be in intel_pps.[ch] and protected with the pps mutex.
>>>>
>>>
>>> OK! We will move icl_exec_gpio() into intel_pps.c and use pps mutex to protect it.
>>>
>>>>> + break;
>>>>> + case ICL_GPIO_L_BKLTEN_1:
>>>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>>>> + if (value)
>>>>> + val |= BACKLIGHT_ENABLE;
>>>>> + else
>>>>> + val &= ~BACKLIGHT_ENABLE;
>>>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>>>> + break;
>>>>> + case ICL_GPIO_DDPA_CTRLCLK_1:
>>>>> + val = intel_de_read(dev_priv, GPIO(1));
>>>>> + if (value)
>>>>> + val |= GPIO_CLOCK_VAL_OUT;
>>>>> + else
>>>>> + val &= ~GPIO_CLOCK_VAL_OUT;
>>>>> + val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
>>>>> + intel_de_write(dev_priv, GPIO(1), val);
>>>>> + break;
>>>>> + case ICL_GPIO_DDPA_CTRLDATA_1:
>>>>> + val = intel_de_read(dev_priv, GPIO(1));
>>>>> + if (value)
>>>>> + val |= GPIO_DATA_VAL_OUT;
>>>>> + else
>>>>> + val &= ~GPIO_DATA_VAL_OUT;
>>>>> + val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
>>>>> + intel_de_write(dev_priv, GPIO(1), val);
>>>>> + break;
>>>>> + default:
>>>>> + /* TODO: Add support for remaining GPIOs */
>>>>> + DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
>>>>> + break;
>>>>> + }
>>>>> }
>>>>>
>>>>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8
>>>>> *data) diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>>>> b/drivers/gpu/drm/i915/i915_reg.h index 943fe485c662..b725234e0e9c
>>>>> 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>> @@ -5143,6 +5143,16 @@ enum {
>>>>> #define _PP_STATUS 0x61200
>>>>> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
>>>>> #define PP_ON REG_BIT(31)
>>>>> +
>>>>> +#define _PP_CONTROL_1 0xc7204
>>>>> +#define _PP_CONTROL_2 0xc7304
>>>>> +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
>>>>> + _PP_CONTROL_2)
>>>>> +#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
>>>>> +#define VDD_OVERRIDE_FORCE REG_BIT(3)
>>>>> +#define BACKLIGHT_ENABLE REG_BIT(2)
>>>>> +#define PWR_DOWN_ON_RESET REG_BIT(1)
>>>>> +#define PWR_STATE_TARGET REG_BIT(0)
>>>>
>>>>These are all duplicate defines for existing PP_CONTROL() registers and macros.
>>>
>>> I found this patch on drm-tip branch and removed PP_CONTRL() defines.
>>> https://patchwork.freedesktop.org/patch/291095/
>>
>>Look for PP_CONTROL(), not ICL_PP_CONTROL().
>>
>
> PP_CONTROL() mapped to PPS_BASE (0x61200) register. It looks to me driver may need
> a new define like _MMIO_PPS that map to PCH_PPS_BASE (0xC7200). What do you think?
This is covered with:
/* Panel power sequencing */
#define PPS_BASE 0x61200
#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
#define PCH_PPS_BASE 0xC7200
#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
PPS_BASE + (reg) + \
(pps_idx) * 0x100)
and dev_priv->pps_mmio_base being initialized in intel_pps_setup().
BR,
Jani.
>
>>
>>>
>>> Best regards,
>>> Shawn
>>>
>>>>
>>>>> /*
>>>>> * Indicates that all dependencies of the panel are on:
>>>>> *
>>>>
>>>>--
>>>>Jani Nikula, Intel Open Source Graphics Center
>>>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
2021-08-11 14:10 ` Lee, Shawn C
@ 2021-08-12 14:52 ` Lee, Shawn C
0 siblings, 0 replies; 27+ messages in thread
From: Lee, Shawn C @ 2021-08-12 14:52 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
Cc: ville.syrjala, Kulkarni, Vandita, Chiou, Cooper, Tseng, William
On Thu, 12 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>On Wed, 11 Aug 2021, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
>> On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>On Tue, 10 Aug 2021, "Lee, Shawn C" <shawn.c.lee@intel.com> wrote:
>>>> On Tue, 10 Aug 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>>>On Fri, 23 Jul 2021, Lee Shawn C <shawn.c.lee@intel.com> wrote:
>>>>>> DSI driver should have its own implementation to toggle gpio pins
>>>>>> based on GPIO info coming from VBT sequences.
>>>>>
>>>>>Why?
>>>>>
>>>>
>>>> Without this change, we are not able to control gpio signal output to
>>>> meet MIPI panel's requirement for power on/off sequence.
>>>>
>>>>>>
>>>>>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>>>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>>>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>>>>>> Cc: Cooper Chiou <cooper.chiou@intel.com>
>>>>>> Cc: William Tseng <william.tseng@intel.com>
>>>>>> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
>>>>>> drivers/gpu/drm/i915/i915_reg.h | 10 +++++
>>>>>> 2 files changed, 53 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>>> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>>> index cc93e045a425..dd03e5629ba6 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
>>>>>> @@ -43,6 +43,7 @@
>>>>>> #include "intel_display_types.h"
>>>>>> #include "intel_dsi.h"
>>>>>> #include "intel_sideband.h"
>>>>>> +#include "intel_de.h"
>>>>>>
>>>>>> #define MIPI_TRANSFER_MODE_SHIFT 0
>>>>>> #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
>>>>>> @@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private
>>>>>> *dev_priv, static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>>>>>> u8 gpio_source, u8 gpio_index, bool value) {
>>>>>> - drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
>>>>>> + u32 val;
>>>>>> +
>>>>>> + switch (gpio_index) {
>>>>>> + case ICL_GPIO_L_VDDEN_1:
>>>>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>>>>> + if (value)
>>>>>> + val |= PWR_STATE_TARGET;
>>>>>> + else
>>>>>> + val &= ~PWR_STATE_TARGET;
>>>>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>>>>
>>>>>All the PPS access should be in intel_pps.[ch] and protected with the pps mutex.
>>>>>
>>>>
>>>> OK! We will move icl_exec_gpio() into intel_pps.c and use pps mutex to protect it.
>>>>
>>>>>> + break;
>>>>>> + case ICL_GPIO_L_BKLTEN_1:
>>>>>> + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
>>>>>> + if (value)
>>>>>> + val |= BACKLIGHT_ENABLE;
>>>>>> + else
>>>>>> + val &= ~BACKLIGHT_ENABLE;
>>>>>> + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
>>>>>> + break;
>>>>>> + case ICL_GPIO_DDPA_CTRLCLK_1:
>>>>>> + val = intel_de_read(dev_priv, GPIO(1));
>>>>>> + if (value)
>>>>>> + val |= GPIO_CLOCK_VAL_OUT;
>>>>>> + else
>>>>>> + val &= ~GPIO_CLOCK_VAL_OUT;
>>>>>> + val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
>>>>>> + intel_de_write(dev_priv, GPIO(1), val);
>>>>>> + break;
>>>>>> + case ICL_GPIO_DDPA_CTRLDATA_1:
>>>>>> + val = intel_de_read(dev_priv, GPIO(1));
>>>>>> + if (value)
>>>>>> + val |= GPIO_DATA_VAL_OUT;
>>>>>> + else
>>>>>> + val &= ~GPIO_DATA_VAL_OUT;
>>>>>> + val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
>>>>>> + intel_de_write(dev_priv, GPIO(1), val);
>>>>>> + break;
>>>>>> + default:
>>>>>> + /* TODO: Add support for remaining GPIOs */
>>>>>> + DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
>>>>>> + break;
>>>>>> + }
>>>>>> }
>>>>>>
>>>>>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8
>>>>>> *data) diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>>>>> b/drivers/gpu/drm/i915/i915_reg.h index 943fe485c662..b725234e0e9c
>>>>>> 100644
>>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>>> @@ -5143,6 +5143,16 @@ enum {
>>>>>> #define _PP_STATUS 0x61200
>>>>>> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
>>>>>> #define PP_ON REG_BIT(31)
>>>>>> +
>>>>>> +#define _PP_CONTROL_1 0xc7204
>>>>>> +#define _PP_CONTROL_2 0xc7304
>>>>>> +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
>>>>>> + _PP_CONTROL_2)
>>>>>> +#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
>>>>>> +#define VDD_OVERRIDE_FORCE REG_BIT(3)
>>>>>> +#define BACKLIGHT_ENABLE REG_BIT(2)
>>>>>> +#define PWR_DOWN_ON_RESET REG_BIT(1)
>>>>>> +#define PWR_STATE_TARGET REG_BIT(0)
>>>>>
>>>>>These are all duplicate defines for existing PP_CONTROL() registers and macros.
>>>>
>>>> I found this patch on drm-tip branch and removed PP_CONTRL() defines.
>>>> https://patchwork.freedesktop.org/patch/291095/
>>>
>>>Look for PP_CONTROL(), not ICL_PP_CONTROL().
>>>
>>
>> PP_CONTROL() mapped to PPS_BASE (0x61200) register. It looks to me driver may need
>> a new define like _MMIO_PPS that map to PCH_PPS_BASE (0xC7200). What do you think?
>
>This is covered with:
>
>/* Panel power sequencing */
>#define PPS_BASE 0x61200
>#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
>#define PCH_PPS_BASE 0xC7200
>
>#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
> PPS_BASE + (reg) + \
> (pps_idx) * 0x100)
>
>and dev_priv->pps_mmio_base being initialized in intel_pps_setup().
>
>BR,
>Jani.
>
PP_CONTROL() is able to control via different pps_mmio_base. I will update this patch
to remove redundant defines.
Best regards,
Shawn
>>
>>>
>>>>
>>>> Best regards,
>>>> Shawn
>>>>
>>>>>
>>>>>> /*
>>>>>> * Indicates that all dependencies of the panel are on:
>>>>>> *
>>>>>
>>>>>--
>>>>>Jani Nikula, Intel Open Source Graphics Center
>>>>>
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2021-08-12 14:52 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs Lee Shawn C
2021-08-10 9:31 ` Jani Nikula
2021-08-10 10:04 ` Lee, Shawn C
2021-08-10 11:53 ` Jani Nikula
2021-08-11 1:50 ` Lee, Shawn C
2021-08-11 14:10 ` Lee, Shawn C
2021-08-12 14:52 ` Lee, Shawn C
2021-08-12 12:22 ` Jani Nikula
2021-07-23 7:05 ` [Intel-gfx] [V3 3/7] drm/i915/dsi: wait for header and payload credit available Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 4/7] drm/i915/dsi: refine send MIPI DCS command sequence Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled Lee Shawn C
2021-07-23 7:06 ` Kulkarni, Vandita
2021-07-23 7:05 ` [Intel-gfx] [V3 6/7] drm/i915/dsi: Retrieve max brightness level from VBT Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command Lee Shawn C
2021-07-23 11:14 ` kernel test robot
2021-07-23 11:14 ` kernel test robot
2021-07-26 6:54 ` [Intel-gfx] [v2] " Lee Shawn C
2021-07-23 7:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev3) Patchwork
2021-07-23 7:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-23 8:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-23 12:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-26 6:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev4) Patchwork
2021-07-26 6:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-26 7:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-26 9:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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