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* [PATCH] drm/amdgpu: correct reference clock value on vega10
@ 2017-10-11  8:48 Wang, Ken
       [not found] ` <CY1PR12MB0474780D27899B282A97EE988C4A0-1s8aH8ViOEcpMFOGHKGq/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 12+ messages in thread
From: Wang, Ken @ 2017-10-11  8:48 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Deucher, Alexander


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From: Ken Wang <Ken.Wang-5C7GfCeVMHo@public.gmane.org>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..a510c8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -279,10 +279,8 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 }
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
-       if (adev->asic_type == CHIP_VEGA10)
-               return adev->clock.spll.reference_freq/4;
-       else
-               return adev->clock.spll.reference_freq;
+       /* return the value in Khz instead of 10Khz*/
+       return adev->clock.spll.reference_freq * 10;
 }


--
2.7.4


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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* Re: [PATCH] drm/amdgpu: correct reference clock value on vega10
       [not found] ` <CY1PR12MB0474780D27899B282A97EE988C4A0-1s8aH8ViOEcpMFOGHKGq/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-10-11 13:30   ` Alex Deucher
       [not found]     ` <CADnq5_N0Nw5ZzDaqq5iwBrCKEhfC8eZPTUBxMw-vqCefy1sA4g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
  0 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2017-10-11 13:30 UTC (permalink / raw)
  To: Wang, Ken; +Cc: Deucher, Alexander, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

On Wed, Oct 11, 2017 at 4:48 AM, Wang, Ken <Ken.Wang@amd.com> wrote:
> From: Ken Wang <Ken.Wang@amd.com>
>
> Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
> Signed-off-by: Ken Wang <Ken.Wang@amd.com>

NAK.  We use 10khz units for all other asics.  We already multiply
this by 10 in amdgpu_kms.c before sending it to userspace:
        /* return all clocks in KHz */
        dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;

Just return adev->clock.spll.reference_freq.

Alex


> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7839677..a510c8c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -279,10 +279,8 @@ static void soc15_init_golden_registers(struct
> amdgpu_device *adev)
>  }
>  static u32 soc15_get_xclk(struct amdgpu_device *adev)
>  {
> -       if (adev->asic_type == CHIP_VEGA10)
> -               return adev->clock.spll.reference_freq/4;
> -       else
> -               return adev->clock.spll.reference_freq;
> +       /* return the value in Khz instead of 10Khz*/
> +       return adev->clock.spll.reference_freq * 10;
>  }
>
>
> --
> 2.7.4
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] drm/amdgpu: correct reference clock value on vega10
       [not found]     ` <CADnq5_N0Nw5ZzDaqq5iwBrCKEhfC8eZPTUBxMw-vqCefy1sA4g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-10-12  2:41       ` Wang, Ken
  0 siblings, 0 replies; 12+ messages in thread
From: Wang, Ken @ 2017-10-12  2:41 UTC (permalink / raw)
  To: Alex Deucher; +Cc: Deucher, Alexander, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 1970 bytes --]

got it, I will send another patch for reviewing.

________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Wednesday, October 11, 2017 9:30:01 PM
To: Wang, Ken
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: correct reference clock value on vega10

On Wed, Oct 11, 2017 at 4:48 AM, Wang, Ken <Ken.Wang-5C7GfCeVMHo@public.gmane.org> wrote:
> From: Ken Wang <Ken.Wang-5C7GfCeVMHo@public.gmane.org>
>
> Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
> Signed-off-by: Ken Wang <Ken.Wang-5C7GfCeVMHo@public.gmane.org>

NAK.  We use 10khz units for all other asics.  We already multiply
this by 10 in amdgpu_kms.c before sending it to userspace:
        /* return all clocks in KHz */
        dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;

Just return adev->clock.spll.reference_freq.

Alex


> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7839677..a510c8c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -279,10 +279,8 @@ static void soc15_init_golden_registers(struct
> amdgpu_device *adev)
>  }
>  static u32 soc15_get_xclk(struct amdgpu_device *adev)
>  {
> -       if (adev->asic_type == CHIP_VEGA10)
> -               return adev->clock.spll.reference_freq/4;
> -       else
> -               return adev->clock.spll.reference_freq;
> +       /* return the value in Khz instead of 10Khz*/
> +       return adev->clock.spll.reference_freq * 10;
>  }
>
>
> --
> 2.7.4
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>

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_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: correct reference clock value on vega10
       [not found] ` <1507776036-20726-1-git-send-email-Ken.Wang-5C7GfCeVMHo@public.gmane.org>
@ 2017-10-12  2:41   ` Deucher, Alexander
  0 siblings, 0 replies; 12+ messages in thread
From: Deucher, Alexander @ 2017-10-12  2:41 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wang, Ken

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Ken.Wang@amd.com
> Sent: Wednesday, October 11, 2017 10:41 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wang, Ken
> Subject: [PATCH] drm/amdgpu: correct reference clock value on vega10
> 
> From: Ken Wang <Ken.Wang@amd.com>
> 
> Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
> Signed-off-by: Ken Wang <Ken.Wang@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7839677..88d5498 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -279,10 +279,7 @@ static void soc15_init_golden_registers(struct
> amdgpu_device *adev)
>  }
>  static u32 soc15_get_xclk(struct amdgpu_device *adev)
>  {
> -	if (adev->asic_type == CHIP_VEGA10)
> -		return adev->clock.spll.reference_freq/4;
> -	else
> -		return adev->clock.spll.reference_freq;
> +	return adev->clock.spll.reference_freq;
>  }
> 
> 
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu: correct reference clock value on vega10
@ 2017-10-12  2:40 Ken.Wang-5C7GfCeVMHo
       [not found] ` <1507776036-20726-1-git-send-email-Ken.Wang-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 12+ messages in thread
From: Ken.Wang-5C7GfCeVMHo @ 2017-10-12  2:40 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang

From: Ken Wang <Ken.Wang@amd.com>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..88d5498 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -279,10 +279,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 }
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
-	if (adev->asic_type == CHIP_VEGA10)
-		return adev->clock.spll.reference_freq/4;
-	else
-		return adev->clock.spll.reference_freq;
+	return adev->clock.spll.reference_freq;
 }
 
 
-- 
2.7.4

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu: correct reference clock value on vega10
@ 2017-10-11  8:44 Ken.Wang-5C7GfCeVMHo
  0 siblings, 0 replies; 12+ messages in thread
From: Ken.Wang-5C7GfCeVMHo @ 2017-10-11  8:44 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang

From: Ken Wang <Ken.Wang@amd.com>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..a510c8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -279,10 +279,8 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 }
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
-	if (adev->asic_type == CHIP_VEGA10)
-		return adev->clock.spll.reference_freq/4;
-	else
-		return adev->clock.spll.reference_freq;
+	/* return the value in Khz instead of 10Khz*/
+	return adev->clock.spll.reference_freq * 10;
 }
 
 
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* RE: [PATCH] drm/amdgpu: correct reference clock value on vega10
       [not found] ` <1506674119-19979-1-git-send-email-Ken.Wang-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-30  3:11   ` Zhu, Rex
  0 siblings, 0 replies; 12+ messages in thread
From: Zhu, Rex @ 2017-09-30  3:11 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wang, Ken

Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com>

Best Regards
Rex
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Ken.Wang@amd.com
Sent: Friday, September 29, 2017 4:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken
Subject: [PATCH] drm/amdgpu: correct reference clock value on vega10

From: Ken Wang <Ken.Wang@amd.com>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)  static u32 soc15_get_xclk(struct amdgpu_device *adev)  {
 	if (adev->asic_type == CHIP_VEGA10)
-		return adev->clock.spll.reference_freq/4;
+		return 27000;
 	else
 		return adev->clock.spll.reference_freq;  }
--
2.7.4

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* Re: [PATCH] drm/amdgpu: correct reference clock value on vega10
       [not found] ` <1506670965-19065-1-git-send-email-ken.wang-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-29 12:32   ` Alex Deucher
  0 siblings, 0 replies; 12+ messages in thread
From: Alex Deucher @ 2017-09-29 12:32 UTC (permalink / raw)
  To: Wang, Ken; +Cc: amd-gfx list

On Fri, Sep 29, 2017 at 3:42 AM,  <ken.wang@amd.com> wrote:
> From: Ken Wang <Ken.Wang@amd.com>
>
> Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
> Signed-off-by: Ken Wang <Ken.Wang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7839677..631b1e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
>  static u32 soc15_get_xclk(struct amdgpu_device *adev)
>  {
>         if (adev->asic_type == CHIP_VEGA10)
> -               return adev->clock.spll.reference_freq/4;
> +               return 27000;

Why do we need to change this?  Is the vbios table wrong?  See
amdgpu_atomfirmware_get_clock_info().

Alex

>         else
>                 return adev->clock.spll.reference_freq;
>  }
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu: correct reference clock value on vega10
@ 2017-09-29  8:38 Ken.Wang-5C7GfCeVMHo
  0 siblings, 0 replies; 12+ messages in thread
From: Ken.Wang-5C7GfCeVMHo @ 2017-09-29  8:38 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang

From: Ken Wang <Ken.Wang@amd.com>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
 	if (adev->asic_type == CHIP_VEGA10)
-		return adev->clock.spll.reference_freq/4;
+		return 27000;
 	else
 		return adev->clock.spll.reference_freq;
 }
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu: correct reference clock value on vega10
@ 2017-09-29  8:35 Ken.Wang-5C7GfCeVMHo
       [not found] ` <1506674119-19979-1-git-send-email-Ken.Wang-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 12+ messages in thread
From: Ken.Wang-5C7GfCeVMHo @ 2017-09-29  8:35 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang

From: Ken Wang <Ken.Wang@amd.com>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
 	if (adev->asic_type == CHIP_VEGA10)
-		return adev->clock.spll.reference_freq/4;
+		return 27000;
 	else
 		return adev->clock.spll.reference_freq;
 }
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu: correct reference clock value on vega10
@ 2017-09-29  8:14 Ken.Wang-5C7GfCeVMHo
  0 siblings, 0 replies; 12+ messages in thread
From: Ken.Wang-5C7GfCeVMHo @ 2017-09-29  8:14 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang

From: Ken Wang <Ken.Wang@amd.com>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
 	if (adev->asic_type == CHIP_VEGA10)
-		return adev->clock.spll.reference_freq/4;
+		return 27000;
 	else
 		return adev->clock.spll.reference_freq;
 }
-- 
2.7.4

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu: correct reference clock value on vega10
@ 2017-09-29  7:42 ken.wang-5C7GfCeVMHo
       [not found] ` <1506670965-19065-1-git-send-email-ken.wang-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 12+ messages in thread
From: ken.wang-5C7GfCeVMHo @ 2017-09-29  7:42 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang

From: Ken Wang <Ken.Wang@amd.com>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
 	if (adev->asic_type == CHIP_VEGA10)
-		return adev->clock.spll.reference_freq/4;
+		return 27000;
 	else
 		return adev->clock.spll.reference_freq;
 }
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-10-12  2:41 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
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2017-10-11  8:48 [PATCH] drm/amdgpu: correct reference clock value on vega10 Wang, Ken
     [not found] ` <CY1PR12MB0474780D27899B282A97EE988C4A0-1s8aH8ViOEcpMFOGHKGq/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-10-11 13:30   ` Alex Deucher
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2017-10-12  2:41       ` Wang, Ken
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2017-10-12  2:40 Ken.Wang-5C7GfCeVMHo
     [not found] ` <1507776036-20726-1-git-send-email-Ken.Wang-5C7GfCeVMHo@public.gmane.org>
2017-10-12  2:41   ` Deucher, Alexander
2017-10-11  8:44 Ken.Wang-5C7GfCeVMHo
2017-09-29  8:38 Ken.Wang-5C7GfCeVMHo
2017-09-29  8:35 Ken.Wang-5C7GfCeVMHo
     [not found] ` <1506674119-19979-1-git-send-email-Ken.Wang-5C7GfCeVMHo@public.gmane.org>
2017-09-30  3:11   ` Zhu, Rex
2017-09-29  8:14 Ken.Wang-5C7GfCeVMHo
2017-09-29  7:42 ken.wang-5C7GfCeVMHo
     [not found] ` <1506670965-19065-1-git-send-email-ken.wang-5C7GfCeVMHo@public.gmane.org>
2017-09-29 12:32   ` Alex Deucher

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