[Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn

[Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn

[Anusha Srivatsa]

No functional changes. The series is more of a prep series
for the mid_cdclk_config series:
https://patchwork.freedesktop.org/series/109694/

Main change:
 - Change usage of "crawler" and "squasher". Use crawling and
squashing instead.
 - Handle bot hsquash and cralw similar in terms of checking
if the platform supports them or not. With the changes introduced,
both are a display feature flag.
 - Move code from bxt_set_cdclk() to make it more modularized
and easy to read and understand.

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Anusha Srivatsa (4):
  drm/i915/display: Change terminology for cdclk actions
  drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
  drm/i915/display: Move chunks of code out of bxt_set_cdclk()
  drm/i915/display: Move squash_ctl register programming to its own
    function

 drivers/gpu/drm/i915/display/intel_cdclk.c | 80 ++++++++++++----------
 drivers/gpu/drm/i915/i915_drv.h            |  1 +
 drivers/gpu/drm/i915/i915_pci.c            |  1 +
 drivers/gpu/drm/i915/intel_device_info.h   |  1 +
 4 files changed, 48 insertions(+), 35 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions

[Anusha Srivatsa]

No functional changes. Changing terminolgy in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad401357ab66..0f5add2fc51b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squasher(struct drm_i915_private *i915)
+static bool has_cdclk_squash(struct drm_i915_private *i915)
 {
 	return IS_DG2(i915);
 }
@@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (has_cdclk_squasher(dev_priv))
+	if (has_cdclk_squash(dev_priv))
 		squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
 	if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	else
 		clock = cdclk;
 
-	if (has_cdclk_squasher(dev_priv)) {
+	if (has_cdclk_squash(dev_priv)) {
 		u32 squash_ctl = 0;
 
 		if (waveform)
@@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	expected = skl_cdclk_decimal(cdclk);
 
 	/* Figure out what CD2X divider we should be using for this cdclk */
-	if (has_cdclk_squasher(dev_priv))
+	if (has_cdclk_squash(dev_priv))
 		clock = dev_priv->display.cdclk.hw.vco / 2;
 	else
 		clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
 	 * the moment all platforms with squasher use a fixed cd2x
 	 * divider.
 	 */
-	if (!has_cdclk_squasher(dev_priv))
+	if (!has_cdclk_squash(dev_priv))
 		return false;
 
 	return a->cdclk != b->cdclk &&
@@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
 	 * the moment all platforms with squasher use a fixed cd2x
 	 * divider.
 	 */
-	if (has_cdclk_squasher(dev_priv))
+	if (has_cdclk_squash(dev_priv))
 		return false;
 
 	return a->cdclk != b->cdclk &&
@@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 				   &old_cdclk_state->actual,
 				   &new_cdclk_state->actual)) {
 		drm_dbg_kms(&dev_priv->drm,
-			    "Can change cdclk via squasher\n");
+			    "Can change cdclk via squashing\n");
 	} else if (intel_cdclk_can_crawl(dev_priv,
 					 &old_cdclk_state->actual,
 					 &new_cdclk_state->actual)) {
 		drm_dbg_kms(&dev_priv->drm,
-			    "Can change cdclk via crawl\n");
+			    "Can change cdclk via crawling\n");
 	} else if (pipe != INVALID_PIPE) {
 		new_cdclk_state->pipe = pipe;
 
-- 
2.25.1

[Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

[Anusha Srivatsa]

Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++----------
 drivers/gpu/drm/i915/i915_drv.h            |  1 +
 drivers/gpu/drm/i915/i915_pci.c            |  1 +
 drivers/gpu/drm/i915/intel_device_info.h   |  1 +
 4 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0f5add2fc51b..45babbc6290f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squash(struct drm_i915_private *i915)
-{
-	return IS_DG2(i915);
-}
-
 struct intel_cdclk_vals {
 	u32 cdclk;
 	u16 refclk;
@@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (has_cdclk_squash(dev_priv))
+	if (HAS_CDCLK_SQUASH(dev_priv))
 		squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
 	if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	else
 		clock = cdclk;
 
-	if (has_cdclk_squash(dev_priv)) {
+	if (HAS_CDCLK_SQUASH(dev_priv)) {
 		u32 squash_ctl = 0;
 
 		if (waveform)
@@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	expected = skl_cdclk_decimal(cdclk);
 
 	/* Figure out what CD2X divider we should be using for this cdclk */
-	if (has_cdclk_squash(dev_priv))
+	if (HAS_CDCLK_SQUASH(dev_priv))
 		clock = dev_priv->display.cdclk.hw.vco / 2;
 	else
 		clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
 	 * the moment all platforms with squasher use a fixed cd2x
 	 * divider.
 	 */
-	if (!has_cdclk_squash(dev_priv))
+	if (!HAS_CDCLK_SQUASH(dev_priv))
 		return false;
 
 	return a->cdclk != b->cdclk &&
@@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
 	 * the moment all platforms with squasher use a fixed cd2x
 	 * divider.
 	 */
-	if (has_cdclk_squash(dev_priv))
+	if (HAS_CDCLK_SQUASH(dev_priv))
 		return false;
 
 	return a->cdclk != b->cdclk &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7b8eb9d4117..db51050e3ba2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 19bf5ef6a20d..a88e1439a426 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
 	.has_guc_deprivilege = 1, \
 	.has_heci_pxp = 1, \
 	.has_media_ratio_mode = 1, \
+	.display.has_cdclk_squash = 1, \
 	.__runtime.platform_engine_mask = \
 		BIT(RCS0) | BIT(BCS0) | \
 		BIT(VECS0) | BIT(VECS1) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index cdf78728dcad..67d8759c802c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ enum intel_ppgtt_type {
 	/* Keep in alphabetical order */ \
 	func(cursor_needs_physical); \
 	func(has_cdclk_crawl); \
+	func(has_cdclk_squash); \
 	func(has_ddi); \
 	func(has_dp_mst); \
 	func(has_dsb); \
-- 
2.25.1

Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

[Balasubramani Vivekanandan]

On 20.10.2022 17:20, Anusha Srivatsa wrote:
> Driver had discrepancy in how cdclk squash and crawl support
> were checked. Like crawl, add squash as a 1 bit feature flag
> to the display section of DG2.
> 
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++----------
>  drivers/gpu/drm/i915/i915_drv.h            |  1 +
>  drivers/gpu/drm/i915/i915_pci.c            |  1 +
>  drivers/gpu/drm/i915/intel_device_info.h   |  1 +
>  4 files changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0f5add2fc51b..45babbc6290f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>  	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
>  
> -static bool has_cdclk_squash(struct drm_i915_private *i915)
> -{
> -	return IS_DG2(i915);
> -}
> -
>  struct intel_cdclk_vals {
>  	u32 cdclk;
>  	u16 refclk;
> @@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> -	if (has_cdclk_squash(dev_priv))
> +	if (HAS_CDCLK_SQUASH(dev_priv))
>  		squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>  
>  	if (squash_ctl & CDCLK_SQUASH_ENABLE) {
> @@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	else
>  		clock = cdclk;
>  
> -	if (has_cdclk_squash(dev_priv)) {
> +	if (HAS_CDCLK_SQUASH(dev_priv)) {
>  		u32 squash_ctl = 0;
>  
>  		if (waveform)
> @@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	expected = skl_cdclk_decimal(cdclk);
>  
>  	/* Figure out what CD2X divider we should be using for this cdclk */
> -	if (has_cdclk_squash(dev_priv))
> +	if (HAS_CDCLK_SQUASH(dev_priv))
>  		clock = dev_priv->display.cdclk.hw.vco / 2;
>  	else
>  		clock = dev_priv->display.cdclk.hw.cdclk;
> @@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
>  	 * the moment all platforms with squasher use a fixed cd2x
>  	 * divider.
>  	 */
> -	if (!has_cdclk_squash(dev_priv))
> +	if (!HAS_CDCLK_SQUASH(dev_priv))
>  		return false;
>  
>  	return a->cdclk != b->cdclk &&
> @@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
>  	 * the moment all platforms with squasher use a fixed cd2x
>  	 * divider.
>  	 */
> -	if (has_cdclk_squash(dev_priv))
> +	if (HAS_CDCLK_SQUASH(dev_priv))
>  		return false;
>  
>  	return a->cdclk != b->cdclk &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d7b8eb9d4117..db51050e3ba2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>  
>  #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
> +#define HAS_CDCLK_SQUASH(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
>  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 19bf5ef6a20d..a88e1439a426 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
>  	.has_guc_deprivilege = 1, \
>  	.has_heci_pxp = 1, \
>  	.has_media_ratio_mode = 1, \
> +	.display.has_cdclk_squash = 1, \

Shouldn't this line be under dg2_info definition and not here?

Regards,
Bala

>  	.__runtime.platform_engine_mask = \
>  		BIT(RCS0) | BIT(BCS0) | \
>  		BIT(VECS0) | BIT(VECS1) | \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index cdf78728dcad..67d8759c802c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -180,6 +180,7 @@ enum intel_ppgtt_type {
>  	/* Keep in alphabetical order */ \
>  	func(cursor_needs_physical); \
>  	func(has_cdclk_crawl); \
> +	func(has_cdclk_squash); \
>  	func(has_ddi); \
>  	func(has_dp_mst); \
>  	func(has_dsb); \
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

[Jani Nikula]

On Fri, 21 Oct 2022, Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> wrote:
> On 20.10.2022 17:20, Anusha Srivatsa wrote:
>> Driver had discrepancy in how cdclk squash and crawl support
>> were checked. Like crawl, add squash as a 1 bit feature flag
>> to the display section of DG2.
>> 
>> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++----------
>>  drivers/gpu/drm/i915/i915_drv.h            |  1 +
>>  drivers/gpu/drm/i915/i915_pci.c            |  1 +
>>  drivers/gpu/drm/i915/intel_device_info.h   |  1 +
>>  4 files changed, 8 insertions(+), 10 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 0f5add2fc51b..45babbc6290f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>>  	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>>  }
>>  
>> -static bool has_cdclk_squash(struct drm_i915_private *i915)
>> -{
>> -	return IS_DG2(i915);
>> -}
>> -
>>  struct intel_cdclk_vals {
>>  	u32 cdclk;
>>  	u16 refclk;
>> @@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>>  		return;
>>  	}
>>  
>> -	if (has_cdclk_squash(dev_priv))
>> +	if (HAS_CDCLK_SQUASH(dev_priv))
>>  		squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>>  
>>  	if (squash_ctl & CDCLK_SQUASH_ENABLE) {
>> @@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  	else
>>  		clock = cdclk;
>>  
>> -	if (has_cdclk_squash(dev_priv)) {
>> +	if (HAS_CDCLK_SQUASH(dev_priv)) {
>>  		u32 squash_ctl = 0;
>>  
>>  		if (waveform)
>> @@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>>  	expected = skl_cdclk_decimal(cdclk);
>>  
>>  	/* Figure out what CD2X divider we should be using for this cdclk */
>> -	if (has_cdclk_squash(dev_priv))
>> +	if (HAS_CDCLK_SQUASH(dev_priv))
>>  		clock = dev_priv->display.cdclk.hw.vco / 2;
>>  	else
>>  		clock = dev_priv->display.cdclk.hw.cdclk;
>> @@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
>>  	 * the moment all platforms with squasher use a fixed cd2x
>>  	 * divider.
>>  	 */
>> -	if (!has_cdclk_squash(dev_priv))
>> +	if (!HAS_CDCLK_SQUASH(dev_priv))
>>  		return false;
>>  
>>  	return a->cdclk != b->cdclk &&
>> @@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
>>  	 * the moment all platforms with squasher use a fixed cd2x
>>  	 * divider.
>>  	 */
>> -	if (has_cdclk_squash(dev_priv))
>> +	if (HAS_CDCLK_SQUASH(dev_priv))
>>  		return false;
>>  
>>  	return a->cdclk != b->cdclk &&
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index d7b8eb9d4117..db51050e3ba2 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>>  
>>  #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
>> +#define HAS_CDCLK_SQUASH(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
>>  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
>>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 19bf5ef6a20d..a88e1439a426 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
>>  	.has_guc_deprivilege = 1, \
>>  	.has_heci_pxp = 1, \
>>  	.has_media_ratio_mode = 1, \
>> +	.display.has_cdclk_squash = 1, \
>
> Shouldn't this line be under dg2_info definition and not here?

It's in DG2_FEATURES macro, which is where it should be. You're probably
thrown off by the diff context symbol xehpsdv_info.

BR,
Jani.


>
> Regards,
> Bala
>
>>  	.__runtime.platform_engine_mask = \
>>  		BIT(RCS0) | BIT(BCS0) | \
>>  		BIT(VECS0) | BIT(VECS1) | \
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index cdf78728dcad..67d8759c802c 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -180,6 +180,7 @@ enum intel_ppgtt_type {
>>  	/* Keep in alphabetical order */ \
>>  	func(cursor_needs_physical); \
>>  	func(has_cdclk_crawl); \
>> +	func(has_cdclk_squash); \
>>  	func(has_ddi); \
>>  	func(has_dp_mst); \
>>  	func(has_dsb); \
>> -- 
>> 2.25.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

[Srivatsa, Anusha]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, October 21, 2022 1:47 AM
> To: Vivekanandan, Balasubramani
> <balasubramani.vivekanandan@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce
> HAS_CDCLK_SQUASH macro
> 
> On Fri, 21 Oct 2022, Balasubramani Vivekanandan
> <balasubramani.vivekanandan@intel.com> wrote:
> > On 20.10.2022 17:20, Anusha Srivatsa wrote:
> >> Driver had discrepancy in how cdclk squash and crawl support were
> >> checked. Like crawl, add squash as a 1 bit feature flag to the
> >> display section of DG2.
> >>
> >> Cc: Balasubramani Vivekanandan
> <balasubramani.vivekanandan@intel.com>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++----------
> >>  drivers/gpu/drm/i915/i915_drv.h            |  1 +
> >>  drivers/gpu/drm/i915/i915_pci.c            |  1 +
> >>  drivers/gpu/drm/i915/intel_device_info.h   |  1 +
> >>  4 files changed, 8 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> index 0f5add2fc51b..45babbc6290f 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> @@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct
> drm_i915_private *dev_priv)
> >>  	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);  }
> >>
> >> -static bool has_cdclk_squash(struct drm_i915_private *i915) -{
> >> -	return IS_DG2(i915);
> >> -}
> >> -
> >>  struct intel_cdclk_vals {
> >>  	u32 cdclk;
> >>  	u16 refclk;
> >> @@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct
> drm_i915_private *dev_priv,
> >>  		return;
> >>  	}
> >>
> >> -	if (has_cdclk_squash(dev_priv))
> >> +	if (HAS_CDCLK_SQUASH(dev_priv))
> >>  		squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
> >>
> >>  	if (squash_ctl & CDCLK_SQUASH_ENABLE) { @@ -1747,7 +1742,7 @@
> >> static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> >>  	else
> >>  		clock = cdclk;
> >>
> >> -	if (has_cdclk_squash(dev_priv)) {
> >> +	if (HAS_CDCLK_SQUASH(dev_priv)) {
> >>  		u32 squash_ctl = 0;
> >>
> >>  		if (waveform)
> >> @@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
> >>  	expected = skl_cdclk_decimal(cdclk);
> >>
> >>  	/* Figure out what CD2X divider we should be using for this cdclk */
> >> -	if (has_cdclk_squash(dev_priv))
> >> +	if (HAS_CDCLK_SQUASH(dev_priv))
> >>  		clock = dev_priv->display.cdclk.hw.vco / 2;
> >>  	else
> >>  		clock = dev_priv->display.cdclk.hw.cdclk; @@ -1976,7
> +1971,7 @@
> >> static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
> >>  	 * the moment all platforms with squasher use a fixed cd2x
> >>  	 * divider.
> >>  	 */
> >> -	if (!has_cdclk_squash(dev_priv))
> >> +	if (!HAS_CDCLK_SQUASH(dev_priv))
> >>  		return false;
> >>
> >>  	return a->cdclk != b->cdclk &&
> >> @@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct
> drm_i915_private *dev_priv,
> >>  	 * the moment all platforms with squasher use a fixed cd2x
> >>  	 * divider.
> >>  	 */
> >> -	if (has_cdclk_squash(dev_priv))
> >> +	if (HAS_CDCLK_SQUASH(dev_priv))
> >>  		return false;
> >>
> >>  	return a->cdclk != b->cdclk &&
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> b/drivers/gpu/drm/i915/i915_drv.h index d7b8eb9d4117..db51050e3ba2
> >> 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> >>  #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)
> 	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> >>
> >>  #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)-
> >display.has_cdclk_crawl)
> >> +#define HAS_CDCLK_SQUASH(dev_priv)	 (INTEL_INFO(dev_priv)-
> >display.has_cdclk_squash)
> >>  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)-
> >display.has_ddi)
> >>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)-
> >display.has_fpga_dbg)
> >>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)-
> >display.has_psr)
> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> >> b/drivers/gpu/drm/i915/i915_pci.c index 19bf5ef6a20d..a88e1439a426
> >> 100644
> >> --- a/drivers/gpu/drm/i915/i915_pci.c
> >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> @@ -1064,6 +1064,7 @@ static const struct intel_device_info
> xehpsdv_info = {
> >>  	.has_guc_deprivilege = 1, \
> >>  	.has_heci_pxp = 1, \
> >>  	.has_media_ratio_mode = 1, \
> >> +	.display.has_cdclk_squash = 1, \
> >
> > Shouldn't this line be under dg2_info definition and not here?
> 
> It's in DG2_FEATURES macro, which is where it should be. You're probably
> thrown off by the diff context symbol xehpsdv_info.

@Vivekanandan, Balasubramani apply the patch so the diff doesn’t get confusing.

Anusha
> 
> BR,
> Jani.
> 
> 
> >
> > Regards,
> > Bala
> >
> >>  	.__runtime.platform_engine_mask = \
> >>  		BIT(RCS0) | BIT(BCS0) | \
> >>  		BIT(VECS0) | BIT(VECS1) | \
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> >> b/drivers/gpu/drm/i915/intel_device_info.h
> >> index cdf78728dcad..67d8759c802c 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -180,6 +180,7 @@ enum intel_ppgtt_type {
> >>  	/* Keep in alphabetical order */ \
> >>  	func(cursor_needs_physical); \
> >>  	func(has_cdclk_crawl); \
> >> +	func(has_cdclk_squash); \
> >>  	func(has_ddi); \
> >>  	func(has_dp_mst); \
> >>  	func(has_dsb); \
> >> --
> >> 2.25.1
> >>
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

[Anusha Srivatsa]

No functional change. Moving segments out to simplify
bxt_set_cdlck()

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++++--------
 1 file changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 45babbc6290f..8701796788e3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
 	return 0xffff;
 }
 
+static void icl_cdclk_pll(struct drm_i915_private *i915, int vco)
+{
+	if (i915->display.cdclk.hw.vco != 0 &&
+	    i915->display.cdclk.hw.vco != vco)
+		icl_cdclk_pll_disable(i915);
+
+	if (i915->display.cdclk.hw.vco != vco)
+		icl_cdclk_pll_enable(i915, vco);
+}
+
+static void bxt_cdclk_pll(struct drm_i915_private *i915, int vco)
+{
+	if (i915->display.cdclk.hw.vco != 0 &&
+	    i915->display.cdclk.hw.vco != vco)
+		bxt_de_pll_disable(i915);
+
+	if (i915->display.cdclk.hw.vco != vco)
+		bxt_de_pll_enable(i915, vco);
+
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
 		if (dev_priv->display.cdclk.hw.vco != vco)
 			adlp_cdclk_pll_crawl(dev_priv, vco);
-	} else if (DISPLAY_VER(dev_priv) >= 11) {
-		if (dev_priv->display.cdclk.hw.vco != 0 &&
-		    dev_priv->display.cdclk.hw.vco != vco)
-			icl_cdclk_pll_disable(dev_priv);
-
-		if (dev_priv->display.cdclk.hw.vco != vco)
-			icl_cdclk_pll_enable(dev_priv, vco);
-	} else {
-		if (dev_priv->display.cdclk.hw.vco != 0 &&
-		    dev_priv->display.cdclk.hw.vco != vco)
-			bxt_de_pll_disable(dev_priv);
-
-		if (dev_priv->display.cdclk.hw.vco != vco)
-			bxt_de_pll_enable(dev_priv, vco);
-	}
+	} else if (DISPLAY_VER(dev_priv) >= 11)
+		icl_cdclk_pll(dev_priv, vco);
+	else
+		bxt_cdclk_pll(dev_priv, vco);
 
 	waveform = cdclk_squash_waveform(dev_priv, cdclk);
 
-- 
2.25.1

Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

[Jani Nikula]

On Thu, 20 Oct 2022, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> No functional change. Moving segments out to simplify
> bxt_set_cdlck()
>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++++--------
>  1 file changed, 25 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 45babbc6290f..8701796788e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
>  	return 0xffff;
>  }
>  
> +static void icl_cdclk_pll(struct drm_i915_private *i915, int vco)

The function name reads like it leaves something hanging in the air.

icl cdclk pll *what*?

Maybe update?

BR,
Jani.

> +{
> +	if (i915->display.cdclk.hw.vco != 0 &&
> +	    i915->display.cdclk.hw.vco != vco)
> +		icl_cdclk_pll_disable(i915);
> +
> +	if (i915->display.cdclk.hw.vco != vco)
> +		icl_cdclk_pll_enable(i915, vco);
> +}
> +
> +static void bxt_cdclk_pll(struct drm_i915_private *i915, int vco)
> +{
> +	if (i915->display.cdclk.hw.vco != 0 &&
> +	    i915->display.cdclk.hw.vco != vco)
> +		bxt_de_pll_disable(i915);
> +
> +	if (i915->display.cdclk.hw.vco != vco)
> +		bxt_de_pll_enable(i915, vco);
> +
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
>  		if (dev_priv->display.cdclk.hw.vco != vco)
>  			adlp_cdclk_pll_crawl(dev_priv, vco);
> -	} else if (DISPLAY_VER(dev_priv) >= 11) {
> -		if (dev_priv->display.cdclk.hw.vco != 0 &&
> -		    dev_priv->display.cdclk.hw.vco != vco)
> -			icl_cdclk_pll_disable(dev_priv);
> -
> -		if (dev_priv->display.cdclk.hw.vco != vco)
> -			icl_cdclk_pll_enable(dev_priv, vco);
> -	} else {
> -		if (dev_priv->display.cdclk.hw.vco != 0 &&
> -		    dev_priv->display.cdclk.hw.vco != vco)
> -			bxt_de_pll_disable(dev_priv);
> -
> -		if (dev_priv->display.cdclk.hw.vco != vco)
> -			bxt_de_pll_enable(dev_priv, vco);
> -	}
> +	} else if (DISPLAY_VER(dev_priv) >= 11)
> +		icl_cdclk_pll(dev_priv, vco);
> +	else
> +		bxt_cdclk_pll(dev_priv, vco);
>  
>  	waveform = cdclk_squash_waveform(dev_priv, cdclk);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, October 21, 2022 1:32 AM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Vivekanandan, Balasubramani
> <balasubramani.vivekanandan@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code
> out of bxt_set_cdclk()
> 
> On Thu, 20 Oct 2022, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> > No functional change. Moving segments out to simplify
> > bxt_set_cdlck()
> >
> > Cc: Balasubramani Vivekanandan
> <balasubramani.vivekanandan@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 40
> > ++++++++++++++--------
> >  1 file changed, 25 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 45babbc6290f..8701796788e3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct
> drm_i915_private *dev_priv,
> >  	return 0xffff;
> >  }
> >
> > +static void icl_cdclk_pll(struct drm_i915_private *i915, int vco)
> 
> The function name reads like it leaves something hanging in the air.
> 
> icl cdclk pll *what*?
> 
> Maybe update?

s/ icl_cdclk_pll/ icl_cdclk_pll_update.

Will make this ichange.

Thanks,
Anusha

> BR,
> Jani.
> 
> > +{
> > +	if (i915->display.cdclk.hw.vco != 0 &&
> > +	    i915->display.cdclk.hw.vco != vco)
> > +		icl_cdclk_pll_disable(i915);
> > +
> > +	if (i915->display.cdclk.hw.vco != vco)
> > +		icl_cdclk_pll_enable(i915, vco);
> > +}
> > +
> > +static void bxt_cdclk_pll(struct drm_i915_private *i915, int vco) {
> > +	if (i915->display.cdclk.hw.vco != 0 &&
> > +	    i915->display.cdclk.hw.vco != vco)
> > +		bxt_de_pll_disable(i915);
> > +
> > +	if (i915->display.cdclk.hw.vco != vco)
> > +		bxt_de_pll_enable(i915, vco);
> > +
> > +}
> > +
> >  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> >  			  const struct intel_cdclk_config *cdclk_config,
> >  			  enum pipe pipe)
> > @@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> >  	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco
> > 0 && vco > 0) {
> >  		if (dev_priv->display.cdclk.hw.vco != vco)
> >  			adlp_cdclk_pll_crawl(dev_priv, vco);
> > -	} else if (DISPLAY_VER(dev_priv) >= 11) {
> > -		if (dev_priv->display.cdclk.hw.vco != 0 &&
> > -		    dev_priv->display.cdclk.hw.vco != vco)
> > -			icl_cdclk_pll_disable(dev_priv);
> > -
> > -		if (dev_priv->display.cdclk.hw.vco != vco)
> > -			icl_cdclk_pll_enable(dev_priv, vco);
> > -	} else {
> > -		if (dev_priv->display.cdclk.hw.vco != 0 &&
> > -		    dev_priv->display.cdclk.hw.vco != vco)
> > -			bxt_de_pll_disable(dev_priv);
> > -
> > -		if (dev_priv->display.cdclk.hw.vco != vco)
> > -			bxt_de_pll_enable(dev_priv, vco);
> > -	}
> > +	} else if (DISPLAY_VER(dev_priv) >= 11)
> > +		icl_cdclk_pll(dev_priv, vco);
> > +	else
> > +		bxt_cdclk_pll(dev_priv, vco);
> >
> >  	waveform = cdclk_squash_waveform(dev_priv, cdclk);
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Anusha Srivatsa]

No functional change. Introduce dg2_cdclk_squash_programming and
move squash_ctl register programming bits to this.

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 8701796788e3..b692186c8f02 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll(struct drm_i915_private *i915, int vco)
 
 }
 
+static void dg2_cdclk_squash_programming(struct drm_i915_private *i915,
+					 u16 waveform)
+{
+	u32 squash_ctl = 0;
+
+	if (waveform)
+		squash_ctl = CDCLK_SQUASH_ENABLE |
+			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+
+	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	else
 		clock = cdclk;
 
-	if (HAS_CDCLK_SQUASH(dev_priv)) {
-		u32 squash_ctl = 0;
-
-		if (waveform)
-			squash_ctl = CDCLK_SQUASH_ENABLE |
-				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
-		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
-	}
+	if (HAS_CDCLK_SQUASH(dev_priv))
+		dg2_cdclk_squash_programming(dev_priv, waveform);
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
 		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-- 
2.25.1

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Balasubramani Vivekanandan]

On 20.10.2022 17:20, Anusha Srivatsa wrote:
> No functional change. Introduce dg2_cdclk_squash_programming and
> move squash_ctl register programming bits to this.
> 
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++---------
>  1 file changed, 14 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8701796788e3..b692186c8f02 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll(struct drm_i915_private *i915, int vco)
>  
>  }
>  
> +static void dg2_cdclk_squash_programming(struct drm_i915_private *i915,
> +					 u16 waveform)
> +{
> +	u32 squash_ctl = 0;
> +
> +	if (waveform)
> +		squash_ctl = CDCLK_SQUASH_ENABLE |
> +			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> +
> +	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	else
>  		clock = cdclk;
>  
> -	if (HAS_CDCLK_SQUASH(dev_priv)) {
> -		u32 squash_ctl = 0;
> -
> -		if (waveform)
> -			squash_ctl = CDCLK_SQUASH_ENABLE |
> -				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> -
> -		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> -	}
> +	if (HAS_CDCLK_SQUASH(dev_priv))
> +		dg2_cdclk_squash_programming(dev_priv, waveform);

Is it possible to move also the function cdclk_squash_waveform() inside
dg2_cdclk_squash_programming()?

Regards,
Bala

>  
>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>  		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Srivatsa, Anusha]

> -----Original Message-----
> From: Vivekanandan, Balasubramani
> <balasubramani.vivekanandan@intel.com>
> Sent: Friday, October 21, 2022 12:08 AM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: Re: [PATCH 4/4] drm/i915/display: Move squash_ctl register
> programming to its own function
> 
> On 20.10.2022 17:20, Anusha Srivatsa wrote:
> > No functional change. Introduce dg2_cdclk_squash_programming and
> move
> > squash_ctl register programming bits to this.
> >
> > Cc: Balasubramani Vivekanandan
> <balasubramani.vivekanandan@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 23
> > +++++++++++++---------
> >  1 file changed, 14 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 8701796788e3..b692186c8f02 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll(struct
> > drm_i915_private *i915, int vco)
> >
> >  }
> >
> > +static void dg2_cdclk_squash_programming(struct drm_i915_private
> *i915,
> > +					 u16 waveform)
> > +{
> > +	u32 squash_ctl = 0;
> > +
> > +	if (waveform)
> > +		squash_ctl = CDCLK_SQUASH_ENABLE |
> > +			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> > +
> > +	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); }
> > +
> >  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> >  			  const struct intel_cdclk_config *cdclk_config,
> >  			  enum pipe pipe)
> > @@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> >  	else
> >  		clock = cdclk;
> >
> > -	if (HAS_CDCLK_SQUASH(dev_priv)) {
> > -		u32 squash_ctl = 0;
> > -
> > -		if (waveform)
> > -			squash_ctl = CDCLK_SQUASH_ENABLE |
> > -				CDCLK_SQUASH_WINDOW_SIZE(0xf) |
> waveform;
> > -
> > -		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> > -	}
> > +	if (HAS_CDCLK_SQUASH(dev_priv))
> > +		dg2_cdclk_squash_programming(dev_priv, waveform);
> 
> Is it possible to move also the function cdclk_squash_waveform() inside
> dg2_cdclk_squash_programming()?

Hmmm. Are you thinking it is better to have both grabbing the squash waveform and programming the squash_ctl registers in one place better? IMO the fact that they are separate makes it more readable. We will have to return waveform and calculate the clock anyway.... 

Anusha
> Regards,
> Bala
> 
> >
> >  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> >  		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> > --
> > 2.25.1
> >

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Jani Nikula]

On Thu, 20 Oct 2022, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> No functional change. Introduce dg2_cdclk_squash_programming and
> move squash_ctl register programming bits to this.
>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++---------
>  1 file changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8701796788e3..b692186c8f02 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll(struct drm_i915_private *i915, int vco)
>  
>  }
>  
> +static void dg2_cdclk_squash_programming(struct drm_i915_private *i915,
> +					 u16 waveform)

Function names that are verbs should preferrably use the imperative
mood, i.e. program() instead of programmed(), programs() or
programming().

I'm also not sure "programming" or "program" is a very descriptive
thing; almost everything here is about "programming" something or other.

BR,
Jani.


> +{
> +	u32 squash_ctl = 0;
> +
> +	if (waveform)
> +		squash_ctl = CDCLK_SQUASH_ENABLE |
> +			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> +
> +	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	else
>  		clock = cdclk;
>  
> -	if (HAS_CDCLK_SQUASH(dev_priv)) {
> -		u32 squash_ctl = 0;
> -
> -		if (waveform)
> -			squash_ctl = CDCLK_SQUASH_ENABLE |
> -				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> -
> -		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> -	}
> +	if (HAS_CDCLK_SQUASH(dev_priv))
> +		dg2_cdclk_squash_programming(dev_priv, waveform);
>  
>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>  		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Srivatsa, Anusha]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, October 21, 2022 1:41 AM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Vivekanandan, Balasubramani
> <balasubramani.vivekanandan@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl
> register programming to its own function
> 
> On Thu, 20 Oct 2022, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> > No functional change. Introduce dg2_cdclk_squash_programming and
> move
> > squash_ctl register programming bits to this.
> >
> > Cc: Balasubramani Vivekanandan
> <balasubramani.vivekanandan@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 23
> > +++++++++++++---------
> >  1 file changed, 14 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 8701796788e3..b692186c8f02 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll(struct
> > drm_i915_private *i915, int vco)
> >
> >  }
> >
> > +static void dg2_cdclk_squash_programming(struct drm_i915_private
> *i915,
> > +					 u16 waveform)
> 
> Function names that are verbs should preferrably use the imperative mood,
> i.e. program() instead of programmed(), programs() or programming().
> 
> I'm also not sure "programming" or "program" is a very descriptive thing;
> almost everything here is about "programming" something or other.

Makes sense. Didn’t have a good feeling about the name in the first place. Thanks for the validation.

Anusha
> BR,
> Jani.
> 
> 
> > +{
> > +	u32 squash_ctl = 0;
> > +
> > +	if (waveform)
> > +		squash_ctl = CDCLK_SQUASH_ENABLE |
> > +			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> > +
> > +	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); }
> > +
> >  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> >  			  const struct intel_cdclk_config *cdclk_config,
> >  			  enum pipe pipe)
> > @@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> >  	else
> >  		clock = cdclk;
> >
> > -	if (HAS_CDCLK_SQUASH(dev_priv)) {
> > -		u32 squash_ctl = 0;
> > -
> > -		if (waveform)
> > -			squash_ctl = CDCLK_SQUASH_ENABLE |
> > -				CDCLK_SQUASH_WINDOW_SIZE(0xf) |
> waveform;
> > -
> > -		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> > -	}
> > +	if (HAS_CDCLK_SQUASH(dev_priv))
> > +		dg2_cdclk_squash_programming(dev_priv, waveform);
> >
> >  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> >  		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prep series - CDCLK code churn

[Patchwork]

== Series Details ==

Series: Prep series - CDCLK code churn
URL   : https://patchwork.freedesktop.org/series/109974/
State : warning

== Summary ==

Error: dim checkpatch failed
3be032201e8d drm/i915/display: Change terminology for cdclk actions
abff0975aed0 drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
2c0640029569 drm/i915/display: Move chunks of code out of bxt_set_cdclk()
-:43: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#43: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1706:
+
+}

total: 0 errors, 0 warnings, 1 checks, 52 lines checked
5edbe27ec9bb drm/i915/display: Move squash_ctl register programming to its own function

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Prep series - CDCLK code churn

[Patchwork]

== Series Details ==

Series: Prep series - CDCLK code churn
URL   : https://patchwork.freedesktop.org/series/109974/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Prep series - CDCLK code churn

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5238 bytes --]

== Series Details ==

Series: Prep series - CDCLK code churn
URL   : https://patchwork.freedesktop.org/series/109974/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12269 -> Patchwork_109974v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/index.html

Participating hosts (45 -> 42)
------------------------------

  Additional (1): bat-atsm-1 
  Missing    (4): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus fi-hsw-4200u 

Known issues
------------

  Here are the changes found in Patchwork_109974v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [PASS][1] -> [FAIL][2] ([i915#7229])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-rkl-11600:       NOTRUN -> [FAIL][3] ([fdo#103375])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_tiled_blits@basic:
    - fi-pnv-d510:        [PASS][4] -> [SKIP][5] ([fdo#109271]) +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/fi-pnv-d510/igt@gem_tiled_blits@basic.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/fi-pnv-d510/igt@gem_tiled_blits@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-rkl-11600:       NOTRUN -> [SKIP][6] ([fdo#111827])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/fi-rkl-11600/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@runner@aborted:
    - fi-hsw-4770:        NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#4312] / [i915#5594])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/fi-hsw-4770/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {bat-adlm-1}:       [DMESG-WARN][8] ([i915#2867]) -> [PASS][9] +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - {bat-rplp-1}:       [DMESG-WARN][10] ([i915#2867]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/bat-rplp-1/igt@gem_exec_suspend@basic-s3@smem.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/bat-rplp-1/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-rkl-11600:       [INCOMPLETE][12] ([i915#4817] / [i915#5982]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
  [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
  [i915#7030]: https://gitlab.freedesktop.org/drm/intel/issues/7030
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-------------

  * Linux: CI_DRM_12269 -> Patchwork_109974v1

  CI-20190529: 20190529
  CI_DRM_12269: 2aad56367e58b500195158a1abb0e1380965bb04 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7021: b99f94fc3652f6838b8803032373a419372b17b1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_109974v1: 2aad56367e58b500195158a1abb0e1380965bb04 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

1261bab00314 drm/i915/display: Move squash_ctl register programming to its own function
873c2ab9ba40 drm/i915/display: Move chunks of code out of bxt_set_cdclk()
0c9b1d891e20 drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
e867c0ba8d18 drm/i915/display: Change terminology for cdclk actions

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/index.html

[-- Attachment #2: Type: text/html, Size: 5721 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for Prep series - CDCLK code churn

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 48249 bytes --]

== Series Details ==

Series: Prep series - CDCLK code churn
URL   : https://patchwork.freedesktop.org/series/109974/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12269_full -> Patchwork_109974v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_109974v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109974v1_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_109974v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_pread@exhaustion:
    - shard-glk:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/igt@gem_pread@exhaustion.html

  
#### Warnings ####

  * igt@runner@aborted:
    - shard-skl:          ([FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6]) ([i915#4312]) -> ([FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11]) ([i915#3002] / [i915#4312])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl10/igt@runner@aborted.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl7/igt@runner@aborted.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl7/igt@runner@aborted.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl6/igt@runner@aborted.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl2/igt@runner@aborted.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl2/igt@runner@aborted.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl7/igt@runner@aborted.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl9/igt@runner@aborted.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl6/igt@runner@aborted.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl4/igt@runner@aborted.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a3:
    - {shard-dg1}:        NOTRUN -> [FAIL][12]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-dg1-19/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a3.html

  
Known issues
------------

  Here are the changes found in Patchwork_109974v1_full that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - shard-snb:          ([PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [FAIL][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37]) ([i915#4338]) -> ([PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb7/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb7/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb7/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb7/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb7/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb6/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb6/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb6/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb6/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb6/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb5/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb5/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb5/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb5/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb5/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb4/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb4/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb4/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb4/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb4/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb2/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb2/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb2/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb2/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-snb2/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb7/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb7/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb7/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb7/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb7/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb7/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb6/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb6/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb6/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb6/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb6/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb5/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb5/boot.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb5/boot.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb5/boot.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb4/boot.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb4/boot.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb4/boot.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb4/boot.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb4/boot.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb2/boot.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb2/boot.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb2/boot.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb2/boot.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb2/boot.html
    - shard-glk:          ([PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [FAIL][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87]) ([i915#4392]) -> ([PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk9/boot.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk9/boot.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk8/boot.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk8/boot.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk8/boot.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk7/boot.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk7/boot.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk6/boot.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk6/boot.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk6/boot.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk5/boot.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk5/boot.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk5/boot.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk5/boot.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk3/boot.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk3/boot.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk3/boot.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk2/boot.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk2/boot.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk2/boot.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk2/boot.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk1/boot.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk1/boot.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk1/boot.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-glk9/boot.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk1/boot.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk1/boot.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk1/boot.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk2/boot.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk2/boot.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk2/boot.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk3/boot.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk3/boot.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk3/boot.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk5/boot.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk5/boot.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk5/boot.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk6/boot.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk6/boot.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk6/boot.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk6/boot.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk7/boot.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk7/boot.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk7/boot.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk8/boot.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk8/boot.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk8/boot.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/boot.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/boot.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@legacy-engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#1099]) +1 similar issue
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb5/igt@gem_ctx_persistence@legacy-engines-queued.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][114] ([i915#2842])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][115] -> [SKIP][116] ([i915#2190])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-tglb8/igt@gem_huc_copy@huc-copy.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb7/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-tglb:         NOTRUN -> [SKIP][117] ([i915#4613])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-skl:          NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#4613]) +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl4/igt@gem_lmem_swapping@parallel-random-verify.html
    - shard-glk:          NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#4613])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@verify:
    - shard-apl:          NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#4613]) +1 similar issue
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl3/igt@gem_lmem_swapping@verify.html

  * igt@gem_pxp@verify-pxp-stale-buf-execution:
    - shard-tglb:         NOTRUN -> [SKIP][121] ([i915#4270])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@gem_pxp@verify-pxp-stale-buf-execution.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
    - shard-glk:          NOTRUN -> [SKIP][122] ([fdo#109271]) +37 similar issues
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html

  * igt@gem_softpin@evict-single-offset:
    - shard-tglb:         [PASS][123] -> [FAIL][124] ([i915#4171])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-tglb5/igt@gem_softpin@evict-single-offset.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb3/igt@gem_softpin@evict-single-offset.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-tglb:         NOTRUN -> [SKIP][125] ([fdo#110542])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-skl:          NOTRUN -> [DMESG-WARN][126] ([i915#4991])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl6/igt@gem_userptr_blits@input-checking.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-skl:          [PASS][127] -> [INCOMPLETE][128] ([i915#7259] / [i915#7299])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl7/igt@gem_workarounds@suspend-resume-fd.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl10/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_module_load@load:
    - shard-skl:          NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#6227])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl10/igt@i915_module_load@load.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         NOTRUN -> [FAIL][130] ([i915#3989] / [i915#454])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-apl:          NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#1937])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-tglb:         NOTRUN -> [SKIP][132] ([i915#5286])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [SKIP][133] ([fdo#109271]) +66 similar issues
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl10/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglb:         [PASS][134] -> [FAIL][135] ([i915#3743]) +1 similar issue
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-tglb5/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-tglb:         NOTRUN -> [SKIP][136] ([fdo#111615])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_joiner@basic:
    - shard-tglb:         NOTRUN -> [SKIP][137] ([i915#2705])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#3886]) +5 similar issues
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl1/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][139] ([i915#3689] / [i915#3886])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
    - shard-tglb:         NOTRUN -> [SKIP][140] ([i915#3689] / [i915#6095])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][141] ([fdo#109271] / [i915#3886])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_ccs:
    - shard-apl:          NOTRUN -> [SKIP][142] ([fdo#109271]) +97 similar issues
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_rc_ccs_cc:
    - shard-tglb:         NOTRUN -> [SKIP][143] ([i915#6095])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][144] ([i915#3689])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-crc-single:
    - shard-snb:          NOTRUN -> [SKIP][145] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb5/igt@kms_chamelium@dp-crc-single.html

  * igt@kms_chamelium@hdmi-aspect-ratio:
    - shard-tglb:         NOTRUN -> [SKIP][146] ([fdo#109284] / [fdo#111827])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_chamelium@hdmi-aspect-ratio.html

  * igt@kms_chamelium@hdmi-hpd-storm-disable:
    - shard-skl:          NOTRUN -> [SKIP][147] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl10/igt@kms_chamelium@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium@vga-frame-dump:
    - shard-glk:          NOTRUN -> [SKIP][148] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/igt@kms_chamelium@vga-frame-dump.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
    - shard-apl:          NOTRUN -> [SKIP][149] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl6/igt@kms_chamelium@vga-hpd-after-suspend.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-tglb:         NOTRUN -> [SKIP][150] ([i915#3555])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size:
    - shard-skl:          [PASS][151] -> [INCOMPLETE][152] ([i915#7096])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl10/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl10/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [PASS][153] -> [INCOMPLETE][154] ([i915#180] / [i915#4939])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
    - shard-apl:          [PASS][155] -> [FAIL][156] ([i915#79])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][157] ([i915#2587] / [i915#2672])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][158] ([i915#2672]) +3 similar issues
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][159] ([i915#3555])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][160] ([i915#2672] / [i915#3555])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
    - shard-tglb:         NOTRUN -> [SKIP][161] ([i915#6497]) +1 similar issue
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-pwrite:
    - shard-tglb:         NOTRUN -> [SKIP][162] ([fdo#109280] / [fdo#111825]) +5 similar issues
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][163] ([fdo#112054] / [i915#5288])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
    - shard-tglb:         NOTRUN -> [SKIP][164] ([i915#2920])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][165] ([fdo#109271] / [i915#658])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-apl:          NOTRUN -> [SKIP][166] ([fdo#109271] / [i915#658])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl6/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-skl:          NOTRUN -> [SKIP][167] ([fdo#109271] / [i915#658]) +1 similar issue
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl10/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][168] -> [SKIP][169] ([fdo#109441])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb5/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-tglb:         NOTRUN -> [FAIL][170] ([i915#132] / [i915#3467])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_psr@psr2_sprite_plane_onoff:
    - shard-snb:          NOTRUN -> [SKIP][171] ([fdo#109271]) +60 similar issues
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-snb5/igt@kms_psr@psr2_sprite_plane_onoff.html

  * igt@perf@polling-parameterized:
    - shard-iclb:         [PASS][172] -> [FAIL][173] ([i915#5639])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb6/igt@perf@polling-parameterized.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb8/igt@perf@polling-parameterized.html
    - shard-skl:          [PASS][174] -> [FAIL][175] ([i915#5639])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl7/igt@perf@polling-parameterized.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl7/igt@perf@polling-parameterized.html

  * igt@sysfs_clients@sema-10:
    - shard-apl:          NOTRUN -> [SKIP][176] ([fdo#109271] / [i915#2994])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl6/igt@sysfs_clients@sema-10.html

  * igt@sysfs_clients@split-50:
    - shard-skl:          NOTRUN -> [SKIP][177] ([fdo#109271] / [i915#2994]) +1 similar issue
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl4/igt@sysfs_clients@split-50.html
    - shard-glk:          NOTRUN -> [SKIP][178] ([fdo#109271] / [i915#2994])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-glk9/igt@sysfs_clients@split-50.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-rkl}:        [FAIL][179] ([i915#6268]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-apl:          [DMESG-WARN][181] ([i915#180]) -> [PASS][182] +6 similar issues
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-apl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-iclb:         [SKIP][183] ([i915#4525]) -> [PASS][184] +1 similar issue
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][185] ([i915#2842]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_reloc@basic-gtt-cpu-active:
    - {shard-rkl}:        [SKIP][187] ([i915#3281]) -> [PASS][188] +10 similar issues
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-1/igt@gem_exec_reloc@basic-gtt-cpu-active.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-cpu-active.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - {shard-rkl}:        [SKIP][189] ([i915#3282]) -> [PASS][190] +2 similar issues
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-1/igt@gem_partial_pwrite_pread@reads-uncached.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_softpin@evict-single-offset:
    - {shard-rkl}:        [FAIL][191] ([i915#4171]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-5/igt@gem_softpin@evict-single-offset.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-4/igt@gem_softpin@evict-single-offset.html

  * igt@gen9_exec_parse@secure-batches:
    - {shard-rkl}:        [SKIP][193] ([i915#2527]) -> [PASS][194]
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-4/igt@gen9_exec_parse@secure-batches.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-5/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_module_load@reload:
    - shard-skl:          [DMESG-WARN][195] ([i915#1982]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl9/igt@i915_module_load@reload.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl6/igt@i915_module_load@reload.html

  * igt@i915_pm_dc@dc6-psr:
    - {shard-rkl}:        [SKIP][197] ([i915#658]) -> [PASS][198]
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-4/igt@i915_pm_dc@dc6-psr.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-6/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rps@engine-order:
    - shard-apl:          [FAIL][199] ([i915#6537]) -> [PASS][200]
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-apl1/igt@i915_pm_rps@engine-order.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl7/igt@i915_pm_rps@engine-order.html

  * igt@kms_atomic@atomic_plane_damage:
    - {shard-rkl}:        [SKIP][201] ([i915#4098]) -> [PASS][202]
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-4/igt@kms_atomic@atomic_plane_damage.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-6/igt@kms_atomic@atomic_plane_damage.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglb:         [FAIL][203] ([i915#3743]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-tglb8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_flip@blocking-absolute-wf_vblank@b-edp1:
    - shard-skl:          [INCOMPLETE][205] -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl2/igt@kms_flip@blocking-absolute-wf_vblank@b-edp1.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl6/igt@kms_flip@blocking-absolute-wf_vblank@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [FAIL][207] ([i915#79]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@plain-flip-ts-check@b-edp1:
    - shard-skl:          [FAIL][209] ([i915#2122]) -> [PASS][210] +3 similar issues
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-skl10/igt@kms_flip@plain-flip-ts-check@b-edp1.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-skl9/igt@kms_flip@plain-flip-ts-check@b-edp1.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - {shard-rkl}:        [SKIP][211] ([i915#1849] / [i915#4098]) -> [PASS][212] +5 similar issues
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
    - shard-iclb:         [SKIP][213] ([i915#5235]) -> [PASS][214] +2 similar issues
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb5/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [SKIP][215] ([fdo#109441]) -> [PASS][216] +1 similar issue
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_vblank@pipe-a-query-forked-busy-hang:
    - {shard-rkl}:        [SKIP][217] ([i915#1845] / [i915#4098]) -> [PASS][218] +5 similar issues
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-4/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-6/igt@kms_vblank@pipe-a-query-forked-busy-hang.html

  * igt@perf@gen12-mi-rpc:
    - {shard-rkl}:        [SKIP][219] ([fdo#109289]) -> [PASS][220]
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-rkl-5/igt@perf@gen12-mi-rpc.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-rkl-4/igt@perf@gen12-mi-rpc.html

  
#### Warnings ####

  * igt@gem_pwrite@basic-exhaustion:
    - shard-apl:          [INCOMPLETE][221] ([i915#7248]) -> [INCOMPLETE][222] ([i915#7227] / [i915#7248])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-apl1/igt@gem_pwrite@basic-exhaustion.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-apl7/igt@gem_pwrite@basic-exhaustion.html
    - shard-tglb:         [WARN][223] ([i915#2658]) -> [INCOMPLETE][224] ([i915#7248])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-tglb3/igt@gem_pwrite@basic-exhaustion.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-tglb6/igt@gem_pwrite@basic-exhaustion.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][225] ([i915#588]) -> [SKIP][226] ([i915#658])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-iclb:         [SKIP][227] ([i915#658]) -> [SKIP][228] ([i915#2920])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@runner@aborted:
    - shard-iclb:         ([FAIL][229], [FAIL][230], [FAIL][231], [FAIL][232], [FAIL][233], [FAIL][234], [FAIL][235]) ([i915#3002] / [i915#4312]) -> ([FAIL][236], [FAIL][237], [FAIL][238], [FAIL][239], [FAIL][240], [FAIL][241], [FAIL][242]) ([i915#3002] / [i915#4312] / [i915#7300])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb8/igt@runner@aborted.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb1/igt@runner@aborted.html
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb3/igt@runner@aborted.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb2/igt@runner@aborted.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb6/igt@runner@aborted.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb8/igt@runner@aborted.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12269/shard-iclb4/igt@runner@aborted.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb6/igt@runner@aborted.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb1/igt@runner@aborted.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb2/igt@runner@aborted.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb3/igt@runner@aborted.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb5/igt@runner@aborted.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb3/igt@runner@aborted.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/shard-iclb4/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
  [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338
  [i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#7096]: https://gitlab.freedesktop.org/drm/intel/issues/7096
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142
  [i915#7227]: https://gitlab.freedesktop.org/drm/intel/issues/7227
  [i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
  [i915#7259]: https://gitlab.freedesktop.org/drm/intel/issues/7259
  [i915#7299]: https://gitlab.freedesktop.org/drm/intel/issues/7299
  [i915#7300]: https://gitlab.freedesktop.org/drm/intel/issues/7300
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_12269 -> Patchwork_109974v1

  CI-20190529: 20190529
  CI_DRM_12269: 2aad56367e58b500195158a1abb0e1380965bb04 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7021: b99f94fc3652f6838b8803032373a419372b17b1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_109974v1: 2aad56367e58b500195158a1abb0e1380965bb04 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109974v1/index.html

[-- Attachment #2: Type: text/html, Size: 51849 bytes --]

Re: [Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn

[Balasubramani Vivekanandan]

On 20.10.2022 17:20, Anusha Srivatsa wrote:
> No functional changes. The series is more of a prep series
> for the mid_cdclk_config series:
> https://patchwork.freedesktop.org/series/109694/
> 
> Main change:
>  - Change usage of "crawler" and "squasher". Use crawling and
> squashing instead.
>  - Handle bot hsquash and cralw similar in terms of checking
Please check the typos here

Regards,
Bala

> if the platform supports them or not. With the changes introduced,
> both are a display feature flag.
>  - Move code from bxt_set_cdclk() to make it more modularized
> and easy to read and understand.
> 
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Anusha Srivatsa (4):
>   drm/i915/display: Change terminology for cdclk actions
>   drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
>   drm/i915/display: Move chunks of code out of bxt_set_cdclk()
>   drm/i915/display: Move squash_ctl register programming to its own
>     function
> 
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 80 ++++++++++++----------
>  drivers/gpu/drm/i915/i915_drv.h            |  1 +
>  drivers/gpu/drm/i915/i915_pci.c            |  1 +
>  drivers/gpu/drm/i915/intel_device_info.h   |  1 +
>  4 files changed, 48 insertions(+), 35 deletions(-)
> 
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn

[Jani Nikula]

On Fri, 21 Oct 2022, Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> wrote:
> On 20.10.2022 17:20, Anusha Srivatsa wrote:
>> No functional changes. The series is more of a prep series
>> for the mid_cdclk_config series:
>> https://patchwork.freedesktop.org/series/109694/
>> 
>> Main change:
>>  - Change usage of "crawler" and "squasher". Use crawling and
>> squashing instead.
>>  - Handle bot hsquash and cralw similar in terms of checking
> Please check the typos here

This is a cover letter. It's not merged anywhere. It's not necessary to
point out typos here.

BR,
Jani.

>
> Regards,
> Bala
>
>> if the platform supports them or not. With the changes introduced,
>> both are a display feature flag.
>>  - Move code from bxt_set_cdclk() to make it more modularized
>> and easy to read and understand.
>> 
>> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> 
>> Anusha Srivatsa (4):
>>   drm/i915/display: Change terminology for cdclk actions
>>   drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
>>   drm/i915/display: Move chunks of code out of bxt_set_cdclk()
>>   drm/i915/display: Move squash_ctl register programming to its own
>>     function
>> 
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 80 ++++++++++++----------
>>  drivers/gpu/drm/i915/i915_drv.h            |  1 +
>>  drivers/gpu/drm/i915/i915_pci.c            |  1 +
>>  drivers/gpu/drm/i915/intel_device_info.h   |  1 +
>>  4 files changed, 48 insertions(+), 35 deletions(-)
>> 
>> -- 
>> 2.25.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 0/4] Prep series - CDCLK code churn

[Anusha Srivatsa]

No functional changes. The series is more of a prep series
for the mid_cdclk_config series:
https://patchwork.freedesktop.org/series/109694/

Main change:
 - Change usage of "crawler" and "squasher". Use crawling and
squashing instead.
 - Handle both squash and crawl similar in terms of checking
if the platform supports them or not. With the changes introduced,
both are a display feature flag.
 - Move code from bxt_set_cdclk() to make it more modularized
and easy to read and understand.

v2: Change function names to align with rest of the driver.
No major changes.

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Anusha Srivatsa (4):
  drm/i915/display: Change terminology for cdclk actions
  drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
  drm/i915/display: Move chunks of code out of bxt_set_cdclk()
  drm/i915/display: Move squash_ctl register programming to its own
    function

 drivers/gpu/drm/i915/display/intel_cdclk.c | 80 ++++++++++++----------
 drivers/gpu/drm/i915/i915_drv.h            |  1 +
 drivers/gpu/drm/i915/i915_pci.c            |  1 +
 drivers/gpu/drm/i915/intel_device_info.h   |  1 +
 4 files changed, 48 insertions(+), 35 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Anusha Srivatsa]

No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.

v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3893779e0c23..e21cd0fbe29a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
 
 }
 
+static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+					 u16 waveform)
+{
+	u32 squash_ctl = 0;
+
+	if (waveform)
+		squash_ctl = CDCLK_SQUASH_ENABLE |
+			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+
+	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	else
 		clock = cdclk;
 
-	if (HAS_CDCLK_SQUASH(dev_priv)) {
-		u32 squash_ctl = 0;
-
-		if (waveform)
-			squash_ctl = CDCLK_SQUASH_ENABLE |
-				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
-		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
-	}
+	if (HAS_CDCLK_SQUASH(dev_priv))
+		dg2_cdclk_squash_program(dev_priv, waveform);
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
 		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-- 
2.25.1

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Balasubramani Vivekanandan]

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional change. Introduce dg2_cdclk_squash_program and
> move squash_ctl register programming bits to this.
> 
> v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++---------
>  1 file changed, 14 insertions(+), 9 deletions(-)

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3893779e0c23..e21cd0fbe29a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
>  
>  }
>  
> +static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
> +					 u16 waveform)
> +{
> +	u32 squash_ctl = 0;
> +
> +	if (waveform)
> +		squash_ctl = CDCLK_SQUASH_ENABLE |
> +			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> +
> +	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	else
>  		clock = cdclk;
>  
> -	if (HAS_CDCLK_SQUASH(dev_priv)) {
> -		u32 squash_ctl = 0;
> -
> -		if (waveform)
> -			squash_ctl = CDCLK_SQUASH_ENABLE |
> -				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> -
> -		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> -	}
> +	if (HAS_CDCLK_SQUASH(dev_priv))
> +		dg2_cdclk_squash_program(dev_priv, waveform);
>  
>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>  		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> -- 
> 2.25.1
> 

[Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions

[Anusha Srivatsa]

No functional changes. Changing terminology in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad401357ab66..0f5add2fc51b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squasher(struct drm_i915_private *i915)
+static bool has_cdclk_squash(struct drm_i915_private *i915)
 {
 	return IS_DG2(i915);
 }
@@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (has_cdclk_squasher(dev_priv))
+	if (has_cdclk_squash(dev_priv))
 		squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
 	if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	else
 		clock = cdclk;
 
-	if (has_cdclk_squasher(dev_priv)) {
+	if (has_cdclk_squash(dev_priv)) {
 		u32 squash_ctl = 0;
 
 		if (waveform)
@@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	expected = skl_cdclk_decimal(cdclk);
 
 	/* Figure out what CD2X divider we should be using for this cdclk */
-	if (has_cdclk_squasher(dev_priv))
+	if (has_cdclk_squash(dev_priv))
 		clock = dev_priv->display.cdclk.hw.vco / 2;
 	else
 		clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
 	 * the moment all platforms with squasher use a fixed cd2x
 	 * divider.
 	 */
-	if (!has_cdclk_squasher(dev_priv))
+	if (!has_cdclk_squash(dev_priv))
 		return false;
 
 	return a->cdclk != b->cdclk &&
@@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
 	 * the moment all platforms with squasher use a fixed cd2x
 	 * divider.
 	 */
-	if (has_cdclk_squasher(dev_priv))
+	if (has_cdclk_squash(dev_priv))
 		return false;
 
 	return a->cdclk != b->cdclk &&
@@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 				   &old_cdclk_state->actual,
 				   &new_cdclk_state->actual)) {
 		drm_dbg_kms(&dev_priv->drm,
-			    "Can change cdclk via squasher\n");
+			    "Can change cdclk via squashing\n");
 	} else if (intel_cdclk_can_crawl(dev_priv,
 					 &old_cdclk_state->actual,
 					 &new_cdclk_state->actual)) {
 		drm_dbg_kms(&dev_priv->drm,
-			    "Can change cdclk via crawl\n");
+			    "Can change cdclk via crawling\n");
 	} else if (pipe != INVALID_PIPE) {
 		new_cdclk_state->pipe = pipe;
 
-- 
2.25.1

[Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Anusha Srivatsa]

No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.

v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3893779e0c23..e21cd0fbe29a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
 
 }
 
+static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+					 u16 waveform)
+{
+	u32 squash_ctl = 0;
+
+	if (waveform)
+		squash_ctl = CDCLK_SQUASH_ENABLE |
+			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+
+	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	else
 		clock = cdclk;
 
-	if (HAS_CDCLK_SQUASH(dev_priv)) {
-		u32 squash_ctl = 0;
-
-		if (waveform)
-			squash_ctl = CDCLK_SQUASH_ENABLE |
-				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
-		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
-	}
+	if (HAS_CDCLK_SQUASH(dev_priv))
+		dg2_cdclk_squash_program(dev_priv, waveform);
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
 		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-- 
2.25.1