* [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
@ 2020-07-27 8:32 Clements, John
2020-07-27 8:50 ` Chen, Guchun
2020-07-27 9:40 ` Christian König
0 siblings, 2 replies; 5+ messages in thread
From: Clements, John @ 2020-07-27 8:32 UTC (permalink / raw)
To: amd-gfx list, Zhang, Hawking
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[AMD Public Use]
Submitting patch to enable UMC 8.7 GECC functions in GMC v10
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From afedf7a585cd2db2bd54c1d6e3b6082d9e22d2c4 Mon Sep 17 00:00:00 2001
From: John Clements <john.clements@amd.com>
Date: Mon, 27 Jul 2020 16:27:54 +0800
Subject: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
add support for umc 8.7 initialzation and RAS interrupt
Signed-off-by: John Clements <john.clements@amd.com>
Change-Id: I9679571893a3dedf33918c151991f0572a4e8fed
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 50 +++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 1a78073c2f05..35d21f330b0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -25,6 +25,7 @@
#include "amdgpu.h"
#include "amdgpu_atomfirmware.h"
#include "gmc_v10_0.h"
+#include "umc_v8_7.h"
#include "hdp/hdp_5_0_0_offset.h"
#include "hdp/hdp_5_0_0_sh_mask.h"
@@ -55,6 +56,14 @@ static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
};
#endif
+static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *src,
+ unsigned type,
+ enum amdgpu_interrupt_state state)
+{
+ return 0;
+}
+
static int
gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src, unsigned type,
@@ -131,10 +140,20 @@ static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
.process = gmc_v10_0_process_interrupt,
};
-static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
+static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
+ .set = gmc_v10_0_ecc_interrupt_state,
+ .process = amdgpu_umc_process_ecc_irq,
+};
+
+ static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
{
adev->gmc.vm_fault.num_types = 1;
adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
+
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->gmc.ecc_irq.num_types = 1;
+ adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
+ }
}
/**
@@ -569,12 +588,29 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
}
+static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
+{
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
+ adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
+ adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
+ adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
+ adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
+ adev->umc.funcs = &umc_v8_7_funcs;
+ break;
+ default:
+ break;
+ }
+}
+
static int gmc_v10_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gmc_v10_0_set_gmc_funcs(adev);
gmc_v10_0_set_irq_funcs(adev);
+ gmc_v10_0_set_umc_funcs(adev);
adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
adev->gmc.shared_aperture_end =
@@ -790,6 +826,14 @@ static int gmc_v10_0_sw_init(void *handle)
if (r)
return r;
+ if (!amdgpu_sriov_vf(adev)) {
+ /* interrupt sent to DF. */
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
+ &adev->gmc.ecc_irq);
+ if (r)
+ return r;
+ }
+
/*
* Set the internal MC address mask This is the max address of the GPU's
* internal address space.
@@ -950,6 +994,9 @@ static int gmc_v10_0_hw_init(void *handle)
if (r)
return r;
+ if (adev->umc.funcs && adev->umc.funcs->init_registers)
+ adev->umc.funcs->init_registers(adev);
+
return 0;
}
@@ -981,6 +1028,7 @@ static int gmc_v10_0_hw_fini(void *handle)
return 0;
}
+ amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
gmc_v10_0_gart_disable(adev);
--
2.17.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
2020-07-27 8:32 [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10 Clements, John
@ 2020-07-27 8:50 ` Chen, Guchun
2020-07-28 2:55 ` Clements, John
2020-07-27 9:40 ` Christian König
1 sibling, 1 reply; 5+ messages in thread
From: Chen, Guchun @ 2020-07-27 8:50 UTC (permalink / raw)
To: Clements, John, amd-gfx list, Zhang, Hawking
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[AMD Public Use]
One typo in commit subject.
add support for umc 8.7 initialzation and RAS interrupt
s/initialzation /initialization
With this fixed, the patch is:
Reviewed-by: Guchun Chen guchun.chen@amd.com<mailto:guchun.chen@amd.com>
Regards,
Guchun
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Clements, John
Sent: Monday, July 27, 2020 4:32 PM
To: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
[AMD Public Use]
Submitting patch to enable UMC 8.7 GECC functions in GMC v10
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
2020-07-27 8:32 [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10 Clements, John
2020-07-27 8:50 ` Chen, Guchun
@ 2020-07-27 9:40 ` Christian König
1 sibling, 0 replies; 5+ messages in thread
From: Christian König @ 2020-07-27 9:40 UTC (permalink / raw)
To: Clements, John, amd-gfx list, Zhang, Hawking
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Please use the "git send-email" command to send patches to the mailing list.
Christian.
Am 27.07.20 um 10:32 schrieb Clements, John:
>
> [AMD Public Use]
>
>
> Submitting patch to enable UMC 8.7 GECC functions in GMC v10
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
2020-07-27 8:50 ` Chen, Guchun
@ 2020-07-28 2:55 ` Clements, John
2020-07-28 4:27 ` Chen, Guchun
0 siblings, 1 reply; 5+ messages in thread
From: Clements, John @ 2020-07-28 2:55 UTC (permalink / raw)
To: Chen, Guchun, amd-gfx list, Zhang, Hawking
[-- Attachment #1.1: Type: text/plain, Size: 1284 bytes --]
[AMD Public Use]
Thank you for the feedback @Chen, Guchun<mailto:Guchun.Chen@amd.com>,
I've attached an updated patch with the corrected typo and also an additional change to add the new UMC source to the makefile
Thank you,
John Clements
From: Chen, Guchun <Guchun.Chen@amd.com>
Sent: Monday, July 27, 2020 4:50 PM
To: Clements, John <John.Clements@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: RE: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
[AMD Public Use]
One typo in commit subject.
add support for umc 8.7 initialzation and RAS interrupt
s/initialzation /initialization
With this fixed, the patch is:
Reviewed-by: Guchun Chen guchun.chen@amd.com<mailto:guchun.chen@amd.com>
Regards,
Guchun
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> On Behalf Of Clements, John
Sent: Monday, July 27, 2020 4:32 PM
To: amd-gfx list <amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>>; Zhang, Hawking <Hawking.Zhang@amd.com<mailto:Hawking.Zhang@amd.com>>
Subject: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
[AMD Public Use]
Submitting patch to enable UMC 8.7 GECC functions in GMC v10
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[-- Attachment #2: 0001-drm-amdgpu-enable-umc-8.7-functions-in-gmc-v10.patch --]
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From 0e2dbf75f25295e7f83dd269ed3a247a863ee45e Mon Sep 17 00:00:00 2001
From: John Clements <john.clements@amd.com>
Date: Tue, 28 Jul 2020 10:53:18 +0800
Subject: [PATCH 1/1] drm/amdgpu: enable umc 8.7 functions in gmc v10
add support for umc 8.7 initialization
add umc 8.7 source to makefile
Signed-off-by: John Clements <john.clements@amd.com>
Change-Id: I50b33944d0a1165c166fe90b5d1289d09835cdd3
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 50 +++++++++++++++++++++++++-
2 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 403ec3db29df..0ba396e9d7e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -85,7 +85,7 @@ amdgpu-y += \
# add UMC block
amdgpu-y += \
- umc_v6_1.o umc_v6_0.o
+ umc_v6_1.o umc_v6_0.o umc_v8_7.o
# add IH block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 1a78073c2f05..35d21f330b0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -25,6 +25,7 @@
#include "amdgpu.h"
#include "amdgpu_atomfirmware.h"
#include "gmc_v10_0.h"
+#include "umc_v8_7.h"
#include "hdp/hdp_5_0_0_offset.h"
#include "hdp/hdp_5_0_0_sh_mask.h"
@@ -55,6 +56,14 @@ static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
};
#endif
+static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *src,
+ unsigned type,
+ enum amdgpu_interrupt_state state)
+{
+ return 0;
+}
+
static int
gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src, unsigned type,
@@ -131,10 +140,20 @@ static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
.process = gmc_v10_0_process_interrupt,
};
-static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
+static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
+ .set = gmc_v10_0_ecc_interrupt_state,
+ .process = amdgpu_umc_process_ecc_irq,
+};
+
+ static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
{
adev->gmc.vm_fault.num_types = 1;
adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
+
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->gmc.ecc_irq.num_types = 1;
+ adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
+ }
}
/**
@@ -569,12 +588,29 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
}
+static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
+{
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
+ adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
+ adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
+ adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
+ adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
+ adev->umc.funcs = &umc_v8_7_funcs;
+ break;
+ default:
+ break;
+ }
+}
+
static int gmc_v10_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gmc_v10_0_set_gmc_funcs(adev);
gmc_v10_0_set_irq_funcs(adev);
+ gmc_v10_0_set_umc_funcs(adev);
adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
adev->gmc.shared_aperture_end =
@@ -790,6 +826,14 @@ static int gmc_v10_0_sw_init(void *handle)
if (r)
return r;
+ if (!amdgpu_sriov_vf(adev)) {
+ /* interrupt sent to DF. */
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
+ &adev->gmc.ecc_irq);
+ if (r)
+ return r;
+ }
+
/*
* Set the internal MC address mask This is the max address of the GPU's
* internal address space.
@@ -950,6 +994,9 @@ static int gmc_v10_0_hw_init(void *handle)
if (r)
return r;
+ if (adev->umc.funcs && adev->umc.funcs->init_registers)
+ adev->umc.funcs->init_registers(adev);
+
return 0;
}
@@ -981,6 +1028,7 @@ static int gmc_v10_0_hw_fini(void *handle)
return 0;
}
+ amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
gmc_v10_0_gart_disable(adev);
--
2.17.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
2020-07-28 2:55 ` Clements, John
@ 2020-07-28 4:27 ` Chen, Guchun
0 siblings, 0 replies; 5+ messages in thread
From: Chen, Guchun @ 2020-07-28 4:27 UTC (permalink / raw)
To: Clements, John, amd-gfx list, Zhang, Hawking
[-- Attachment #1.1: Type: text/plain, Size: 1785 bytes --]
[AMD Public Use]
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Regards,
Guchun
From: Clements, John <John.Clements@amd.com>
Sent: Tuesday, July 28, 2020 10:56 AM
To: Chen, Guchun <Guchun.Chen@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: RE: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
[AMD Public Use]
Thank you for the feedback @Chen, Guchun<mailto:Guchun.Chen@amd.com>,
I've attached an updated patch with the corrected typo and also an additional change to add the new UMC source to the makefile
Thank you,
John Clements
From: Chen, Guchun <Guchun.Chen@amd.com<mailto:Guchun.Chen@amd.com>>
Sent: Monday, July 27, 2020 4:50 PM
To: Clements, John <John.Clements@amd.com<mailto:John.Clements@amd.com>>; amd-gfx list <amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>>; Zhang, Hawking <Hawking.Zhang@amd.com<mailto:Hawking.Zhang@amd.com>>
Subject: RE: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
[AMD Public Use]
One typo in commit subject.
add support for umc 8.7 initialzation and RAS interrupt
s/initialzation /initialization
With this fixed, the patch is:
Reviewed-by: Guchun Chen guchun.chen@amd.com<mailto:guchun.chen@amd.com>
Regards,
Guchun
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> On Behalf Of Clements, John
Sent: Monday, July 27, 2020 4:32 PM
To: amd-gfx list <amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>>; Zhang, Hawking <Hawking.Zhang@amd.com<mailto:Hawking.Zhang@amd.com>>
Subject: [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10
[AMD Public Use]
Submitting patch to enable UMC 8.7 GECC functions in GMC v10
[-- Attachment #1.2: Type: text/html, Size: 6868 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-07-27 8:32 [PATCH] drm/amdgpu: enable umc 8.7 functions in gmc v10 Clements, John
2020-07-27 8:50 ` Chen, Guchun
2020-07-28 2:55 ` Clements, John
2020-07-28 4:27 ` Chen, Guchun
2020-07-27 9:40 ` Christian König
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