VCE3 MGCG for Stoney/Carrizo

VCE3 MGCG for Stoney/Carrizo

[Tom St Denis]

These patches fix the MGCG initialization as well enable the
feature for Stoney and Carrizo.  Tested by inspection of the 
clock status registers and with consultation with the HW
team.


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[PATCH 1/6] drm/amd/amdgpu: fix indentation in vce3 CG

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index e5b18ad42721..26fb606e2d3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -126,6 +126,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
 					     bool gated)
 {
 	u32 tmp, data;
+
 	/* Set Override to disable Clock Gating */
 	vce_v3_0_override_vce_clock_gating(adev, true);
 
@@ -165,9 +166,9 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
 		/* Force VCE_UENC_DMA_DCLK_CTRL Clock ON */
 		tmp = data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
 		data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
-				VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
-				VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
-				0x8;
+			VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
+			VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
+			0x8;
 		if (tmp != data)
 			WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
 	} else {
@@ -201,9 +202,9 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
 		/* Set VCE_UENC_DMA_DCLK_CTRL CG always in dynamic mode */
 		tmp = data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
 		data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
-				VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
-				VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
-				0x8);
+			  VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
+			  VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
+			  0x8);
 		if (tmp != data)
 			WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
 	}
-- 
2.9.2

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[PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

[Tom St Denis]

CG was being enabled in reverse sense from dpm/powerplay.
Also fix the default CLK_EN signal to enable all of the blocks.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 26fb606e2d3e..93604bb78257 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -130,7 +130,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
 	/* Set Override to disable Clock Gating */
 	vce_v3_0_override_vce_clock_gating(adev, true);
 
-	if (!gated) {
+	if (gated) {
 		/* Force CLOCK ON for VCE_CLOCK_GATING_B,
 		 * {*_FORCE_ON, *_FORCE_OFF} = {1, 0}
 		 * VREG can be FORCE ON or set to Dynamic, but can't be OFF
@@ -153,7 +153,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
 		/* set VCE_UENC_CLOCK_GATING_2 */
 		tmp = data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
 		data |= 0x2;
-		data &= ~0x2;
+		data &= ~0x00010000;
 		if (tmp != data)
 			WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
 
@@ -538,7 +538,7 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
 	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
 	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
 	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
-	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
+	WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
 
 	WREG32(mmVCE_LMI_CTRL, 0x00398000);
 	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
-- 
2.9.2

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[PATCH 3/6] drm/amd/amdgpu: Don't set VCE CG in startup

[Tom St Denis]

It's handled by DPM/PP properly.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 93604bb78257..9d1924e4e2bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -297,10 +297,6 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
 		/* clear BUSY flag */
 		WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
 
-		/* Set Clock-Gating off */
-		if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
-			vce_v3_0_set_vce_sw_clock_gating(adev, false);
-
 		if (r) {
 			DRM_ERROR("VCE not responding, giving up!!!\n");
 			mutex_unlock(&adev->grbm_idx_mutex);
-- 
2.9.2

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[PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

[Tom St Denis]

Only issue bypass if MGCG enabled

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 9d1924e4e2bc..63c9efefa583 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -769,12 +769,12 @@ static int vce_v3_0_set_clockgating_state(void *handle,
 	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 	int i;
 
-	if (adev->asic_type == CHIP_POLARIS10)
-		vce_v3_set_bypass_mode(adev, enable);
-
 	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
 		return 0;
 
+	if (adev->asic_type == CHIP_POLARIS10)
+		vce_v3_set_bypass_mode(adev, enable);
+
 	mutex_lock(&adev->grbm_idx_mutex);
 	for (i = 0; i < 2; i++) {
 		/* Program VCE Instance 0 or 1 if not harvested */
-- 
2.9.2

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[PATCH 5/6] drm/amd/amdgpu: Enable VCE MGCG for Carrizo

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 33bad99176fe..5449a3c8c9eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1577,7 +1577,8 @@ static int vi_common_early_init(void *handle)
 			AMD_CG_SUPPORT_HDP_MGCG |
 			AMD_CG_SUPPORT_HDP_LS |
 			AMD_CG_SUPPORT_SDMA_MGCG |
-			AMD_CG_SUPPORT_SDMA_LS;
+			AMD_CG_SUPPORT_SDMA_LS |
+			AMD_CG_SUPPORT_VCE_MGCG;
 		/* rev0 hardware requires workarounds to support PG */
 		adev->pg_flags = 0;
 		if (adev->rev_id != 0x00) {
-- 
2.9.2

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[PATCH 6/6] drm/amd/amdgpu: Enable VCE MGCG for Stoney

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 5449a3c8c9eb..07ea150f85f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1605,7 +1605,8 @@ static int vi_common_early_init(void *handle)
 			AMD_CG_SUPPORT_HDP_MGCG |
 			AMD_CG_SUPPORT_HDP_LS |
 			AMD_CG_SUPPORT_SDMA_MGCG |
-			AMD_CG_SUPPORT_SDMA_LS;
+			AMD_CG_SUPPORT_SDMA_LS |
+			AMD_CG_SUPPORT_VCE_MGCG;
 		adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 			AMD_PG_SUPPORT_GFX_SMG |
 			AMD_PG_SUPPORT_GFX_PIPELINE |
-- 
2.9.2

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RE: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Wednesday, August 03, 2016 11:52 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test
> 
> Only issue bypass if MGCG enabled

NACK.  We need this for Polaris right now since we don't enable CG yet and setting bypass mode saves power.

Alex

> 
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 9d1924e4e2bc..63c9efefa583 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -769,12 +769,12 @@ static int vce_v3_0_set_clockgating_state(void
> *handle,
>  	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>  	int i;
> 
> -	if (adev->asic_type == CHIP_POLARIS10)
> -		vce_v3_set_bypass_mode(adev, enable);
> -
>  	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
>  		return 0;
> 
> +	if (adev->asic_type == CHIP_POLARIS10)
> +		vce_v3_set_bypass_mode(adev, enable);
> +
>  	mutex_lock(&adev->grbm_idx_mutex);
>  	for (i = 0; i < 2; i++) {
>  		/* Program VCE Instance 0 or 1 if not harvested */
> --
> 2.9.2
> 
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> amd-gfx@lists.freedesktop.org
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RE: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Wednesday, August 03, 2016 11:52 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume
> defaults
> 
> CG was being enabled in reverse sense from dpm/powerplay.
> Also fix the default CLK_EN signal to enable all of the blocks.
> 
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 26fb606e2d3e..93604bb78257 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -130,7 +130,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct
> amdgpu_device *adev,
>  	/* Set Override to disable Clock Gating */
>  	vce_v3_0_override_vce_clock_gating(adev, true);
> 
> -	if (!gated) {
> +	if (gated) {
>  		/* Force CLOCK ON for VCE_CLOCK_GATING_B,
>  		 * {*_FORCE_ON, *_FORCE_OFF} = {1, 0}

This doesn't make sense to me unless I'm mis-understanding the specific CG feature.  Forcing the clocks on, implies ungating, not gating.  In this case if forcing the clocks on part of the fw controlled clockgating configuration?  If so, please add a comment to that effect in the function.

Alex

>  		 * VREG can be FORCE ON or set to Dynamic, but can't be OFF
> @@ -153,7 +153,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct
> amdgpu_device *adev,
>  		/* set VCE_UENC_CLOCK_GATING_2 */
>  		tmp = data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
>  		data |= 0x2;
> -		data &= ~0x2;
> +		data &= ~0x00010000;
>  		if (tmp != data)
>  			WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
> 
> @@ -538,7 +538,7 @@ static void vce_v3_0_mc_resume(struct
> amdgpu_device *adev, int idx)
>  	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
>  	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000,
> ~0xFF9FF000);
>  	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
> -	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
> +	WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
> 
>  	WREG32(mmVCE_LMI_CTRL, 0x00398000);
>  	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
> --
> 2.9.2
> 
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Re: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

[StDenis, Tom]

[-- Attachment #1.1: Type: text/plain, Size: 2207 bytes --]

Hi Alex,


Ok, a similar change was introduced for UVD in 7a6526488b60283cec91852196a5423b1dfb14d8, should that be reverted in part too?


Tom


________________________________
From: Deucher, Alexander
Sent: Wednesday, August 3, 2016 12:27
To: 'Tom St Denis'; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: StDenis, Tom
Subject: RE: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> Of Tom St Denis
> Sent: Wednesday, August 03, 2016 11:52 AM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Cc: StDenis, Tom
> Subject: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test
>
> Only issue bypass if MGCG enabled

NACK.  We need this for Polaris right now since we don't enable CG yet and setting bypass mode saves power.

Alex

>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 9d1924e4e2bc..63c9efefa583 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -769,12 +769,12 @@ static int vce_v3_0_set_clockgating_state(void
> *handle,
>        bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>        int i;
>
> -     if (adev->asic_type == CHIP_POLARIS10)
> -             vce_v3_set_bypass_mode(adev, enable);
> -
>        if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
>                return 0;
>
> +     if (adev->asic_type == CHIP_POLARIS10)
> +             vce_v3_set_bypass_mode(adev, enable);
> +
>        mutex_lock(&adev->grbm_idx_mutex);
>        for (i = 0; i < 2; i++) {
>                /* Program VCE Instance 0 or 1 if not harvested */
> --
> 2.9.2
>
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[-- Attachment #1.2: Type: text/html, Size: 4124 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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RE: VCE3 MGCG for Stoney/Carrizo

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Wednesday, August 03, 2016 11:52 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: VCE3 MGCG for Stoney/Carrizo
> 
> These patches fix the MGCG initialization as well enable the
> feature for Stoney and Carrizo.  Tested by inspection of the
> clock status registers and with consultation with the HW
> team.

Comments on 2, 4.  The rest are:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> 
> 
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Re: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

[StDenis, Tom]

[-- Attachment #1.1: Type: text/plain, Size: 3473 bytes --]

The logic is a bit confusing at first.  "gated" means that SW CG is enabled not that the clocks are turned off.  When I sampled the registers in the original configuration the clocks were reading 100% when the core was active.  It would read 0% when idle but only because power was gated.


With the logic the way it is when the core is active I see many of the clocks throttle as they should.


Tom


________________________________
From: Deucher, Alexander
Sent: Wednesday, August 3, 2016 12:28
To: 'Tom St Denis'; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: StDenis, Tom
Subject: RE: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> Of Tom St Denis
> Sent: Wednesday, August 03, 2016 11:52 AM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Cc: StDenis, Tom
> Subject: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume
> defaults
>
> CG was being enabled in reverse sense from dpm/powerplay.
> Also fix the default CLK_EN signal to enable all of the blocks.
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 26fb606e2d3e..93604bb78257 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -130,7 +130,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct
> amdgpu_device *adev,
>        /* Set Override to disable Clock Gating */
>        vce_v3_0_override_vce_clock_gating(adev, true);
>
> -     if (!gated) {
> +     if (gated) {
>                /* Force CLOCK ON for VCE_CLOCK_GATING_B,
>                 * {*_FORCE_ON, *_FORCE_OFF} = {1, 0}

This doesn't make sense to me unless I'm mis-understanding the specific CG feature.  Forcing the clocks on, implies ungating, not gating.  In this case if forcing the clocks on part of the fw controlled clockgating configuration?  If so, please add a comment to that effect in the function.

Alex

>                 * VREG can be FORCE ON or set to Dynamic, but can't be OFF
> @@ -153,7 +153,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct
> amdgpu_device *adev,
>                /* set VCE_UENC_CLOCK_GATING_2 */
>                tmp = data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
>                data |= 0x2;
> -             data &= ~0x2;
> +             data &= ~0x00010000;
>                if (tmp != data)
>                        WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
>
> @@ -538,7 +538,7 @@ static void vce_v3_0_mc_resume(struct
> amdgpu_device *adev, int idx)
>        WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
>        WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000,
> ~0xFF9FF000);
>        WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
> -     WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
> +     WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
>
>        WREG32(mmVCE_LMI_CTRL, 0x00398000);
>        WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
> --
> 2.9.2
>
> _______________________________________________
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> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
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RE: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

[Deucher, Alexander]

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Yes, please.

Thanks,

Alex

From: StDenis, Tom
Sent: Wednesday, August 03, 2016 12:29 PM
To: Deucher, Alexander; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test


Hi Alex,



Ok, a similar change was introduced for UVD in 7a6526488b60283cec91852196a5423b1dfb14d8, should that be reverted in part too?



Tom

________________________________
From: Deucher, Alexander
Sent: Wednesday, August 3, 2016 12:27
To: 'Tom St Denis'; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32mptlylMvRsHA@public.gmane.orgdesktop.org>
Cc: StDenis, Tom
Subject: RE: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> Of Tom St Denis
> Sent: Wednesday, August 03, 2016 11:52 AM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> Cc: StDenis, Tom
> Subject: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test
>
> Only issue bypass if MGCG enabled

NACK.  We need this for Polaris right now since we don't enable CG yet and setting bypass mode saves power.

Alex

>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org<mailto:tom.stdenis@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 9d1924e4e2bc..63c9efefa583 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -769,12 +769,12 @@ static int vce_v3_0_set_clockgating_state(void
> *handle,
>        bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>        int i;
>
> -     if (adev->asic_type == CHIP_POLARIS10)
> -             vce_v3_set_bypass_mode(adev, enable);
> -
>        if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
>                return 0;
>
> +     if (adev->asic_type == CHIP_POLARIS10)
> +             vce_v3_set_bypass_mode(adev, enable);
> +
>        mutex_lock(&adev->grbm_idx_mutex);
>        for (i = 0; i < 2; i++) {
>                /* Program VCE Instance 0 or 1 if not harvested */
> --
> 2.9.2
>
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> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
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RE: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

[Deucher, Alexander]

[-- Attachment #1.1: Type: text/plain, Size: 4080 bytes --]

Maybe add a comment to that effect.  With that added,  this patch is:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

From: StDenis, Tom
Sent: Wednesday, August 03, 2016 12:31 PM
To: Deucher, Alexander; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults


The logic is a bit confusing at first.  "gated" means that SW CG is enabled not that the clocks are turned off.  When I sampled the registers in the original configuration the clocks were reading 100% when the core was active.  It would read 0% when idle but only because power was gated.



With the logic the way it is when the core is active I see many of the clocks throttle as they should.



Tom

________________________________
From: Deucher, Alexander
Sent: Wednesday, August 3, 2016 12:28
To: 'Tom St Denis'; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32mptlylMvRsHA@public.gmane.orgdesktop.org>
Cc: StDenis, Tom
Subject: RE: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> Of Tom St Denis
> Sent: Wednesday, August 03, 2016 11:52 AM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> Cc: StDenis, Tom
> Subject: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume
> defaults
>
> CG was being enabled in reverse sense from dpm/powerplay.
> Also fix the default CLK_EN signal to enable all of the blocks.
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org<mailto:tom.stdenis@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 26fb606e2d3e..93604bb78257 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -130,7 +130,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct
> amdgpu_device *adev,
>        /* Set Override to disable Clock Gating */
>        vce_v3_0_override_vce_clock_gating(adev, true);
>
> -     if (!gated) {
> +     if (gated) {
>                /* Force CLOCK ON for VCE_CLOCK_GATING_B,
>                 * {*_FORCE_ON, *_FORCE_OFF} = {1, 0}

This doesn't make sense to me unless I'm mis-understanding the specific CG feature.  Forcing the clocks on, implies ungating, not gating.  In this case if forcing the clocks on part of the fw controlled clockgating configuration?  If so, please add a comment to that effect in the function.

Alex

>                 * VREG can be FORCE ON or set to Dynamic, but can't be OFF
> @@ -153,7 +153,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct
> amdgpu_device *adev,
>                /* set VCE_UENC_CLOCK_GATING_2 */
>                tmp = data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
>                data |= 0x2;
> -             data &= ~0x2;
> +             data &= ~0x00010000;
>                if (tmp != data)
>                        WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
>
> @@ -538,7 +538,7 @@ static void vce_v3_0_mc_resume(struct
> amdgpu_device *adev, int idx)
>        WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
>        WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000,
> ~0xFF9FF000);
>        WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
> -     WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
> +     WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
>
>        WREG32(mmVCE_LMI_CTRL, 0x00398000);
>        WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
> --
> 2.9.2
>
> _______________________________________________
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> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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Re: [PATCH 1/6] drm/amd/amdgpu: fix indentation in vce3 CG

[Christian König]

Am 03.08.2016 um 17:51 schrieb Tom St Denis:
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>

This one is Reviewed-by: Christian König <christian.koenig@amd.com>.

For the rest I'm not deep enough into the topic to judge.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 13 +++++++------
>   1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index e5b18ad42721..26fb606e2d3e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -126,6 +126,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
>   					     bool gated)
>   {
>   	u32 tmp, data;
> +
>   	/* Set Override to disable Clock Gating */
>   	vce_v3_0_override_vce_clock_gating(adev, true);
>   
> @@ -165,9 +166,9 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
>   		/* Force VCE_UENC_DMA_DCLK_CTRL Clock ON */
>   		tmp = data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
>   		data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
> -				VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
> -				VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
> -				0x8;
> +			VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
> +			VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
> +			0x8;
>   		if (tmp != data)
>   			WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
>   	} else {
> @@ -201,9 +202,9 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
>   		/* Set VCE_UENC_DMA_DCLK_CTRL CG always in dynamic mode */
>   		tmp = data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
>   		data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
> -				VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
> -				VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
> -				0x8);
> +			  VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
> +			  VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
> +			  0x8);
>   		if (tmp != data)
>   			WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
>   	}


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