* [PATCH 1/4] drm/amd/pp: Move helper functions to smu_help.c
@ 2018-03-12 12:34 Rex Zhu
[not found] ` <1520858050-7338-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 9+ messages in thread
From: Rex Zhu @ 2018-03-12 12:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 513 +---------------------
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 536 +++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h | 180 ++++++++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 155 +------
5 files changed, 723 insertions(+), 663 deletions(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 1fa9a97..455e572 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -31,7 +31,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
smu7_clockpowergating.o \
vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
vega10_thermal.o smu10_hwmgr.o pp_psm.o\
- pp_overdriver.o
+ pp_overdriver.o smu_helper.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 3432dc0..5563b65 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -30,8 +30,6 @@
#include <drm/amdgpu_drm.h>
#include "power_state.h"
#include "hwmgr.h"
-#include "pppcielanes.h"
-#include "ppatomctrl.h"
#include "ppsmc.h"
#include "amd_acpi.h"
#include "pp_psm.h"
@@ -45,7 +43,11 @@
extern const struct pp_smumgr_func vega10_smu_funcs;
extern const struct pp_smumgr_func smu10_smu_funcs;
+extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);
+extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
+extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
+
static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
@@ -54,32 +56,6 @@
static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
-uint8_t convert_to_vid(uint16_t vddc)
-{
- return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
-}
-
-uint16_t convert_to_vddc(uint8_t vid)
-{
- return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE);
-}
-
-uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)
-{
- u32 mask = 0;
- u32 shift = 0;
-
- shift = (offset % 4) << 3;
- if (size == sizeof(uint8_t))
- mask = 0xFF << shift;
- else if (size == sizeof(uint16_t))
- mask = 0xFFFF << shift;
-
- original_data &= ~mask;
- original_data |= (field << shift);
- return original_data;
-}
-
static int phm_thermal_l2h_irq(void *private_data,
unsigned src_id, const uint32_t *iv_entry)
{
@@ -432,468 +408,6 @@ int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id,
}
return ret;
}
-/**
- * Returns once the part of the register indicated by the mask has
- * reached the given value.
- */
-int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
- uint32_t value, uint32_t mask)
-{
- uint32_t i;
- uint32_t cur_value;
-
- if (hwmgr == NULL || hwmgr->device == NULL) {
- pr_err("Invalid Hardware Manager!");
- return -EINVAL;
- }
-
- for (i = 0; i < hwmgr->usec_timeout; i++) {
- cur_value = cgs_read_register(hwmgr->device, index);
- if ((cur_value & mask) == (value & mask))
- break;
- udelay(1);
- }
-
- /* timeout means wrong logic*/
- if (i == hwmgr->usec_timeout)
- return -1;
- return 0;
-}
-
-
-/**
- * Returns once the part of the register indicated by the mask has
- * reached the given value.The indirect space is described by giving
- * the memory-mapped index of the indirect index register.
- */
-int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
- uint32_t indirect_port,
- uint32_t index,
- uint32_t value,
- uint32_t mask)
-{
- if (hwmgr == NULL || hwmgr->device == NULL) {
- pr_err("Invalid Hardware Manager!");
- return -EINVAL;
- }
-
- cgs_write_register(hwmgr->device, indirect_port, index);
- return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
-}
-
-int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
- uint32_t index,
- uint32_t value, uint32_t mask)
-{
- uint32_t i;
- uint32_t cur_value;
-
- if (hwmgr == NULL || hwmgr->device == NULL)
- return -EINVAL;
-
- for (i = 0; i < hwmgr->usec_timeout; i++) {
- cur_value = cgs_read_register(hwmgr->device,
- index);
- if ((cur_value & mask) != (value & mask))
- break;
- udelay(1);
- }
-
- /* timeout means wrong logic */
- if (i == hwmgr->usec_timeout)
- return -ETIME;
- return 0;
-}
-
-int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
- uint32_t indirect_port,
- uint32_t index,
- uint32_t value,
- uint32_t mask)
-{
- if (hwmgr == NULL || hwmgr->device == NULL)
- return -EINVAL;
-
- cgs_write_register(hwmgr->device, indirect_port, index);
- return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
- value, mask);
-}
-
-bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
-{
- return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
-}
-
-bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
-{
- return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
-}
-
-
-int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
-{
- uint32_t i, j;
- uint16_t vvalue;
- bool found = false;
- struct pp_atomctrl_voltage_table *table;
-
- PP_ASSERT_WITH_CODE((NULL != vol_table),
- "Voltage Table empty.", return -EINVAL);
-
- table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
- GFP_KERNEL);
-
- if (NULL == table)
- return -EINVAL;
-
- table->mask_low = vol_table->mask_low;
- table->phase_delay = vol_table->phase_delay;
-
- for (i = 0; i < vol_table->count; i++) {
- vvalue = vol_table->entries[i].value;
- found = false;
-
- for (j = 0; j < table->count; j++) {
- if (vvalue == table->entries[j].value) {
- found = true;
- break;
- }
- }
-
- if (!found) {
- table->entries[table->count].value = vvalue;
- table->entries[table->count].smio_low =
- vol_table->entries[i].smio_low;
- table->count++;
- }
- }
-
- memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
- kfree(table);
- table = NULL;
- return 0;
-}
-
-int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
- phm_ppt_v1_clock_voltage_dependency_table *dep_table)
-{
- uint32_t i;
- int result;
-
- PP_ASSERT_WITH_CODE((0 != dep_table->count),
- "Voltage Dependency Table empty.", return -EINVAL);
-
- PP_ASSERT_WITH_CODE((NULL != vol_table),
- "vol_table empty.", return -EINVAL);
-
- vol_table->mask_low = 0;
- vol_table->phase_delay = 0;
- vol_table->count = dep_table->count;
-
- for (i = 0; i < dep_table->count; i++) {
- vol_table->entries[i].value = dep_table->entries[i].mvdd;
- vol_table->entries[i].smio_low = 0;
- }
-
- result = phm_trim_voltage_table(vol_table);
- PP_ASSERT_WITH_CODE((0 == result),
- "Failed to trim MVDD table.", return result);
-
- return 0;
-}
-
-int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
- phm_ppt_v1_clock_voltage_dependency_table *dep_table)
-{
- uint32_t i;
- int result;
-
- PP_ASSERT_WITH_CODE((0 != dep_table->count),
- "Voltage Dependency Table empty.", return -EINVAL);
-
- PP_ASSERT_WITH_CODE((NULL != vol_table),
- "vol_table empty.", return -EINVAL);
-
- vol_table->mask_low = 0;
- vol_table->phase_delay = 0;
- vol_table->count = dep_table->count;
-
- for (i = 0; i < dep_table->count; i++) {
- vol_table->entries[i].value = dep_table->entries[i].vddci;
- vol_table->entries[i].smio_low = 0;
- }
-
- result = phm_trim_voltage_table(vol_table);
- PP_ASSERT_WITH_CODE((0 == result),
- "Failed to trim VDDCI table.", return result);
-
- return 0;
-}
-
-int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
- phm_ppt_v1_voltage_lookup_table *lookup_table)
-{
- int i = 0;
-
- PP_ASSERT_WITH_CODE((0 != lookup_table->count),
- "Voltage Lookup Table empty.", return -EINVAL);
-
- PP_ASSERT_WITH_CODE((NULL != vol_table),
- "vol_table empty.", return -EINVAL);
-
- vol_table->mask_low = 0;
- vol_table->phase_delay = 0;
-
- vol_table->count = lookup_table->count;
-
- for (i = 0; i < vol_table->count; i++) {
- vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
- vol_table->entries[i].smio_low = 0;
- }
-
- return 0;
-}
-
-void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,
- struct pp_atomctrl_voltage_table *vol_table)
-{
- unsigned int i, diff;
-
- if (vol_table->count <= max_vol_steps)
- return;
-
- diff = vol_table->count - max_vol_steps;
-
- for (i = 0; i < max_vol_steps; i++)
- vol_table->entries[i] = vol_table->entries[i + diff];
-
- vol_table->count = max_vol_steps;
-
- return;
-}
-
-int phm_reset_single_dpm_table(void *table,
- uint32_t count, int max)
-{
- int i;
-
- struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-
- dpm_table->count = count > max ? max : count;
-
- for (i = 0; i < dpm_table->count; i++)
- dpm_table->dpm_level[i].enabled = false;
-
- return 0;
-}
-
-void phm_setup_pcie_table_entry(
- void *table,
- uint32_t index, uint32_t pcie_gen,
- uint32_t pcie_lanes)
-{
- struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
- dpm_table->dpm_level[index].value = pcie_gen;
- dpm_table->dpm_level[index].param1 = pcie_lanes;
- dpm_table->dpm_level[index].enabled = 1;
-}
-
-int32_t phm_get_dpm_level_enable_mask_value(void *table)
-{
- int32_t i;
- int32_t mask = 0;
- struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-
- for (i = dpm_table->count; i > 0; i--) {
- mask = mask << 1;
- if (dpm_table->dpm_level[i - 1].enabled)
- mask |= 0x1;
- else
- mask &= 0xFFFFFFFE;
- }
-
- return mask;
-}
-
-uint8_t phm_get_voltage_index(
- struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
-{
- uint8_t count = (uint8_t) (lookup_table->count);
- uint8_t i;
-
- PP_ASSERT_WITH_CODE((NULL != lookup_table),
- "Lookup Table empty.", return 0);
- PP_ASSERT_WITH_CODE((0 != count),
- "Lookup Table empty.", return 0);
-
- for (i = 0; i < lookup_table->count; i++) {
- /* find first voltage equal or bigger than requested */
- if (lookup_table->entries[i].us_vdd >= voltage)
- return i;
- }
- /* voltage is bigger than max voltage in the table */
- return i - 1;
-}
-
-uint8_t phm_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
- uint32_t voltage)
-{
- uint8_t count = (uint8_t) (voltage_table->count);
- uint8_t i = 0;
-
- PP_ASSERT_WITH_CODE((NULL != voltage_table),
- "Voltage Table empty.", return 0;);
- PP_ASSERT_WITH_CODE((0 != count),
- "Voltage Table empty.", return 0;);
-
- for (i = 0; i < count; i++) {
- /* find first voltage bigger than requested */
- if (voltage_table->entries[i].value >= voltage)
- return i;
- }
-
- /* voltage is bigger than max voltage in the table */
- return i - 1;
-}
-
-uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
-{
- uint32_t i;
-
- for (i = 0; i < vddci_table->count; i++) {
- if (vddci_table->entries[i].value >= vddci)
- return vddci_table->entries[i].value;
- }
-
- pr_debug("vddci is larger than max value in vddci_table\n");
- return vddci_table->entries[i-1].value;
-}
-
-int phm_find_boot_level(void *table,
- uint32_t value, uint32_t *boot_level)
-{
- int result = -EINVAL;
- uint32_t i;
- struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-
- for (i = 0; i < dpm_table->count; i++) {
- if (value == dpm_table->dpm_level[i].value) {
- *boot_level = i;
- result = 0;
- }
- }
-
- return result;
-}
-
-int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
- phm_ppt_v1_voltage_lookup_table *lookup_table,
- uint16_t virtual_voltage_id, int32_t *sclk)
-{
- uint8_t entry_id;
- uint8_t voltage_id;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
-
- /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
- for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
- voltage_id = table_info->vdd_dep_on_sclk->entries[entry_id].vddInd;
- if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
- break;
- }
-
- if (entry_id >= table_info->vdd_dep_on_sclk->count) {
- pr_debug("Can't find requested voltage id in vdd_dep_on_sclk table\n");
- return -EINVAL;
- }
-
- *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk;
-
- return 0;
-}
-
-/**
- * Initialize Dynamic State Adjustment Rule Settings
- *
- * @param hwmgr the address of the powerplay hardware manager.
- */
-int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
-{
- uint32_t table_size;
- struct phm_clock_voltage_dependency_table *table_clk_vlt;
- struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- /* initialize vddc_dep_on_dal_pwrl table */
- table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
- table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
-
- if (NULL == table_clk_vlt) {
- pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n");
- return -ENOMEM;
- } else {
- table_clk_vlt->count = 4;
- table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
- table_clk_vlt->entries[0].v = 0;
- table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
- table_clk_vlt->entries[1].v = 720;
- table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
- table_clk_vlt->entries[2].v = 810;
- table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
- table_clk_vlt->entries[3].v = 900;
- if (pptable_info != NULL)
- pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
- hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
- }
-
- return 0;
-}
-
-uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
-{
- uint32_t level = 0;
-
- while (0 == (mask & (1 << level)))
- level++;
-
- return level;
-}
-
-void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-{
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)hwmgr->pptable;
- struct phm_clock_voltage_dependency_table *table =
- table_info->vddc_dep_on_dal_pwrl;
- struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
- enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
- uint32_t req_vddc = 0, req_volt, i;
-
- if (!table || table->count <= 0
- || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW
- || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE)
- return;
-
- for (i = 0; i < table->count; i++) {
- if (dal_power_level == table->entries[i].clk) {
- req_vddc = table->entries[i].v;
- break;
- }
- }
-
- vddc_table = table_info->vdd_dep_on_sclk;
- for (i = 0; i < vddc_table->count; i++) {
- if (req_vddc <= vddc_table->entries[i].vddc) {
- req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_VddC_Request, req_volt);
- return;
- }
- }
- pr_err("DAL requested level can not"
- " found a available voltage in VDDC DPM Table \n");
-}
void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
{
@@ -954,25 +468,6 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
return 0;
}
-int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
- uint32_t sclk, uint16_t id, uint16_t *voltage)
-{
- uint32_t vol;
- int ret = 0;
-
- if (hwmgr->chip_id < CHIP_TONGA) {
- ret = atomctrl_get_voltage_evv(hwmgr, id, voltage);
- } else if (hwmgr->chip_id < CHIP_POLARIS10) {
- ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
- if (*voltage >= 2000 || *voltage == 0)
- *voltage = 1150;
- } else {
- ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
- *voltage = (uint16_t)(vol/100);
- }
- return ret;
-}
-
int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
new file mode 100644
index 0000000..e11daf5
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -0,0 +1,536 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "hwmgr.h"
+#include "pp_debug.h"
+#include "ppatomctrl.h"
+#include "ppsmc.h"
+
+uint8_t convert_to_vid(uint16_t vddc)
+{
+ return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
+}
+
+uint16_t convert_to_vddc(uint8_t vid)
+{
+ return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE);
+}
+
+uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)
+{
+ u32 mask = 0;
+ u32 shift = 0;
+
+ shift = (offset % 4) << 3;
+ if (size == sizeof(uint8_t))
+ mask = 0xFF << shift;
+ else if (size == sizeof(uint16_t))
+ mask = 0xFFFF << shift;
+
+ original_data &= ~mask;
+ original_data |= (field << shift);
+ return original_data;
+}
+
+/**
+ * Returns once the part of the register indicated by the mask has
+ * reached the given value.
+ */
+int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
+ uint32_t value, uint32_t mask)
+{
+ uint32_t i;
+ uint32_t cur_value;
+
+ if (hwmgr == NULL || hwmgr->device == NULL) {
+ pr_err("Invalid Hardware Manager!");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < hwmgr->usec_timeout; i++) {
+ cur_value = cgs_read_register(hwmgr->device, index);
+ if ((cur_value & mask) == (value & mask))
+ break;
+ udelay(1);
+ }
+
+ /* timeout means wrong logic*/
+ if (i == hwmgr->usec_timeout)
+ return -1;
+ return 0;
+}
+
+
+/**
+ * Returns once the part of the register indicated by the mask has
+ * reached the given value.The indirect space is described by giving
+ * the memory-mapped index of the indirect index register.
+ */
+int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port,
+ uint32_t index,
+ uint32_t value,
+ uint32_t mask)
+{
+ if (hwmgr == NULL || hwmgr->device == NULL) {
+ pr_err("Invalid Hardware Manager!");
+ return -EINVAL;
+ }
+
+ cgs_write_register(hwmgr->device, indirect_port, index);
+ return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
+}
+
+int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t index,
+ uint32_t value, uint32_t mask)
+{
+ uint32_t i;
+ uint32_t cur_value;
+
+ if (hwmgr == NULL || hwmgr->device == NULL)
+ return -EINVAL;
+
+ for (i = 0; i < hwmgr->usec_timeout; i++) {
+ cur_value = cgs_read_register(hwmgr->device,
+ index);
+ if ((cur_value & mask) != (value & mask))
+ break;
+ udelay(1);
+ }
+
+ /* timeout means wrong logic */
+ if (i == hwmgr->usec_timeout)
+ return -ETIME;
+ return 0;
+}
+
+int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port,
+ uint32_t index,
+ uint32_t value,
+ uint32_t mask)
+{
+ if (hwmgr == NULL || hwmgr->device == NULL)
+ return -EINVAL;
+
+ cgs_write_register(hwmgr->device, indirect_port, index);
+ return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
+ value, mask);
+}
+
+bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
+{
+ return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
+}
+
+bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
+{
+ return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
+}
+
+
+int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
+{
+ uint32_t i, j;
+ uint16_t vvalue;
+ bool found = false;
+ struct pp_atomctrl_voltage_table *table;
+
+ PP_ASSERT_WITH_CODE((NULL != vol_table),
+ "Voltage Table empty.", return -EINVAL);
+
+ table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
+ GFP_KERNEL);
+
+ if (NULL == table)
+ return -EINVAL;
+
+ table->mask_low = vol_table->mask_low;
+ table->phase_delay = vol_table->phase_delay;
+
+ for (i = 0; i < vol_table->count; i++) {
+ vvalue = vol_table->entries[i].value;
+ found = false;
+
+ for (j = 0; j < table->count; j++) {
+ if (vvalue == table->entries[j].value) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ table->entries[table->count].value = vvalue;
+ table->entries[table->count].smio_low =
+ vol_table->entries[i].smio_low;
+ table->count++;
+ }
+ }
+
+ memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
+ kfree(table);
+ table = NULL;
+ return 0;
+}
+
+int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
+ phm_ppt_v1_clock_voltage_dependency_table *dep_table)
+{
+ uint32_t i;
+ int result;
+
+ PP_ASSERT_WITH_CODE((0 != dep_table->count),
+ "Voltage Dependency Table empty.", return -EINVAL);
+
+ PP_ASSERT_WITH_CODE((NULL != vol_table),
+ "vol_table empty.", return -EINVAL);
+
+ vol_table->mask_low = 0;
+ vol_table->phase_delay = 0;
+ vol_table->count = dep_table->count;
+
+ for (i = 0; i < dep_table->count; i++) {
+ vol_table->entries[i].value = dep_table->entries[i].mvdd;
+ vol_table->entries[i].smio_low = 0;
+ }
+
+ result = phm_trim_voltage_table(vol_table);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Failed to trim MVDD table.", return result);
+
+ return 0;
+}
+
+int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
+ phm_ppt_v1_clock_voltage_dependency_table *dep_table)
+{
+ uint32_t i;
+ int result;
+
+ PP_ASSERT_WITH_CODE((0 != dep_table->count),
+ "Voltage Dependency Table empty.", return -EINVAL);
+
+ PP_ASSERT_WITH_CODE((NULL != vol_table),
+ "vol_table empty.", return -EINVAL);
+
+ vol_table->mask_low = 0;
+ vol_table->phase_delay = 0;
+ vol_table->count = dep_table->count;
+
+ for (i = 0; i < dep_table->count; i++) {
+ vol_table->entries[i].value = dep_table->entries[i].vddci;
+ vol_table->entries[i].smio_low = 0;
+ }
+
+ result = phm_trim_voltage_table(vol_table);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Failed to trim VDDCI table.", return result);
+
+ return 0;
+}
+
+int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
+ phm_ppt_v1_voltage_lookup_table *lookup_table)
+{
+ int i = 0;
+
+ PP_ASSERT_WITH_CODE((0 != lookup_table->count),
+ "Voltage Lookup Table empty.", return -EINVAL);
+
+ PP_ASSERT_WITH_CODE((NULL != vol_table),
+ "vol_table empty.", return -EINVAL);
+
+ vol_table->mask_low = 0;
+ vol_table->phase_delay = 0;
+
+ vol_table->count = lookup_table->count;
+
+ for (i = 0; i < vol_table->count; i++) {
+ vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
+ vol_table->entries[i].smio_low = 0;
+ }
+
+ return 0;
+}
+
+void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,
+ struct pp_atomctrl_voltage_table *vol_table)
+{
+ unsigned int i, diff;
+
+ if (vol_table->count <= max_vol_steps)
+ return;
+
+ diff = vol_table->count - max_vol_steps;
+
+ for (i = 0; i < max_vol_steps; i++)
+ vol_table->entries[i] = vol_table->entries[i + diff];
+
+ vol_table->count = max_vol_steps;
+
+ return;
+}
+
+int phm_reset_single_dpm_table(void *table,
+ uint32_t count, int max)
+{
+ int i;
+
+ struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
+
+ dpm_table->count = count > max ? max : count;
+
+ for (i = 0; i < dpm_table->count; i++)
+ dpm_table->dpm_level[i].enabled = false;
+
+ return 0;
+}
+
+void phm_setup_pcie_table_entry(
+ void *table,
+ uint32_t index, uint32_t pcie_gen,
+ uint32_t pcie_lanes)
+{
+ struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
+ dpm_table->dpm_level[index].value = pcie_gen;
+ dpm_table->dpm_level[index].param1 = pcie_lanes;
+ dpm_table->dpm_level[index].enabled = 1;
+}
+
+int32_t phm_get_dpm_level_enable_mask_value(void *table)
+{
+ int32_t i;
+ int32_t mask = 0;
+ struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
+
+ for (i = dpm_table->count; i > 0; i--) {
+ mask = mask << 1;
+ if (dpm_table->dpm_level[i - 1].enabled)
+ mask |= 0x1;
+ else
+ mask &= 0xFFFFFFFE;
+ }
+
+ return mask;
+}
+
+uint8_t phm_get_voltage_index(
+ struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
+{
+ uint8_t count = (uint8_t) (lookup_table->count);
+ uint8_t i;
+
+ PP_ASSERT_WITH_CODE((NULL != lookup_table),
+ "Lookup Table empty.", return 0);
+ PP_ASSERT_WITH_CODE((0 != count),
+ "Lookup Table empty.", return 0);
+
+ for (i = 0; i < lookup_table->count; i++) {
+ /* find first voltage equal or bigger than requested */
+ if (lookup_table->entries[i].us_vdd >= voltage)
+ return i;
+ }
+ /* voltage is bigger than max voltage in the table */
+ return i - 1;
+}
+
+uint8_t phm_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
+ uint32_t voltage)
+{
+ uint8_t count = (uint8_t) (voltage_table->count);
+ uint8_t i = 0;
+
+ PP_ASSERT_WITH_CODE((NULL != voltage_table),
+ "Voltage Table empty.", return 0;);
+ PP_ASSERT_WITH_CODE((0 != count),
+ "Voltage Table empty.", return 0;);
+
+ for (i = 0; i < count; i++) {
+ /* find first voltage bigger than requested */
+ if (voltage_table->entries[i].value >= voltage)
+ return i;
+ }
+
+ /* voltage is bigger than max voltage in the table */
+ return i - 1;
+}
+
+uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
+{
+ uint32_t i;
+
+ for (i = 0; i < vddci_table->count; i++) {
+ if (vddci_table->entries[i].value >= vddci)
+ return vddci_table->entries[i].value;
+ }
+
+ pr_debug("vddci is larger than max value in vddci_table\n");
+ return vddci_table->entries[i-1].value;
+}
+
+int phm_find_boot_level(void *table,
+ uint32_t value, uint32_t *boot_level)
+{
+ int result = -EINVAL;
+ uint32_t i;
+ struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
+
+ for (i = 0; i < dpm_table->count; i++) {
+ if (value == dpm_table->dpm_level[i].value) {
+ *boot_level = i;
+ result = 0;
+ }
+ }
+
+ return result;
+}
+
+int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
+ phm_ppt_v1_voltage_lookup_table *lookup_table,
+ uint16_t virtual_voltage_id, int32_t *sclk)
+{
+ uint8_t entry_id;
+ uint8_t voltage_id;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
+
+ /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
+ for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
+ voltage_id = table_info->vdd_dep_on_sclk->entries[entry_id].vddInd;
+ if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
+ break;
+ }
+
+ if (entry_id >= table_info->vdd_dep_on_sclk->count) {
+ pr_debug("Can't find requested voltage id in vdd_dep_on_sclk table\n");
+ return -EINVAL;
+ }
+
+ *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk;
+
+ return 0;
+}
+
+/**
+ * Initialize Dynamic State Adjustment Rule Settings
+ *
+ * @param hwmgr the address of the powerplay hardware manager.
+ */
+int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
+{
+ uint32_t table_size;
+ struct phm_clock_voltage_dependency_table *table_clk_vlt;
+ struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ /* initialize vddc_dep_on_dal_pwrl table */
+ table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
+ table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
+
+ if (NULL == table_clk_vlt) {
+ pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n");
+ return -ENOMEM;
+ } else {
+ table_clk_vlt->count = 4;
+ table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
+ table_clk_vlt->entries[0].v = 0;
+ table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
+ table_clk_vlt->entries[1].v = 720;
+ table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
+ table_clk_vlt->entries[2].v = 810;
+ table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
+ table_clk_vlt->entries[3].v = 900;
+ if (pptable_info != NULL)
+ pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
+ hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
+ }
+
+ return 0;
+}
+
+uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
+{
+ uint32_t level = 0;
+
+ while (0 == (mask & (1 << level)))
+ level++;
+
+ return level;
+}
+
+void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
+{
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)hwmgr->pptable;
+ struct phm_clock_voltage_dependency_table *table =
+ table_info->vddc_dep_on_dal_pwrl;
+ struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
+ enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
+ uint32_t req_vddc = 0, req_volt, i;
+
+ if (!table || table->count <= 0
+ || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW
+ || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE)
+ return;
+
+ for (i = 0; i < table->count; i++) {
+ if (dal_power_level == table->entries[i].clk) {
+ req_vddc = table->entries[i].v;
+ break;
+ }
+ }
+
+ vddc_table = table_info->vdd_dep_on_sclk;
+ for (i = 0; i < vddc_table->count; i++) {
+ if (req_vddc <= vddc_table->entries[i].vddc) {
+ req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_VddC_Request, req_volt);
+ return;
+ }
+ }
+ pr_err("DAL requested level can not"
+ " found a available voltage in VDDC DPM Table \n");
+}
+
+int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+ uint32_t sclk, uint16_t id, uint16_t *voltage)
+{
+ uint32_t vol;
+ int ret = 0;
+
+ if (hwmgr->chip_id < CHIP_TONGA) {
+ ret = atomctrl_get_voltage_evv(hwmgr, id, voltage);
+ } else if (hwmgr->chip_id < CHIP_POLARIS10) {
+ ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
+ if (*voltage >= 2000 || *voltage == 0)
+ *voltage = 1150;
+ } else {
+ ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
+ *voltage = (uint16_t)(vol/100);
+ }
+ return ret;
+}
+
+
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
new file mode 100644
index 0000000..a1a4913
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _SMU_HELPER_H_
+#define _SMU_HELPER_H_
+
+struct pp_atomctrl_voltage_table;
+struct pp_hwmgr;
+struct phm_ppt_v1_voltage_lookup_table;
+
+extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t index,
+ uint32_t value, uint32_t mask);
+extern int phm_wait_for_indirect_register_unequal(
+ struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port, uint32_t index,
+ uint32_t value, uint32_t mask);
+
+
+extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
+extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
+extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
+
+extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
+extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
+extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
+extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
+extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
+extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
+extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
+extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
+extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
+ uint32_t voltage);
+extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
+extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
+extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
+extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
+ uint16_t virtual_voltage_id, int32_t *sclk);
+extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
+extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
+extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
+
+extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+ uint32_t sclk, uint16_t id, uint16_t *voltage);
+
+extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);
+
+extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
+ uint32_t value, uint32_t mask);
+
+extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port,
+ uint32_t index,
+ uint32_t value,
+ uint32_t mask);
+
+#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
+#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
+
+#define PHM_SET_FIELD(origval, reg, field, fieldval) \
+ (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
+ (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
+
+#define PHM_GET_FIELD(value, reg, field) \
+ (((value) & PHM_FIELD_MASK(reg, field)) >> \
+ PHM_FIELD_SHIFT(reg, field))
+
+
+/* Operations on named fields. */
+
+#define PHM_READ_FIELD(device, reg, field) \
+ PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
+
+#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
+ PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
+ reg, field)
+
+#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
+ PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
+ reg, field)
+
+#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
+ cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
+ cgs_read_register(device, mm##reg), reg, field, fieldval))
+
+#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
+ cgs_write_ind_register(device, port, ix##reg, \
+ PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
+ reg, field, fieldval))
+
+#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
+ cgs_write_ind_register(device, port, ix##reg, \
+ PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
+ reg, field, fieldval))
+
+#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
+ phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
+
+
+#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
+ << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
+
+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
+ phm_wait_for_indirect_register_unequal(hwmgr, \
+ mm##port##_INDEX, index, value, mask)
+
+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field) )
+
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ port, index, value, mask) \
+ phm_wait_for_indirect_register_unequal(hwmgr, \
+ mm##port##_INDEX_11, index, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
+
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
+ port, index, value, mask) \
+ phm_wait_on_indirect_register(hwmgr, \
+ mm##port##_INDEX_11, index, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
+
+#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ index, value, mask) \
+ phm_wait_for_register_unequal(hwmgr, \
+ index, value, mask)
+
+#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
+ PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ mm##reg, value, mask)
+
+#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
+ PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
+
+#endif /* _SMU_HELPER_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 9bdad48..2e2e4d0 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -32,7 +32,7 @@
#include "ppatomctrl.h"
#include "hwmgr_ppt.h"
#include "power_state.h"
-#include "cgs_linux.h"
+#include "smu_helper.h"
struct pp_instance;
struct pp_hwmgr;
@@ -777,160 +777,9 @@ struct cgs_irq_src_funcs {
extern int hwmgr_handle_task(struct pp_instance *handle,
enum amd_pp_task task_id,
enum amd_pm_state_type *user_state);
-extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
- uint32_t value, uint32_t mask);
-
-extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
- uint32_t indirect_port,
- uint32_t index,
- uint32_t value,
- uint32_t mask);
-
-extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
- uint32_t index,
- uint32_t value, uint32_t mask);
-extern int phm_wait_for_indirect_register_unequal(
- struct pp_hwmgr *hwmgr,
- uint32_t indirect_port, uint32_t index,
- uint32_t value, uint32_t mask);
-
-
-extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
-extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
-extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
-
-extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
-extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
-extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
-extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
-extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
-extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
-extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
-extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
-extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
- uint32_t voltage);
-extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
-extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
-extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
-extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
- uint16_t virtual_voltage_id, int32_t *sclk);
-extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
-extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
-extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
-
-extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
-extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
-extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
-
-extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
- uint32_t sclk, uint16_t id, uint16_t *voltage);
-
-extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);
-#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
-
-#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
-#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
-
-#define PHM_SET_FIELD(origval, reg, field, fieldval) \
- (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
- (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
-
-#define PHM_GET_FIELD(value, reg, field) \
- (((value) & PHM_FIELD_MASK(reg, field)) >> \
- PHM_FIELD_SHIFT(reg, field))
-
-
-/* Operations on named fields. */
-
-#define PHM_READ_FIELD(device, reg, field) \
- PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
-
-#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
- PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field)
-
-#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
- PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field)
-
-#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
- cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
- cgs_read_register(device, mm##reg), reg, field, fieldval))
-
-#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
- cgs_write_ind_register(device, port, ix##reg, \
- PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field, fieldval))
-
-#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
- cgs_write_ind_register(device, port, ix##reg, \
- PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field, fieldval))
-
-#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
- phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
-
-
-#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
- PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
- PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
- << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
-
-#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
- phm_wait_for_indirect_register_unequal(hwmgr, \
- mm##port##_INDEX, index, value, mask)
-
-#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
- PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-
-#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
- PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
- (fieldval) << PHM_FIELD_SHIFT(reg, field), \
- PHM_FIELD_MASK(reg, field) )
-
-
-#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
- port, index, value, mask) \
- phm_wait_for_indirect_register_unequal(hwmgr, \
- mm##port##_INDEX_11, index, value, mask)
-
-#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
- PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-
-#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
- PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
- (fieldval) << PHM_FIELD_SHIFT(reg, field), \
- PHM_FIELD_MASK(reg, field))
-
-
-#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
- port, index, value, mask) \
- phm_wait_on_indirect_register(hwmgr, \
- mm##port##_INDEX_11, index, value, mask)
-
-#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
- PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-
-#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
- PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
- (fieldval) << PHM_FIELD_SHIFT(reg, field), \
- PHM_FIELD_MASK(reg, field))
-
-#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
- index, value, mask) \
- phm_wait_for_register_unequal(hwmgr, \
- index, value, mask)
-
-#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
- PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
- mm##reg, value, mask)
+#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
-#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
- PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
- (fieldval) << PHM_FIELD_SHIFT(reg, field), \
- PHM_FIELD_MASK(reg, field))
#endif /* _HWMGR_H_ */
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] drm/amdgpu: Plus NULL function pointer check
[not found] ` <1520858050-7338-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-12 12:34 ` Rex Zhu
[not found] ` <1520858050-7338-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-12 12:34 ` [PATCH 3/4] drm/amdgpu: Remove wrapper layer of amdgpu_powerplay Rex Zhu
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Rex Zhu @ 2018-03-12 12:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Ifd6553646e7468bc935504075816074373e1d58d
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 56b2245..d60ecc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1415,12 +1415,14 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
/* enable clockgating to save power */
- r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
+ if (adev->ip_blocks[i].version->funcs->set_clockgating_state) {
+ r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
AMD_CG_STATE_GATE);
- if (r) {
- DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
- adev->ip_blocks[i].version->funcs->name, r);
- return r;
+ if (r) {
+ DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
}
}
}
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] drm/amdgpu: Remove wrapper layer of amdgpu_powerplay
[not found] ` <1520858050-7338-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-12 12:34 ` [PATCH 2/4] drm/amdgpu: Plus NULL function pointer check Rex Zhu
@ 2018-03-12 12:34 ` Rex Zhu
[not found] ` <1520858050-7338-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-12 12:34 ` [PATCH 4/4] drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c Rex Zhu
2018-03-13 15:56 ` [PATCH 1/4] drm/amd/pp: Move helper functions to smu_help.c Alex Deucher
3 siblings, 1 reply; 9+ messages in thread
From: Rex Zhu @ 2018-03-12 12:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
delete struct pp_instance,
make struct hwmgr as the smu hw context.
Change-Id: I444aabe20477fc2fc1288542d45bf887d45bf0cd
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 285 -----------
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h | 33 --
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 16 +-
drivers/gpu/drm/amd/amdgpu/cik.c | 15 +-
drivers/gpu/drm/amd/amdgpu/cik_dpm.h | 7 +-
drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 16 +-
drivers/gpu/drm/amd/amdgpu/si.c | 8 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.h | 3 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +-
drivers/gpu/drm/amd/amdgpu/vi.c | 13 +-
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 3 +-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 611 ++++++++++--------------
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 50 +-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 16 +-
drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 36 --
19 files changed, 336 insertions(+), 804 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
delete mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 353c937..94db35a 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -87,8 +87,7 @@ amdgpu-y += \
# add SMC block
amdgpu-y += \
- amdgpu_dpm.o \
- amdgpu_powerplay.o
+ amdgpu_dpm.o
# add DCE block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 96bcdb9..62773b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1398,9 +1398,7 @@ enum amd_hw_ip_block_type {
#define HWIP_MAX_INSTANCE 6
struct amd_powerplay {
- struct cgs_device *cgs_device;
void *pp_handle;
- const struct amd_ip_funcs *ip_funcs;
const struct amd_pm_funcs *pp_funcs;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 632b186..361975c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1154,7 +1154,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
umode_t effective_mode = attr->mode;
/* handle non-powerplay limitations */
- if (!adev->powerplay.cgs_device) {
+ if (!adev->powerplay.pp_handle) {
/* Skip fan attributes if fan is not present */
if (adev->pm.no_fan &&
(attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
deleted file mode 100644
index 825c9b9..0000000
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#include "atom.h"
-#include "amdgpu.h"
-#include "amd_shared.h"
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include "amdgpu_pm.h"
-#include <drm/amdgpu_drm.h>
-#include "amdgpu_powerplay.h"
-#include "si_dpm.h"
-#include "cik_dpm.h"
-#include "vi_dpm.h"
-
-static int amdgpu_pp_early_init(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- struct amd_powerplay *amd_pp;
- int ret = 0;
-
- amd_pp = &(adev->powerplay);
- amd_pp->pp_handle = (void *)adev;
-
- switch (adev->asic_type) {
- case CHIP_POLARIS11:
- case CHIP_POLARIS10:
- case CHIP_POLARIS12:
- case CHIP_TONGA:
- case CHIP_FIJI:
- case CHIP_TOPAZ:
- case CHIP_CARRIZO:
- case CHIP_STONEY:
- case CHIP_VEGA10:
- case CHIP_RAVEN:
- amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
- amd_pp->ip_funcs = &pp_ip_funcs;
- amd_pp->pp_funcs = &pp_dpm_funcs;
- break;
- /* These chips don't have powerplay implemenations */
-#ifdef CONFIG_DRM_AMDGPU_SI
- case CHIP_TAHITI:
- case CHIP_PITCAIRN:
- case CHIP_VERDE:
- case CHIP_OLAND:
- case CHIP_HAINAN:
- amd_pp->ip_funcs = &si_dpm_ip_funcs;
- amd_pp->pp_funcs = &si_dpm_funcs;
- break;
-#endif
-#ifdef CONFIG_DRM_AMDGPU_CIK
- case CHIP_BONAIRE:
- case CHIP_HAWAII:
- if (amdgpu_dpm == -1) {
- amd_pp->ip_funcs = &ci_dpm_ip_funcs;
- amd_pp->pp_funcs = &ci_dpm_funcs;
- } else {
- amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
- amd_pp->ip_funcs = &pp_ip_funcs;
- amd_pp->pp_funcs = &pp_dpm_funcs;
- }
- break;
- case CHIP_KABINI:
- case CHIP_MULLINS:
- case CHIP_KAVERI:
- amd_pp->ip_funcs = &kv_dpm_ip_funcs;
- amd_pp->pp_funcs = &kv_dpm_funcs;
- break;
-#endif
- default:
- ret = -EINVAL;
- break;
- }
-
- if (adev->powerplay.ip_funcs->early_init)
- ret = adev->powerplay.ip_funcs->early_init(adev);
-
- return ret;
-}
-
-
-static int amdgpu_pp_late_init(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->late_init)
- ret = adev->powerplay.ip_funcs->late_init(
- adev->powerplay.pp_handle);
-
- return ret;
-}
-
-static int amdgpu_pp_sw_init(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->sw_init)
- ret = adev->powerplay.ip_funcs->sw_init(
- adev->powerplay.pp_handle);
-
- return ret;
-}
-
-static int amdgpu_pp_sw_fini(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->sw_fini)
- ret = adev->powerplay.ip_funcs->sw_fini(
- adev->powerplay.pp_handle);
- if (ret)
- return ret;
-
- return ret;
-}
-
-static int amdgpu_pp_hw_init(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- amdgpu_ucode_init_bo(adev);
-
- if (adev->powerplay.ip_funcs->hw_init)
- ret = adev->powerplay.ip_funcs->hw_init(
- adev->powerplay.pp_handle);
-
- return ret;
-}
-
-static int amdgpu_pp_hw_fini(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->hw_fini)
- ret = adev->powerplay.ip_funcs->hw_fini(
- adev->powerplay.pp_handle);
-
- return ret;
-}
-
-static void amdgpu_pp_late_fini(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->late_fini)
- adev->powerplay.ip_funcs->late_fini(
- adev->powerplay.pp_handle);
-
- if (adev->powerplay.cgs_device)
- amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
-}
-
-static int amdgpu_pp_suspend(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->suspend)
- ret = adev->powerplay.ip_funcs->suspend(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static int amdgpu_pp_resume(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->resume)
- ret = adev->powerplay.ip_funcs->resume(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static int amdgpu_pp_set_clockgating_state(void *handle,
- enum amd_clockgating_state state)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->set_clockgating_state)
- ret = adev->powerplay.ip_funcs->set_clockgating_state(
- adev->powerplay.pp_handle, state);
- return ret;
-}
-
-static int amdgpu_pp_set_powergating_state(void *handle,
- enum amd_powergating_state state)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->set_powergating_state)
- ret = adev->powerplay.ip_funcs->set_powergating_state(
- adev->powerplay.pp_handle, state);
- return ret;
-}
-
-
-static bool amdgpu_pp_is_idle(void *handle)
-{
- bool ret = true;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->is_idle)
- ret = adev->powerplay.ip_funcs->is_idle(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static int amdgpu_pp_wait_for_idle(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->wait_for_idle)
- ret = adev->powerplay.ip_funcs->wait_for_idle(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static int amdgpu_pp_soft_reset(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->soft_reset)
- ret = adev->powerplay.ip_funcs->soft_reset(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
- .name = "amdgpu_powerplay",
- .early_init = amdgpu_pp_early_init,
- .late_init = amdgpu_pp_late_init,
- .sw_init = amdgpu_pp_sw_init,
- .sw_fini = amdgpu_pp_sw_fini,
- .hw_init = amdgpu_pp_hw_init,
- .hw_fini = amdgpu_pp_hw_fini,
- .late_fini = amdgpu_pp_late_fini,
- .suspend = amdgpu_pp_suspend,
- .resume = amdgpu_pp_resume,
- .is_idle = amdgpu_pp_is_idle,
- .wait_for_idle = amdgpu_pp_wait_for_idle,
- .soft_reset = amdgpu_pp_soft_reset,
- .set_clockgating_state = amdgpu_pp_set_clockgating_state,
- .set_powergating_state = amdgpu_pp_set_powergating_state,
-};
-
-const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
-{
- .type = AMD_IP_BLOCK_TYPE_SMC,
- .major = 1,
- .minor = 0,
- .rev = 0,
- .funcs = &amdgpu_pp_ip_funcs,
-};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
deleted file mode 100644
index c0c4bfd..0000000
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __AMDGPU_POWERPLAY_H__
-#define __AMDGPU_POWERPLAY_H__
-
-#include "amd_shared.h"
-
-extern const struct amdgpu_ip_block_version amdgpu_pp_ip_block;
-
-#endif /* __AMDGPU_POWERPLAY_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index ddb814f..fa151f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -65,6 +65,8 @@
#define VOLTAGE_VID_OFFSET_SCALE1 625
#define VOLTAGE_VID_OFFSET_SCALE2 100
+static const struct amd_pm_funcs ci_dpm_funcs;
+
static const struct ci_pt_defaults defaults_hawaii_xt =
{
1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
@@ -6241,6 +6243,7 @@ static int ci_dpm_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ adev->powerplay.pp_funcs = &ci_dpm_funcs;
ci_dpm_set_irq_funcs(adev);
return 0;
@@ -6760,7 +6763,7 @@ static int ci_dpm_read_sensor(void *handle, int idx,
}
}
-const struct amd_ip_funcs ci_dpm_ip_funcs = {
+static const struct amd_ip_funcs ci_dpm_ip_funcs = {
.name = "ci_dpm",
.early_init = ci_dpm_early_init,
.late_init = ci_dpm_late_init,
@@ -6777,7 +6780,16 @@ static int ci_dpm_read_sensor(void *handle, int idx,
.set_powergating_state = ci_dpm_set_powergating_state,
};
-const struct amd_pm_funcs ci_dpm_funcs = {
+const struct amdgpu_ip_block_version ci_smu_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_SMC,
+ .major = 1,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &ci_dpm_ip_funcs,
+};
+
+static const struct amd_pm_funcs ci_dpm_funcs = {
.pre_set_power_state = &ci_dpm_pre_set_power_state,
.set_power_state = &ci_dpm_set_power_state,
.post_set_power_state = &ci_dpm_post_set_power_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 4324184..b229028 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -67,7 +67,6 @@
#include "amdgpu_dm.h"
#include "amdgpu_amdkfd.h"
-#include "amdgpu_powerplay.h"
#include "dce_virtual.h"
/*
@@ -2000,7 +1999,10 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ if (amdgpu_dpm == -1)
+ amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
+ else
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -2018,7 +2020,10 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ if (amdgpu_dpm == -1)
+ amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
+ else
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -2036,7 +2041,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -2055,7 +2060,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
index c7b4349..2a08661 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
@@ -24,8 +24,7 @@
#ifndef __CIK_DPM_H__
#define __CIK_DPM_H__
-extern const struct amd_ip_funcs ci_dpm_ip_funcs;
-extern const struct amd_ip_funcs kv_dpm_ip_funcs;
-extern const struct amd_pm_funcs ci_dpm_funcs;
-extern const struct amd_pm_funcs kv_dpm_funcs;
+extern const struct amdgpu_ip_block_version ci_smu_ip_block;
+extern const struct amdgpu_ip_block_version kv_smu_ip_block;
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 8766681..81babe0 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -42,6 +42,8 @@
#define KV_MINIMUM_ENGINE_CLOCK 800
#define SMC_RAM_END 0x40000
+static const struct amd_pm_funcs kv_dpm_funcs;
+
static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
static int kv_enable_nb_dpm(struct amdgpu_device *adev,
bool enable);
@@ -2960,6 +2962,7 @@ static int kv_dpm_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ adev->powerplay.pp_funcs = &kv_dpm_funcs;
kv_dpm_set_irq_funcs(adev);
return 0;
@@ -3301,7 +3304,7 @@ static int kv_dpm_read_sensor(void *handle, int idx,
}
}
-const struct amd_ip_funcs kv_dpm_ip_funcs = {
+static const struct amd_ip_funcs kv_dpm_ip_funcs = {
.name = "kv_dpm",
.early_init = kv_dpm_early_init,
.late_init = kv_dpm_late_init,
@@ -3318,7 +3321,16 @@ static int kv_dpm_read_sensor(void *handle, int idx,
.set_powergating_state = kv_dpm_set_powergating_state,
};
-const struct amd_pm_funcs kv_dpm_funcs = {
+const struct amdgpu_ip_block_version kv_smu_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_SMC,
+ .major = 1,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &kv_dpm_ip_funcs,
+};
+
+static const struct amd_pm_funcs kv_dpm_funcs = {
.pre_set_power_state = &kv_dpm_pre_set_power_state,
.set_power_state = &kv_dpm_set_power_state,
.post_set_power_state = &kv_dpm_post_set_power_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 6e61b56..b154667 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -32,7 +32,7 @@
#include "amdgpu_vce.h"
#include "atom.h"
#include "amd_pcie.h"
-#include "amdgpu_powerplay.h"
+#include "si_dpm.h"
#include "sid.h"
#include "si_ih.h"
#include "gfx_v6_0.h"
@@ -1983,7 +1983,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else
@@ -1997,7 +1997,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else
@@ -2011,7 +2011,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 8137c02..6d68bcd 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -67,6 +67,8 @@
MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
+static const struct amd_pm_funcs si_dpm_funcs;
+
union power_info {
struct _ATOM_POWERPLAY_INFO info;
struct _ATOM_POWERPLAY_INFO_V2 info_2;
@@ -7914,6 +7916,7 @@ static int si_dpm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ adev->powerplay.pp_funcs = &si_dpm_funcs;
si_dpm_set_irq_funcs(adev);
return 0;
}
@@ -8014,7 +8017,7 @@ static int si_dpm_read_sensor(void *handle, int idx,
}
}
-const struct amd_ip_funcs si_dpm_ip_funcs = {
+static const struct amd_ip_funcs si_dpm_ip_funcs = {
.name = "si_dpm",
.early_init = si_dpm_early_init,
.late_init = si_dpm_late_init,
@@ -8031,7 +8034,16 @@ static int si_dpm_read_sensor(void *handle, int idx,
.set_powergating_state = si_dpm_set_powergating_state,
};
-const struct amd_pm_funcs si_dpm_funcs = {
+const struct amdgpu_ip_block_version si_smu_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_SMC,
+ .major = 1,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &si_dpm_ip_funcs,
+};
+
+static const struct amd_pm_funcs si_dpm_funcs = {
.pre_set_power_state = &si_dpm_pre_set_power_state,
.set_power_state = &si_dpm_set_power_state,
.post_set_power_state = &si_dpm_post_set_power_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.h b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
index 9fe343d..6b7d292 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
@@ -245,8 +245,7 @@ enum si_display_gap
SI_PM_DISPLAY_GAP_IGNORE = 3,
};
-extern const struct amd_ip_funcs si_dpm_ip_funcs;
-extern const struct amd_pm_funcs si_dpm_funcs;
+extern const struct amdgpu_ip_block_version si_smu_ip_block;
struct ni_leakage_coeffients
{
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8dc8b72..feb383a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -57,7 +57,6 @@
#include "uvd_v7_0.h"
#include "vce_v4_0.h"
#include "vcn_v1_0.h"
-#include "amdgpu_powerplay.h"
#include "dce_virtual.h"
#include "mxgpu_ai.h"
@@ -534,7 +533,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
if (!amdgpu_sriov_vf(adev))
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -553,7 +552,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 61360a1..7f01650 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -71,7 +71,6 @@
#include "uvd_v5_0.h"
#include "uvd_v6_0.h"
#include "vce_v3_0.h"
-#include "amdgpu_powerplay.h"
#if defined(CONFIG_DRM_AMD_ACP)
#include "amdgpu_acp.h"
#endif
@@ -1516,7 +1515,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
@@ -1526,7 +1525,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -1546,7 +1545,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -1568,7 +1567,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -1586,7 +1585,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
@@ -1607,7 +1606,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 15bd0f9..5c840c0 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -24,8 +24,7 @@
#ifndef __KGD_PP_INTERFACE_H__
#define __KGD_PP_INTERFACE_H__
-extern const struct amd_ip_funcs pp_ip_funcs;
-extern const struct amd_pm_funcs pp_dpm_funcs;
+extern const struct amdgpu_ip_block_version pp_smu_ip_block;
struct amd_vce_state {
/* vce clocks */
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index b989bf3..a5bc52c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -27,7 +27,6 @@
#include <linux/slab.h>
#include "amd_shared.h"
#include "amd_powerplay.h"
-#include "pp_instance.h"
#include "power_state.h"
#include "amdgpu.h"
#include "hwmgr.h"
@@ -37,18 +36,14 @@
static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
enum amd_pm_state_type *user_state);
-static inline int pp_check(struct pp_instance *handle)
-{
- if (handle == NULL)
- return -EINVAL;
+static const struct amd_pm_funcs pp_dpm_funcs;
- if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
+static inline int pp_check(struct pp_hwmgr *hwmgr)
+{
+ if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
return -EINVAL;
- if (handle->pm_en == 0)
- return PP_DPM_DISABLED;
-
- if (handle->hwmgr->hwmgr_func == NULL)
+ if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
return PP_DPM_DISABLED;
return 0;
@@ -56,54 +51,52 @@ static inline int pp_check(struct pp_instance *handle)
static int amd_powerplay_create(struct amdgpu_device *adev)
{
- struct pp_instance *instance;
+ struct pp_hwmgr *hwmgr;
if (adev == NULL)
return -EINVAL;
- instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
- if (instance == NULL)
+ hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
+ if (hwmgr == NULL)
return -ENOMEM;
- instance->parent = adev;
- instance->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
- instance->device = adev->powerplay.cgs_device;
- mutex_init(&instance->pp_lock);
- adev->powerplay.pp_handle = instance;
-
+ hwmgr->adev = adev;
+ hwmgr->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
+ hwmgr->device = amdgpu_cgs_create_device(adev);
+ mutex_init(&hwmgr->smu_lock);
+ hwmgr->chip_family = adev->family;
+ hwmgr->chip_id = adev->asic_type;
+ hwmgr->feature_mask = amdgpu_pp_feature_mask;
+ adev->powerplay.pp_handle = hwmgr;
+ adev->powerplay.pp_funcs = &pp_dpm_funcs;
return 0;
}
-static int amd_powerplay_destroy(void *handle)
+static int amd_powerplay_destroy(struct amdgpu_device *adev)
{
- struct pp_instance *instance = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- kfree(instance->hwmgr->hardcode_pp_table);
- instance->hwmgr->hardcode_pp_table = NULL;
+ kfree(hwmgr->hardcode_pp_table);
+ hwmgr->hardcode_pp_table = NULL;
- kfree(instance->hwmgr);
- instance->hwmgr = NULL;
+ kfree(hwmgr);
+ hwmgr = NULL;
- kfree(instance);
- instance = NULL;
return 0;
}
static int pp_early_init(void *handle)
{
int ret;
- struct pp_instance *pp_handle = NULL;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = handle;
ret = amd_powerplay_create(adev);
if (ret != 0)
return ret;
- pp_handle = adev->powerplay.pp_handle;
-
- ret = hwmgr_early_init(pp_handle);
+ ret = hwmgr_early_init(adev->powerplay.pp_handle);
if (ret)
return -EINVAL;
@@ -112,15 +105,13 @@ static int pp_early_init(void *handle)
static int pp_sw_init(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->smumgr_funcs->smu_init == NULL)
return -EINVAL;
@@ -128,55 +119,53 @@ static int pp_sw_init(void *handle)
pr_debug("amdgpu: powerplay sw initialized\n");
}
+
return ret;
}
static int pp_sw_fini(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
-
- if (hwmgr->smumgr_funcs->smu_fini == NULL)
- return -EINVAL;
-
- ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
+ if (hwmgr->smumgr_funcs->smu_fini != NULL)
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
}
- return ret;
+ return 0;
}
static int pp_hw_init(void *handle)
{
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- ret = pp_check(pp_handle);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ amdgpu_ucode_init_bo(adev);
- if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
+ ret = pp_check(hwmgr);
+ if (ret >= 0) {
if (hwmgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
- if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
pr_err("smc start failed\n");
- hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
return -EINVAL;
}
if (ret == PP_DPM_DISABLED)
goto exit;
- ret = hwmgr_hw_init(pp_handle);
+ ret = hwmgr_hw_init(hwmgr);
if (ret)
goto exit;
}
return ret;
exit:
- pp_handle->pm_en = 0;
+ hwmgr->pm_en = 0;
cgs_notify_dpm_enabled(hwmgr->device, false);
return 0;
@@ -184,24 +173,27 @@ static int pp_hw_init(void *handle)
static int pp_hw_fini(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret == 0)
- hwmgr_hw_fini(pp_handle);
+ hwmgr_hw_fini(hwmgr);
return 0;
}
static int pp_late_init(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
+
if (ret == 0)
- pp_dpm_dispatch_tasks(pp_handle,
+ pp_dpm_dispatch_tasks(hwmgr,
AMD_PP_TASK_COMPLETE_INIT, NULL);
return 0;
@@ -231,17 +223,15 @@ static int pp_sw_reset(void *handle)
static int pp_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
@@ -254,44 +244,43 @@ static int pp_set_powergating_state(void *handle,
static int pp_suspend(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret == 0)
- hwmgr_hw_suspend(pp_handle);
+ hwmgr_hw_suspend(hwmgr);
return 0;
}
static int pp_resume(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret < 0)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
- if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
pr_err("smc start failed\n");
- hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
return -EINVAL;
}
if (ret == PP_DPM_DISABLED)
return 0;
- return hwmgr_hw_resume(pp_handle);
+ return hwmgr_hw_resume(hwmgr);
}
-const struct amd_ip_funcs pp_ip_funcs = {
+static const struct amd_ip_funcs pp_ip_funcs = {
.name = "powerplay",
.early_init = pp_early_init,
.late_init = pp_late_init,
@@ -309,6 +298,15 @@ static int pp_resume(void *handle)
.set_powergating_state = pp_set_powergating_state,
};
+const struct amdgpu_ip_block_version pp_smu_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_SMC,
+ .major = 1,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &pp_ip_funcs,
+};
+
static int pp_dpm_load_fw(void *handle)
{
return 0;
@@ -321,17 +319,14 @@ static int pp_dpm_fw_loading_complete(void *handle)
static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
@@ -379,25 +374,22 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
static int pp_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (level == hwmgr->dpm_level)
return 0;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
pp_dpm_en_umd_pstate(hwmgr, &level);
hwmgr->request_dpm_level = level;
- hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
- mutex_unlock(&pp_handle->pp_lock);
+ hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
@@ -405,152 +397,135 @@ static int pp_dpm_force_performance_level(void *handle,
static enum amd_dpm_forced_level pp_dpm_get_performance_level(
void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
enum amd_dpm_forced_level level;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
level = hwmgr->dpm_level;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return level;
}
static uint32_t pp_dpm_get_sclk(void *handle, bool low)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t clk = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_sclk == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return clk;
}
static uint32_t pp_dpm_get_mclk(void *handle, bool low)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t clk = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_mclk == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return clk;
}
static void pp_dpm_powergate_vce(void *handle, bool gate)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->powergate_vce == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static void pp_dpm_powergate_uvd(void *handle, bool gate)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
enum amd_pm_state_type *user_state)
{
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr_handle_task(pp_handle, task_id, user_state);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
+ ret = hwmgr_handle_task(hwmgr, task_id, user_state);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct pp_hwmgr *hwmgr = handle;
struct pp_power_state *state;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
enum amd_pm_state_type pm_type;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->current_ps == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
state = hwmgr->current_ps;
@@ -571,147 +546,129 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return pm_type;
}
static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static uint32_t pp_dpm_get_fan_control_mode(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t mode = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return mode;
}
static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_pp_num_states(void *handle,
struct pp_states_info *data)
{
- struct pp_hwmgr *hwmgr;
+ struct pp_hwmgr *hwmgr = handle;
int i;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
memset(data, 0, sizeof(*data));
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->ps == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
data->nums = hwmgr->num_ps;
@@ -735,73 +692,68 @@ static int pp_dpm_get_pp_num_states(void *handle,
data->states[i] = POWER_STATE_TYPE_DEFAULT;
}
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_dpm_get_pp_table(void *handle, char **table)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
int size = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (!hwmgr->soft_pp_table)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
*table = (char *)hwmgr->soft_pp_table;
size = hwmgr->soft_pp_table_size;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return size;
}
static int amd_powerplay_reset(void *handle)
{
- struct pp_instance *instance = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret;
- ret = pp_check(instance);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- ret = pp_hw_fini(instance);
+ ret = pp_hw_fini(hwmgr);
if (ret)
return ret;
- ret = hwmgr_hw_init(instance);
+ ret = hwmgr_hw_init(hwmgr);
if (ret)
return ret;
- return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL);
+ return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
}
static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (!hwmgr->hardcode_pp_table) {
hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
hwmgr->soft_pp_table_size,
GFP_KERNEL);
if (!hwmgr->hardcode_pp_table) {
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return -ENOMEM;
}
}
@@ -809,7 +761,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
memcpy(hwmgr->hardcode_pp_table, buf, size);
hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
ret = amd_powerplay_reset(handle);
if (ret)
@@ -827,163 +779,142 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
static int pp_dpm_force_clock_level(void *handle,
enum pp_clock_type type, uint32_t mask)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->force_clock_level == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
else
ret = -EINVAL;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_print_clock_levels(void *handle,
enum pp_clock_type type, char *buf)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_sclk_od(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_mclk_od(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_read_sensor(void *handle, int idx,
void *value, int *size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (value == NULL)
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
switch (idx) {
case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
*((uint32_t *)value) = hwmgr->pstate_sclk;
@@ -992,9 +923,9 @@ static int pp_dpm_read_sensor(void *handle, int idx,
*((uint32_t *)value) = hwmgr->pstate_mclk;
return 0;
default:
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
}
@@ -1002,17 +933,14 @@ static int pp_dpm_read_sensor(void *handle, int idx,
static struct amd_vce_state*
pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return NULL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr && idx < hwmgr->num_vce_state_tables)
return &hwmgr->vce_states[idx];
return NULL;
@@ -1020,14 +948,11 @@ static int pp_dpm_read_sensor(void *handle, int idx,
static int pp_get_power_profile_mode(void *handle, char *buf)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
- if (!buf || pp_check(pp_handle))
+ if (!buf || pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return snprintf(buf, PAGE_SIZE, "\n");
@@ -1038,36 +963,30 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = -EINVAL;
- if (pp_check(pp_handle))
+ if (pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
- if (pp_check(pp_handle))
+ if (pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
@@ -1079,16 +998,13 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
static int pp_dpm_switch_power_profile(void *handle,
enum PP_SMC_POWER_PROFILE type, bool en)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
long workload;
uint32_t index;
- if (pp_check(pp_handle))
+ if (pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
@@ -1097,7 +1013,7 @@ static int pp_dpm_switch_power_profile(void *handle,
if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (!en) {
hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
@@ -1113,7 +1029,7 @@ static int pp_dpm_switch_power_profile(void *handle,
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
@@ -1125,46 +1041,40 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
uint32_t mc_addr_hi,
uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
virtual_addr_hi, mc_addr_low, mc_addr_hi,
size);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_set_power_limit(void *handle, uint32_t limit)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_power_limit == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
@@ -1176,20 +1086,19 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
if (limit > hwmgr->default_power_limit)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
hwmgr->power_limit = limit;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
@@ -1197,16 +1106,14 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
if (limit == NULL)
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (default_limit)
*limit = hwmgr->default_power_limit;
else
*limit = hwmgr->power_limit;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1214,42 +1121,37 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
static int pp_display_configuration_change(void *handle,
const struct amd_pp_display_configuration *display_config)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
phm_store_dal_configuration_data(hwmgr, display_config);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_get_display_power_level(void *handle,
struct amd_pp_simple_clock_info *output)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (output == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_dal_power_level(hwmgr, output);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1258,18 +1160,15 @@ static int pp_get_current_clocks(void *handle,
{
struct amd_pp_simple_clock_info simple_clocks;
struct pp_clock_info hw_clocks;
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
phm_get_dal_power_level(hwmgr, &simple_clocks);
@@ -1283,7 +1182,7 @@ static int pp_get_current_clocks(void *handle,
if (ret) {
pr_info("Error in phm_get_clock_info \n");
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return -EINVAL;
}
@@ -1303,29 +1202,26 @@ static int pp_get_current_clocks(void *handle,
clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (clocks == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1333,21 +1229,19 @@ static int pp_get_clock_by_type_with_latency(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clocks)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1355,47 +1249,41 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clocks)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_set_watermarks_for_clocks_ranges(void *handle,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!wm_with_clock_ranges)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
wm_with_clock_ranges);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1403,22 +1291,19 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
static int pp_display_clock_voltage_request(void *handle,
struct pp_display_clock_request *clock)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clock)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_display_clock_voltage_request(hwmgr, clock);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1426,42 +1311,36 @@ static int pp_display_clock_voltage_request(void *handle,
static int pp_get_display_mode_validation_clocks(void *handle,
struct amd_pp_simple_clock_info *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (clocks == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
ret = phm_get_max_high_clocks(hwmgr, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_set_mmhub_powergating_by_smu(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
@@ -1470,7 +1349,7 @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
}
-const struct amd_pm_funcs pp_dpm_funcs = {
+static const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
.force_performance_level = pp_dpm_force_performance_level,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 5563b65..238dd59 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -116,23 +116,11 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
}
-int hwmgr_early_init(struct pp_instance *handle)
+int hwmgr_early_init(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
-
- if (handle == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
- if (hwmgr == NULL)
- return -ENOMEM;
-
- handle->hwmgr = hwmgr;
- hwmgr->adev = handle->parent;
- hwmgr->device = handle->device;
- hwmgr->chip_family = ((struct amdgpu_device *)handle->parent)->family;
- hwmgr->chip_id = ((struct amdgpu_device *)handle->parent)->asic_type;
- hwmgr->feature_mask = amdgpu_pp_feature_mask;
hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
hwmgr->power_source = PP_PowerSource_AC;
hwmgr->pp_table_version = PP_TABLE_V1;
@@ -220,16 +208,13 @@ int hwmgr_early_init(struct pp_instance *handle)
return 0;
}
-int hwmgr_hw_init(struct pp_instance *handle)
+int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
int ret = 0;
- if (handle == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
-
if (hwmgr->pptable_func == NULL ||
hwmgr->pptable_func->pptable_init == NULL ||
hwmgr->hwmgr_func->backend_init == NULL)
@@ -275,15 +260,11 @@ int hwmgr_hw_init(struct pp_instance *handle)
return ret;
}
-int hwmgr_hw_fini(struct pp_instance *handle)
+int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
-
- if (handle == NULL || handle->hwmgr == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
-
phm_stop_thermal_controller(hwmgr);
psm_set_boot_states(hwmgr);
psm_adjust_power_state_dynamic(hwmgr, false, NULL);
@@ -297,15 +278,13 @@ int hwmgr_hw_fini(struct pp_instance *handle)
return psm_fini_power_state_table(hwmgr);
}
-int hwmgr_hw_suspend(struct pp_instance *handle)
+int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
int ret = 0;
- if (handle == NULL || handle->hwmgr == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
phm_disable_smc_firmware_ctf(hwmgr);
ret = psm_set_boot_states(hwmgr);
if (ret)
@@ -318,15 +297,13 @@ int hwmgr_hw_suspend(struct pp_instance *handle)
return ret;
}
-int hwmgr_hw_resume(struct pp_instance *handle)
+int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
int ret = 0;
- if (handle == NULL || handle->hwmgr == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
ret = phm_setup_asic(hwmgr);
if (ret)
return ret;
@@ -361,17 +338,14 @@ static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
}
}
-int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id,
+int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
enum amd_pm_state_type *user_state)
{
int ret = 0;
- struct pp_hwmgr *hwmgr;
- if (handle == NULL || handle->hwmgr == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
-
switch (task_id) {
case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
ret = phm_set_cpu_power_state(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 2e2e4d0..85b46ad 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -25,7 +25,6 @@
#include <linux/seq_file.h>
#include "amd_powerplay.h"
-#include "pp_instance.h"
#include "hardwaremanager.h"
#include "pp_power_source.h"
#include "hwmgr_ppt.h"
@@ -34,7 +33,6 @@
#include "power_state.h"
#include "smu_helper.h"
-struct pp_instance;
struct pp_hwmgr;
struct phm_fan_speed_info;
struct pp_atomctrl_voltage_table;
@@ -703,6 +701,8 @@ struct pp_hwmgr {
uint32_t chip_family;
uint32_t chip_id;
uint32_t smu_version;
+ bool pm_en;
+ struct mutex smu_lock;
uint32_t pp_table_version;
void *device;
@@ -769,12 +769,12 @@ struct cgs_irq_src_funcs {
cgs_irq_handler_func_t handler;
};
-extern int hwmgr_early_init(struct pp_instance *handle);
-extern int hwmgr_hw_init(struct pp_instance *handle);
-extern int hwmgr_hw_fini(struct pp_instance *handle);
-extern int hwmgr_hw_suspend(struct pp_instance *handle);
-extern int hwmgr_hw_resume(struct pp_instance *handle);
-extern int hwmgr_handle_task(struct pp_instance *handle,
+extern int hwmgr_early_init(struct pp_hwmgr *hwmgr);
+extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
+extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
+extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
+extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
+extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
enum amd_pp_task task_id,
enum amd_pm_state_type *user_state);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
deleted file mode 100644
index 6c2fa33..0000000
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _PP_INSTANCE_H_
-#define _PP_INSTANCE_H_
-
-struct pp_hwmgr;
-
-struct pp_instance {
- void *parent; /* e.g. amdgpu_device */
- void *device; /* e.g. cgs_device */
- bool pm_en;
- struct pp_hwmgr *hwmgr;
- struct mutex pp_lock;
-};
-
-#endif
--
1.9.1
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
[not found] ` <1520858050-7338-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-12 12:34 ` [PATCH 2/4] drm/amdgpu: Plus NULL function pointer check Rex Zhu
2018-03-12 12:34 ` [PATCH 3/4] drm/amdgpu: Remove wrapper layer of amdgpu_powerplay Rex Zhu
@ 2018-03-12 12:34 ` Rex Zhu
[not found] ` <1520858050-7338-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-13 15:56 ` [PATCH 1/4] drm/amd/pp: Move helper functions to smu_help.c Alex Deucher
3 siblings, 1 reply; 9+ messages in thread
From: Rex Zhu @ 2018-03-12 12:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
make it symmetric with the init bo in amd_powerplay.c
refine the "commit b22558bb4ff8fc9fe925222f90297d7a03a5fb20"
Change-Id: I0bca00fa2a376cf6539b046eefff2ca3d30c3cae
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 ++++++-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d60ecc5..9aa726e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1485,9 +1485,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
}
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC &&
- adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- amdgpu_ucode_fini_bo(adev);
if (!adev->ip_blocks[i].status.hw)
continue;
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index a5bc52c..ed480db 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -201,7 +201,12 @@ static int pp_late_init(void *handle)
static void pp_late_fini(void *handle)
{
- amd_powerplay_destroy(handle);
+ struct amdgpu_device *adev = handle;
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ amdgpu_ucode_fini_bo(adev);
+
+ amd_powerplay_destroy(adev);
}
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] drm/amdgpu: Plus NULL function pointer check
[not found] ` <1520858050-7338-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-12 12:54 ` Christian König
[not found] ` <71e3bf37-5289-422b-7b04-de2d4e60ce9c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 9+ messages in thread
From: Christian König @ 2018-03-12 12:54 UTC (permalink / raw)
To: Rex Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 12.03.2018 um 13:34 schrieb Rex Zhu:
> Change-Id: Ifd6553646e7468bc935504075816074373e1d58d
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 56b2245..d60ecc5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1415,12 +1415,14 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
> if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
> adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
> /* enable clockgating to save power */
> - r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> + if (adev->ip_blocks[i].version->funcs->set_clockgating_state) {
Why not add it to the if check above?
Christian.
> + r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> AMD_CG_STATE_GATE);
> - if (r) {
> - DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
> - adev->ip_blocks[i].version->funcs->name, r);
> - return r;
> + if (r) {
> + DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
> + adev->ip_blocks[i].version->funcs->name, r);
> + return r;
> + }
> }
> }
> }
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] drm/amdgpu: Plus NULL function pointer check
[not found] ` <71e3bf37-5289-422b-7b04-de2d4e60ce9c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2018-03-12 14:13 ` Zhu, Rex
0 siblings, 0 replies; 9+ messages in thread
From: Zhu, Rex @ 2018-03-12 14:13 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Koenig, Christian
[-- Attachment #1.1: Type: text/plain, Size: 2341 bytes --]
Sure.
Thanks.
Best Regards
Rex
________________________________
From: Christian König <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Monday, March 12, 2018 8:54 PM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 2/4] drm/amdgpu: Plus NULL function pointer check
Am 12.03.2018 um 13:34 schrieb Rex Zhu:
> Change-Id: Ifd6553646e7468bc935504075816074373e1d58d
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 56b2245..d60ecc5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1415,12 +1415,14 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
> if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
> adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
> /* enable clockgating to save power */
> - r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> + if (adev->ip_blocks[i].version->funcs->set_clockgating_state) {
Why not add it to the if check above?
Christian.
> + r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> AMD_CG_STATE_GATE);
> - if (r) {
> - DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
> - adev->ip_blocks[i].version->funcs->name, r);
> - return r;
> + if (r) {
> + DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
> + adev->ip_blocks[i].version->funcs->name, r);
> + return r;
> + }
> }
> }
> }
[-- Attachment #1.2: Type: text/html, Size: 6453 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
[not found] ` <1520858050-7338-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-13 15:55 ` Alex Deucher
0 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2018-03-13 15:55 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Mon, Mar 12, 2018 at 8:34 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> make it symmetric with the init bo in amd_powerplay.c
>
> refine the "commit b22558bb4ff8fc9fe925222f90297d7a03a5fb20"
>
> Change-Id: I0bca00fa2a376cf6539b046eefff2ca3d30c3cae
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 ++++++-
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index d60ecc5..9aa726e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1485,9 +1485,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
> }
>
> for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> - if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC &&
> - adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> - amdgpu_ucode_fini_bo(adev);
> if (!adev->ip_blocks[i].status.hw)
> continue;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index a5bc52c..ed480db 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -201,7 +201,12 @@ static int pp_late_init(void *handle)
>
> static void pp_late_fini(void *handle)
> {
> - amd_powerplay_destroy(handle);
> + struct amdgpu_device *adev = handle;
> +
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> + amdgpu_ucode_fini_bo(adev);
> +
> + amd_powerplay_destroy(adev);
> }
>
>
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] drm/amd/pp: Move helper functions to smu_help.c
[not found] ` <1520858050-7338-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-03-12 12:34 ` [PATCH 4/4] drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c Rex Zhu
@ 2018-03-13 15:56 ` Alex Deucher
3 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2018-03-13 15:56 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Mon, Mar 12, 2018 at 8:34 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] drm/amdgpu: Remove wrapper layer of amdgpu_powerplay
[not found] ` <1520858050-7338-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-13 16:02 ` Alex Deucher
0 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2018-03-13 16:02 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Mon, Mar 12, 2018 at 8:34 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> delete struct pp_instance,
> make struct hwmgr as the smu hw context.
>
> Change-Id: I444aabe20477fc2fc1288542d45bf887d45bf0cd
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 285 -----------
> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h | 33 --
> drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/cik.c | 15 +-
> drivers/gpu/drm/amd/amdgpu/cik_dpm.h | 7 +-
> drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/si.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/si_dpm.h | 3 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +-
> drivers/gpu/drm/amd/amdgpu/vi.c | 13 +-
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 3 +-
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 611 ++++++++++--------------
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 50 +-
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 16 +-
> drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 36 --
> 19 files changed, 336 insertions(+), 804 deletions(-)
> delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
> delete mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 353c937..94db35a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -87,8 +87,7 @@ amdgpu-y += \
>
> # add SMC block
> amdgpu-y += \
> - amdgpu_dpm.o \
> - amdgpu_powerplay.o
> + amdgpu_dpm.o
>
> # add DCE block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 96bcdb9..62773b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1398,9 +1398,7 @@ enum amd_hw_ip_block_type {
> #define HWIP_MAX_INSTANCE 6
>
> struct amd_powerplay {
> - struct cgs_device *cgs_device;
> void *pp_handle;
> - const struct amd_ip_funcs *ip_funcs;
> const struct amd_pm_funcs *pp_funcs;
> };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 632b186..361975c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1154,7 +1154,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
> umode_t effective_mode = attr->mode;
>
> /* handle non-powerplay limitations */
> - if (!adev->powerplay.cgs_device) {
> + if (!adev->powerplay.pp_handle) {
> /* Skip fan attributes if fan is not present */
> if (adev->pm.no_fan &&
> (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> deleted file mode 100644
> index 825c9b9..0000000
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ /dev/null
> @@ -1,285 +0,0 @@
> -/*
> - * Copyright 2015 Advanced Micro Devices, Inc.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -#include "atom.h"
> -#include "amdgpu.h"
> -#include "amd_shared.h"
> -#include <linux/module.h>
> -#include <linux/moduleparam.h>
> -#include "amdgpu_pm.h"
> -#include <drm/amdgpu_drm.h>
> -#include "amdgpu_powerplay.h"
> -#include "si_dpm.h"
> -#include "cik_dpm.h"
> -#include "vi_dpm.h"
> -
> -static int amdgpu_pp_early_init(void *handle)
> -{
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> - struct amd_powerplay *amd_pp;
> - int ret = 0;
> -
> - amd_pp = &(adev->powerplay);
> - amd_pp->pp_handle = (void *)adev;
> -
> - switch (adev->asic_type) {
> - case CHIP_POLARIS11:
> - case CHIP_POLARIS10:
> - case CHIP_POLARIS12:
> - case CHIP_TONGA:
> - case CHIP_FIJI:
> - case CHIP_TOPAZ:
> - case CHIP_CARRIZO:
> - case CHIP_STONEY:
> - case CHIP_VEGA10:
> - case CHIP_RAVEN:
> - amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
> - amd_pp->ip_funcs = &pp_ip_funcs;
> - amd_pp->pp_funcs = &pp_dpm_funcs;
> - break;
> - /* These chips don't have powerplay implemenations */
> -#ifdef CONFIG_DRM_AMDGPU_SI
> - case CHIP_TAHITI:
> - case CHIP_PITCAIRN:
> - case CHIP_VERDE:
> - case CHIP_OLAND:
> - case CHIP_HAINAN:
> - amd_pp->ip_funcs = &si_dpm_ip_funcs;
> - amd_pp->pp_funcs = &si_dpm_funcs;
> - break;
> -#endif
> -#ifdef CONFIG_DRM_AMDGPU_CIK
> - case CHIP_BONAIRE:
> - case CHIP_HAWAII:
> - if (amdgpu_dpm == -1) {
> - amd_pp->ip_funcs = &ci_dpm_ip_funcs;
> - amd_pp->pp_funcs = &ci_dpm_funcs;
> - } else {
> - amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
> - amd_pp->ip_funcs = &pp_ip_funcs;
> - amd_pp->pp_funcs = &pp_dpm_funcs;
> - }
> - break;
> - case CHIP_KABINI:
> - case CHIP_MULLINS:
> - case CHIP_KAVERI:
> - amd_pp->ip_funcs = &kv_dpm_ip_funcs;
> - amd_pp->pp_funcs = &kv_dpm_funcs;
> - break;
> -#endif
> - default:
> - ret = -EINVAL;
> - break;
> - }
> -
> - if (adev->powerplay.ip_funcs->early_init)
> - ret = adev->powerplay.ip_funcs->early_init(adev);
> -
> - return ret;
> -}
> -
> -
> -static int amdgpu_pp_late_init(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->late_init)
> - ret = adev->powerplay.ip_funcs->late_init(
> - adev->powerplay.pp_handle);
> -
> - return ret;
> -}
> -
> -static int amdgpu_pp_sw_init(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->sw_init)
> - ret = adev->powerplay.ip_funcs->sw_init(
> - adev->powerplay.pp_handle);
> -
> - return ret;
> -}
> -
> -static int amdgpu_pp_sw_fini(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->sw_fini)
> - ret = adev->powerplay.ip_funcs->sw_fini(
> - adev->powerplay.pp_handle);
> - if (ret)
> - return ret;
> -
> - return ret;
> -}
> -
> -static int amdgpu_pp_hw_init(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> - amdgpu_ucode_init_bo(adev);
> -
> - if (adev->powerplay.ip_funcs->hw_init)
> - ret = adev->powerplay.ip_funcs->hw_init(
> - adev->powerplay.pp_handle);
> -
> - return ret;
> -}
> -
> -static int amdgpu_pp_hw_fini(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->hw_fini)
> - ret = adev->powerplay.ip_funcs->hw_fini(
> - adev->powerplay.pp_handle);
> -
> - return ret;
> -}
> -
> -static void amdgpu_pp_late_fini(void *handle)
> -{
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->late_fini)
> - adev->powerplay.ip_funcs->late_fini(
> - adev->powerplay.pp_handle);
> -
> - if (adev->powerplay.cgs_device)
> - amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
> -}
> -
> -static int amdgpu_pp_suspend(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->suspend)
> - ret = adev->powerplay.ip_funcs->suspend(
> - adev->powerplay.pp_handle);
> - return ret;
> -}
> -
> -static int amdgpu_pp_resume(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->resume)
> - ret = adev->powerplay.ip_funcs->resume(
> - adev->powerplay.pp_handle);
> - return ret;
> -}
> -
> -static int amdgpu_pp_set_clockgating_state(void *handle,
> - enum amd_clockgating_state state)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->set_clockgating_state)
> - ret = adev->powerplay.ip_funcs->set_clockgating_state(
> - adev->powerplay.pp_handle, state);
> - return ret;
> -}
> -
> -static int amdgpu_pp_set_powergating_state(void *handle,
> - enum amd_powergating_state state)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->set_powergating_state)
> - ret = adev->powerplay.ip_funcs->set_powergating_state(
> - adev->powerplay.pp_handle, state);
> - return ret;
> -}
> -
> -
> -static bool amdgpu_pp_is_idle(void *handle)
> -{
> - bool ret = true;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->is_idle)
> - ret = adev->powerplay.ip_funcs->is_idle(
> - adev->powerplay.pp_handle);
> - return ret;
> -}
> -
> -static int amdgpu_pp_wait_for_idle(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->wait_for_idle)
> - ret = adev->powerplay.ip_funcs->wait_for_idle(
> - adev->powerplay.pp_handle);
> - return ret;
> -}
> -
> -static int amdgpu_pp_soft_reset(void *handle)
> -{
> - int ret = 0;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (adev->powerplay.ip_funcs->soft_reset)
> - ret = adev->powerplay.ip_funcs->soft_reset(
> - adev->powerplay.pp_handle);
> - return ret;
> -}
> -
> -static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
> - .name = "amdgpu_powerplay",
> - .early_init = amdgpu_pp_early_init,
> - .late_init = amdgpu_pp_late_init,
> - .sw_init = amdgpu_pp_sw_init,
> - .sw_fini = amdgpu_pp_sw_fini,
> - .hw_init = amdgpu_pp_hw_init,
> - .hw_fini = amdgpu_pp_hw_fini,
> - .late_fini = amdgpu_pp_late_fini,
> - .suspend = amdgpu_pp_suspend,
> - .resume = amdgpu_pp_resume,
> - .is_idle = amdgpu_pp_is_idle,
> - .wait_for_idle = amdgpu_pp_wait_for_idle,
> - .soft_reset = amdgpu_pp_soft_reset,
> - .set_clockgating_state = amdgpu_pp_set_clockgating_state,
> - .set_powergating_state = amdgpu_pp_set_powergating_state,
> -};
> -
> -const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
> -{
> - .type = AMD_IP_BLOCK_TYPE_SMC,
> - .major = 1,
> - .minor = 0,
> - .rev = 0,
> - .funcs = &amdgpu_pp_ip_funcs,
> -};
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
> deleted file mode 100644
> index c0c4bfd..0000000
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/*
> - * Copyright 2015 Advanced Micro Devices, Inc.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -#ifndef __AMDGPU_POWERPLAY_H__
> -#define __AMDGPU_POWERPLAY_H__
> -
> -#include "amd_shared.h"
> -
> -extern const struct amdgpu_ip_block_version amdgpu_pp_ip_block;
> -
> -#endif /* __AMDGPU_POWERPLAY_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> index ddb814f..fa151f0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> @@ -65,6 +65,8 @@
> #define VOLTAGE_VID_OFFSET_SCALE1 625
> #define VOLTAGE_VID_OFFSET_SCALE2 100
>
> +static const struct amd_pm_funcs ci_dpm_funcs;
> +
> static const struct ci_pt_defaults defaults_hawaii_xt =
> {
> 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
> @@ -6241,6 +6243,7 @@ static int ci_dpm_early_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + adev->powerplay.pp_funcs = &ci_dpm_funcs;
> ci_dpm_set_irq_funcs(adev);
>
> return 0;
> @@ -6760,7 +6763,7 @@ static int ci_dpm_read_sensor(void *handle, int idx,
> }
> }
>
> -const struct amd_ip_funcs ci_dpm_ip_funcs = {
> +static const struct amd_ip_funcs ci_dpm_ip_funcs = {
> .name = "ci_dpm",
> .early_init = ci_dpm_early_init,
> .late_init = ci_dpm_late_init,
> @@ -6777,7 +6780,16 @@ static int ci_dpm_read_sensor(void *handle, int idx,
> .set_powergating_state = ci_dpm_set_powergating_state,
> };
>
> -const struct amd_pm_funcs ci_dpm_funcs = {
> +const struct amdgpu_ip_block_version ci_smu_ip_block =
> +{
> + .type = AMD_IP_BLOCK_TYPE_SMC,
> + .major = 1,
For correctness, this should be major = 7.
> + .minor = 0,
> + .rev = 0,
> + .funcs = &ci_dpm_ip_funcs,
> +};
> +
> +static const struct amd_pm_funcs ci_dpm_funcs = {
> .pre_set_power_state = &ci_dpm_pre_set_power_state,
> .set_power_state = &ci_dpm_set_power_state,
> .post_set_power_state = &ci_dpm_post_set_power_state,
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 4324184..b229028 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -67,7 +67,6 @@
>
> #include "amdgpu_dm.h"
> #include "amdgpu_amdkfd.h"
> -#include "amdgpu_powerplay.h"
> #include "dce_virtual.h"
>
> /*
> @@ -2000,7 +1999,10 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
> amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + if (amdgpu_dpm == -1)
> + amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
> + else
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> @@ -2018,7 +2020,10 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
> amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + if (amdgpu_dpm == -1)
> + amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
> + else
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> @@ -2036,7 +2041,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
> amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> @@ -2055,7 +2060,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
> amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
> index c7b4349..2a08661 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
> @@ -24,8 +24,7 @@
> #ifndef __CIK_DPM_H__
> #define __CIK_DPM_H__
>
> -extern const struct amd_ip_funcs ci_dpm_ip_funcs;
> -extern const struct amd_ip_funcs kv_dpm_ip_funcs;
> -extern const struct amd_pm_funcs ci_dpm_funcs;
> -extern const struct amd_pm_funcs kv_dpm_funcs;
> +extern const struct amdgpu_ip_block_version ci_smu_ip_block;
> +extern const struct amdgpu_ip_block_version kv_smu_ip_block;
> +
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> index 8766681..81babe0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> @@ -42,6 +42,8 @@
> #define KV_MINIMUM_ENGINE_CLOCK 800
> #define SMC_RAM_END 0x40000
>
> +static const struct amd_pm_funcs kv_dpm_funcs;
> +
> static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
> static int kv_enable_nb_dpm(struct amdgpu_device *adev,
> bool enable);
> @@ -2960,6 +2962,7 @@ static int kv_dpm_early_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + adev->powerplay.pp_funcs = &kv_dpm_funcs;
> kv_dpm_set_irq_funcs(adev);
>
> return 0;
> @@ -3301,7 +3304,7 @@ static int kv_dpm_read_sensor(void *handle, int idx,
> }
> }
>
> -const struct amd_ip_funcs kv_dpm_ip_funcs = {
> +static const struct amd_ip_funcs kv_dpm_ip_funcs = {
> .name = "kv_dpm",
> .early_init = kv_dpm_early_init,
> .late_init = kv_dpm_late_init,
> @@ -3318,7 +3321,16 @@ static int kv_dpm_read_sensor(void *handle, int idx,
> .set_powergating_state = kv_dpm_set_powergating_state,
> };
>
> -const struct amd_pm_funcs kv_dpm_funcs = {
> +const struct amdgpu_ip_block_version kv_smu_ip_block =
> +{
> + .type = AMD_IP_BLOCK_TYPE_SMC,
> + .major = 1,
major should be 7 here as well.
> + .minor = 0,
> + .rev = 0,
> + .funcs = &kv_dpm_ip_funcs,
> +};
> +
> +static const struct amd_pm_funcs kv_dpm_funcs = {
> .pre_set_power_state = &kv_dpm_pre_set_power_state,
> .set_power_state = &kv_dpm_set_power_state,
> .post_set_power_state = &kv_dpm_post_set_power_state,
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 6e61b56..b154667 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -32,7 +32,7 @@
> #include "amdgpu_vce.h"
> #include "atom.h"
> #include "amd_pcie.h"
> -#include "amdgpu_powerplay.h"
> +#include "si_dpm.h"
> #include "sid.h"
> #include "si_ih.h"
> #include "gfx_v6_0.h"
> @@ -1983,7 +1983,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &si_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
> amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> else
> @@ -1997,7 +1997,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &si_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
> amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> else
> @@ -2011,7 +2011,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &si_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
> amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> index 8137c02..6d68bcd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> @@ -67,6 +67,8 @@
> MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
> MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
>
> +static const struct amd_pm_funcs si_dpm_funcs;
> +
> union power_info {
> struct _ATOM_POWERPLAY_INFO info;
> struct _ATOM_POWERPLAY_INFO_V2 info_2;
> @@ -7914,6 +7916,7 @@ static int si_dpm_early_init(void *handle)
>
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + adev->powerplay.pp_funcs = &si_dpm_funcs;
> si_dpm_set_irq_funcs(adev);
> return 0;
> }
> @@ -8014,7 +8017,7 @@ static int si_dpm_read_sensor(void *handle, int idx,
> }
> }
>
> -const struct amd_ip_funcs si_dpm_ip_funcs = {
> +static const struct amd_ip_funcs si_dpm_ip_funcs = {
> .name = "si_dpm",
> .early_init = si_dpm_early_init,
> .late_init = si_dpm_late_init,
> @@ -8031,7 +8034,16 @@ static int si_dpm_read_sensor(void *handle, int idx,
> .set_powergating_state = si_dpm_set_powergating_state,
> };
>
> -const struct amd_pm_funcs si_dpm_funcs = {
> +const struct amdgpu_ip_block_version si_smu_ip_block =
> +{
> + .type = AMD_IP_BLOCK_TYPE_SMC,
> + .major = 1,
major = 6.
> + .minor = 0,
> + .rev = 0,
> + .funcs = &si_dpm_ip_funcs,
> +};
> +
> +static const struct amd_pm_funcs si_dpm_funcs = {
> .pre_set_power_state = &si_dpm_pre_set_power_state,
> .set_power_state = &si_dpm_set_power_state,
> .post_set_power_state = &si_dpm_post_set_power_state,
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.h b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
> index 9fe343d..6b7d292 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
> @@ -245,8 +245,7 @@ enum si_display_gap
> SI_PM_DISPLAY_GAP_IGNORE = 3,
> };
>
> -extern const struct amd_ip_funcs si_dpm_ip_funcs;
> -extern const struct amd_pm_funcs si_dpm_funcs;
> +extern const struct amdgpu_ip_block_version si_smu_ip_block;
>
> struct ni_leakage_coeffients
> {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 8dc8b72..feb383a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -57,7 +57,6 @@
> #include "uvd_v7_0.h"
> #include "vce_v4_0.h"
> #include "vcn_v1_0.h"
> -#include "amdgpu_powerplay.h"
> #include "dce_virtual.h"
> #include "mxgpu_ai.h"
>
> @@ -534,7 +533,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
> amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
> if (!amdgpu_sriov_vf(adev))
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> @@ -553,7 +552,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
> amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
> amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 61360a1..7f01650 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -71,7 +71,6 @@
> #include "uvd_v5_0.h"
> #include "uvd_v6_0.h"
> #include "vce_v3_0.h"
> -#include "amdgpu_powerplay.h"
> #if defined(CONFIG_DRM_AMD_ACP)
> #include "amdgpu_acp.h"
> #endif
> @@ -1516,7 +1515,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
> amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
> @@ -1526,7 +1525,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
> amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> @@ -1546,7 +1545,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
> amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> @@ -1568,7 +1567,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
> amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> @@ -1586,7 +1585,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
> amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> @@ -1607,7 +1606,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
> amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
> - amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> if (adev->enable_virtual_display)
> amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 15bd0f9..5c840c0 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -24,8 +24,7 @@
> #ifndef __KGD_PP_INTERFACE_H__
> #define __KGD_PP_INTERFACE_H__
>
> -extern const struct amd_ip_funcs pp_ip_funcs;
> -extern const struct amd_pm_funcs pp_dpm_funcs;
> +extern const struct amdgpu_ip_block_version pp_smu_ip_block;
>
> struct amd_vce_state {
> /* vce clocks */
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index b989bf3..a5bc52c 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -27,7 +27,6 @@
> #include <linux/slab.h>
> #include "amd_shared.h"
> #include "amd_powerplay.h"
> -#include "pp_instance.h"
> #include "power_state.h"
> #include "amdgpu.h"
> #include "hwmgr.h"
> @@ -37,18 +36,14 @@
> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
>
> -static inline int pp_check(struct pp_instance *handle)
> -{
> - if (handle == NULL)
> - return -EINVAL;
> +static const struct amd_pm_funcs pp_dpm_funcs;
>
> - if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
> +static inline int pp_check(struct pp_hwmgr *hwmgr)
> +{
> + if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
> return -EINVAL;
>
> - if (handle->pm_en == 0)
> - return PP_DPM_DISABLED;
> -
> - if (handle->hwmgr->hwmgr_func == NULL)
> + if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
> return PP_DPM_DISABLED;
>
> return 0;
> @@ -56,54 +51,52 @@ static inline int pp_check(struct pp_instance *handle)
>
> static int amd_powerplay_create(struct amdgpu_device *adev)
> {
> - struct pp_instance *instance;
> + struct pp_hwmgr *hwmgr;
>
> if (adev == NULL)
> return -EINVAL;
>
> - instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
> - if (instance == NULL)
> + hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
> + if (hwmgr == NULL)
> return -ENOMEM;
>
> - instance->parent = adev;
> - instance->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
> - instance->device = adev->powerplay.cgs_device;
> - mutex_init(&instance->pp_lock);
> - adev->powerplay.pp_handle = instance;
> -
> + hwmgr->adev = adev;
> + hwmgr->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
> + hwmgr->device = amdgpu_cgs_create_device(adev);
> + mutex_init(&hwmgr->smu_lock);
> + hwmgr->chip_family = adev->family;
> + hwmgr->chip_id = adev->asic_type;
> + hwmgr->feature_mask = amdgpu_pp_feature_mask;
> + adev->powerplay.pp_handle = hwmgr;
> + adev->powerplay.pp_funcs = &pp_dpm_funcs;
> return 0;
> }
>
>
> -static int amd_powerplay_destroy(void *handle)
> +static int amd_powerplay_destroy(struct amdgpu_device *adev)
> {
> - struct pp_instance *instance = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>
> - kfree(instance->hwmgr->hardcode_pp_table);
> - instance->hwmgr->hardcode_pp_table = NULL;
> + kfree(hwmgr->hardcode_pp_table);
> + hwmgr->hardcode_pp_table = NULL;
>
> - kfree(instance->hwmgr);
> - instance->hwmgr = NULL;
> + kfree(hwmgr);
> + hwmgr = NULL;
>
> - kfree(instance);
> - instance = NULL;
> return 0;
> }
>
> static int pp_early_init(void *handle)
> {
> int ret;
> - struct pp_instance *pp_handle = NULL;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = handle;
>
> ret = amd_powerplay_create(adev);
>
> if (ret != 0)
> return ret;
>
> - pp_handle = adev->powerplay.pp_handle;
> -
> - ret = hwmgr_early_init(pp_handle);
> + ret = hwmgr_early_init(adev->powerplay.pp_handle);
> if (ret)
> return -EINVAL;
>
> @@ -112,15 +105,13 @@ static int pp_early_init(void *handle)
>
> static int pp_sw_init(void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> + struct amdgpu_device *adev = handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret >= 0) {
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->smumgr_funcs->smu_init == NULL)
> return -EINVAL;
>
> @@ -128,55 +119,53 @@ static int pp_sw_init(void *handle)
>
> pr_debug("amdgpu: powerplay sw initialized\n");
> }
> +
> return ret;
> }
>
> static int pp_sw_fini(void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> + struct amdgpu_device *adev = handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> if (ret >= 0) {
> - hwmgr = pp_handle->hwmgr;
> -
> - if (hwmgr->smumgr_funcs->smu_fini == NULL)
> - return -EINVAL;
> -
> - ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
> + if (hwmgr->smumgr_funcs->smu_fini != NULL)
> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
> }
> - return ret;
> + return 0;
> }
>
> static int pp_hw_init(void *handle)
> {
> int ret = 0;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> - struct pp_hwmgr *hwmgr;
> + struct amdgpu_device *adev = handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>
> - ret = pp_check(pp_handle);
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> + amdgpu_ucode_init_bo(adev);
>
> - if (ret >= 0) {
> - hwmgr = pp_handle->hwmgr;
> + ret = pp_check(hwmgr);
>
> + if (ret >= 0) {
> if (hwmgr->smumgr_funcs->start_smu == NULL)
> return -EINVAL;
>
> - if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> pr_err("smc start failed\n");
> - hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
> return -EINVAL;
> }
> if (ret == PP_DPM_DISABLED)
> goto exit;
> - ret = hwmgr_hw_init(pp_handle);
> + ret = hwmgr_hw_init(hwmgr);
> if (ret)
> goto exit;
> }
> return ret;
> exit:
> - pp_handle->pm_en = 0;
> + hwmgr->pm_en = 0;
> cgs_notify_dpm_enabled(hwmgr->device, false);
> return 0;
>
> @@ -184,24 +173,27 @@ static int pp_hw_init(void *handle)
>
> static int pp_hw_fini(void *handle)
> {
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct amdgpu_device *adev = handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> if (ret == 0)
> - hwmgr_hw_fini(pp_handle);
> + hwmgr_hw_fini(hwmgr);
>
> return 0;
> }
>
> static int pp_late_init(void *handle)
> {
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct amdgpu_device *adev = handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> +
> if (ret == 0)
> - pp_dpm_dispatch_tasks(pp_handle,
> + pp_dpm_dispatch_tasks(hwmgr,
> AMD_PP_TASK_COMPLETE_INIT, NULL);
>
> return 0;
> @@ -231,17 +223,15 @@ static int pp_sw_reset(void *handle)
> static int pp_set_powergating_state(void *handle,
> enum amd_powergating_state state)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct amdgpu_device *adev = handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> @@ -254,44 +244,43 @@ static int pp_set_powergating_state(void *handle,
>
> static int pp_suspend(void *handle)
> {
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct amdgpu_device *adev = handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> if (ret == 0)
> - hwmgr_hw_suspend(pp_handle);
> + hwmgr_hw_suspend(hwmgr);
> return 0;
> }
>
> static int pp_resume(void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> + struct amdgpu_device *adev = handle;
> + struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret < 0)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->smumgr_funcs->start_smu == NULL)
> return -EINVAL;
>
> - if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> pr_err("smc start failed\n");
> - hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
> return -EINVAL;
> }
>
> if (ret == PP_DPM_DISABLED)
> return 0;
>
> - return hwmgr_hw_resume(pp_handle);
> + return hwmgr_hw_resume(hwmgr);
> }
>
> -const struct amd_ip_funcs pp_ip_funcs = {
> +static const struct amd_ip_funcs pp_ip_funcs = {
> .name = "powerplay",
> .early_init = pp_early_init,
> .late_init = pp_late_init,
> @@ -309,6 +298,15 @@ static int pp_resume(void *handle)
> .set_powergating_state = pp_set_powergating_state,
> };
>
> +const struct amdgpu_ip_block_version pp_smu_ip_block =
> +{
> + .type = AMD_IP_BLOCK_TYPE_SMC,
> + .major = 1,
> + .minor = 0,
> + .rev = 0,
> + .funcs = &pp_ip_funcs,
> +};
In theory we could add multiple ip_block definitions with the same
funcs, one for each IP version (7, 8, 9) and assign them as
appropriate so that the version reporting is correct, but that could
be a follow up patch.
With the above addressed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> +
> static int pp_dpm_load_fw(void *handle)
> {
> return 0;
> @@ -321,17 +319,14 @@ static int pp_dpm_fw_loading_complete(void *handle)
>
> static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> @@ -379,25 +374,22 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
> static int pp_dpm_force_performance_level(void *handle,
> enum amd_dpm_forced_level level)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (level == hwmgr->dpm_level)
> return 0;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> pp_dpm_en_umd_pstate(hwmgr, &level);
> hwmgr->request_dpm_level = level;
> - hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
> - mutex_unlock(&pp_handle->pp_lock);
> + hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
> + mutex_unlock(&hwmgr->smu_lock);
>
> return 0;
> }
> @@ -405,152 +397,135 @@ static int pp_dpm_force_performance_level(void *handle,
> static enum amd_dpm_forced_level pp_dpm_get_performance_level(
> void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
> enum amd_dpm_forced_level level;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> level = hwmgr->dpm_level;
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return level;
> }
>
> static uint32_t pp_dpm_get_sclk(void *handle, bool low)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
> uint32_t clk = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->get_sclk == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return clk;
> }
>
> static uint32_t pp_dpm_get_mclk(void *handle, bool low)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
> uint32_t clk = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->get_mclk == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return clk;
> }
>
> static void pp_dpm_powergate_vce(void *handle, bool gate)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->powergate_vce == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> }
>
> static void pp_dpm_powergate_uvd(void *handle, bool gate)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> }
>
> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state)
> {
> int ret = 0;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - mutex_lock(&pp_handle->pp_lock);
> - ret = hwmgr_handle_task(pp_handle, task_id, user_state);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> + ret = hwmgr_handle_task(hwmgr, task_id, user_state);
> + mutex_unlock(&hwmgr->smu_lock);
>
> return ret;
> }
>
> static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> + struct pp_hwmgr *hwmgr = handle;
> struct pp_power_state *state;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> int ret = 0;
> enum amd_pm_state_type pm_type;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->current_ps == NULL)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
>
> state = hwmgr->current_ps;
>
> @@ -571,147 +546,129 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> pm_type = POWER_STATE_TYPE_DEFAULT;
> break;
> }
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
>
> return pm_type;
> }
>
> static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> }
>
> static uint32_t pp_dpm_get_fan_control_mode(void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
> uint32_t mode = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return mode;
> }
>
> static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_get_pp_num_states(void *handle,
> struct pp_states_info *data)
> {
> - struct pp_hwmgr *hwmgr;
> + struct pp_hwmgr *hwmgr = handle;
> int i;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> int ret = 0;
>
> memset(data, 0, sizeof(*data));
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->ps == NULL)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
>
> data->nums = hwmgr->num_ps;
>
> @@ -735,73 +692,68 @@ static int pp_dpm_get_pp_num_states(void *handle,
> data->states[i] = POWER_STATE_TYPE_DEFAULT;
> }
> }
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return 0;
> }
>
> static int pp_dpm_get_pp_table(void *handle, char **table)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
> int size = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (!hwmgr->soft_pp_table)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> *table = (char *)hwmgr->soft_pp_table;
> size = hwmgr->soft_pp_table_size;
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return size;
> }
>
> static int amd_powerplay_reset(void *handle)
> {
> - struct pp_instance *instance = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret;
>
> - ret = pp_check(instance);
> + ret = pp_check(hwmgr);
> if (ret)
> return ret;
>
> - ret = pp_hw_fini(instance);
> + ret = pp_hw_fini(hwmgr);
> if (ret)
> return ret;
>
> - ret = hwmgr_hw_init(instance);
> + ret = hwmgr_hw_init(hwmgr);
> if (ret)
> return ret;
>
> - return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL);
> + return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
> }
>
> static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> if (!hwmgr->hardcode_pp_table) {
> hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
> hwmgr->soft_pp_table_size,
> GFP_KERNEL);
> if (!hwmgr->hardcode_pp_table) {
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return -ENOMEM;
> }
> }
> @@ -809,7 +761,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> memcpy(hwmgr->hardcode_pp_table, buf, size);
>
> hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
>
> ret = amd_powerplay_reset(handle);
> if (ret)
> @@ -827,163 +779,142 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> static int pp_dpm_force_clock_level(void *handle,
> enum pp_clock_type type, uint32_t mask)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->force_clock_level == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
> ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
> else
> ret = -EINVAL;
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_print_clock_levels(void *handle,
> enum pp_clock_type type, char *buf)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_get_sclk_od(void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_get_mclk_od(void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_dpm_read_sensor(void *handle, int idx,
> void *value, int *size)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> if (ret)
> return ret;
>
> if (value == NULL)
> return -EINVAL;
>
> - hwmgr = pp_handle->hwmgr;
> -
> switch (idx) {
> case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
> *((uint32_t *)value) = hwmgr->pstate_sclk;
> @@ -992,9 +923,9 @@ static int pp_dpm_read_sensor(void *handle, int idx,
> *((uint32_t *)value) = hwmgr->pstate_mclk;
> return 0;
> default:
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
> }
> @@ -1002,17 +933,14 @@ static int pp_dpm_read_sensor(void *handle, int idx,
> static struct amd_vce_state*
> pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return NULL;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr && idx < hwmgr->num_vce_state_tables)
> return &hwmgr->vce_states[idx];
> return NULL;
> @@ -1020,14 +948,11 @@ static int pp_dpm_read_sensor(void *handle, int idx,
>
> static int pp_get_power_profile_mode(void *handle, char *buf)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
>
> - if (!buf || pp_check(pp_handle))
> + if (!buf || pp_check(hwmgr))
> return -EINVAL;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return snprintf(buf, PAGE_SIZE, "\n");
> @@ -1038,36 +963,30 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
>
> static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = -EINVAL;
>
> - if (pp_check(pp_handle))
> + if (pp_check(hwmgr))
> return -EINVAL;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return -EINVAL;
> }
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
> ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
>
> - if (pp_check(pp_handle))
> + if (pp_check(hwmgr))
> return -EINVAL;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return -EINVAL;
> @@ -1079,16 +998,13 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
> static int pp_dpm_switch_power_profile(void *handle,
> enum PP_SMC_POWER_PROFILE type, bool en)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> long workload;
> uint32_t index;
>
> - if (pp_check(pp_handle))
> + if (pp_check(hwmgr))
> return -EINVAL;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return -EINVAL;
> @@ -1097,7 +1013,7 @@ static int pp_dpm_switch_power_profile(void *handle,
> if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
>
> if (!en) {
> hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
> @@ -1113,7 +1029,7 @@ static int pp_dpm_switch_power_profile(void *handle,
>
> if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
> hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
>
> return 0;
> }
> @@ -1125,46 +1041,40 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
> uint32_t mc_addr_hi,
> uint32_t size)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return -EINVAL;
> }
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
>
> ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
> virtual_addr_hi, mc_addr_low, mc_addr_hi,
> size);
>
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
>
> return ret;
> }
>
> static int pp_set_power_limit(void *handle, uint32_t limit)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->set_power_limit == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return -EINVAL;
> @@ -1176,20 +1086,19 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
> if (limit > hwmgr->default_power_limit)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
> hwmgr->power_limit = limit;
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
> @@ -1197,16 +1106,14 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
> if (limit == NULL)
> return -EINVAL;
>
> - hwmgr = pp_handle->hwmgr;
> -
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
>
> if (default_limit)
> *limit = hwmgr->default_power_limit;
> else
> *limit = hwmgr->power_limit;
>
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
>
> return ret;
> }
> @@ -1214,42 +1121,37 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
> static int pp_display_configuration_change(void *handle,
> const struct amd_pp_display_configuration *display_config)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> phm_store_dal_configuration_data(hwmgr, display_config);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return 0;
> }
>
> static int pp_get_display_power_level(void *handle,
> struct amd_pp_simple_clock_info *output)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (output == NULL)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = phm_get_dal_power_level(hwmgr, output);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> @@ -1258,18 +1160,15 @@ static int pp_get_current_clocks(void *handle,
> {
> struct amd_pp_simple_clock_info simple_clocks;
> struct pp_clock_info hw_clocks;
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
>
> phm_get_dal_power_level(hwmgr, &simple_clocks);
>
> @@ -1283,7 +1182,7 @@ static int pp_get_current_clocks(void *handle,
>
> if (ret) {
> pr_info("Error in phm_get_clock_info \n");
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return -EINVAL;
> }
>
> @@ -1303,29 +1202,26 @@ static int pp_get_current_clocks(void *handle,
> clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
> clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
> }
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return 0;
> }
>
> static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (clocks == NULL)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = phm_get_clock_by_type(hwmgr, type, clocks);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> @@ -1333,21 +1229,19 @@ static int pp_get_clock_by_type_with_latency(void *handle,
> enum amd_pp_clock_type type,
> struct pp_clock_levels_with_latency *clocks)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> if (ret)
> return ret;
>
> if (!clocks)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> - hwmgr = ((struct pp_instance *)handle)->hwmgr;
> + mutex_lock(&hwmgr->smu_lock);
> ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> @@ -1355,47 +1249,41 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
> enum amd_pp_clock_type type,
> struct pp_clock_levels_with_voltage *clocks)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> if (ret)
> return ret;
>
> if (!clocks)
> return -EINVAL;
>
> - hwmgr = ((struct pp_instance *)handle)->hwmgr;
> -
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
>
> ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
>
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_set_watermarks_for_clocks_ranges(void *handle,
> struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> if (ret)
> return ret;
>
> if (!wm_with_clock_ranges)
> return -EINVAL;
>
> - hwmgr = ((struct pp_instance *)handle)->hwmgr;
> -
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
> wm_with_clock_ranges);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
>
> return ret;
> }
> @@ -1403,22 +1291,19 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
> static int pp_display_clock_voltage_request(void *handle,
> struct pp_display_clock_request *clock)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
> if (ret)
> return ret;
>
> if (!clock)
> return -EINVAL;
>
> - hwmgr = ((struct pp_instance *)handle)->hwmgr;
> -
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
> ret = phm_display_clock_voltage_request(hwmgr, clock);
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
>
> return ret;
> }
> @@ -1426,42 +1311,36 @@ static int pp_display_clock_voltage_request(void *handle,
> static int pp_get_display_mode_validation_clocks(void *handle,
> struct amd_pp_simple_clock_info *clocks)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (clocks == NULL)
> return -EINVAL;
>
> - mutex_lock(&pp_handle->pp_lock);
> + mutex_lock(&hwmgr->smu_lock);
>
> if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
> ret = phm_get_max_high_clocks(hwmgr, clocks);
>
> - mutex_unlock(&pp_handle->pp_lock);
> + mutex_unlock(&hwmgr->smu_lock);
> return ret;
> }
>
> static int pp_set_mmhub_powergating_by_smu(void *handle)
> {
> - struct pp_hwmgr *hwmgr;
> - struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(pp_handle);
> + ret = pp_check(hwmgr);
>
> if (ret)
> return ret;
>
> - hwmgr = pp_handle->hwmgr;
> -
> if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> return 0;
> @@ -1470,7 +1349,7 @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
> return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
> }
>
> -const struct amd_pm_funcs pp_dpm_funcs = {
> +static const struct amd_pm_funcs pp_dpm_funcs = {
> .load_firmware = pp_dpm_load_fw,
> .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
> .force_performance_level = pp_dpm_force_performance_level,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 5563b65..238dd59 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -116,23 +116,11 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
> hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
> }
>
> -int hwmgr_early_init(struct pp_instance *handle)
> +int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> {
> - struct pp_hwmgr *hwmgr;
> -
> - if (handle == NULL)
> + if (hwmgr == NULL)
> return -EINVAL;
>
> - hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
> - if (hwmgr == NULL)
> - return -ENOMEM;
> -
> - handle->hwmgr = hwmgr;
> - hwmgr->adev = handle->parent;
> - hwmgr->device = handle->device;
> - hwmgr->chip_family = ((struct amdgpu_device *)handle->parent)->family;
> - hwmgr->chip_id = ((struct amdgpu_device *)handle->parent)->asic_type;
> - hwmgr->feature_mask = amdgpu_pp_feature_mask;
> hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
> hwmgr->power_source = PP_PowerSource_AC;
> hwmgr->pp_table_version = PP_TABLE_V1;
> @@ -220,16 +208,13 @@ int hwmgr_early_init(struct pp_instance *handle)
> return 0;
> }
>
> -int hwmgr_hw_init(struct pp_instance *handle)
> +int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
> {
> - struct pp_hwmgr *hwmgr;
> int ret = 0;
>
> - if (handle == NULL)
> + if (hwmgr == NULL)
> return -EINVAL;
>
> - hwmgr = handle->hwmgr;
> -
> if (hwmgr->pptable_func == NULL ||
> hwmgr->pptable_func->pptable_init == NULL ||
> hwmgr->hwmgr_func->backend_init == NULL)
> @@ -275,15 +260,11 @@ int hwmgr_hw_init(struct pp_instance *handle)
> return ret;
> }
>
> -int hwmgr_hw_fini(struct pp_instance *handle)
> +int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
> {
> - struct pp_hwmgr *hwmgr;
> -
> - if (handle == NULL || handle->hwmgr == NULL)
> + if (hwmgr == NULL)
> return -EINVAL;
>
> - hwmgr = handle->hwmgr;
> -
> phm_stop_thermal_controller(hwmgr);
> psm_set_boot_states(hwmgr);
> psm_adjust_power_state_dynamic(hwmgr, false, NULL);
> @@ -297,15 +278,13 @@ int hwmgr_hw_fini(struct pp_instance *handle)
> return psm_fini_power_state_table(hwmgr);
> }
>
> -int hwmgr_hw_suspend(struct pp_instance *handle)
> +int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
> {
> - struct pp_hwmgr *hwmgr;
> int ret = 0;
>
> - if (handle == NULL || handle->hwmgr == NULL)
> + if (hwmgr == NULL)
> return -EINVAL;
>
> - hwmgr = handle->hwmgr;
> phm_disable_smc_firmware_ctf(hwmgr);
> ret = psm_set_boot_states(hwmgr);
> if (ret)
> @@ -318,15 +297,13 @@ int hwmgr_hw_suspend(struct pp_instance *handle)
> return ret;
> }
>
> -int hwmgr_hw_resume(struct pp_instance *handle)
> +int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
> {
> - struct pp_hwmgr *hwmgr;
> int ret = 0;
>
> - if (handle == NULL || handle->hwmgr == NULL)
> + if (hwmgr == NULL)
> return -EINVAL;
>
> - hwmgr = handle->hwmgr;
> ret = phm_setup_asic(hwmgr);
> if (ret)
> return ret;
> @@ -361,17 +338,14 @@ static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
> }
> }
>
> -int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id,
> +int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state)
> {
> int ret = 0;
> - struct pp_hwmgr *hwmgr;
>
> - if (handle == NULL || handle->hwmgr == NULL)
> + if (hwmgr == NULL)
> return -EINVAL;
>
> - hwmgr = handle->hwmgr;
> -
> switch (task_id) {
> case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
> ret = phm_set_cpu_power_state(hwmgr);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 2e2e4d0..85b46ad 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -25,7 +25,6 @@
>
> #include <linux/seq_file.h>
> #include "amd_powerplay.h"
> -#include "pp_instance.h"
> #include "hardwaremanager.h"
> #include "pp_power_source.h"
> #include "hwmgr_ppt.h"
> @@ -34,7 +33,6 @@
> #include "power_state.h"
> #include "smu_helper.h"
>
> -struct pp_instance;
> struct pp_hwmgr;
> struct phm_fan_speed_info;
> struct pp_atomctrl_voltage_table;
> @@ -703,6 +701,8 @@ struct pp_hwmgr {
> uint32_t chip_family;
> uint32_t chip_id;
> uint32_t smu_version;
> + bool pm_en;
> + struct mutex smu_lock;
>
> uint32_t pp_table_version;
> void *device;
> @@ -769,12 +769,12 @@ struct cgs_irq_src_funcs {
> cgs_irq_handler_func_t handler;
> };
>
> -extern int hwmgr_early_init(struct pp_instance *handle);
> -extern int hwmgr_hw_init(struct pp_instance *handle);
> -extern int hwmgr_hw_fini(struct pp_instance *handle);
> -extern int hwmgr_hw_suspend(struct pp_instance *handle);
> -extern int hwmgr_hw_resume(struct pp_instance *handle);
> -extern int hwmgr_handle_task(struct pp_instance *handle,
> +extern int hwmgr_early_init(struct pp_hwmgr *hwmgr);
> +extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
> +extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
> +extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
> +extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
> +extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
> enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> deleted file mode 100644
> index 6c2fa33..0000000
> --- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/*
> - * Copyright 2015 Advanced Micro Devices, Inc.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - */
> -#ifndef _PP_INSTANCE_H_
> -#define _PP_INSTANCE_H_
> -
> -struct pp_hwmgr;
> -
> -struct pp_instance {
> - void *parent; /* e.g. amdgpu_device */
> - void *device; /* e.g. cgs_device */
> - bool pm_en;
> - struct pp_hwmgr *hwmgr;
> - struct mutex pp_lock;
> -};
> -
> -#endif
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-03-13 16:02 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-12 12:34 [PATCH 1/4] drm/amd/pp: Move helper functions to smu_help.c Rex Zhu
[not found] ` <1520858050-7338-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-12 12:34 ` [PATCH 2/4] drm/amdgpu: Plus NULL function pointer check Rex Zhu
[not found] ` <1520858050-7338-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-12 12:54 ` Christian König
[not found] ` <71e3bf37-5289-422b-7b04-de2d4e60ce9c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-03-12 14:13 ` Zhu, Rex
2018-03-12 12:34 ` [PATCH 3/4] drm/amdgpu: Remove wrapper layer of amdgpu_powerplay Rex Zhu
[not found] ` <1520858050-7338-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-13 16:02 ` Alex Deucher
2018-03-12 12:34 ` [PATCH 4/4] drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c Rex Zhu
[not found] ` <1520858050-7338-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-13 15:55 ` Alex Deucher
2018-03-13 15:56 ` [PATCH 1/4] drm/amd/pp: Move helper functions to smu_help.c Alex Deucher
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