* [PATCH] drm/amdgpu: refine vce3.0 initialize.
@ 2017-01-09 13:34 Rex Zhu
[not found] ` <1483968878-1370-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Rex Zhu @ 2017-01-09 13:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
1. disable vce cg when vce hw initialize.
2. initizlize vce clock to 10KHz.
3: no need to set bypass clock to vce.
Change-Id: I18d5c2debc6688be201af8bb85022ac25020bd8f
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 18 +++---------------
drivers/gpu/drm/amd/amdgpu/vi.c | 32 +++++++++++++++++++++++++++++++-
2 files changed, 34 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 5fb0b7f..eb99ee6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -223,6 +223,9 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
struct amdgpu_ring *ring;
int idx, r;
+ vce_v3_0_override_vce_clock_gating(adev, true); /* force all clocks on */
+ amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
+
ring = &adev->vce.ring[0];
WREG32(mmVCE_RB_RPTR, ring->wptr);
WREG32(mmVCE_RB_WPTR, ring->wptr);
@@ -701,17 +704,7 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
-{
- u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
-
- if (enable)
- tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
- else
- tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
- WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
-}
static int vce_v3_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
@@ -720,11 +713,6 @@ static int vce_v3_0_set_clockgating_state(void *handle,
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
int i;
- if ((adev->asic_type == CHIP_POLARIS10) ||
- (adev->asic_type == CHIP_TONGA) ||
- (adev->asic_type == CHIP_FIJI))
- vce_v3_0_set_bypass_mode(adev, enable);
-
if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 16ba943..b9924e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -789,7 +789,37 @@ static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
{
- /* todo */
+ int r, i;
+ struct atom_clock_dividers dividers;
+ u32 tmp;
+
+ r = amdgpu_atombios_get_clock_dividers(adev,
+ COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
+ ecclk, false, ÷rs);
+ if (r)
+ return r;
+
+ for (i = 0; i < 100; i++) {
+ if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
+ break;
+ mdelay(10);
+ }
+ if (i == 100)
+ return -ETIMEDOUT;
+
+ tmp = RREG32_SMC(ixCG_ECLK_CNTL);
+ tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
+ CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
+ tmp |= dividers.post_divider;
+ WREG32_SMC(ixCG_ECLK_CNTL, tmp);
+
+ for (i = 0; i < 100; i++) {
+ if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
+ break;
+ mdelay(10);
+ }
+ if (i == 100)
+ return -ETIMEDOUT;
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: refine vce3.0 initialize.
[not found] ` <1483968878-1370-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-01-09 14:16 ` StDenis, Tom
2017-01-09 14:34 ` Deucher, Alexander
1 sibling, 0 replies; 5+ messages in thread
From: StDenis, Tom @ 2017-01-09 14:16 UTC (permalink / raw)
To: Zhu, Rex, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 4911 bytes --]
On my Carrizo, I have to NAK since monitoring the clocks I see GFX and VCE pegged high on a setup with a staging kernel .
Doing a test signal encode I see 1000 fences/sec being handled and GFX_POWER throttles (not idle or full) . I don't see VCE load from SRBM_STATUS2 though ...
Something is up for sure.
I haven't tried HEAD~ (I last tried a 4.9 kernel about 15 commits ago) so I'll try that now.
Tom
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, January 9, 2017 08:34
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amdgpu: refine vce3.0 initialize.
1. disable vce cg when vce hw initialize.
2. initizlize vce clock to 10KHz.
3: no need to set bypass clock to vce.
Change-Id: I18d5c2debc6688be201af8bb85022ac25020bd8f
Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 18 +++---------------
drivers/gpu/drm/amd/amdgpu/vi.c | 32 +++++++++++++++++++++++++++++++-
2 files changed, 34 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 5fb0b7f..eb99ee6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -223,6 +223,9 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
struct amdgpu_ring *ring;
int idx, r;
+ vce_v3_0_override_vce_clock_gating(adev, true); /* force all clocks on */
+ amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
+
ring = &adev->vce.ring[0];
WREG32(mmVCE_RB_RPTR, ring->wptr);
WREG32(mmVCE_RB_WPTR, ring->wptr);
@@ -701,17 +704,7 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
-{
- u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
-
- if (enable)
- tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
- else
- tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
- WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
-}
static int vce_v3_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
@@ -720,11 +713,6 @@ static int vce_v3_0_set_clockgating_state(void *handle,
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
int i;
- if ((adev->asic_type == CHIP_POLARIS10) ||
- (adev->asic_type == CHIP_TONGA) ||
- (adev->asic_type == CHIP_FIJI))
- vce_v3_0_set_bypass_mode(adev, enable);
-
if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 16ba943..b9924e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -789,7 +789,37 @@ static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
{
- /* todo */
+ int r, i;
+ struct atom_clock_dividers dividers;
+ u32 tmp;
+
+ r = amdgpu_atombios_get_clock_dividers(adev,
+ COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
+ ecclk, false, ÷rs);
+ if (r)
+ return r;
+
+ for (i = 0; i < 100; i++) {
+ if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
+ break;
+ mdelay(10);
+ }
+ if (i == 100)
+ return -ETIMEDOUT;
+
+ tmp = RREG32_SMC(ixCG_ECLK_CNTL);
+ tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
+ CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
+ tmp |= dividers.post_divider;
+ WREG32_SMC(ixCG_ECLK_CNTL, tmp);
+
+ for (i = 0; i < 100; i++) {
+ if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
+ break;
+ mdelay(10);
+ }
+ if (i == 100)
+ return -ETIMEDOUT;
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: refine vce3.0 initialize.
[not found] ` <1483968878-1370-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-01-09 14:16 ` StDenis, Tom
@ 2017-01-09 14:34 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652DFF695E7EA9413F49C27F7640-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
1 sibling, 1 reply; 5+ messages in thread
From: Deucher, Alexander @ 2017-01-09 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, Rex
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Monday, January 09, 2017 8:35 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amdgpu: refine vce3.0 initialize.
>
> 1. disable vce cg when vce hw initialize.
> 2. initizlize vce clock to 10KHz.
> 3: no need to set bypass clock to vce.
>
> Change-Id: I18d5c2debc6688be201af8bb85022ac25020bd8f
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Does this patch fix this bug by any chance?
https://bugzilla.kernel.org/show_bug.cgi?id=191281
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 18 +++---------------
> drivers/gpu/drm/amd/amdgpu/vi.c | 32
> +++++++++++++++++++++++++++++++-
> 2 files changed, 34 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 5fb0b7f..eb99ee6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -223,6 +223,9 @@ static int vce_v3_0_start(struct amdgpu_device
> *adev)
> struct amdgpu_ring *ring;
> int idx, r;
>
> + vce_v3_0_override_vce_clock_gating(adev, true); /* force all clocks
> on */
> + amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
> +
> ring = &adev->vce.ring[0];
> WREG32(mmVCE_RB_RPTR, ring->wptr);
> WREG32(mmVCE_RB_WPTR, ring->wptr);
> @@ -701,17 +704,7 @@ static int vce_v3_0_process_interrupt(struct
> amdgpu_device *adev,
> return 0;
> }
>
> -static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool
> enable)
> -{
> - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
> -
> - if (enable)
> - tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
> - else
> - tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
>
> - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
> -}
>
> static int vce_v3_0_set_clockgating_state(void *handle,
> enum amd_clockgating_state state)
> @@ -720,11 +713,6 @@ static int vce_v3_0_set_clockgating_state(void
> *handle,
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> int i;
>
> - if ((adev->asic_type == CHIP_POLARIS10) ||
> - (adev->asic_type == CHIP_TONGA) ||
> - (adev->asic_type == CHIP_FIJI))
> - vce_v3_0_set_bypass_mode(adev, enable);
> -
> if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
> return 0;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
> b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 16ba943..b9924e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -789,7 +789,37 @@ static int vi_set_uvd_clocks(struct amdgpu_device
> *adev, u32 vclk, u32 dclk)
>
> static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32
> ecclk)
> {
> - /* todo */
> + int r, i;
> + struct atom_clock_dividers dividers;
> + u32 tmp;
> +
> + r = amdgpu_atombios_get_clock_dividers(adev,
> +
> COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
> + ecclk, false, ÷rs);
> + if (r)
> + return r;
> +
> + for (i = 0; i < 100; i++) {
> + if (RREG32_SMC(ixCG_ECLK_STATUS) &
> CG_ECLK_STATUS__ECLK_STATUS_MASK)
> + break;
> + mdelay(10);
> + }
> + if (i == 100)
> + return -ETIMEDOUT;
> +
> + tmp = RREG32_SMC(ixCG_ECLK_CNTL);
> + tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
> + CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
> + tmp |= dividers.post_divider;
> + WREG32_SMC(ixCG_ECLK_CNTL, tmp);
> +
> + for (i = 0; i < 100; i++) {
> + if (RREG32_SMC(ixCG_ECLK_STATUS) &
> CG_ECLK_STATUS__ECLK_STATUS_MASK)
> + break;
> + mdelay(10);
> + }
> + if (i == 100)
> + return -ETIMEDOUT;
>
> return 0;
> }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: refine vce3.0 initialize.
[not found] ` <BN6PR12MB1652DFF695E7EA9413F49C27F7640-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-01-09 16:58 ` StDenis, Tom
[not found] ` <CY4PR12MB176891CF60F99D5E2B57952CF7640-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: StDenis, Tom @ 2017-01-09 16:58 UTC (permalink / raw)
To: Deucher, Alexander, Zhu, Rex, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 5197 bytes --]
Just a heads up there is a CG/PG regression. On the tip of 4.7 I can encode with cg/pg disabled but with it enabled it locks up.
I'll try to bisect.
Tom
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, January 9, 2017 09:34
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: RE: [PATCH] drm/amdgpu: refine vce3.0 initialize.
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> Of Rex Zhu
> Sent: Monday, January 09, 2017 8:35 AM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amdgpu: refine vce3.0 initialize.
>
> 1. disable vce cg when vce hw initialize.
> 2. initizlize vce clock to 10KHz.
> 3: no need to set bypass clock to vce.
>
> Change-Id: I18d5c2debc6688be201af8bb85022ac25020bd8f
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
Does this patch fix this bug by any chance?
https://bugzilla.kernel.org/show_bug.cgi?id=191281
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 18 +++---------------
> drivers/gpu/drm/amd/amdgpu/vi.c | 32
> +++++++++++++++++++++++++++++++-
> 2 files changed, 34 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 5fb0b7f..eb99ee6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -223,6 +223,9 @@ static int vce_v3_0_start(struct amdgpu_device
> *adev)
> struct amdgpu_ring *ring;
> int idx, r;
>
> + vce_v3_0_override_vce_clock_gating(adev, true); /* force all clocks
> on */
> + amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
> +
> ring = &adev->vce.ring[0];
> WREG32(mmVCE_RB_RPTR, ring->wptr);
> WREG32(mmVCE_RB_WPTR, ring->wptr);
> @@ -701,17 +704,7 @@ static int vce_v3_0_process_interrupt(struct
> amdgpu_device *adev,
> return 0;
> }
>
> -static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool
> enable)
> -{
> - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
> -
> - if (enable)
> - tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
> - else
> - tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
>
> - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
> -}
>
> static int vce_v3_0_set_clockgating_state(void *handle,
> enum amd_clockgating_state state)
> @@ -720,11 +713,6 @@ static int vce_v3_0_set_clockgating_state(void
> *handle,
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> int i;
>
> - if ((adev->asic_type == CHIP_POLARIS10) ||
> - (adev->asic_type == CHIP_TONGA) ||
> - (adev->asic_type == CHIP_FIJI))
> - vce_v3_0_set_bypass_mode(adev, enable);
> -
> if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
> return 0;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
> b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 16ba943..b9924e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -789,7 +789,37 @@ static int vi_set_uvd_clocks(struct amdgpu_device
> *adev, u32 vclk, u32 dclk)
>
> static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32
> ecclk)
> {
> - /* todo */
> + int r, i;
> + struct atom_clock_dividers dividers;
> + u32 tmp;
> +
> + r = amdgpu_atombios_get_clock_dividers(adev,
> +
> COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
> + ecclk, false, ÷rs);
> + if (r)
> + return r;
> +
> + for (i = 0; i < 100; i++) {
> + if (RREG32_SMC(ixCG_ECLK_STATUS) &
> CG_ECLK_STATUS__ECLK_STATUS_MASK)
> + break;
> + mdelay(10);
> + }
> + if (i == 100)
> + return -ETIMEDOUT;
> +
> + tmp = RREG32_SMC(ixCG_ECLK_CNTL);
> + tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
> + CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
> + tmp |= dividers.post_divider;
> + WREG32_SMC(ixCG_ECLK_CNTL, tmp);
> +
> + for (i = 0; i < 100; i++) {
> + if (RREG32_SMC(ixCG_ECLK_STATUS) &
> CG_ECLK_STATUS__ECLK_STATUS_MASK)
> + break;
> + mdelay(10);
> + }
> + if (i == 100)
> + return -ETIMEDOUT;
>
> return 0;
> }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: refine vce3.0 initialize.
[not found] ` <CY4PR12MB176891CF60F99D5E2B57952CF7640-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-01-09 17:53 ` StDenis, Tom
0 siblings, 0 replies; 5+ messages in thread
From: StDenis, Tom @ 2017-01-09 17:53 UTC (permalink / raw)
To: Deucher, Alexander, Zhu, Rex, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
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I suspect the patch I NAK'ed on 4.9 "worked but with odd clocks" because it never engaged PG properly. I'm finding on 4.9 and 4.7 if PG is enabled VCE doesn't wake properly.
I've found a "good commit" on 4.7 so I'll continue bisecting.
Tom
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of StDenis, Tom <Tom.StDenis-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, January 9, 2017 11:58
To: Deucher, Alexander; Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH] drm/amdgpu: refine vce3.0 initialize.
Just a heads up there is a CG/PG regression. On the tip of 4.7 I can encode with cg/pg disabled but with it enabled it locks up.
I'll try to bisect.
Tom
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, January 9, 2017 09:34
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: RE: [PATCH] drm/amdgpu: refine vce3.0 initialize.
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> Of Rex Zhu
> Sent: Monday, January 09, 2017 8:35 AM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amdgpu: refine vce3.0 initialize.
>
> 1. disable vce cg when vce hw initialize.
> 2. initizlize vce clock to 10KHz.
> 3: no need to set bypass clock to vce.
>
> Change-Id: I18d5c2debc6688be201af8bb85022ac25020bd8f
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
Does this patch fix this bug by any chance?
https://bugzilla.kernel.org/show_bug.cgi?id=191281
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 18 +++---------------
> drivers/gpu/drm/amd/amdgpu/vi.c | 32
> +++++++++++++++++++++++++++++++-
> 2 files changed, 34 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 5fb0b7f..eb99ee6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -223,6 +223,9 @@ static int vce_v3_0_start(struct amdgpu_device
> *adev)
> struct amdgpu_ring *ring;
> int idx, r;
>
> + vce_v3_0_override_vce_clock_gating(adev, true); /* force all clocks
> on */
> + amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
> +
> ring = &adev->vce.ring[0];
> WREG32(mmVCE_RB_RPTR, ring->wptr);
> WREG32(mmVCE_RB_WPTR, ring->wptr);
> @@ -701,17 +704,7 @@ static int vce_v3_0_process_interrupt(struct
> amdgpu_device *adev,
> return 0;
> }
>
> -static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool
> enable)
> -{
> - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
> -
> - if (enable)
> - tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
> - else
> - tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
>
> - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
> -}
>
> static int vce_v3_0_set_clockgating_state(void *handle,
> enum amd_clockgating_state state)
> @@ -720,11 +713,6 @@ static int vce_v3_0_set_clockgating_state(void
> *handle,
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> int i;
>
> - if ((adev->asic_type == CHIP_POLARIS10) ||
> - (adev->asic_type == CHIP_TONGA) ||
> - (adev->asic_type == CHIP_FIJI))
> - vce_v3_0_set_bypass_mode(adev, enable);
> -
> if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
> return 0;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
> b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 16ba943..b9924e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -789,7 +789,37 @@ static int vi_set_uvd_clocks(struct amdgpu_device
> *adev, u32 vclk, u32 dclk)
>
> static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32
> ecclk)
> {
> - /* todo */
> + int r, i;
> + struct atom_clock_dividers dividers;
> + u32 tmp;
> +
> + r = amdgpu_atombios_get_clock_dividers(adev,
> +
> COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
> + ecclk, false, ÷rs);
> + if (r)
> + return r;
> +
> + for (i = 0; i < 100; i++) {
> + if (RREG32_SMC(ixCG_ECLK_STATUS) &
> CG_ECLK_STATUS__ECLK_STATUS_MASK)
> + break;
> + mdelay(10);
> + }
> + if (i == 100)
> + return -ETIMEDOUT;
> +
> + tmp = RREG32_SMC(ixCG_ECLK_CNTL);
> + tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
> + CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
> + tmp |= dividers.post_divider;
> + WREG32_SMC(ixCG_ECLK_CNTL, tmp);
> +
> + for (i = 0; i < 100; i++) {
> + if (RREG32_SMC(ixCG_ECLK_STATUS) &
> CG_ECLK_STATUS__ECLK_STATUS_MASK)
> + break;
> + mdelay(10);
> + }
> + if (i == 100)
> + return -ETIMEDOUT;
>
> return 0;
> }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-01-09 17:53 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2017-01-09 13:34 [PATCH] drm/amdgpu: refine vce3.0 initialize Rex Zhu
[not found] ` <1483968878-1370-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-01-09 14:16 ` StDenis, Tom
2017-01-09 14:34 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652DFF695E7EA9413F49C27F7640-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-01-09 16:58 ` StDenis, Tom
[not found] ` <CY4PR12MB176891CF60F99D5E2B57952CF7640-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-01-09 17:53 ` StDenis, Tom
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