From: Jianheng Zhang <Jianheng.Zhang@synopsys.com> To: Alexandre Torgue <alexandre.torgue@foss.st.com>, Jose Abreu <Jose.Abreu@synopsys.com>, "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: "open list:STMMAC ETHERNET DRIVER" <netdev@vger.kernel.org>, "moderated list:ARM/STM32 ARCHITECTURE" <linux-stm32@st-md-mailman.stormreply.com>, "moderated list:ARM/STM32 ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>, open list <linux-kernel@vger.kernel.org>, James Li <James.Li1@synopsys.com>, Martin McKenny <Martin.McKenny@synopsys.com> Subject: [PATCH net-next] net: stmmac: xgmac3+: add FPE handshaking support Date: Mon, 11 Dec 2023 06:13:21 +0000 [thread overview] Message-ID: <CY5PR12MB63726FED738099761A9B81E7BF8FA@CY5PR12MB6372.namprd12.prod.outlook.com> (raw) Adds the HW specific support for Frame Preemption handshaking on XGMAC3+ cores. Signed-off-by: Jianheng Zhang <Jianheng.Zhang@synopsys.com> --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 6 ++ .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 65 ++++++++++++++++++---- 2 files changed, 60 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 207ff17..306d15b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -194,6 +194,12 @@ #define XGMAC_MDIO_DATA 0x00000204 #define XGMAC_MDIO_C22P 0x00000220 #define XGMAC_FPE_CTRL_STS 0x00000280 +#define XGMAC_TRSP BIT(19) +#define XGMAC_TVER BIT(18) +#define XGMAC_RRSP BIT(17) +#define XGMAC_RVER BIT(16) +#define XGMAC_SRSP BIT(2) +#define XGMAC_SVER BIT(1) #define XGMAC_EFPE BIT(0) #define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8) #define XGMAC_ADDR_MAX 32 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c index eb48211..091d932 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -1439,22 +1439,63 @@ static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg * { u32 value; - if (!enable) { - value = readl(ioaddr + XGMAC_FPE_CTRL_STS); + if (enable) { + cfg->fpe_csr = XGMAC_EFPE; + value = readl(ioaddr + XGMAC_RXQ_CTRL1); + value &= ~XGMAC_RQ; + value |= (num_rxq - 1) << XGMAC_RQ_SHIFT; + writel(value, ioaddr + XGMAC_RXQ_CTRL1); + } else { + cfg->fpe_csr = 0; + } + writel(cfg->fpe_csr, ioaddr + XGMAC_FPE_CTRL_STS); +} - value &= ~XGMAC_EFPE; +static int dwxgmac3_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) +{ + u32 value; + int status; - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); - return; + status = FPE_EVENT_UNKNOWN; + + /* Reads from the XGMAC_FPE_CTRL_STS register should only be performed + * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" + */ + value = readl(ioaddr + XGMAC_FPE_CTRL_STS); + + if (value & XGMAC_TRSP) { + status |= FPE_EVENT_TRSP; + netdev_info(dev, "FPE: Respond mPacket is transmitted\n"); } - value = readl(ioaddr + XGMAC_RXQ_CTRL1); - value &= ~XGMAC_RQ; - value |= (num_rxq - 1) << XGMAC_RQ_SHIFT; - writel(value, ioaddr + XGMAC_RXQ_CTRL1); + if (value & XGMAC_TVER) { + status |= FPE_EVENT_TVER; + netdev_info(dev, "FPE: Verify mPacket is transmitted\n"); + } + + if (value & XGMAC_RRSP) { + status |= FPE_EVENT_RRSP; + netdev_info(dev, "FPE: Respond mPacket is received\n"); + } + + if (value & XGMAC_RVER) { + status |= FPE_EVENT_RVER; + netdev_info(dev, "FPE: Verify mPacket is received\n"); + } + + return status; +} + +static void dwxgmac3_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, + enum stmmac_mpacket_type type) +{ + u32 value = cfg->fpe_csr; + + if (type == MPACKET_VERIFY) + value |= XGMAC_SVER; + else if (type == MPACKET_RESPONSE) + value |= XGMAC_SRSP; - value = readl(ioaddr + XGMAC_FPE_CTRL_STS); - value |= XGMAC_EFPE; writel(value, ioaddr + XGMAC_FPE_CTRL_STS); } @@ -1503,6 +1544,8 @@ static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg * .config_l4_filter = dwxgmac2_config_l4_filter, .set_arp_offload = dwxgmac2_set_arp_offload, .fpe_configure = dwxgmac3_fpe_configure, + .fpe_send_mpacket = dwxgmac3_fpe_send_mpacket, + .fpe_irq_status = dwxgmac3_fpe_irq_status, }; static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode, -- 1.8.3.1
WARNING: multiple messages have this Message-ID (diff)
From: Jianheng Zhang <Jianheng.Zhang@synopsys.com> To: Alexandre Torgue <alexandre.torgue@foss.st.com>, Jose Abreu <Jose.Abreu@synopsys.com>, "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: "open list:STMMAC ETHERNET DRIVER" <netdev@vger.kernel.org>, "moderated list:ARM/STM32 ARCHITECTURE" <linux-stm32@st-md-mailman.stormreply.com>, "moderated list:ARM/STM32 ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>, open list <linux-kernel@vger.kernel.org>, James Li <James.Li1@synopsys.com>, Martin McKenny <Martin.McKenny@synopsys.com> Subject: [PATCH net-next] net: stmmac: xgmac3+: add FPE handshaking support Date: Mon, 11 Dec 2023 06:13:21 +0000 [thread overview] Message-ID: <CY5PR12MB63726FED738099761A9B81E7BF8FA@CY5PR12MB6372.namprd12.prod.outlook.com> (raw) Adds the HW specific support for Frame Preemption handshaking on XGMAC3+ cores. Signed-off-by: Jianheng Zhang <Jianheng.Zhang@synopsys.com> --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 6 ++ .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 65 ++++++++++++++++++---- 2 files changed, 60 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 207ff17..306d15b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -194,6 +194,12 @@ #define XGMAC_MDIO_DATA 0x00000204 #define XGMAC_MDIO_C22P 0x00000220 #define XGMAC_FPE_CTRL_STS 0x00000280 +#define XGMAC_TRSP BIT(19) +#define XGMAC_TVER BIT(18) +#define XGMAC_RRSP BIT(17) +#define XGMAC_RVER BIT(16) +#define XGMAC_SRSP BIT(2) +#define XGMAC_SVER BIT(1) #define XGMAC_EFPE BIT(0) #define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8) #define XGMAC_ADDR_MAX 32 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c index eb48211..091d932 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -1439,22 +1439,63 @@ static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg * { u32 value; - if (!enable) { - value = readl(ioaddr + XGMAC_FPE_CTRL_STS); + if (enable) { + cfg->fpe_csr = XGMAC_EFPE; + value = readl(ioaddr + XGMAC_RXQ_CTRL1); + value &= ~XGMAC_RQ; + value |= (num_rxq - 1) << XGMAC_RQ_SHIFT; + writel(value, ioaddr + XGMAC_RXQ_CTRL1); + } else { + cfg->fpe_csr = 0; + } + writel(cfg->fpe_csr, ioaddr + XGMAC_FPE_CTRL_STS); +} - value &= ~XGMAC_EFPE; +static int dwxgmac3_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) +{ + u32 value; + int status; - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); - return; + status = FPE_EVENT_UNKNOWN; + + /* Reads from the XGMAC_FPE_CTRL_STS register should only be performed + * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" + */ + value = readl(ioaddr + XGMAC_FPE_CTRL_STS); + + if (value & XGMAC_TRSP) { + status |= FPE_EVENT_TRSP; + netdev_info(dev, "FPE: Respond mPacket is transmitted\n"); } - value = readl(ioaddr + XGMAC_RXQ_CTRL1); - value &= ~XGMAC_RQ; - value |= (num_rxq - 1) << XGMAC_RQ_SHIFT; - writel(value, ioaddr + XGMAC_RXQ_CTRL1); + if (value & XGMAC_TVER) { + status |= FPE_EVENT_TVER; + netdev_info(dev, "FPE: Verify mPacket is transmitted\n"); + } + + if (value & XGMAC_RRSP) { + status |= FPE_EVENT_RRSP; + netdev_info(dev, "FPE: Respond mPacket is received\n"); + } + + if (value & XGMAC_RVER) { + status |= FPE_EVENT_RVER; + netdev_info(dev, "FPE: Verify mPacket is received\n"); + } + + return status; +} + +static void dwxgmac3_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, + enum stmmac_mpacket_type type) +{ + u32 value = cfg->fpe_csr; + + if (type == MPACKET_VERIFY) + value |= XGMAC_SVER; + else if (type == MPACKET_RESPONSE) + value |= XGMAC_SRSP; - value = readl(ioaddr + XGMAC_FPE_CTRL_STS); - value |= XGMAC_EFPE; writel(value, ioaddr + XGMAC_FPE_CTRL_STS); } @@ -1503,6 +1544,8 @@ static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg * .config_l4_filter = dwxgmac2_config_l4_filter, .set_arp_offload = dwxgmac2_set_arp_offload, .fpe_configure = dwxgmac3_fpe_configure, + .fpe_send_mpacket = dwxgmac3_fpe_send_mpacket, + .fpe_irq_status = dwxgmac3_fpe_irq_status, }; static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode, -- 1.8.3.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2023-12-11 6:13 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-12-11 6:13 Jianheng Zhang [this message] 2023-12-11 6:13 ` [PATCH net-next] net: stmmac: xgmac3+: add FPE handshaking support Jianheng Zhang 2023-12-11 11:14 ` Serge Semin 2023-12-11 11:14 ` Serge Semin 2023-12-11 22:59 ` Jakub Kicinski 2023-12-11 22:59 ` Jakub Kicinski 2023-12-12 9:20 ` Serge Semin 2023-12-12 9:20 ` Serge Semin 2023-12-11 13:40 ` Vladimir Oltean 2023-12-11 13:40 ` Vladimir Oltean 2023-12-12 7:30 ` Jianheng Zhang 2023-12-12 7:30 ` Jianheng Zhang 2023-12-11 20:03 ` Andrew Lunn 2023-12-11 20:03 ` Andrew Lunn 2023-12-12 7:22 ` Jianheng Zhang 2023-12-12 7:22 ` Jianheng Zhang 2023-12-12 9:08 ` Serge Semin 2023-12-12 9:08 ` Serge Semin
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