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* [PATCH 1/3] imx: imx8mm: Update clock bindings header
@ 2020-12-04 23:27 Adam Ford
  2020-12-04 23:27 ` [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6 Adam Ford
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Adam Ford @ 2020-12-04 23:27 UTC (permalink / raw)
  To: u-boot

Import clock bindings header file from Linux 5.10-rc6

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 07e6c686f3..e63a5530ae 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -248,6 +248,32 @@
 #define IMX8MM_CLK_SNVS_ROOT			228
 #define IMX8MM_CLK_GIC				229
 
-#define IMX8MM_CLK_END				230
+#define IMX8MM_SYS_PLL1_40M_CG			230
+#define IMX8MM_SYS_PLL1_80M_CG			231
+#define IMX8MM_SYS_PLL1_100M_CG			232
+#define IMX8MM_SYS_PLL1_133M_CG			233
+#define IMX8MM_SYS_PLL1_160M_CG			234
+#define IMX8MM_SYS_PLL1_200M_CG			235
+#define IMX8MM_SYS_PLL1_266M_CG			236
+#define IMX8MM_SYS_PLL1_400M_CG			237
+#define IMX8MM_SYS_PLL2_50M_CG			238
+#define IMX8MM_SYS_PLL2_100M_CG			239
+#define IMX8MM_SYS_PLL2_125M_CG			240
+#define IMX8MM_SYS_PLL2_166M_CG			241
+#define IMX8MM_SYS_PLL2_200M_CG			242
+#define IMX8MM_SYS_PLL2_250M_CG			243
+#define IMX8MM_SYS_PLL2_333M_CG			244
+#define IMX8MM_SYS_PLL2_500M_CG			245
+
+#define IMX8MM_CLK_M4_CORE			246
+#define IMX8MM_CLK_VPU_CORE			247
+#define IMX8MM_CLK_GPU3D_CORE			248
+#define IMX8MM_CLK_GPU2D_CORE			249
+
+#define IMX8MM_CLK_CLKO2			250
+
+#define IMX8MM_CLK_A53_CORE			251
+
+#define IMX8MM_CLK_END				252
 
 #endif
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6
  2020-12-04 23:27 [PATCH 1/3] imx: imx8mm: Update clock bindings header Adam Ford
@ 2020-12-04 23:27 ` Adam Ford
  2020-12-07  2:11   ` Peng Fan
  2020-12-26 15:53   ` sbabic at denx.de
  2020-12-04 23:27 ` [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6 Adam Ford
                   ` (2 subsequent siblings)
  3 siblings, 2 replies; 9+ messages in thread
From: Adam Ford @ 2020-12-04 23:27 UTC (permalink / raw)
  To: u-boot

There have been some updates to the device tree since 5.6.
This also includes some clocks, and makes it easier to keep
board device tree files in sync with Linux

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index 1e5e11592f..05ee062548 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -18,10 +18,18 @@
 
 	aliases {
 		ethernet0 = &fec1;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
 		i2c0 = &i2c1;
 		i2c1 = &i2c2;
 		i2c2 = &i2c3;
 		i2c3 = &i2c4;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
 		serial0 = &uart1;
 		serial1 = &uart2;
 		serial2 = &uart3;
@@ -29,14 +37,6 @@
 		spi0 = &ecspi1;
 		spi1 = &ecspi2;
 		spi2 = &ecspi3;
-		mmc0 = &usdhc1;
-		mmc1 = &usdhc2;
-		mmc2 = &usdhc3;
-		gpio0 = &gpio1;
-		gpio1 = &gpio2;
-		gpio2 = &gpio3;
-		gpio3 = &gpio4;
-		gpio4 = &gpio5;
 	};
 
 	cpus {
@@ -68,6 +68,7 @@
 			nvmem-cells = <&cpu_speed_grade>;
 			nvmem-cell-names = "speed_grade";
 			cpu-idle-states = <&cpu_pd_wait>;
+			#cooling-cells = <2>;
 		};
 
 		A53_1: cpu at 1 {
@@ -80,6 +81,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			cpu-idle-states = <&cpu_pd_wait>;
+			#cooling-cells = <2>;
 		};
 
 		A53_2: cpu at 2 {
@@ -92,6 +94,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			cpu-idle-states = <&cpu_pd_wait>;
+			#cooling-cells = <2>;
 		};
 
 		A53_3: cpu at 3 {
@@ -104,6 +107,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			cpu-idle-states = <&cpu_pd_wait>;
+			#cooling-cells = <2>;
 		};
 
 		A53_L2: l2-cache0 {
@@ -125,7 +129,7 @@
 
 		opp-1600000000 {
 			opp-hz = /bits/ 64 <1600000000>;
-			opp-microvolt = <900000>;
+			opp-microvolt = <950000>;
 			opp-supported-hw = <0xc>, <0x7>;
 			clock-latency-ns = <150000>;
 			opp-suspend;
@@ -204,6 +208,38 @@
 		arm,no-tick-in-suspend;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tmu>;
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit0: trip1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	usbphynop1: usbphynop1 {
 		compatible = "usb-nop-xceiv";
 		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
@@ -227,12 +263,14 @@
 		ranges = <0x0 0x0 0x0 0x3e000000>;
 
 		aips1: bus at 30000000 {
-			compatible = "simple-bus";
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x30000000 0x400000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x30000000 0x30000000 0x400000>;
 
 			sai1: sai at 30010000 {
+				#sound-dai-cells = <0>;
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30010000 0x10000>;
 				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -246,6 +284,7 @@
 			};
 
 			sai2: sai at 30020000 {
+				#sound-dai-cells = <0>;
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30020000 0x10000>;
 				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
@@ -273,6 +312,7 @@
 			};
 
 			sai5: sai at 30050000 {
+				#sound-dai-cells = <0>;
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30050000 0x10000>;
 				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
@@ -286,6 +326,7 @@
 			};
 
 			sai6: sai at 30060000 {
+				#sound-dai-cells = <0>;
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30060000 0x10000>;
 				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
@@ -363,6 +404,13 @@
 				gpio-ranges = <&iomuxc 0 119 30>;
 			};
 
+			tmu: tmu at 30260000 {
+				compatible = "fsl,imx8mm-tmu";
+				reg = <0x30260000 0x10000>;
+				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
+				#thermal-sensor-cells = <0>;
+			};
+
 			wdog1: watchdog at 30280000 {
 				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 				reg = <0x30280000 0x10000>;
@@ -419,7 +467,7 @@
 				reg = <0x30340000 0x10000>;
 			};
 
-			ocotp: ocotp-ctrl at 30350000 {
+			ocotp: efuse at 30350000 {
 				compatible = "fsl,imx8mm-ocotp", "syscon";
 				reg = <0x30350000 0x10000>;
 				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
@@ -455,6 +503,8 @@
 					compatible = "fsl,sec-v4.0-pwrkey";
 					regmap = <&snvs>;
 					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
+					clock-names = "snvs-pwrkey";
 					linux,keycode = <KEY_POWER>;
 					wakeup-source;
 					status = "disabled";
@@ -469,16 +519,20 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
+				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
+						<&clk IMX8MM_CLK_A53_CORE>,
+						<&clk IMX8MM_CLK_NOC>,
 						<&clk IMX8MM_CLK_AUDIO_AHB>,
 						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 						<&clk IMX8MM_SYS_PLL3>,
 						<&clk IMX8MM_VIDEO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL2>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+							 <&clk IMX8MM_ARM_PLL_OUT>,
+							 <&clk IMX8MM_SYS_PLL3_OUT>,
 							 <&clk IMX8MM_SYS_PLL1_800M>;
-				assigned-clock-rates = <0>,
+				assigned-clock-rates = <0>, <0>, <0>,
 							<400000000>,
 							<400000000>,
 							<750000000>,
@@ -496,7 +550,8 @@
 		};
 
 		aips2: bus at 30400000 {
-			compatible = "simple-bus";
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x30400000 0x400000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x30400000 0x30400000 0x400000>;
@@ -555,10 +610,12 @@
 		};
 
 		aips3: bus at 30800000 {
-			compatible = "simple-bus";
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x30800000 0x400000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x30800000 0x30800000 0x400000>;
+			ranges = <0x30800000 0x30800000 0x400000>,
+				 <0x8000000 0x8000000 0x10000000>;
 
 			ecspi1: spi at 30820000 {
 				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
@@ -718,6 +775,14 @@
 				status = "disabled";
 			};
 
+			mu: mailbox at 30aa0000 {
+				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
+				reg = <0x30aa0000 0x10000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
+				#mbox-cells = <2>;
+			};
+
 			usdhc1: mmc at 30b40000 {
 				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x30b40000 0x10000>;
@@ -760,6 +825,19 @@
 				status = "disabled";
 			};
 
+			flexspi: spi at 30bb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "nxp,imx8mm-fspi";
+				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+				reg-names = "fspi_base", "fspi_mmap";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
+					 <&clk IMX8MM_CLK_QSPI_ROOT>;
+				clock-names = "fspi", "fspi_en";
+				status = "disabled";
+			};
+
 			sdma1: dma-controller at 30bd0000 {
 				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 				reg = <0x30bd0000 0x10000>;
@@ -776,7 +854,8 @@
 				reg = <0x30be0000 0x10000>;
 				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
 					 <&clk IMX8MM_CLK_ENET1_ROOT>,
 					 <&clk IMX8MM_CLK_ENET_TIMER>,
@@ -800,7 +879,8 @@
 		};
 
 		aips4: bus at 32c00000 {
-			compatible = "simple-bus";
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x32c00000 0x400000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
@@ -896,7 +976,6 @@
 		ddr-pmu at 3d800000 {
 			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
 			reg = <0x3d800000 0x400000>;
-			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6
  2020-12-04 23:27 [PATCH 1/3] imx: imx8mm: Update clock bindings header Adam Ford
  2020-12-04 23:27 ` [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6 Adam Ford
@ 2020-12-04 23:27 ` Adam Ford
  2020-12-07  2:11   ` Peng Fan
  2020-12-26 15:53   ` sbabic at denx.de
  2020-12-07  2:11 ` [PATCH 1/3] imx: imx8mm: Update clock bindings header Peng Fan
  2020-12-26 15:53 ` sbabic at denx.de
  3 siblings, 2 replies; 9+ messages in thread
From: Adam Ford @ 2020-12-04 23:27 UTC (permalink / raw)
  To: u-boot

There have been some updates to the device trees, so re-sync.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
index baa5f997d0..d6b9dedd16 100644
--- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
@@ -10,19 +10,19 @@
 		led0 {
 			label = "gen_led0";
 			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};
 
 		led1 {
 			label = "gen_led1";
 			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};
 
 		led2 {
 			label = "gen_led2";
 			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};
 
 		led3 {
@@ -70,7 +70,7 @@
 &ecspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_espi2>;
-	cs-gpios = <&gpio5 9 0>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	eeprom at 0 {
@@ -210,7 +210,7 @@
 		>;
 	};
 
-	pinctrl_pcal6414: pcal6414-gpio {
+	pinctrl_pcal6414: pcal6414-gpiogrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
 		>;
@@ -240,7 +240,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
 			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
@@ -259,7 +259,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
 			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
@@ -271,7 +271,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
 			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi
index 801bd02eae..b88c3c99b0 100644
--- a/arch/arm/dts/imx8mm-beacon-som.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
@@ -24,6 +24,26 @@
 	cpu-supply = <&buck2_reg>;
 };
 
+&ddrc {
+	operating-points-v2 = <&ddrc_opp_table>;
+
+	ddrc_opp_table: opp-table {
+		compatible = "operating-points-v2";
+
+		opp-25M {
+			opp-hz = /bits/ 64 <25000000>;
+		};
+
+		opp-100M {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+
+		opp-750M {
+			opp-hz = /bits/ 64 <750000000>;
+		};
+	};
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
@@ -52,9 +72,10 @@
 	pmic at 4b {
 		compatible = "rohm,bd71847";
 		reg = <0x4b>;
+		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <3 GPIO_ACTIVE_LOW>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 		rohm,reset-snvs-powered;
 
 		regulators {
@@ -116,7 +137,7 @@
 
 			ldo1_reg: LDO1 {
 				regulator-name = "ldo1";
-				regulator-min-microvolt = <3000000>;
+				regulator-min-microvolt = <1600000>;
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
@@ -124,7 +145,7 @@
 
 			ldo2_reg: LDO2 {
 				regulator-name = "ldo2";
-				regulator-min-microvolt = <900000>;
+				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <900000>;
 				regulator-boot-on;
 				regulator-always-on;
@@ -164,7 +185,7 @@
 	status = "okay";
 
 	eeprom at 50 {
-		compatible = "microchip, at24c64d", "atmel,24c64";
+		compatible = "microchip,24c64", "atmel,24c64";
 		pagesize = <32>;
 		read-only;	/* Manufacturing EEPROM programmed at factory */
 		reg = <0x50>;
@@ -190,6 +211,7 @@
 		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 		clocks = <&osc_32k>;
+		max-speed = <4000000>;
 		clock-names = "extclk";
 	};
 };
@@ -270,9 +292,9 @@
 			>;
 		};
 
-		pinctrl_pmic: pmicirq {
+		pinctrl_pmic: pmicirqgrp {
 			fsl,pins = <
-				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
+				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
 			>;
 		};
 
@@ -289,7 +311,7 @@
 			>;
 		};
 
-		pinctrl_usdhc1_gpio: usdhc1grpgpio {
+		pinctrl_usdhc1_gpio: usdhc1gpiogrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
 			>;
@@ -306,7 +328,7 @@
 			>;
 		};
 
-		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
 				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
@@ -317,7 +339,7 @@
 			>;
 		};
 
-		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
 				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
@@ -344,7 +366,7 @@
 			>;
 		};
 
-		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
 				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
@@ -360,7 +382,7 @@
 			>;
 		};
 
-		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
 				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 1/3] imx: imx8mm: Update clock bindings header
  2020-12-04 23:27 [PATCH 1/3] imx: imx8mm: Update clock bindings header Adam Ford
  2020-12-04 23:27 ` [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6 Adam Ford
  2020-12-04 23:27 ` [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6 Adam Ford
@ 2020-12-07  2:11 ` Peng Fan
  2020-12-26 15:53 ` sbabic at denx.de
  3 siblings, 0 replies; 9+ messages in thread
From: Peng Fan @ 2020-12-07  2:11 UTC (permalink / raw)
  To: u-boot

> Subject: [PATCH 1/3] imx: imx8mm: Update clock bindings header
> 
> Import clock bindings header file from Linux 5.10-rc6
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Acked-by: Peng Fan <peng.fan@nxp.com>

> 
> diff --git a/include/dt-bindings/clock/imx8mm-clock.h
> b/include/dt-bindings/clock/imx8mm-clock.h
> index 07e6c686f3..e63a5530ae 100644
> --- a/include/dt-bindings/clock/imx8mm-clock.h
> +++ b/include/dt-bindings/clock/imx8mm-clock.h
> @@ -248,6 +248,32 @@
>  #define IMX8MM_CLK_SNVS_ROOT			228
>  #define IMX8MM_CLK_GIC				229
> 
> -#define IMX8MM_CLK_END				230
> +#define IMX8MM_SYS_PLL1_40M_CG			230
> +#define IMX8MM_SYS_PLL1_80M_CG			231
> +#define IMX8MM_SYS_PLL1_100M_CG			232
> +#define IMX8MM_SYS_PLL1_133M_CG			233
> +#define IMX8MM_SYS_PLL1_160M_CG			234
> +#define IMX8MM_SYS_PLL1_200M_CG			235
> +#define IMX8MM_SYS_PLL1_266M_CG			236
> +#define IMX8MM_SYS_PLL1_400M_CG			237
> +#define IMX8MM_SYS_PLL2_50M_CG			238
> +#define IMX8MM_SYS_PLL2_100M_CG			239
> +#define IMX8MM_SYS_PLL2_125M_CG			240
> +#define IMX8MM_SYS_PLL2_166M_CG			241
> +#define IMX8MM_SYS_PLL2_200M_CG			242
> +#define IMX8MM_SYS_PLL2_250M_CG			243
> +#define IMX8MM_SYS_PLL2_333M_CG			244
> +#define IMX8MM_SYS_PLL2_500M_CG			245
> +
> +#define IMX8MM_CLK_M4_CORE			246
> +#define IMX8MM_CLK_VPU_CORE			247
> +#define IMX8MM_CLK_GPU3D_CORE			248
> +#define IMX8MM_CLK_GPU2D_CORE			249
> +
> +#define IMX8MM_CLK_CLKO2			250
> +
> +#define IMX8MM_CLK_A53_CORE			251
> +
> +#define IMX8MM_CLK_END				252
> 
>  #endif
> --
> 2.25.1

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6
  2020-12-04 23:27 ` [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6 Adam Ford
@ 2020-12-07  2:11   ` Peng Fan
  2020-12-26 15:53   ` sbabic at denx.de
  1 sibling, 0 replies; 9+ messages in thread
From: Peng Fan @ 2020-12-07  2:11 UTC (permalink / raw)
  To: u-boot

> Subject: [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6
> 
> There have been some updates to the device tree since 5.6.
> This also includes some clocks, and makes it easier to keep board device tree
> files in sync with Linux
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>


Acked-by: Peng Fan <peng.fan@nxp.com>

> 
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index
> 1e5e11592f..05ee062548 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -18,10 +18,18 @@
> 
>  	aliases {
>  		ethernet0 = &fec1;
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +		gpio3 = &gpio4;
> +		gpio4 = &gpio5;
>  		i2c0 = &i2c1;
>  		i2c1 = &i2c2;
>  		i2c2 = &i2c3;
>  		i2c3 = &i2c4;
> +		mmc0 = &usdhc1;
> +		mmc1 = &usdhc2;
> +		mmc2 = &usdhc3;
>  		serial0 = &uart1;
>  		serial1 = &uart2;
>  		serial2 = &uart3;
> @@ -29,14 +37,6 @@
>  		spi0 = &ecspi1;
>  		spi1 = &ecspi2;
>  		spi2 = &ecspi3;
> -		mmc0 = &usdhc1;
> -		mmc1 = &usdhc2;
> -		mmc2 = &usdhc3;
> -		gpio0 = &gpio1;
> -		gpio1 = &gpio2;
> -		gpio2 = &gpio3;
> -		gpio3 = &gpio4;
> -		gpio4 = &gpio5;
>  	};
> 
>  	cpus {
> @@ -68,6 +68,7 @@
>  			nvmem-cells = <&cpu_speed_grade>;
>  			nvmem-cell-names = "speed_grade";
>  			cpu-idle-states = <&cpu_pd_wait>;
> +			#cooling-cells = <2>;
>  		};
> 
>  		A53_1: cpu at 1 {
> @@ -80,6 +81,7 @@
>  			next-level-cache = <&A53_L2>;
>  			operating-points-v2 = <&a53_opp_table>;
>  			cpu-idle-states = <&cpu_pd_wait>;
> +			#cooling-cells = <2>;
>  		};
> 
>  		A53_2: cpu at 2 {
> @@ -92,6 +94,7 @@
>  			next-level-cache = <&A53_L2>;
>  			operating-points-v2 = <&a53_opp_table>;
>  			cpu-idle-states = <&cpu_pd_wait>;
> +			#cooling-cells = <2>;
>  		};
> 
>  		A53_3: cpu at 3 {
> @@ -104,6 +107,7 @@
>  			next-level-cache = <&A53_L2>;
>  			operating-points-v2 = <&a53_opp_table>;
>  			cpu-idle-states = <&cpu_pd_wait>;
> +			#cooling-cells = <2>;
>  		};
> 
>  		A53_L2: l2-cache0 {
> @@ -125,7 +129,7 @@
> 
>  		opp-1600000000 {
>  			opp-hz = /bits/ 64 <1600000000>;
> -			opp-microvolt = <900000>;
> +			opp-microvolt = <950000>;
>  			opp-supported-hw = <0xc>, <0x7>;
>  			clock-latency-ns = <150000>;
>  			opp-suspend;
> @@ -204,6 +208,38 @@
>  		arm,no-tick-in-suspend;
>  	};
> 
> +	thermal-zones {
> +		cpu-thermal {
> +			polling-delay-passive = <250>;
> +			polling-delay = <2000>;
> +			thermal-sensors = <&tmu>;
> +			trips {
> +				cpu_alert0: trip0 {
> +					temperature = <85000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				cpu_crit0: trip1 {
> +					temperature = <95000>;
> +					hysteresis = <2000>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_alert0>;
> +					cooling-device =
> +						<&A53_0 THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> +						<&A53_1 THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> +						<&A53_2 THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> +						<&A53_3 THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>;
> +				};
> +			};
> +		};
> +	};
> +
>  	usbphynop1: usbphynop1 {
>  		compatible = "usb-nop-xceiv";
>  		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; @@ -227,12
> +263,14 @@
>  		ranges = <0x0 0x0 0x0 0x3e000000>;
> 
>  		aips1: bus at 30000000 {
> -			compatible = "simple-bus";
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			reg = <0x30000000 0x400000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges = <0x30000000 0x30000000 0x400000>;
> 
>  			sai1: sai at 30010000 {
> +				#sound-dai-cells = <0>;
>  				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
>  				reg = <0x30010000 0x10000>;
>  				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@
> -246,6 +284,7 @@
>  			};
> 
>  			sai2: sai at 30020000 {
> +				#sound-dai-cells = <0>;
>  				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
>  				reg = <0x30020000 0x10000>;
>  				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@
> -273,6 +312,7 @@
>  			};
> 
>  			sai5: sai at 30050000 {
> +				#sound-dai-cells = <0>;
>  				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
>  				reg = <0x30050000 0x10000>;
>  				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; @@
> -286,6 +326,7 @@
>  			};
> 
>  			sai6: sai at 30060000 {
> +				#sound-dai-cells = <0>;
>  				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
>  				reg = <0x30060000 0x10000>;
>  				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; @@
> -363,6 +404,13 @@
>  				gpio-ranges = <&iomuxc 0 119 30>;
>  			};
> 
> +			tmu: tmu at 30260000 {
> +				compatible = "fsl,imx8mm-tmu";
> +				reg = <0x30260000 0x10000>;
> +				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
> +				#thermal-sensor-cells = <0>;
> +			};
> +
>  			wdog1: watchdog at 30280000 {
>  				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
>  				reg = <0x30280000 0x10000>;
> @@ -419,7 +467,7 @@
>  				reg = <0x30340000 0x10000>;
>  			};
> 
> -			ocotp: ocotp-ctrl at 30350000 {
> +			ocotp: efuse at 30350000 {
>  				compatible = "fsl,imx8mm-ocotp", "syscon";
>  				reg = <0x30350000 0x10000>;
>  				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; @@ -455,6
> +503,8 @@
>  					compatible = "fsl,sec-v4.0-pwrkey";
>  					regmap = <&snvs>;
>  					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
> +					clock-names = "snvs-pwrkey";
>  					linux,keycode = <KEY_POWER>;
>  					wakeup-source;
>  					status = "disabled";
> @@ -469,16 +519,20 @@
>  					 <&clk_ext3>, <&clk_ext4>;
>  				clock-names = "osc_32k", "osc_24m", "clk_ext1",
> "clk_ext2",
>  					      "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
> +				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
> +						<&clk IMX8MM_CLK_A53_CORE>,
> +						<&clk IMX8MM_CLK_NOC>,
>  						<&clk IMX8MM_CLK_AUDIO_AHB>,
>  						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
>  						<&clk IMX8MM_SYS_PLL3>,
>  						<&clk IMX8MM_VIDEO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL2>;
> -				assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL3_OUT>,
> +				assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>,
> +							 <&clk IMX8MM_ARM_PLL_OUT>,
> +							 <&clk IMX8MM_SYS_PLL3_OUT>,
>  							 <&clk IMX8MM_SYS_PLL1_800M>;
> -				assigned-clock-rates = <0>,
> +				assigned-clock-rates = <0>, <0>, <0>,
>  							<400000000>,
>  							<400000000>,
>  							<750000000>,
> @@ -496,7 +550,8 @@
>  		};
> 
>  		aips2: bus at 30400000 {
> -			compatible = "simple-bus";
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			reg = <0x30400000 0x400000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges = <0x30400000 0x30400000 0x400000>; @@ -555,10
> +610,12 @@
>  		};
> 
>  		aips3: bus at 30800000 {
> -			compatible = "simple-bus";
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			reg = <0x30800000 0x400000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> -			ranges = <0x30800000 0x30800000 0x400000>;
> +			ranges = <0x30800000 0x30800000 0x400000>,
> +				 <0x8000000 0x8000000 0x10000000>;
> 
>  			ecspi1: spi at 30820000 {
>  				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; @@
> -718,6 +775,14 @@
>  				status = "disabled";
>  			};
> 
> +			mu: mailbox at 30aa0000 {
> +				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
> +				reg = <0x30aa0000 0x10000>;
> +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
> +				#mbox-cells = <2>;
> +			};
> +
>  			usdhc1: mmc at 30b40000 {
>  				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
>  				reg = <0x30b40000 0x10000>;
> @@ -760,6 +825,19 @@
>  				status = "disabled";
>  			};
> 
> +			flexspi: spi at 30bb0000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "nxp,imx8mm-fspi";
> +				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
> +				reg-names = "fspi_base", "fspi_mmap";
> +				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
> +					 <&clk IMX8MM_CLK_QSPI_ROOT>;
> +				clock-names = "fspi", "fspi_en";
> +				status = "disabled";
> +			};
> +
>  			sdma1: dma-controller at 30bd0000 {
>  				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
>  				reg = <0x30bd0000 0x10000>;
> @@ -776,7 +854,8 @@
>  				reg = <0x30be0000 0x10000>;
>  				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>  					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> -					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
>  					 <&clk IMX8MM_CLK_ENET1_ROOT>,
>  					 <&clk IMX8MM_CLK_ENET_TIMER>,
> @@ -800,7 +879,8 @@
>  		};
> 
>  		aips4: bus at 32c00000 {
> -			compatible = "simple-bus";
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			reg = <0x32c00000 0x400000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges = <0x32c00000 0x32c00000 0x400000>; @@ -896,7
> +976,6 @@
>  		ddr-pmu at 3d800000 {
>  			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
>  			reg = <0x3d800000 0x400000>;
> -			interrupt-parent = <&gic>;
>  			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  	};
> --
> 2.25.1

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6
  2020-12-04 23:27 ` [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6 Adam Ford
@ 2020-12-07  2:11   ` Peng Fan
  2020-12-26 15:53   ` sbabic at denx.de
  1 sibling, 0 replies; 9+ messages in thread
From: Peng Fan @ 2020-12-07  2:11 UTC (permalink / raw)
  To: u-boot

> Subject: [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux
> 5.10-rc6
> 
> There have been some updates to the device trees, so re-sync.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>


Acked-by: Peng Fan <peng.fan@nxp.com>

> 
> diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> index baa5f997d0..d6b9dedd16 100644
> --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> @@ -10,19 +10,19 @@
>  		led0 {
>  			label = "gen_led0";
>  			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
> 
>  		led1 {
>  			label = "gen_led1";
>  			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
> 
>  		led2 {
>  			label = "gen_led2";
>  			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
> 
>  		led3 {
> @@ -70,7 +70,7 @@
>  &ecspi2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_espi2>;
> -	cs-gpios = <&gpio5 9 0>;
> +	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
>  	status = "okay";
> 
>  	eeprom at 0 {
> @@ -210,7 +210,7 @@
>  		>;
>  	};
> 
> -	pinctrl_pcal6414: pcal6414-gpio {
> +	pinctrl_pcal6414: pcal6414-gpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
>  		>;
> @@ -240,7 +240,7 @@
>  		>;
>  	};
> 
> -	pinctrl_usdhc2_gpio: usdhc2grpgpio {
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
>  			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
> @@ -259,7 +259,7 @@
>  		>;
>  	};
> 
> -	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
>  			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
> @@ -271,7 +271,7 @@
>  		>;
>  	};
> 
> -	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
>  			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
> diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi
> b/arch/arm/dts/imx8mm-beacon-som.dtsi
> index 801bd02eae..b88c3c99b0 100644
> --- a/arch/arm/dts/imx8mm-beacon-som.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
> @@ -24,6 +24,26 @@
>  	cpu-supply = <&buck2_reg>;
>  };
> 
> +&ddrc {
> +	operating-points-v2 = <&ddrc_opp_table>;
> +
> +	ddrc_opp_table: opp-table {
> +		compatible = "operating-points-v2";
> +
> +		opp-25M {
> +			opp-hz = /bits/ 64 <25000000>;
> +		};
> +
> +		opp-100M {
> +			opp-hz = /bits/ 64 <100000000>;
> +		};
> +
> +		opp-750M {
> +			opp-hz = /bits/ 64 <750000000>;
> +		};
> +	};
> +};
> +
>  &fec1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_fec1>;
> @@ -52,9 +72,10 @@
>  	pmic at 4b {
>  		compatible = "rohm,bd71847";
>  		reg = <0x4b>;
> +		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_pmic>;
>  		interrupt-parent = <&gpio1>;
> -		interrupts = <3 GPIO_ACTIVE_LOW>;
> +		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>  		rohm,reset-snvs-powered;
> 
>  		regulators {
> @@ -116,7 +137,7 @@
> 
>  			ldo1_reg: LDO1 {
>  				regulator-name = "ldo1";
> -				regulator-min-microvolt = <3000000>;
> +				regulator-min-microvolt = <1600000>;
>  				regulator-max-microvolt = <3300000>;
>  				regulator-boot-on;
>  				regulator-always-on;
> @@ -124,7 +145,7 @@
> 
>  			ldo2_reg: LDO2 {
>  				regulator-name = "ldo2";
> -				regulator-min-microvolt = <900000>;
> +				regulator-min-microvolt = <800000>;
>  				regulator-max-microvolt = <900000>;
>  				regulator-boot-on;
>  				regulator-always-on;
> @@ -164,7 +185,7 @@
>  	status = "okay";
> 
>  	eeprom at 50 {
> -		compatible = "microchip, at24c64d", "atmel,24c64";
> +		compatible = "microchip,24c64", "atmel,24c64";
>  		pagesize = <32>;
>  		read-only;	/* Manufacturing EEPROM programmed at factory */
>  		reg = <0x50>;
> @@ -190,6 +211,7 @@
>  		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
>  		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
>  		clocks = <&osc_32k>;
> +		max-speed = <4000000>;
>  		clock-names = "extclk";
>  	};
>  };
> @@ -270,9 +292,9 @@
>  			>;
>  		};
> 
> -		pinctrl_pmic: pmicirq {
> +		pinctrl_pmic: pmicirqgrp {
>  			fsl,pins = <
> -				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
> +				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
>  			>;
>  		};
> 
> @@ -289,7 +311,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc1_gpio: usdhc1grpgpio {
> +		pinctrl_usdhc1_gpio: usdhc1gpiogrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
>  			>;
> @@ -306,7 +328,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +		pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 	0x194
>  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 	0x1d4
> @@ -317,7 +339,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +		pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 	0x196
>  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 	0x1d6
> @@ -344,7 +366,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +		pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK
> 	0x194
>  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
> 	0x1d4
> @@ -360,7 +382,7 @@
>  			>;
>  		};
> 
> -		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +		pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK
> 	0x196
>  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
> 	0x1d6
> --
> 2.25.1

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6
  2020-12-04 23:27 ` [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6 Adam Ford
  2020-12-07  2:11   ` Peng Fan
@ 2020-12-26 15:53   ` sbabic at denx.de
  1 sibling, 0 replies; 9+ messages in thread
From: sbabic at denx.de @ 2020-12-26 15:53 UTC (permalink / raw)
  To: u-boot

> There have been some updates to the device tree since 5.6.
> This also includes some clocks, and makes it easier to keep
> board device tree files in sync with Linux
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
> index 1e5e11592f..05ee062548 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -18,10 +18,18 @@
>  
>  	aliases {
>  		ethernet0 = &fec1;
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +		gpio3 = &gpio4;
> +		gpio4 = &gpio5;
>  		i2c0 = &i2c1;
>  		i2c1 = &i2c2;
>  		i2c2 = &i2c3;
>  		i2c3 = &i2c4;
> +		mmc0 = &usdhc1;
> +		mmc1 = &usdhc2;
> +		mmc2 = &usdhc3;
>  		serial0 = &uart1;
>  		serial1 = &uart2;
>  		serial2 = &uart3;
> @@ -29,14 +37,6 @@
>  		spi0 = &ecspi1;
>  		spi1 = &ecspi2;
>  		spi2 = &ecspi3;
> -		mmc0 = &usdhc1;
> -		mmc1 = &usdhc2;
> -		mmc2 = &usdhc3;
> -		gpio0 = &gpio1;
> -		gpio1 = &gpio2;
> -		gpio2 = &gpio3;
> -		gpio3 = &gpio4;
> -		gpio4 = &gpio5;
>  	};
>  
>  	cpus {
> @@ -68,6 +68,7 @@
>  			nvmem-cells = <&cpu_speed_grade>;
>  			nvmem-cell-names = "speed_grade";
>  			cpu-idle-states = <&cpu_pd_wait>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A53_1: cpu at 1 {
> @@ -80,6 +81,7 @@
>  			next-level-cache = <&A53_L2>;
>  			operating-points-v2 = <&a53_opp_table>;
>  			cpu-idle-states = <&cpu_pd_wait>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A53_2: cpu at 2 {
> @@ -92,6 +94,7 @@
>  			next-level-cache = <&A53_L2>;
>  			operating-points-v2 = <&a53_opp_table>;
>  			cpu-idle-states = <&cpu_pd_wait>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A53_3: cpu at 3 {
> @@ -104,6 +107,7 @@
>  			next-level-cache = <&A53_L2>;
>  			operating-points-v2 = <&a53_opp_table>;
>  			cpu-idle-states = <&cpu_pd_wait>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A53_L2: l2-cache0 {
> @@ -125,7 +129,7 @@
>  
>  		opp-1600000000 {
>  			opp-hz = /bits/ 64 <1600000000>;
> -			opp-microvolt = <900000>;
> +			opp-microvolt = <950000>;
>  			opp-supported-hw = <0xc>, <0x7>;
>  			clock-latency-ns = <150000>;
>  			opp-suspend;
> @@ -204,6 +208,38 @@
>  		arm,no-tick-in-suspend;
>  	};
>  
> +	thermal-zones {
> +		cpu-thermal {
> +			polling-delay-passive = <250>;
> +			polling-delay = <2000>;
> +			thermal-sensors = <&tmu>;
> +			trips {
> +				cpu_alert0: trip0 {
> +					temperature = <85000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				cpu_crit0: trip1 {
> +					temperature = <95000>;
> +					hysteresis = <2000>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_alert0>;
> +					cooling-device =
> +						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
> +		};
> +	};
> +
>  	usbphynop1: usbphynop1 {
>  		compatible = "usb-nop-xceiv";
>  		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
> @@ -227,12 +263,14 @@
>  		ranges = <0x0 0x0 0x0 0x3e000000>;
>  
>  		aips1: bus at 30000000 {
> -			compatible = "simple-bus";
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			reg = <0x30000000 0x400000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges = <0x30000000 0x30000000 0x400000>;
>  
>  			sai1: sai at 30010000 {
> +				#sound-dai-cells = <0>;
>  				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
>  				reg = <0x30010000 0x10000>;
>  				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> @@ -246,6 +284,7 @@
>  			};
>  
>  			sai2: sai at 30020000 {
> +				#sound-dai-cells = <0>;
>  				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
>  				reg = <0x30020000 0x10000>;
>  				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> @@ -273,6 +312,7 @@
>  			};
>  
>  			sai5: sai at 30050000 {
> +				#sound-dai-cells = <0>;
>  				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
>  				reg = <0x30050000 0x10000>;
>  				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> @@ -286,6 +326,7 @@
>  			};
>  
>  			sai6: sai at 30060000 {
> +				#sound-dai-cells = <0>;
>  				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
>  				reg = <0x30060000 0x10000>;
>  				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> @@ -363,6 +404,13 @@
>  				gpio-ranges = <&iomuxc 0 119 30>;
>  			};
>  
> +			tmu: tmu at 30260000 {
> +				compatible = "fsl,imx8mm-tmu";
> +				reg = <0x30260000 0x10000>;
> +				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
> +				#thermal-sensor-cells = <0>;
> +			};
> +
>  			wdog1: watchdog at 30280000 {
>  				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
>  				reg = <0x30280000 0x10000>;
> @@ -419,7 +467,7 @@
>  				reg = <0x30340000 0x10000>;
>  			};
>  
> -			ocotp: ocotp-ctrl at 30350000 {
> +			ocotp: efuse at 30350000 {
>  				compatible = "fsl,imx8mm-ocotp", "syscon";
>  				reg = <0x30350000 0x10000>;
>  				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
> @@ -455,6 +503,8 @@
>  					compatible = "fsl,sec-v4.0-pwrkey";
>  					regmap = <&snvs>;
>  					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
> +					clock-names = "snvs-pwrkey";
>  					linux,keycode = <KEY_POWER>;
>  					wakeup-source;
>  					status = "disabled";
> @@ -469,16 +519,20 @@
>  					 <&clk_ext3>, <&clk_ext4>;
>  				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
>  					      "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
> +				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
> +						<&clk IMX8MM_CLK_A53_CORE>,
> +						<&clk IMX8MM_CLK_NOC>,
>  						<&clk IMX8MM_CLK_AUDIO_AHB>,
>  						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
>  						<&clk IMX8MM_SYS_PLL3>,
>  						<&clk IMX8MM_VIDEO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL2>;
> -				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
> +				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
> +							 <&clk IMX8MM_ARM_PLL_OUT>,
> +							 <&clk IMX8MM_SYS_PLL3_OUT>,
>  							 <&clk IMX8MM_SYS_PLL1_800M>;
> -				assigned-clock-rates = <0>,
> +				assigned-clock-rates = <0>, <0>, <0>,
>  							<400000000>,
>  							<400000000>,
>  							<750000000>,
> @@ -496,7 +550,8 @@
>  		};
>  
>  		aips2: bus at 30400000 {
> -			compatible = "simple-bus";
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			reg = <0x30400000 0x400000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges = <0x30400000 0x30400000 0x400000>;
> @@ -555,10 +610,12 @@
>  		};
>  
>  		aips3: bus at 30800000 {
> -			compatible = "simple-bus";
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			reg = <0x30800000 0x400000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> -			ranges = <0x30800000 0x30800000 0x400000>;
> +			ranges = <0x30800000 0x30800000 0x400000>,
> +				 <0x8000000 0x8000000 0x10000000>;
>  
>  			ecspi1: spi at 30820000 {
>  				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> @@ -718,6 +775,14 @@
>  				status = "disabled";
>  			};
>  
> +			mu: mailbox at 30aa0000 {
> +				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
> +				reg = <0x30aa0000 0x10000>;
> +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
> +				#mbox-cells = <2>;
> +			};
> +
>  			usdhc1: mmc at 30b40000 {
>  				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
>  				reg = <0x30b40000 0x10000>;
> @@ -760,6 +825,19 @@
>  				status = "disabled";
>  			};
>  
> +			flexspi: spi at 30bb0000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "nxp,imx8mm-fspi";
> +				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
> +				reg-names = "fspi_base", "fspi_mmap";
> +				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
> +					 <&clk IMX8MM_CLK_QSPI_ROOT>;
> +				clock-names = "fspi", "fspi_en";
> +				status = "disabled";
> +			};
> +
>  			sdma1: dma-controller at 30bd0000 {
>  				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
>  				reg = <0x30bd0000 0x10000>;
> @@ -776,7 +854,8 @@
>  				reg = <0x30be0000 0x10000>;
>  				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>  					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> -					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
>  					 <&clk IMX8MM_CLK_ENET1_ROOT>,
>  					 <&clk IMX8MM_CLK_ENET_TIMER>,
> @@ -800,7 +879,8 @@
>  		};
>  
>  		aips4: bus at 32c00000 {
> -			compatible = "simple-bus";
> +			compatible = "fsl,aips-bus", "simple-bus";
> +			reg = <0x32c00000 0x400000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges = <0x32c00000 0x32c00000 0x400000>;
> @@ -896,7 +976,6 @@
>  		ddr-pmu at 3d800000 {
>  			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
>  			reg = <0x3d800000 0x400000>;
> -			interrupt-parent = <&gic>;
>  			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  	};
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH 1/3] imx: imx8mm: Update clock bindings header
  2020-12-04 23:27 [PATCH 1/3] imx: imx8mm: Update clock bindings header Adam Ford
                   ` (2 preceding siblings ...)
  2020-12-07  2:11 ` [PATCH 1/3] imx: imx8mm: Update clock bindings header Peng Fan
@ 2020-12-26 15:53 ` sbabic at denx.de
  3 siblings, 0 replies; 9+ messages in thread
From: sbabic at denx.de @ 2020-12-26 15:53 UTC (permalink / raw)
  To: u-boot

> Import clock bindings header file from Linux 5.10-rc6
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
> diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
> index 07e6c686f3..e63a5530ae 100644
> --- a/include/dt-bindings/clock/imx8mm-clock.h
> +++ b/include/dt-bindings/clock/imx8mm-clock.h
> @@ -248,6 +248,32 @@
>  #define IMX8MM_CLK_SNVS_ROOT			228
>  #define IMX8MM_CLK_GIC				229
>  
> -#define IMX8MM_CLK_END				230
> +#define IMX8MM_SYS_PLL1_40M_CG			230
> +#define IMX8MM_SYS_PLL1_80M_CG			231
> +#define IMX8MM_SYS_PLL1_100M_CG			232
> +#define IMX8MM_SYS_PLL1_133M_CG			233
> +#define IMX8MM_SYS_PLL1_160M_CG			234
> +#define IMX8MM_SYS_PLL1_200M_CG			235
> +#define IMX8MM_SYS_PLL1_266M_CG			236
> +#define IMX8MM_SYS_PLL1_400M_CG			237
> +#define IMX8MM_SYS_PLL2_50M_CG			238
> +#define IMX8MM_SYS_PLL2_100M_CG			239
> +#define IMX8MM_SYS_PLL2_125M_CG			240
> +#define IMX8MM_SYS_PLL2_166M_CG			241
> +#define IMX8MM_SYS_PLL2_200M_CG			242
> +#define IMX8MM_SYS_PLL2_250M_CG			243
> +#define IMX8MM_SYS_PLL2_333M_CG			244
> +#define IMX8MM_SYS_PLL2_500M_CG			245
> +
> +#define IMX8MM_CLK_M4_CORE			246
> +#define IMX8MM_CLK_VPU_CORE			247
> +#define IMX8MM_CLK_GPU3D_CORE			248
> +#define IMX8MM_CLK_GPU2D_CORE			249
> +
> +#define IMX8MM_CLK_CLKO2			250
> +
> +#define IMX8MM_CLK_A53_CORE			251
> +
> +#define IMX8MM_CLK_END				252
>  
>  #endif
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6
  2020-12-04 23:27 ` [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6 Adam Ford
  2020-12-07  2:11   ` Peng Fan
@ 2020-12-26 15:53   ` sbabic at denx.de
  1 sibling, 0 replies; 9+ messages in thread
From: sbabic at denx.de @ 2020-12-26 15:53 UTC (permalink / raw)
  To: u-boot

> There have been some updates to the device trees, so re-sync.
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
> diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> index baa5f997d0..d6b9dedd16 100644
> --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
> @@ -10,19 +10,19 @@
>  		led0 {
>  			label = "gen_led0";
>  			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
>  
>  		led1 {
>  			label = "gen_led1";
>  			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
>  
>  		led2 {
>  			label = "gen_led2";
>  			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
> -			default-state = "none";
> +			default-state = "off";
>  		};
>  
>  		led3 {
> @@ -70,7 +70,7 @@
>  &ecspi2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_espi2>;
> -	cs-gpios = <&gpio5 9 0>;
> +	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  
>  	eeprom at 0 {
> @@ -210,7 +210,7 @@
>  		>;
>  	};
>  
> -	pinctrl_pcal6414: pcal6414-gpio {
> +	pinctrl_pcal6414: pcal6414-gpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
>  		>;
> @@ -240,7 +240,7 @@
>  		>;
>  	};
>  
> -	pinctrl_usdhc2_gpio: usdhc2grpgpio {
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
>  			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
> @@ -259,7 +259,7 @@
>  		>;
>  	};
>  
> -	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
>  			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
> @@ -271,7 +271,7 @@
>  		>;
>  	};
>  
> -	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
>  			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
> diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi
> index 801bd02eae..b88c3c99b0 100644
> --- a/arch/arm/dts/imx8mm-beacon-som.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
> @@ -24,6 +24,26 @@
>  	cpu-supply = <&buck2_reg>;
>  };
>  
> +&ddrc {
> +	operating-points-v2 = <&ddrc_opp_table>;
> +
> +	ddrc_opp_table: opp-table {
> +		compatible = "operating-points-v2";
> +
> +		opp-25M {
> +			opp-hz = /bits/ 64 <25000000>;
> +		};
> +
> +		opp-100M {
> +			opp-hz = /bits/ 64 <100000000>;
> +		};
> +
> +		opp-750M {
> +			opp-hz = /bits/ 64 <750000000>;
> +		};
> +	};
> +};
> +
>  &fec1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_fec1>;
> @@ -52,9 +72,10 @@
>  	pmic at 4b {
>  		compatible = "rohm,bd71847";
>  		reg = <0x4b>;
> +		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_pmic>;
>  		interrupt-parent = <&gpio1>;
> -		interrupts = <3 GPIO_ACTIVE_LOW>;
> +		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>  		rohm,reset-snvs-powered;
>  
>  		regulators {
> @@ -116,7 +137,7 @@
>  
>  			ldo1_reg: LDO1 {
>  				regulator-name = "ldo1";
> -				regulator-min-microvolt = <3000000>;
> +				regulator-min-microvolt = <1600000>;
>  				regulator-max-microvolt = <3300000>;
>  				regulator-boot-on;
>  				regulator-always-on;
> @@ -124,7 +145,7 @@
>  
>  			ldo2_reg: LDO2 {
>  				regulator-name = "ldo2";
> -				regulator-min-microvolt = <900000>;
> +				regulator-min-microvolt = <800000>;
>  				regulator-max-microvolt = <900000>;
>  				regulator-boot-on;
>  				regulator-always-on;
> @@ -164,7 +185,7 @@
>  	status = "okay";
>  
>  	eeprom at 50 {
> -		compatible = "microchip, at24c64d", "atmel,24c64";
> +		compatible = "microchip,24c64", "atmel,24c64";
>  		pagesize = <32>;
>  		read-only;	/* Manufacturing EEPROM programmed at factory */
>  		reg = <0x50>;
> @@ -190,6 +211,7 @@
>  		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
>  		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
>  		clocks = <&osc_32k>;
> +		max-speed = <4000000>;
>  		clock-names = "extclk";
>  	};
>  };
> @@ -270,9 +292,9 @@
>  			>;
>  		};
>  
> -		pinctrl_pmic: pmicirq {
> +		pinctrl_pmic: pmicirqgrp {
>  			fsl,pins = <
> -				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
> +				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
>  			>;
>  		};
>  
> @@ -289,7 +311,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc1_gpio: usdhc1grpgpio {
> +		pinctrl_usdhc1_gpio: usdhc1gpiogrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
>  			>;
> @@ -306,7 +328,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +		pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
>  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
> @@ -317,7 +339,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +		pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
>  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
> @@ -344,7 +366,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +		pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
>  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
> @@ -360,7 +382,7 @@
>  			>;
>  		};
>  
> -		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +		pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>  			fsl,pins = <
>  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
>  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-12-26 15:53 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-04 23:27 [PATCH 1/3] imx: imx8mm: Update clock bindings header Adam Ford
2020-12-04 23:27 ` [PATCH 2/3] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6 Adam Ford
2020-12-07  2:11   ` Peng Fan
2020-12-26 15:53   ` sbabic at denx.de
2020-12-04 23:27 ` [PATCH 3/3] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6 Adam Ford
2020-12-07  2:11   ` Peng Fan
2020-12-26 15:53   ` sbabic at denx.de
2020-12-07  2:11 ` [PATCH 1/3] imx: imx8mm: Update clock bindings header Peng Fan
2020-12-26 15:53 ` sbabic at denx.de

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