* [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245
@ 2023-04-25 18:30 Radhakrishna Sripada
2023-04-25 23:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Implement Wa_14019141245 (rev2) Patchwork
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Radhakrishna Sripada @ 2023-04-25 18:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Enable strict RAR to prevent spurious GPU hangs.
v1.1: Rebase
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4 ----
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index e8c3b762a92a..af80d2fe739b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -529,6 +529,11 @@
#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
+#define GEN12_SQCNT1 _MMIO(0x8718)
+#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
+#define GEN12_SQCNT1_OABPC REG_BIT(29)
+#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
+
#define XEHP_SQCM MCR_REG(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index de4f8e2e8e8c..ad9e7f49a6fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ /* Wa_14019141245 */
+ wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
+
if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
/* Wa_14014830051 */
@@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_14015795083 */
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
}
+
/*
* Unlike older platforms, we no longer setup implicit steering here;
* all MCR accesses are explicitly steered.
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
index ba103875e19f..e5ac7a8b5cb6 100644
--- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -134,10 +134,6 @@
#define GDT_CHICKEN_BITS _MMIO(0x9840)
#define GT_NOA_ENABLE 0x00000080
-#define GEN12_SQCNT1 _MMIO(0x8718)
-#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
-#define GEN12_SQCNT1_OABPC REG_BIT(29)
-
/* Gen12 OAM unit */
#define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
#define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Implement Wa_14019141245 (rev2)
2023-04-25 18:30 [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Radhakrishna Sripada
@ 2023-04-25 23:28 ` Patchwork
2023-04-26 3:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2023-04-25 23:28 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3955 bytes --]
== Series Details ==
Series: drm/i915/mtl: Implement Wa_14019141245 (rev2)
URL : https://patchwork.freedesktop.org/series/116939/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13062 -> Patchwork_116939v2
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_116939v2 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116939v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/index.html
Participating hosts (39 -> 38)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116939v2:
### IGT changes ###
#### Warnings ####
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: [INCOMPLETE][1] ([i915#7443]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/fi-tgl-1115g4/igt@i915_suspend@basic-s3-without-i915.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/fi-tgl-1115g4/igt@i915_suspend@basic-s3-without-i915.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {bat-mtlp-8}: NOTRUN -> [FAIL][3] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/bat-mtlp-8/igt@i915_selftest@live@hugepages.html
Known issues
------------
Here are the changes found in Patchwork_116939v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][4] -> [FAIL][5] ([i915#7932])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#5354]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/bat-dg2-11/igt@kms_pipe_crc_basic@read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][7] -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/bat-mtlp-8/igt@i915_selftest@live@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/bat-mtlp-8/igt@i915_selftest@live@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
Build changes
-------------
* Linux: CI_DRM_13062 -> Patchwork_116939v2
CI-20190529: 20190529
CI_DRM_13062: 5a0333cf630a335d7e8f60fd2b8526ed0895900c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7270: 3bd8bf9bca97bbfb7b4b408f9fccd0cf6f742d4c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116939v2: 5a0333cf630a335d7e8f60fd2b8526ed0895900c @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b560912ba833 drm/i915/mtl: Implement Wa_14019141245
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/index.html
[-- Attachment #2: Type: text/html, Size: 4566 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Implement Wa_14019141245 (rev2)
2023-04-25 18:30 [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Radhakrishna Sripada
2023-04-25 23:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Implement Wa_14019141245 (rev2) Patchwork
@ 2023-04-26 3:57 ` Patchwork
2023-04-26 12:35 ` [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Kalvala, Haridhar
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2023-04-26 3:57 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9927 bytes --]
== Series Details ==
Series: drm/i915/mtl: Implement Wa_14019141245 (rev2)
URL : https://patchwork.freedesktop.org/series/116939/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13062_full -> Patchwork_116939v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116939v2_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@hibernate:
- {shard-dg1}: [PASS][1] -> [ABORT][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-dg1-15/igt@gem_eio@hibernate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-dg1-14/igt@gem_eio@hibernate.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [PASS][3] -> [TIMEOUT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a4:
- {shard-dg1}: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-dg1-12/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a4.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-dg1-13/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a4.html
* igt@kms_rotation_crc@sprite-rotation-90:
- {shard-rkl}: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-rkl-1/igt@kms_rotation_crc@sprite-rotation-90.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-rkl-7/igt@kms_rotation_crc@sprite-rotation-90.html
Known issues
------------
Here are the changes found in Patchwork_116939v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2846])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-glk3/igt@gem_exec_fair@basic-deadline.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-glk6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-snb: [PASS][11] -> [FAIL][12] ([i915#8295])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-snb5/igt@gem_ppgtt@blt-vs-render-ctx0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctx0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][13] -> [ABORT][14] ([i915#5566])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-apl3/igt@gen9_exec_parse@allowed-single.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-apl4/igt@gen9_exec_parse@allowed-single.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271]) +26 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-snb5/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_setmode@basic@pipe-a-vga-1:
- shard-snb: NOTRUN -> [FAIL][16] ([i915#5465]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-snb7/igt@kms_setmode@basic@pipe-a-vga-1.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}: [FAIL][17] ([i915#7742]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-rkl-2/igt@drm_fdinfo@idle@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-rkl-1/igt@drm_fdinfo@idle@rcs0.html
* igt@gem_eio@hibernate:
- {shard-tglu}: [ABORT][19] -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-tglu-10/igt@gem_eio@hibernate.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-tglu-4/igt@gem_eio@hibernate.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}: [FAIL][21] ([i915#2842]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-rkl-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
- {shard-tglu}: [FAIL][23] ([i915#2842]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@kms_cursor_legacy@single-move@pipe-b:
- {shard-rkl}: [INCOMPLETE][25] ([i915#8011]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13062/shard-rkl-7/igt@kms_cursor_legacy@single-move@pipe-b.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/shard-rkl-3/igt@kms_cursor_legacy@single-move@pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295
Build changes
-------------
* Linux: CI_DRM_13062 -> Patchwork_116939v2
CI-20190529: 20190529
CI_DRM_13062: 5a0333cf630a335d7e8f60fd2b8526ed0895900c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7270: 3bd8bf9bca97bbfb7b4b408f9fccd0cf6f742d4c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116939v2: 5a0333cf630a335d7e8f60fd2b8526ed0895900c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116939v2/index.html
[-- Attachment #2: Type: text/html, Size: 7767 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245
2023-04-25 18:30 [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Radhakrishna Sripada
2023-04-25 23:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Implement Wa_14019141245 (rev2) Patchwork
2023-04-26 3:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-04-26 12:35 ` Kalvala, Haridhar
2023-04-26 16:11 ` Sripada, Radhakrishna
2023-04-26 16:59 ` Umesh Nerlige Ramappa
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Kalvala, Haridhar @ 2023-04-26 12:35 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: Rodrigo Vivi
On 4/26/2023 12:00 AM, Radhakrishna Sripada wrote:
> Enable strict RAR to prevent spurious GPU hangs.
>
> v1.1: Rebase
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
> drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4 ----
> 3 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index e8c3b762a92a..af80d2fe739b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -529,6 +529,11 @@
>
> #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
>
> +#define GEN12_SQCNT1 _MMIO(0x8718)
> +#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> +#define GEN12_SQCNT1_OABPC REG_BIT(29)
> +#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
> +
> #define XEHP_SQCM MCR_REG(0x8724)
> #define EN_32B_ACCESS REG_BIT(30)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index de4f8e2e8e8c..ad9e7f49a6fa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>
> + /* Wa_14019141245 */
> + wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> +
looks good to me.
> if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> /* Wa_14014830051 */
> @@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_14015795083 */
> wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> }
> +
> /*
> * Unlike older platforms, we no longer setup implicit steering here;
> * all MCR accesses are explicitly steered.
> diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> index ba103875e19f..e5ac7a8b5cb6 100644
> --- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> +++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> @@ -134,10 +134,6 @@
> #define GDT_CHICKEN_BITS _MMIO(0x9840)
> #define GT_NOA_ENABLE 0x00000080
>
> -#define GEN12_SQCNT1 _MMIO(0x8718)
> -#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> -#define GEN12_SQCNT1_OABPC REG_BIT(29)
These two register bit and register(0x8718) moved to "
intel_gt_regs.h"not getting used elsewhere(I mean, in i915_perf.c) ?
> -
> /* Gen12 OAM unit */
> #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
> #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
--
Regards,
Haridhar Kalvala
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245
2023-04-26 12:35 ` [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Kalvala, Haridhar
@ 2023-04-26 16:11 ` Sripada, Radhakrishna
2023-04-26 17:03 ` Kalvala, Haridhar
0 siblings, 1 reply; 10+ messages in thread
From: Sripada, Radhakrishna @ 2023-04-26 16:11 UTC (permalink / raw)
To: Kalvala, Haridhar, intel-gfx; +Cc: Vivi, Rodrigo
> -----Original Message-----
> From: Kalvala, Haridhar <haridhar.kalvala@intel.com>
> Sent: Wednesday, April 26, 2023 5:36 AM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement
> Wa_14019141245
>
>
> On 4/26/2023 12:00 AM, Radhakrishna Sripada wrote:
> > Enable strict RAR to prevent spurious GPU hangs.
> >
> > v1.1: Rebase
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
> > drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4 ----
> > 3 files changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index e8c3b762a92a..af80d2fe739b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -529,6 +529,11 @@
> >
> > #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
> >
> > +#define GEN12_SQCNT1 _MMIO(0x8718)
> > +#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> > +#define GEN12_SQCNT1_OABPC REG_BIT(29)
> > +#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
> > +
> > #define XEHP_SQCM MCR_REG(0x8724)
> > #define EN_32B_ACCESS REG_BIT(30)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index de4f8e2e8e8c..ad9e7f49a6fa 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt,
> struct i915_wa_list *wal)
> > wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> > wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> >
> > + /* Wa_14019141245 */
> > + wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> > +
> looks good to me.
> > if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> > /* Wa_14014830051 */
> > @@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt,
> struct i915_wa_list *wal)
> > /* Wa_14015795083 */
> > wa_write_clr(wal, GEN7_MISCCPCTL,
> GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> > }
> > +
> > /*
> > * Unlike older platforms, we no longer setup implicit steering here;
> > * all MCR accesses are explicitly steered.
> > diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> > index ba103875e19f..e5ac7a8b5cb6 100644
> > --- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> > +++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> > @@ -134,10 +134,6 @@
> > #define GDT_CHICKEN_BITS _MMIO(0x9840)
> > #define GT_NOA_ENABLE 0x00000080
> >
> > -#define GEN12_SQCNT1 _MMIO(0x8718)
> > -#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> > -#define GEN12_SQCNT1_OABPC REG_BIT(29)
> These two register bit and register(0x8718) moved to "
> intel_gt_regs.h"not getting used elsewhere(I mean, in i915_perf.c) ?
1) i915_perf.c includes gt/intel_gt_regs.h so moving the register def. there should not cause any problem.
Moreover,
2) intel_gt_regs.h is used across almost all the files under i915/gt.
i915_perf_oa_regs.h do not have that kind of usage.
3) because of this bit, the usage of this register is not limited to perf subsystem.
Hence the better place in intel_gt_regs.h.
4) we need not have all the i915_pref_oa_regs.h definitions included in intel_workarounds.c
- Radhakrishna(RK) Sripada
> > -
> > /* Gen12 OAM unit */
> > #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
> > #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
>
> --
> Regards,
> Haridhar Kalvala
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245
2023-04-25 18:30 [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Radhakrishna Sripada
` (2 preceding siblings ...)
2023-04-26 12:35 ` [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Kalvala, Haridhar
@ 2023-04-26 16:59 ` Umesh Nerlige Ramappa
2023-04-26 22:07 ` Matt Atwood
2023-05-04 23:37 ` Matt Roper
5 siblings, 0 replies; 10+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-04-26 16:59 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, Rodrigo Vivi
On Tue, Apr 25, 2023 at 11:30:11AM -0700, Radhakrishna Sripada wrote:
>Enable strict RAR to prevent spurious GPU hangs.
>
>v1.1: Rebase
>
>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
> drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4 ----
> 3 files changed, 9 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>index e8c3b762a92a..af80d2fe739b 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>@@ -529,6 +529,11 @@
>
> #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
>
>+#define GEN12_SQCNT1 _MMIO(0x8718)
>+#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
>+#define GEN12_SQCNT1_OABPC REG_BIT(29)
>+#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
>+
> #define XEHP_SQCM MCR_REG(0x8724)
> #define EN_32B_ACCESS REG_BIT(30)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index de4f8e2e8e8c..ad9e7f49a6fa 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>
>+ /* Wa_14019141245 */
>+ wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>+
Was wondering if this should be a rmw, but since this write is at driver
probe and OA always does a rmw on this register, this looks fine.
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Thanks,
Umesh
> if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> /* Wa_14014830051 */
>@@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_14015795083 */
> wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> }
>+
> /*
> * Unlike older platforms, we no longer setup implicit steering here;
> * all MCR accesses are explicitly steered.
>diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
>index ba103875e19f..e5ac7a8b5cb6 100644
>--- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
>+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
>@@ -134,10 +134,6 @@
> #define GDT_CHICKEN_BITS _MMIO(0x9840)
> #define GT_NOA_ENABLE 0x00000080
>
>-#define GEN12_SQCNT1 _MMIO(0x8718)
>-#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
>-#define GEN12_SQCNT1_OABPC REG_BIT(29)
>-
> /* Gen12 OAM unit */
> #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
> #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
>--
>2.34.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245
2023-04-26 16:11 ` Sripada, Radhakrishna
@ 2023-04-26 17:03 ` Kalvala, Haridhar
0 siblings, 0 replies; 10+ messages in thread
From: Kalvala, Haridhar @ 2023-04-26 17:03 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx; +Cc: Vivi, Rodrigo
On 4/26/2023 9:41 PM, Sripada, Radhakrishna wrote:
>
>> -----Original Message-----
>> From: Kalvala, Haridhar <haridhar.kalvala@intel.com>
>> Sent: Wednesday, April 26, 2023 5:36 AM
>> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>> Subject: Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement
>> Wa_14019141245
>>
>>
>> On 4/26/2023 12:00 AM, Radhakrishna Sripada wrote:
>>> Enable strict RAR to prevent spurious GPU hangs.
>>>
>>> v1.1: Rebase
>>>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by:Haridhar Kalvala <haridhar.kalvala@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
>>> drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4 ----
>>> 3 files changed, 9 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> index e8c3b762a92a..af80d2fe739b 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> @@ -529,6 +529,11 @@
>>>
>>> #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
>>>
>>> +#define GEN12_SQCNT1 _MMIO(0x8718)
>>> +#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
>>> +#define GEN12_SQCNT1_OABPC REG_BIT(29)
>>> +#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
>>> +
>>> #define XEHP_SQCM MCR_REG(0x8724)
>>> #define EN_32B_ACCESS REG_BIT(30)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index de4f8e2e8e8c..ad9e7f49a6fa 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt,
>> struct i915_wa_list *wal)
>>> wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
>>> wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>>>
>>> + /* Wa_14019141245 */
>>> + wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>> +
>> looks good to me.
>>> if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>> /* Wa_14014830051 */
>>> @@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt,
>> struct i915_wa_list *wal)
>>> /* Wa_14015795083 */
>>> wa_write_clr(wal, GEN7_MISCCPCTL,
>> GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
>>> }
>>> +
>>> /*
>>> * Unlike older platforms, we no longer setup implicit steering here;
>>> * all MCR accesses are explicitly steered.
>>> diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
>> b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
>>> index ba103875e19f..e5ac7a8b5cb6 100644
>>> --- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
>>> +++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
>>> @@ -134,10 +134,6 @@
>>> #define GDT_CHICKEN_BITS _MMIO(0x9840)
>>> #define GT_NOA_ENABLE 0x00000080
>>>
>>> -#define GEN12_SQCNT1 _MMIO(0x8718)
>>> -#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
>>> -#define GEN12_SQCNT1_OABPC REG_BIT(29)
>> These two register bit and register(0x8718) moved to "
>> intel_gt_regs.h"not getting used elsewhere(I mean, in i915_perf.c) ?
> 1) i915_perf.c includes gt/intel_gt_regs.h so moving the register def. there should not cause any problem.
> Moreover,
> 2) intel_gt_regs.h is used across almost all the files under i915/gt.
> i915_perf_oa_regs.h do not have that kind of usage.
> 3) because of this bit, the usage of this register is not limited to perf subsystem.
> Hence the better place in intel_gt_regs.h.
> 4) we need not have all the i915_pref_oa_regs.h definitions included in intel_workarounds.c
>
>
> - Radhakrishna(RK) Sripada
>
>>> -
>>> /* Gen12 OAM unit */
>>> #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
>>> #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
>> --
>> Regards,
>> Haridhar Kalvala
--
Regards,
Haridhar Kalvala
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245
2023-04-25 18:30 [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Radhakrishna Sripada
` (3 preceding siblings ...)
2023-04-26 16:59 ` Umesh Nerlige Ramappa
@ 2023-04-26 22:07 ` Matt Atwood
2023-05-04 23:37 ` Matt Roper
5 siblings, 0 replies; 10+ messages in thread
From: Matt Atwood @ 2023-04-26 22:07 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: intel-gfx, Rodrigo Vivi
On Tue, Apr 25, 2023 at 11:30:11AM -0700, Radhakrishna Sripada wrote:
> Enable strict RAR to prevent spurious GPU hangs.
>
> v1.1: Rebase
>
Bspec: 51762
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
> drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4 ----
> 3 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index e8c3b762a92a..af80d2fe739b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -529,6 +529,11 @@
>
> #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
>
> +#define GEN12_SQCNT1 _MMIO(0x8718)
> +#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> +#define GEN12_SQCNT1_OABPC REG_BIT(29)
> +#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
> +
> #define XEHP_SQCM MCR_REG(0x8724)
> #define EN_32B_ACCESS REG_BIT(30)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index de4f8e2e8e8c..ad9e7f49a6fa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>
> + /* Wa_14019141245 */
> + wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> +
> if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> /* Wa_14014830051 */
> @@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_14015795083 */
> wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> }
> +
> /*
> * Unlike older platforms, we no longer setup implicit steering here;
> * all MCR accesses are explicitly steered.
> diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> index ba103875e19f..e5ac7a8b5cb6 100644
> --- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> +++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> @@ -134,10 +134,6 @@
> #define GDT_CHICKEN_BITS _MMIO(0x9840)
> #define GT_NOA_ENABLE 0x00000080
>
> -#define GEN12_SQCNT1 _MMIO(0x8718)
> -#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> -#define GEN12_SQCNT1_OABPC REG_BIT(29)
> -
> /* Gen12 OAM unit */
> #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
> #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245
2023-04-25 18:30 [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Radhakrishna Sripada
` (4 preceding siblings ...)
2023-04-26 22:07 ` Matt Atwood
@ 2023-05-04 23:37 ` Matt Roper
2023-05-05 23:32 ` Sripada, Radhakrishna
5 siblings, 1 reply; 10+ messages in thread
From: Matt Roper @ 2023-05-04 23:37 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, Rodrigo Vivi
On Tue, Apr 25, 2023 at 11:30:11AM -0700, Radhakrishna Sripada wrote:
> Enable strict RAR to prevent spurious GPU hangs.
There's no such workaround as "Wa_14019141245." Were you trying to
implement Wa_22016670082 instead?
Matt
>
> v1.1: Rebase
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
> drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4 ----
> 3 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index e8c3b762a92a..af80d2fe739b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -529,6 +529,11 @@
>
> #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
>
> +#define GEN12_SQCNT1 _MMIO(0x8718)
> +#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> +#define GEN12_SQCNT1_OABPC REG_BIT(29)
> +#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
> +
> #define XEHP_SQCM MCR_REG(0x8724)
> #define EN_32B_ACCESS REG_BIT(30)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index de4f8e2e8e8c..ad9e7f49a6fa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>
> + /* Wa_14019141245 */
> + wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> +
> if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> /* Wa_14014830051 */
> @@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_14015795083 */
> wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> }
> +
> /*
> * Unlike older platforms, we no longer setup implicit steering here;
> * all MCR accesses are explicitly steered.
> diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> index ba103875e19f..e5ac7a8b5cb6 100644
> --- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> +++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> @@ -134,10 +134,6 @@
> #define GDT_CHICKEN_BITS _MMIO(0x9840)
> #define GT_NOA_ENABLE 0x00000080
>
> -#define GEN12_SQCNT1 _MMIO(0x8718)
> -#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> -#define GEN12_SQCNT1_OABPC REG_BIT(29)
> -
> /* Gen12 OAM unit */
> #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
> #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245
2023-05-04 23:37 ` Matt Roper
@ 2023-05-05 23:32 ` Sripada, Radhakrishna
0 siblings, 0 replies; 10+ messages in thread
From: Sripada, Radhakrishna @ 2023-05-05 23:32 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx, Vivi, Rodrigo
Hi Matt,
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, May 4, 2023 4:37 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement
> Wa_14019141245
>
> On Tue, Apr 25, 2023 at 11:30:11AM -0700, Radhakrishna Sripada wrote:
> > Enable strict RAR to prevent spurious GPU hangs.
>
> There's no such workaround as "Wa_14019141245." Were you trying to
> implement Wa_22016670082 instead?
Yes that is the correct WA number. Will send a patch to fix the comment.
- Radhakrishna(RK) Sripada
>
>
> Matt
>
> >
> > v1.1: Rebase
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
> > drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4 ----
> > 3 files changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index e8c3b762a92a..af80d2fe739b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -529,6 +529,11 @@
> >
> > #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
> >
> > +#define GEN12_SQCNT1 _MMIO(0x8718)
> > +#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> > +#define GEN12_SQCNT1_OABPC REG_BIT(29)
> > +#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
> > +
> > #define XEHP_SQCM MCR_REG(0x8724)
> > #define EN_32B_ACCESS REG_BIT(30)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index de4f8e2e8e8c..ad9e7f49a6fa 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt,
> struct i915_wa_list *wal)
> > wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> > wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> >
> > + /* Wa_14019141245 */
> > + wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> > +
> > if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> > /* Wa_14014830051 */
> > @@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt,
> struct i915_wa_list *wal)
> > /* Wa_14015795083 */
> > wa_write_clr(wal, GEN7_MISCCPCTL,
> GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> > }
> > +
> > /*
> > * Unlike older platforms, we no longer setup implicit steering here;
> > * all MCR accesses are explicitly steered.
> > diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> > index ba103875e19f..e5ac7a8b5cb6 100644
> > --- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> > +++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
> > @@ -134,10 +134,6 @@
> > #define GDT_CHICKEN_BITS _MMIO(0x9840)
> > #define GT_NOA_ENABLE 0x00000080
> >
> > -#define GEN12_SQCNT1 _MMIO(0x8718)
> > -#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> > -#define GEN12_SQCNT1_OABPC REG_BIT(29)
> > -
> > /* Gen12 OAM unit */
> > #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
> > #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
> > --
> > 2.34.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-05-05 23:32 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-25 18:30 [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Radhakrishna Sripada
2023-04-25 23:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Implement Wa_14019141245 (rev2) Patchwork
2023-04-26 3:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-04-26 12:35 ` [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement Wa_14019141245 Kalvala, Haridhar
2023-04-26 16:11 ` Sripada, Radhakrishna
2023-04-26 17:03 ` Kalvala, Haridhar
2023-04-26 16:59 ` Umesh Nerlige Ramappa
2023-04-26 22:07 ` Matt Atwood
2023-05-04 23:37 ` Matt Roper
2023-05-05 23:32 ` Sripada, Radhakrishna
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