[PATCH 00/13] drm/i915: Implemnt vblank sycnhronized mbus joining changes

[PATCH 00/13] drm/i915: Implemnt vblank sycnhronized mbus joining changes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of the full modeset requirement for changing mbus
joining. Things got quite a bit more complicated than
originally envisioned due to the dynamic cdclk/mdclk ratio.
Sadly we have to do a fairly careful dance between the
dbuf and cdclk code to make sure everything is programmed
in the correct sequence.

Stan did the grunt work, but the sequence vs. cdclk
updates was still not right so I finished that part.
I also reorganized the code quite a bit to make the 
resulting patches more legible. And I tossed in more
debugs and whatnot so we can actually observe what
it's doing.

Quickly smoke tested on tgl and adl, and things seem
pretty decent. Unfortunately I don't have a LNL on me
right now so I haven't fully tested the mdclk/cdclk ratio
changes on real hw, but I did hack my adl to pretend that
the ratio changes with cdclk and double checked that the
logs look sensible for all the combinations of cdclk
increase/decrease and mbus join enable/disable.
So should work (tm) on real hw too.

Stanislav Lisovskiy (3):
  drm/i915: Loop over all active pipes in intel_mbus_dbox_update
  drm/i915: Use old mbus_join value when increasing CDCLK
  drm/i915: Implement vblank synchronized MBUS join changes

Ville Syrjälä (10):
  drm/i915/cdclk: Fix CDCLK programming order when pipes are active
  drm/i915/cdclk: Fix voltage_level programming edge case
  drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks
  drm/i915/cdclk: Indicate whether CDCLK change happens during pre or
    post plane update
  drm/i915: Relocate intel_mbus_dbox_update()
  drm/i915: Extract intel_dbuf_mbus_join_update()
  drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()
  drm/i915: Add debugs for mbus joining and dbuf ratio programming
  drm/i915: Use a plain old int for the cdclk/mdclk ratio
  drm/i915: Optimize out redundant dbuf slice updates

 drivers/gpu/drm/i915/display/intel_cdclk.c   |  85 +++--
 drivers/gpu/drm/i915/display/intel_cdclk.h   |   8 +-
 drivers/gpu/drm/i915/display/intel_display.c |   5 +-
 drivers/gpu/drm/i915/display/skl_watermark.c | 344 ++++++++++++-------
 drivers/gpu/drm/i915/display/skl_watermark.h |   9 +-
 5 files changed, 271 insertions(+), 180 deletions(-)

-- 
2.43.2

[PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we always reprogram CDCLK from the
intel_set_cdclk_pre_plane_update() when using squahs/crawl.
The code only works correctly for the cd2x update or full
modeset cases, and it was simply never updated to deal with
squash/crawl.

If the CDCLK frequency is increasing we must reprogram it
before we do anything else that might depend on the new
higher frequency, and conversely we must not decrease
the frequency until everything that might still depend
on the old higher frequency has been dealt with.

Since cdclk_state->pipe is only relevant when doing a cd2x
update we can't use it to determine the correct sequence
during squash/crawl. To that end introduce cdclk_state->disable_pipes
which simply indicates that we must perform the update
while the pipes are disable (ie. during
intel_set_cdclk_pre_plane_update()). Otherwise we use the
same old vs. new CDCLK frequency comparsiong as for cd2x
updates.

The only remaining problem case is when the voltage_level
needs to increase due to a DDI port, but the CDCLK frequency
is decreasing (and not all pipes are being disabled). The
current approach will not bump the voltage level up until
after the port has already been enabled, which is too late.
But we'll take care of that case separately.

v2: Don't break the "must disable pipes case"

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++++++------
 drivers/gpu/drm/i915/display/intel_cdclk.h |  3 +++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 31aaa9780dfc..619529dba095 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2600,7 +2600,6 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_cdclk_state(state);
 	const struct intel_cdclk_state *new_cdclk_state =
 		intel_atomic_get_new_cdclk_state(state);
-	enum pipe pipe = new_cdclk_state->pipe;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
 				 &new_cdclk_state->actual))
@@ -2609,11 +2608,12 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 	if (IS_DG2(i915))
 		intel_cdclk_pcode_pre_notify(state);
 
-	if (pipe == INVALID_PIPE ||
+	if (new_cdclk_state->disable_pipes ||
 	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
 		drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
 
-		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
+		intel_set_cdclk(i915, &new_cdclk_state->actual,
+				new_cdclk_state->pipe);
 	}
 }
 
@@ -2632,7 +2632,6 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_cdclk_state(state);
 	const struct intel_cdclk_state *new_cdclk_state =
 		intel_atomic_get_new_cdclk_state(state);
-	enum pipe pipe = new_cdclk_state->pipe;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
 				 &new_cdclk_state->actual))
@@ -2641,11 +2640,12 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 	if (IS_DG2(i915))
 		intel_cdclk_pcode_post_notify(state);
 
-	if (pipe != INVALID_PIPE &&
+	if (!new_cdclk_state->disable_pipes &&
 	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
 		drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
 
-		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
+		intel_set_cdclk(i915, &new_cdclk_state->actual,
+				new_cdclk_state->pipe);
 	}
 }
 
@@ -3124,6 +3124,7 @@ static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_globa
 		return NULL;
 
 	cdclk_state->pipe = INVALID_PIPE;
+	cdclk_state->disable_pipes = false;
 
 	return &cdclk_state->base;
 }
@@ -3316,6 +3317,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 		if (ret)
 			return ret;
 
+		new_cdclk_state->disable_pipes = true;
+
 		drm_dbg_kms(&dev_priv->drm,
 			    "Modeset required for cdclk change\n");
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index bc8f86e292d8..2843fc091086 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -53,6 +53,9 @@ struct intel_cdclk_state {
 
 	/* bitmask of active pipes */
 	u8 active_pipes;
+
+	/* update cdclk with pipes disabled */
+	bool disable_pipes;
 };
 
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
-- 
2.43.2

[PATCH 02/13] drm/i915/cdclk: Fix voltage_level programming edge case

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we only consider the relationship of the
old and new CDCLK frequencies when determining whether
to do the repgramming from intel_set_cdclk_pre_plane_update()
or intel_set_cdclk_post_plane_update().

It is technically possible to have a situation where the
CDCLK frequency is decreasing, but the voltage_level is
increasing due a DDI port. In this case we should bump
the voltage level already in intel_set_cdclk_pre_plane_update()
(so that the voltage_level will have been increased by the
time the port gets enabled), while leaving the CDCLK frequency
unchanged (as active planes/etc. may still depend on it).
We can then reduce the CDCLK frequency to its final value
from intel_set_cdclk_post_plane_update().

In order to handle that correctly we shall construct a
suitable amalgam of the old and new cdclk states in
intel_set_cdclk_pre_plane_update().

And we can simply call intel_set_cdclk() unconditionally
in both places as it will not do anything if nothing actually
changes vs. the current hw state.

v2: Handle cdclk_state->disable_pipes

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 27 +++++++++++++---------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 619529dba095..504c5cbbcfff 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2600,6 +2600,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_cdclk_state(state);
 	const struct intel_cdclk_state *new_cdclk_state =
 		intel_atomic_get_new_cdclk_state(state);
+	struct intel_cdclk_config cdclk_config;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
 				 &new_cdclk_state->actual))
@@ -2608,13 +2609,21 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 	if (IS_DG2(i915))
 		intel_cdclk_pcode_pre_notify(state);
 
-	if (new_cdclk_state->disable_pipes ||
-	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
-		drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+	if (new_cdclk_state->disable_pipes) {
+		cdclk_config = new_cdclk_state->actual;
+	} else {
+		if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk)
+			cdclk_config = new_cdclk_state->actual;
+		else
+			cdclk_config = old_cdclk_state->actual;
 
-		intel_set_cdclk(i915, &new_cdclk_state->actual,
-				new_cdclk_state->pipe);
+		cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
+						 old_cdclk_state->actual.voltage_level);
 	}
+
+	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+
+	intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe);
 }
 
 /**
@@ -2640,13 +2649,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 	if (IS_DG2(i915))
 		intel_cdclk_pcode_post_notify(state);
 
-	if (!new_cdclk_state->disable_pipes &&
-	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
-		drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
 
-		intel_set_cdclk(i915, &new_cdclk_state->actual,
-				new_cdclk_state->pipe);
-	}
+	intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe);
 }
 
 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
-- 
2.43.2

[PATCH 03/13] drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No ever figured out why bumping the cdclk helped
with whatever issue we were having at the time.
Remove the hacks and start from scratch so that we
can actually see if any problems still remain.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 504c5cbbcfff..99d2657f29a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2802,25 +2802,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->dsc.compression_enable)
 		min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
 
-	/*
-	 * HACK. Currently for TGL/DG2 platforms we calculate
-	 * min_cdclk initially based on pixel_rate divided
-	 * by 2, accounting for also plane requirements,
-	 * however in some cases the lowest possible CDCLK
-	 * doesn't work and causing the underruns.
-	 * Explicitly stating here that this seems to be currently
-	 * rather a Hack, than final solution.
-	 */
-	if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {
-		/*
-		 * Clamp to max_cdclk_freq in case pixel rate is higher,
-		 * in order not to break an 8K, but still leave W/A at place.
-		 */
-		min_cdclk = max_t(int, min_cdclk,
-				  min_t(int, crtc_state->pixel_rate,
-					dev_priv->display.cdclk.max_cdclk_freq));
-	}
-
 	return min_cdclk;
 }
 
-- 
2.43.2

[PATCH 04/13] drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plane update

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we just get a plain "Changing CDCLK to ..." in the
logs. It would actually be interesting to see whether we're
doing the programming during the pre or post plane phase of
the commit. Include that information in the debug message.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 99d2657f29a7..98546f384023 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2434,18 +2434,9 @@ static void intel_pcode_notify(struct drm_i915_private *i915,
 			ret);
 }
 
-/**
- * intel_set_cdclk - Push the CDCLK configuration to the hardware
- * @dev_priv: i915 device
- * @cdclk_config: new CDCLK configuration
- * @pipe: pipe with which to synchronize the update
- *
- * Program the hardware based on the passed in CDCLK state,
- * if necessary.
- */
 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
 			    const struct intel_cdclk_config *cdclk_config,
-			    enum pipe pipe)
+			    enum pipe pipe, const char *context)
 {
 	struct intel_encoder *encoder;
 
@@ -2455,7 +2446,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
 		return;
 
-	intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
+	intel_cdclk_dump_config(dev_priv, cdclk_config, context);
 
 	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2623,7 +2614,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 
 	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
 
-	intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe);
+	intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe,
+			"Pre changing CDCLK to");
 }
 
 /**
@@ -2651,7 +2643,8 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 
 	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
 
-	intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe);
+	intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe,
+			"Post changing CDCLK to");
 }
 
 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
-- 
2.43.2

[PATCH 05/13] drm/i915: Loop over all active pipes in intel_mbus_dbox_update

[Ville Syrjala]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

We need to loop through all active pipes, not just the ones, that
are in current state, because disabling and enabling even a particular
pipe affects credits in another one.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index bc341abcab2f..f582992592c1 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3680,10 +3680,8 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
-	const struct intel_crtc_state *new_crtc_state;
 	const struct intel_crtc *crtc;
 	u32 val = 0;
-	int i;
 
 	if (DISPLAY_VER(i915) < 11)
 		return;
@@ -3727,12 +3725,9 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
 		val |= MBUS_DBOX_B_CREDIT(8);
 	}
 
-	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
 		u32 pipe_val = val;
 
-		if (!new_crtc_state->hw.active)
-			continue;
-
 		if (DISPLAY_VER(i915) >= 14) {
 			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
 							      new_dbuf_state->active_pipes))
-- 
2.43.2

[PATCH 06/13] drm/i915: Relocate intel_mbus_dbox_update()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_mbus_dbox_update() will become static soon. Relocate it
into a place that avoids having to add a forward declaration
for it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 166 +++++++++----------
 1 file changed, 83 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index f582992592c1..6bd3fec0aa56 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3540,6 +3540,89 @@ int intel_dbuf_init(struct drm_i915_private *i915)
 	return 0;
 }
 
+static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
+{
+	switch (pipe) {
+	case PIPE_A:
+		return !(active_pipes & BIT(PIPE_D));
+	case PIPE_D:
+		return !(active_pipes & BIT(PIPE_A));
+	case PIPE_B:
+		return !(active_pipes & BIT(PIPE_C));
+	case PIPE_C:
+		return !(active_pipes & BIT(PIPE_B));
+	default: /* to suppress compiler warning */
+		MISSING_CASE(pipe);
+		break;
+	}
+
+	return false;
+}
+
+void intel_mbus_dbox_update(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+	const struct intel_crtc *crtc;
+	u32 val = 0;
+
+	if (DISPLAY_VER(i915) < 11)
+		return;
+
+	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+	if (!new_dbuf_state ||
+	    (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+	     new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
+		return;
+
+	if (DISPLAY_VER(i915) >= 14)
+		val |= MBUS_DBOX_I_CREDIT(2);
+
+	if (DISPLAY_VER(i915) >= 12) {
+		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
+		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
+		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
+	}
+
+	if (DISPLAY_VER(i915) >= 14)
+		val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
+						     MBUS_DBOX_A_CREDIT(8);
+	else if (IS_ALDERLAKE_P(i915))
+		/* Wa_22010947358:adl-p */
+		val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
+						     MBUS_DBOX_A_CREDIT(4);
+	else
+		val |= MBUS_DBOX_A_CREDIT(2);
+
+	if (DISPLAY_VER(i915) >= 14) {
+		val |= MBUS_DBOX_B_CREDIT(0xA);
+	} else if (IS_ALDERLAKE_P(i915)) {
+		val |= MBUS_DBOX_BW_CREDIT(2);
+		val |= MBUS_DBOX_B_CREDIT(8);
+	} else if (DISPLAY_VER(i915) >= 12) {
+		val |= MBUS_DBOX_BW_CREDIT(2);
+		val |= MBUS_DBOX_B_CREDIT(12);
+	} else {
+		val |= MBUS_DBOX_BW_CREDIT(1);
+		val |= MBUS_DBOX_B_CREDIT(8);
+	}
+
+	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
+		u32 pipe_val = val;
+
+		if (DISPLAY_VER(i915) >= 14) {
+			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
+							      new_dbuf_state->active_pipes))
+				pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
+			else
+				pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
+		}
+
+		intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
+	}
+}
+
 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio)
 {
 	struct intel_dbuf_state *dbuf_state;
@@ -3657,89 +3740,6 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 				new_dbuf_state->enabled_slices);
 }
 
-static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
-{
-	switch (pipe) {
-	case PIPE_A:
-		return !(active_pipes & BIT(PIPE_D));
-	case PIPE_D:
-		return !(active_pipes & BIT(PIPE_A));
-	case PIPE_B:
-		return !(active_pipes & BIT(PIPE_C));
-	case PIPE_C:
-		return !(active_pipes & BIT(PIPE_B));
-	default: /* to suppress compiler warning */
-		MISSING_CASE(pipe);
-		break;
-	}
-
-	return false;
-}
-
-void intel_mbus_dbox_update(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
-	const struct intel_crtc *crtc;
-	u32 val = 0;
-
-	if (DISPLAY_VER(i915) < 11)
-		return;
-
-	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
-	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
-	if (!new_dbuf_state ||
-	    (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
-	     new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
-		return;
-
-	if (DISPLAY_VER(i915) >= 14)
-		val |= MBUS_DBOX_I_CREDIT(2);
-
-	if (DISPLAY_VER(i915) >= 12) {
-		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
-		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
-		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
-	}
-
-	if (DISPLAY_VER(i915) >= 14)
-		val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
-						     MBUS_DBOX_A_CREDIT(8);
-	else if (IS_ALDERLAKE_P(i915))
-		/* Wa_22010947358:adl-p */
-		val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
-						     MBUS_DBOX_A_CREDIT(4);
-	else
-		val |= MBUS_DBOX_A_CREDIT(2);
-
-	if (DISPLAY_VER(i915) >= 14) {
-		val |= MBUS_DBOX_B_CREDIT(0xA);
-	} else if (IS_ALDERLAKE_P(i915)) {
-		val |= MBUS_DBOX_BW_CREDIT(2);
-		val |= MBUS_DBOX_B_CREDIT(8);
-	} else if (DISPLAY_VER(i915) >= 12) {
-		val |= MBUS_DBOX_BW_CREDIT(2);
-		val |= MBUS_DBOX_B_CREDIT(12);
-	} else {
-		val |= MBUS_DBOX_BW_CREDIT(1);
-		val |= MBUS_DBOX_B_CREDIT(8);
-	}
-
-	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
-		u32 pipe_val = val;
-
-		if (DISPLAY_VER(i915) >= 14) {
-			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
-							      new_dbuf_state->active_pipes))
-				pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
-			else
-				pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
-		}
-
-		intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
-	}
-}
-
 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *i915 = m->private;
-- 
2.43.2

[PATCH 07/13] drm/i915: Extract intel_dbuf_mbus_join_update()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extact the stuff that writes the joining bits in MBUS_CTL
into its own function. Will help with correctly sequencing
the operations done during mbus programming.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 37 +++++++++++++-------
 1 file changed, 25 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 6bd3fec0aa56..f7e03078bd43 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3653,21 +3653,12 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
 			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
 }
 
-/*
- * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
- * update the request state of all DBUS slices.
- */
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_dbuf_state *new_dbuf_state =
+		intel_atomic_get_new_dbuf_state(state);
 	u32 mbus_ctl;
-	const struct intel_dbuf_state *old_dbuf_state =
-		intel_atomic_get_old_dbuf_state(state);
-	const struct intel_dbuf_state *new_dbuf_state =
-		intel_atomic_get_new_dbuf_state(state);
-
-	if (!HAS_MBUS_JOINING(i915))
-		return;
 
 	/*
 	 * TODO: Implement vblank synchronized MBUS joining changes.
@@ -3683,6 +3674,28 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
 	intel_de_rmw(i915, MBUS_CTL,
 		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
 		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
+}
+
+/*
+ * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
+ * update the request state of all DBUS slices.
+ */
+static void update_mbus_pre_enable(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_dbuf_state *old_dbuf_state =
+		intel_atomic_get_old_dbuf_state(state);
+	const struct intel_dbuf_state *new_dbuf_state =
+		intel_atomic_get_new_dbuf_state(state);
+
+	if (!HAS_MBUS_JOINING(i915))
+		return;
+
+	/*
+	 * TODO: Implement vblank synchronized MBUS joining changes.
+	 * Must be properly coordinated with dbuf reprogramming.
+	 */
+	intel_dbuf_mbus_join_update(state);
 
 	if (DISPLAY_VER(i915) >= 20 &&
 	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
-- 
2.43.2

[PATCH 08/13] drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extact the stuff that writes the dbuf/mbus ration stuff
into its own function. Will help with correctly sequencing
the operations done during mbus programming.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 43 ++++++++++++--------
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index f7e03078bd43..7767c5eada36 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3653,6 +3653,30 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
 			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
 }
 
+static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_dbuf_state *old_dbuf_state =
+		intel_atomic_get_old_dbuf_state(state);
+	const struct intel_dbuf_state *new_dbuf_state =
+		intel_atomic_get_new_dbuf_state(state);
+
+	if (DISPLAY_VER(i915) >= 20 &&
+	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
+		/*
+		 * For Xe2LPD and beyond, when there is a change in the ratio
+		 * between MDCLK and CDCLK, updates to related registers need to
+		 * happen at a specific point in the CDCLK change sequence. In
+		 * that case, we defer to the call to
+		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
+		 */
+		return;
+	}
+
+	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
+					    new_dbuf_state->joined_mbus);
+}
+
 static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
@@ -3683,10 +3707,6 @@ static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
 static void update_mbus_pre_enable(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	const struct intel_dbuf_state *old_dbuf_state =
-		intel_atomic_get_old_dbuf_state(state);
-	const struct intel_dbuf_state *new_dbuf_state =
-		intel_atomic_get_new_dbuf_state(state);
 
 	if (!HAS_MBUS_JOINING(i915))
 		return;
@@ -3697,20 +3717,7 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
 	 */
 	intel_dbuf_mbus_join_update(state);
 
-	if (DISPLAY_VER(i915) >= 20 &&
-	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
-		/*
-		 * For Xe2LPD and beyond, when there is a change in the ratio
-		 * between MDCLK and CDCLK, updates to related registers need to
-		 * happen at a specific point in the CDCLK change sequence. In
-		 * that case, we defer to the call to
-		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
-		 */
-		return;
-	}
-
-	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
-					    new_dbuf_state->joined_mbus);
+	intel_dbuf_mdclk_min_tracker_update(state);
 }
 
 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
-- 
2.43.2

[PATCH 09/13] drm/i915: Add debugs for mbus joining and dbuf ratio programming

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add some debugs so that we can actually observe what is
actually happening during the mbus/dbuf programming steps.
We can just shove them into fairly low level functions as
none of them are called during any critical sections/etc.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 7767c5eada36..a118ecf9e532 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3647,6 +3647,9 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
 	if (joined_mbus)
 		ratio *= 2;
 
+	drm_dbg_kms(&i915->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n",
+		    ratio, str_yes_no(joined_mbus));
+
 	for_each_dbuf_slice(i915, slice)
 		intel_de_rmw(i915, DBUF_CTL_S(slice),
 			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
@@ -3680,10 +3683,16 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
 static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_dbuf_state *old_dbuf_state =
+		intel_atomic_get_old_dbuf_state(state);
 	const struct intel_dbuf_state *new_dbuf_state =
 		intel_atomic_get_new_dbuf_state(state);
 	u32 mbus_ctl;
 
+	drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s\n",
+		    str_yes_no(old_dbuf_state->joined_mbus),
+		    str_yes_no(new_dbuf_state->joined_mbus));
+
 	/*
 	 * TODO: Implement vblank synchronized MBUS joining changes.
 	 * Must be properly coordinated with dbuf reprogramming.
-- 
2.43.2

[PATCH 10/13] drm/i915: Use old mbus_join value when increasing CDCLK

[Ville Syrjala]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

In order to make sure we are not breaking the proper sequence
lets to updates step by step and don't change MBUS join value
during MDCLK/CDCLK programming stage.
MBUS join programming would be taken care by pre/post ddb hooks.

v2: - Reworded comment about using old mbus_join value in
      intel_set_cdclk(Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
[v3: vsyrjala: rebase on top of cdclk changes, reword a bit more]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 98546f384023..4024118a7ffb 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2612,6 +2612,12 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 						 old_cdclk_state->actual.voltage_level);
 	}
 
+	/*
+	 * mbus joining will be changed later by
+	 * intel_dbuf_mbus_{pre,post}_ddb_update()
+	 */
+	cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
+
 	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
 
 	intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe,
-- 
2.43.2

[PATCH 11/13] drm/i915: Implement vblank synchronized MBUS join changes

[Ville Syrjala]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Currently we can't change MBUS join status without doing a modeset,
because we are lacking mechanism to synchronize those with vblank.
However then this means that we can't do a fastset, if there is a need
to change MBUS join state. Fix that by implementing such change.
We already call correspondent check and update at pre_plane dbuf update,
so the only thing left is to have a non-modeset version of that.
If active pipes stay the same then fastset is possible and only MBUS
join state/ddb allocation updates would be committed.

The full mbus/cdclk sequence will look as follows:
1. disable pipes
2. increase cdclk if necessary
 2.1 reprogram cdclk
 2.2 update dbuf tracker value
3. enable mbus joining if necessary
 3.1 update mbus_ctl
 3.2 update dbuf tracker value
4. reallocate dbuf for planes on active pipes
5. disable mbus joining if necessary
 5.1 update dbuf tracker value
 5.2 update mbus_ctl
6. enable pipes
7. decrease cdclk if necessary
  7.1 update dbuf tracker value
  7.2 reprogram cdclk

And in order to keep things in sync we need:
Step 2:
- mbus_join == old
- mdclk/cdclk ratio == new
Step 3:
- mbus_join == new
- mdclk/cdclk ratio == old when cdclk is changing in step 7
- mdclk/cdclk ratio == new when cdclk is changing in step 2
Step 5:
- mbus_join == new
- mdclk/cdclk ratio == old when cdclk is changing in step 7
- mdclk/cdclk ratio == new when cdclk is changing in step 2
Step 7:
- mbus_join == new
- mdclk/cdclk ratio == new

v2: - Removed redundant parentheses(Ville Syrjälä)
    - Constified new_crtc_state in intel_mbus_joined_pipe(Ville Syrjälä)
    - Removed pipe_select variable(Ville Syrjälä)
[v3: vsyrjala: Correctly sequence vs. cdclk updates,
               properly describe the full sequence,
	       shuffle code around to make the diff more legible,
	       streamline a few things]

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Co-developed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  11 ++
 drivers/gpu/drm/i915/display/intel_cdclk.h   |   1 +
 drivers/gpu/drm/i915/display/intel_display.c |   5 +-
 drivers/gpu/drm/i915/display/skl_watermark.c | 141 ++++++++++++-------
 drivers/gpu/drm/i915/display/skl_watermark.h |   3 +-
 5 files changed, 112 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4024118a7ffb..66c161d7b485 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2576,6 +2576,17 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 			   update_cdclk, update_pipe_count);
 }
 
+bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
+{
+	const struct intel_cdclk_state *old_cdclk_state =
+		intel_atomic_get_old_cdclk_state(state);
+	const struct intel_cdclk_state *new_cdclk_state =
+		intel_atomic_get_new_cdclk_state(state);
+
+	return new_cdclk_state && !new_cdclk_state->disable_pipes &&
+		new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
+}
+
 /**
  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
  * @state: intel atomic state
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 2843fc091086..5d4faf401774 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -69,6 +69,7 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
 			       const struct intel_cdclk_config *b);
 u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
 			   const struct intel_cdclk_config *cdclk_config);
+bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
 void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
 void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
 void intel_cdclk_dump_config(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4d6668a5f1ab..023cf4a77e6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6915,6 +6915,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 		intel_pre_update_crtc(state, crtc);
 	}
 
+	intel_dbuf_mbus_pre_ddb_update(state);
+
 	while (update_pipes) {
 		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 						    new_crtc_state, i) {
@@ -6945,6 +6947,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 		}
 	}
 
+	intel_dbuf_mbus_post_ddb_update(state);
+
 	update_pipes = modeset_pipes;
 
 	/*
@@ -7191,7 +7195,6 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	intel_encoders_update_prepare(state);
 
 	intel_dbuf_pre_plane_update(state);
-	intel_mbus_dbox_update(state);
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		if (new_crtc_state->do_async_flip)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index a118ecf9e532..ca0f1f89e6d9 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2636,13 +2636,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
 		if (ret)
 			return ret;
 
-		if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
-			/* TODO: Implement vblank synchronized MBUS joining changes */
-			ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
-			if (ret)
-				return ret;
-		}
-
 		drm_dbg_kms(&i915->drm,
 			    "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
 			    old_dbuf_state->enabled_slices,
@@ -3559,7 +3552,7 @@ static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
 	return false;
 }
 
-void intel_mbus_dbox_update(struct intel_atomic_state *state)
+static void intel_mbus_dbox_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
@@ -3640,6 +3633,9 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
 {
 	enum dbuf_slice slice;
 
+	if (!HAS_MBUS_JOINING(i915))
+		return;
+
 	if (DISPLAY_VER(i915) >= 20)
 		intel_de_rmw(i915, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
 			     MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
@@ -3663,24 +3659,42 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
 		intel_atomic_get_old_dbuf_state(state);
 	const struct intel_dbuf_state *new_dbuf_state =
 		intel_atomic_get_new_dbuf_state(state);
+	int mdclk_cdclk_ratio;
 
-	if (DISPLAY_VER(i915) >= 20 &&
-	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
-		/*
-		 * For Xe2LPD and beyond, when there is a change in the ratio
-		 * between MDCLK and CDCLK, updates to related registers need to
-		 * happen at a specific point in the CDCLK change sequence. In
-		 * that case, we defer to the call to
-		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
-		 */
-		return;
+	if (intel_cdclk_is_decreasing_later(state)) {
+		/* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */
+		mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio;
+	} else {
+		/* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */
+		mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio;
 	}
 
-	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
+	intel_dbuf_mdclk_cdclk_ratio_update(i915, mdclk_cdclk_ratio,
 					    new_dbuf_state->joined_mbus);
 }
 
-static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
+static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
+					const struct intel_dbuf_state *dbuf_state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	enum pipe pipe = ffs(dbuf_state->active_pipes) - 1;
+	const struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc *crtc;
+
+	drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);
+	drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes));
+
+	crtc = intel_crtc_for_pipe(i915, pipe);
+	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state))
+		return pipe;
+	else
+		return INVALID_PIPE;
+}
+
+static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state,
+					enum pipe pipe)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	const struct intel_dbuf_state *old_dbuf_state =
@@ -3689,44 +3703,80 @@ static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
 		intel_atomic_get_new_dbuf_state(state);
 	u32 mbus_ctl;
 
-	drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s\n",
+	drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n",
 		    str_yes_no(old_dbuf_state->joined_mbus),
-		    str_yes_no(new_dbuf_state->joined_mbus));
+		    str_yes_no(new_dbuf_state->joined_mbus),
+		    pipe != INVALID_PIPE ? pipe_name(pipe) : '*');
 
-	/*
-	 * TODO: Implement vblank synchronized MBUS joining changes.
-	 * Must be properly coordinated with dbuf reprogramming.
-	 */
 	if (new_dbuf_state->joined_mbus)
-		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
-			MBUS_JOIN_PIPE_SELECT_NONE;
+		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN;
 	else
-		mbus_ctl = MBUS_HASHING_MODE_2x2 |
-			MBUS_JOIN_PIPE_SELECT_NONE;
+		mbus_ctl = MBUS_HASHING_MODE_2x2;
+
+	if (pipe != INVALID_PIPE)
+		mbus_ctl |= MBUS_JOIN_PIPE_SELECT(pipe);
+	else
+		mbus_ctl |= MBUS_JOIN_PIPE_SELECT_NONE;
 
 	intel_de_rmw(i915, MBUS_CTL,
 		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
 		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
 }
 
-/*
- * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
- * update the request state of all DBUS slices.
- */
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state)
+{
+	const struct intel_dbuf_state *new_dbuf_state =
+		intel_atomic_get_new_dbuf_state(state);
+	const struct intel_dbuf_state *old_dbuf_state =
+		intel_atomic_get_old_dbuf_state(state);
+
+	if (!new_dbuf_state)
+		return;
+
+	if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
+		enum pipe pipe = intel_mbus_joined_pipe(state, new_dbuf_state);
+
+		WARN_ON(!new_dbuf_state->base.changed);
+
+		intel_dbuf_mbus_join_update(state, pipe);
+		intel_mbus_dbox_update(state);
+		intel_dbuf_mdclk_min_tracker_update(state);
+	}
+}
+
+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_dbuf_state *new_dbuf_state =
+		intel_atomic_get_new_dbuf_state(state);
+	const struct intel_dbuf_state *old_dbuf_state =
+		intel_atomic_get_old_dbuf_state(state);
 
-	if (!HAS_MBUS_JOINING(i915))
+	if (!new_dbuf_state)
 		return;
 
-	/*
-	 * TODO: Implement vblank synchronized MBUS joining changes.
-	 * Must be properly coordinated with dbuf reprogramming.
-	 */
-	intel_dbuf_mbus_join_update(state);
+	if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
+		enum pipe pipe = intel_mbus_joined_pipe(state, old_dbuf_state);
+
+		WARN_ON(!new_dbuf_state->base.changed);
+
+		intel_dbuf_mdclk_min_tracker_update(state);
+		intel_mbus_dbox_update(state);
+		intel_dbuf_mbus_join_update(state, pipe);
+
+		if (pipe != INVALID_PIPE) {
+			struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);
+
+			intel_crtc_wait_for_next_vblank(crtc);
+		}
+	} else if (old_dbuf_state->joined_mbus == new_dbuf_state->joined_mbus &&
+		   old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) {
+		WARN_ON(!new_dbuf_state->base.changed);
+
+		intel_dbuf_mdclk_min_tracker_update(state);
+		intel_mbus_dbox_update(state);
+	}
 
-	intel_dbuf_mdclk_min_tracker_update(state);
 }
 
 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
@@ -3738,13 +3788,11 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_dbuf_state(state);
 
 	if (!new_dbuf_state ||
-	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
-	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+	    new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
 		return;
 
 	WARN_ON(!new_dbuf_state->base.changed);
 
-	update_mbus_pre_enable(state);
 	gen9_dbuf_slices_update(i915,
 				old_dbuf_state->enabled_slices |
 				new_dbuf_state->enabled_slices);
@@ -3759,8 +3807,7 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_dbuf_state(state);
 
 	if (!new_dbuf_state ||
-	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
-	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+	    new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
 		return;
 
 	WARN_ON(!new_dbuf_state->base.changed);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index bf7516620ab6..3323a1d973f9 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -79,7 +79,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
 void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
 void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
-void intel_mbus_dbox_update(struct intel_atomic_state *state);
+void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
 
 #endif /* __SKL_WATERMARK_H__ */
 
-- 
2.43.2

[PATCH 12/13] drm/i915: Use a plain old int for the cdclk/mdclk ratio

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No point in throwing around u8 when we're dealing with
just an integer. Use a plain old boring 'int'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c   | 6 +++---
 drivers/gpu/drm/i915/display/intel_cdclk.h   | 4 ++--
 drivers/gpu/drm/i915/display/skl_watermark.c | 6 ++++--
 drivers/gpu/drm/i915/display/skl_watermark.h | 6 ++++--
 4 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 66c161d7b485..5cba0d08189b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1893,8 +1893,8 @@ static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
 	return MDCLK_SOURCE_SEL_CD2XCLK;
 }
 
-u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
-			   const struct intel_cdclk_config *cdclk_config)
+int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+			    const struct intel_cdclk_config *cdclk_config)
 {
 	if (mdclk_source_is_cdclk_pll(i915))
 		return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
@@ -3321,7 +3321,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 
 	if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
 	    intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
-		u8 ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
+		int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
 
 		ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
 		if (ret)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 5d4faf401774..cfdcdec07a4d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -67,8 +67,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
 u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
 			       const struct intel_cdclk_config *b);
-u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
-			   const struct intel_cdclk_config *cdclk_config);
+int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+			    const struct intel_cdclk_config *cdclk_config);
 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
 void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
 void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index ca0f1f89e6d9..1b48009efe2b 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3616,7 +3616,8 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state)
 	}
 }
 
-int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio)
+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
+					   int ratio)
 {
 	struct intel_dbuf_state *dbuf_state;
 
@@ -3629,7 +3630,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
 	return intel_atomic_lock_global_state(&dbuf_state->base);
 }
 
-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus)
+void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
+					 int ratio, bool joined_mbus)
 {
 	enum dbuf_slice slice;
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 3323a1d973f9..ef1a008466be 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -74,11 +74,13 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
 	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
 
 int intel_dbuf_init(struct drm_i915_private *i915);
-int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio);
+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
+					   int ratio);
 
 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
 void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
+void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
+					 int ratio, bool joined_mbus);
 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
 
-- 
2.43.2

[PATCH 13/13] drm/i915: Optimize out redundant dbuf slice updates

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

if the new dbuf slices are a superset of the old
dbuf slices then we don't have to do anything in
intel_dbuf_post_plane_update(). Restructure the code
to skip such redundant dbuf slice updates. The main
benefit is slightly less confusing logs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 27 +++++++++++++-------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1b48009efe2b..50ec51065118 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3788,16 +3788,20 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_new_dbuf_state(state);
 	const struct intel_dbuf_state *old_dbuf_state =
 		intel_atomic_get_old_dbuf_state(state);
+	u8 old_slices, new_slices;
 
-	if (!new_dbuf_state ||
-	    new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
+	if (!new_dbuf_state)
+		return;
+
+	old_slices = old_dbuf_state->enabled_slices;
+	new_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices;
+
+	if (old_slices == new_slices)
 		return;
 
 	WARN_ON(!new_dbuf_state->base.changed);
 
-	gen9_dbuf_slices_update(i915,
-				old_dbuf_state->enabled_slices |
-				new_dbuf_state->enabled_slices);
+	gen9_dbuf_slices_update(i915, new_slices);
 }
 
 void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
@@ -3807,15 +3811,20 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_new_dbuf_state(state);
 	const struct intel_dbuf_state *old_dbuf_state =
 		intel_atomic_get_old_dbuf_state(state);
+	u8 old_slices, new_slices;
 
-	if (!new_dbuf_state ||
-	    new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
+	if (!new_dbuf_state)
+		return;
+
+	old_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices;
+	new_slices = new_dbuf_state->enabled_slices;
+
+	if (old_slices == new_slices)
 		return;
 
 	WARN_ON(!new_dbuf_state->base.changed);
 
-	gen9_dbuf_slices_update(i915,
-				new_dbuf_state->enabled_slices);
+	gen9_dbuf_slices_update(i915, new_slices);
 }
 
 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
-- 
2.43.2

✗ Fi.CI.SPARSE: warning for drm/i915: Implemnt vblank sycnhronized mbus joining changes

[Patchwork]

== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes
URL   : https://patchwork.freedesktop.org/series/131700/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

RE: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active

[Murthy, Arun R]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when
> pipes are active
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we always reprogram CDCLK from the
> intel_set_cdclk_pre_plane_update() when using squahs/crawl.
Typo squashs->squash

> The code only works correctly for the cd2x update or full modeset cases, and it
> was simply never updated to deal with squash/crawl.
> 
> If the CDCLK frequency is increasing we must reprogram it before we do
> anything else that might depend on the new higher frequency, and conversely
> we must not decrease the frequency until everything that might still depend on
> the old higher frequency has been dealt with.
> 
> Since cdclk_state->pipe is only relevant when doing a cd2x update we can't use
> it to determine the correct sequence during squash/crawl. To that end
> introduce cdclk_state->disable_pipes which simply indicates that we must
> perform the update while the pipes are disable (ie. during
> intel_set_cdclk_pre_plane_update()). Otherwise we use the same old vs. new
> CDCLK frequency comparsiong as for cd2x updates.
> 
> The only remaining problem case is when the voltage_level needs to increase
> due to a DDI port, but the CDCLK frequency is decreasing (and not all pipes are
> being disabled). The current approach will not bump the voltage level up until
> after the port has already been enabled, which is too late.
> But we'll take care of that case separately.
> 
> v2: Don't break the "must disable pipes case"
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++++++------
> drivers/gpu/drm/i915/display/intel_cdclk.h |  3 +++
>  2 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 31aaa9780dfc..619529dba095 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2600,7 +2600,6 @@ intel_set_cdclk_pre_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_old_cdclk_state(state);
>  	const struct intel_cdclk_state *new_cdclk_state =
>  		intel_atomic_get_new_cdclk_state(state);
> -	enum pipe pipe = new_cdclk_state->pipe;
Looks like this cdclk_state->pipe is not more used in the driver and can it be removed?

Thanks and Regards,
Arun R Murthy
--------------------
> 
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
>  				 &new_cdclk_state->actual))
> @@ -2609,11 +2608,12 @@ intel_set_cdclk_pre_plane_update(struct
> intel_atomic_state *state)
>  	if (IS_DG2(i915))
>  		intel_cdclk_pcode_pre_notify(state);
> 
> -	if (pipe == INVALID_PIPE ||
> +	if (new_cdclk_state->disable_pipes ||
>  	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
>  		drm_WARN_ON(&i915->drm, !new_cdclk_state-
> >base.changed);
> 
> -		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
> +		intel_set_cdclk(i915, &new_cdclk_state->actual,
> +				new_cdclk_state->pipe);
>  	}
>  }
> 
> @@ -2632,7 +2632,6 @@ intel_set_cdclk_post_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_old_cdclk_state(state);
>  	const struct intel_cdclk_state *new_cdclk_state =
>  		intel_atomic_get_new_cdclk_state(state);
> -	enum pipe pipe = new_cdclk_state->pipe;
> 
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
>  				 &new_cdclk_state->actual))
> @@ -2641,11 +2640,12 @@ intel_set_cdclk_post_plane_update(struct
> intel_atomic_state *state)
>  	if (IS_DG2(i915))
>  		intel_cdclk_pcode_post_notify(state);
> 
> -	if (pipe != INVALID_PIPE &&
> +	if (!new_cdclk_state->disable_pipes &&
>  	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
>  		drm_WARN_ON(&i915->drm, !new_cdclk_state-
> >base.changed);
> 
> -		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
> +		intel_set_cdclk(i915, &new_cdclk_state->actual,
> +				new_cdclk_state->pipe);
>  	}
>  }
> 
> @@ -3124,6 +3124,7 @@ static struct intel_global_state
> *intel_cdclk_duplicate_state(struct intel_globa
>  		return NULL;
> 
>  	cdclk_state->pipe = INVALID_PIPE;
> +	cdclk_state->disable_pipes = false;
> 
>  	return &cdclk_state->base;
>  }
> @@ -3316,6 +3317,8 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>  		if (ret)
>  			return ret;
> 
> +		new_cdclk_state->disable_pipes = true;
> +
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Modeset required for cdclk change\n");
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index bc8f86e292d8..2843fc091086 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -53,6 +53,9 @@ struct intel_cdclk_state {
> 
>  	/* bitmask of active pipes */
>  	u8 active_pipes;
> +
> +	/* update cdclk with pipes disabled */
> +	bool disable_pipes;
>  };
> 
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> --
> 2.43.2

RE: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when
> pipes are active
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we always reprogram CDCLK from the
> intel_set_cdclk_pre_plane_update() when using squahs/crawl.

Nitpick: Typo in squash

Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> The code only works correctly for the cd2x update or full modeset cases, and it
> was simply never updated to deal with squash/crawl.
> 
> If the CDCLK frequency is increasing we must reprogram it before we do anything
> else that might depend on the new higher frequency, and conversely we must not
> decrease the frequency until everything that might still depend on the old higher
> frequency has been dealt with.
> 
> Since cdclk_state->pipe is only relevant when doing a cd2x update we can't use it
> to determine the correct sequence during squash/crawl. To that end introduce
> cdclk_state->disable_pipes which simply indicates that we must perform the
> update while the pipes are disable (ie. during
> intel_set_cdclk_pre_plane_update()). Otherwise we use the same old vs. new
> CDCLK frequency comparsiong as for cd2x updates.
> 
> The only remaining problem case is when the voltage_level needs to increase due
> to a DDI port, but the CDCLK frequency is decreasing (and not all pipes are being
> disabled). The current approach will not bump the voltage level up until after the
> port has already been enabled, which is too late.
> But we'll take care of that case separately.
> 
> v2: Don't break the "must disable pipes case"
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++++++------
> drivers/gpu/drm/i915/display/intel_cdclk.h |  3 +++
>  2 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 31aaa9780dfc..619529dba095 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2600,7 +2600,6 @@ intel_set_cdclk_pre_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_old_cdclk_state(state);
>  	const struct intel_cdclk_state *new_cdclk_state =
>  		intel_atomic_get_new_cdclk_state(state);
> -	enum pipe pipe = new_cdclk_state->pipe;
> 
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
>  				 &new_cdclk_state->actual))
> @@ -2609,11 +2608,12 @@ intel_set_cdclk_pre_plane_update(struct
> intel_atomic_state *state)
>  	if (IS_DG2(i915))
>  		intel_cdclk_pcode_pre_notify(state);
> 
> -	if (pipe == INVALID_PIPE ||
> +	if (new_cdclk_state->disable_pipes ||
>  	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
>  		drm_WARN_ON(&i915->drm, !new_cdclk_state-
> >base.changed);
> 
> -		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
> +		intel_set_cdclk(i915, &new_cdclk_state->actual,
> +				new_cdclk_state->pipe);
>  	}
>  }
> 
> @@ -2632,7 +2632,6 @@ intel_set_cdclk_post_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_old_cdclk_state(state);
>  	const struct intel_cdclk_state *new_cdclk_state =
>  		intel_atomic_get_new_cdclk_state(state);
> -	enum pipe pipe = new_cdclk_state->pipe;
> 
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
>  				 &new_cdclk_state->actual))
> @@ -2641,11 +2640,12 @@ intel_set_cdclk_post_plane_update(struct
> intel_atomic_state *state)
>  	if (IS_DG2(i915))
>  		intel_cdclk_pcode_post_notify(state);
> 
> -	if (pipe != INVALID_PIPE &&
> +	if (!new_cdclk_state->disable_pipes &&
>  	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
>  		drm_WARN_ON(&i915->drm, !new_cdclk_state-
> >base.changed);
> 
> -		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
> +		intel_set_cdclk(i915, &new_cdclk_state->actual,
> +				new_cdclk_state->pipe);
>  	}
>  }
> 
> @@ -3124,6 +3124,7 @@ static struct intel_global_state
> *intel_cdclk_duplicate_state(struct intel_globa
>  		return NULL;
> 
>  	cdclk_state->pipe = INVALID_PIPE;
> +	cdclk_state->disable_pipes = false;
> 
>  	return &cdclk_state->base;
>  }
> @@ -3316,6 +3317,8 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>  		if (ret)
>  			return ret;
> 
> +		new_cdclk_state->disable_pipes = true;
> +
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Modeset required for cdclk change\n");
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index bc8f86e292d8..2843fc091086 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -53,6 +53,9 @@ struct intel_cdclk_state {
> 
>  	/* bitmask of active pipes */
>  	u8 active_pipes;
> +
> +	/* update cdclk with pipes disabled */
> +	bool disable_pipes;
>  };
> 
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> --
> 2.43.2

RE: [PATCH 02/13] drm/i915/cdclk: Fix voltage_level programming edge case

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 02/13] drm/i915/cdclk: Fix voltage_level programming edge case
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we only consider the relationship of the old and new CDCLK frequencies
> when determining whether to do the repgramming from
> intel_set_cdclk_pre_plane_update()
> or intel_set_cdclk_post_plane_update().
> 
> It is technically possible to have a situation where the CDCLK frequency is
> decreasing, but the voltage_level is increasing due a DDI port. In this case we
> should bump the voltage level already in intel_set_cdclk_pre_plane_update()
> (so that the voltage_level will have been increased by the time the port gets
> enabled), while leaving the CDCLK frequency unchanged (as active planes/etc.
> may still depend on it).
> We can then reduce the CDCLK frequency to its final value from
> intel_set_cdclk_post_plane_update().
> 
> In order to handle that correctly we shall construct a suitable amalgam of the old
> and new cdclk states in intel_set_cdclk_pre_plane_update().
> 
> And we can simply call intel_set_cdclk() unconditionally in both places as it will
> not do anything if nothing actually changes vs. the current hw state.
> 
> v2: Handle cdclk_state->disable_pipes

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 27 +++++++++++++---------
>  1 file changed, 16 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 619529dba095..504c5cbbcfff 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2600,6 +2600,7 @@ intel_set_cdclk_pre_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_old_cdclk_state(state);
>  	const struct intel_cdclk_state *new_cdclk_state =
>  		intel_atomic_get_new_cdclk_state(state);
> +	struct intel_cdclk_config cdclk_config;
> 
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
>  				 &new_cdclk_state->actual))
> @@ -2608,13 +2609,21 @@ intel_set_cdclk_pre_plane_update(struct
> intel_atomic_state *state)
>  	if (IS_DG2(i915))
>  		intel_cdclk_pcode_pre_notify(state);
> 
> -	if (new_cdclk_state->disable_pipes ||
> -	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
> -		drm_WARN_ON(&i915->drm, !new_cdclk_state-
> >base.changed);
> +	if (new_cdclk_state->disable_pipes) {
> +		cdclk_config = new_cdclk_state->actual;
> +	} else {
> +		if (new_cdclk_state->actual.cdclk >= old_cdclk_state-
> >actual.cdclk)
> +			cdclk_config = new_cdclk_state->actual;
> +		else
> +			cdclk_config = old_cdclk_state->actual;
> 
> -		intel_set_cdclk(i915, &new_cdclk_state->actual,
> -				new_cdclk_state->pipe);
> +		cdclk_config.voltage_level = max(new_cdclk_state-
> >actual.voltage_level,
> +						 old_cdclk_state-
> >actual.voltage_level);
>  	}
> +
> +	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> +
> +	intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe);
>  }
> 
>  /**
> @@ -2640,13 +2649,9 @@ intel_set_cdclk_post_plane_update(struct
> intel_atomic_state *state)
>  	if (IS_DG2(i915))
>  		intel_cdclk_pcode_post_notify(state);
> 
> -	if (!new_cdclk_state->disable_pipes &&
> -	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
> -		drm_WARN_ON(&i915->drm, !new_cdclk_state-
> >base.changed);
> +	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
> -		intel_set_cdclk(i915, &new_cdclk_state->actual,
> -				new_cdclk_state->pipe);
> -	}
> +	intel_set_cdclk(i915, &new_cdclk_state->actual,
> +new_cdclk_state->pipe);
>  }
> 
>  static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> --
> 2.43.2

RE: [PATCH 03/13] drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 03/13] drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> No ever figured out why bumping the cdclk helped with whatever issue we were
> having at the time.
> Remove the hacks and start from scratch so that we can actually see if any
> problems still remain.

Yeah, there can be cases where bumping the clock can help avoid the latency
and suppress an issue. However, this is not recommended by hardware and we
should be able to drive the display as per the calculated clock based on pixel rate.
Having said that, we should brace ourselves for the issues which it was fixing.

Ok to drop the hack,
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 19 -------------------
>  1 file changed, 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 504c5cbbcfff..99d2657f29a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2802,25 +2802,6 @@ int intel_crtc_compute_min_cdclk(const struct
> intel_crtc_state *crtc_state)
>  	if (crtc_state->dsc.compression_enable)
>  		min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
> 
> -	/*
> -	 * HACK. Currently for TGL/DG2 platforms we calculate
> -	 * min_cdclk initially based on pixel_rate divided
> -	 * by 2, accounting for also plane requirements,
> -	 * however in some cases the lowest possible CDCLK
> -	 * doesn't work and causing the underruns.
> -	 * Explicitly stating here that this seems to be currently
> -	 * rather a Hack, than final solution.
> -	 */
> -	if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {
> -		/*
> -		 * Clamp to max_cdclk_freq in case pixel rate is higher,
> -		 * in order not to break an 8K, but still leave W/A at place.
> -		 */
> -		min_cdclk = max_t(int, min_cdclk,
> -				  min_t(int, crtc_state->pixel_rate,
> -					dev_priv-
> >display.cdclk.max_cdclk_freq));
> -	}
> -
>  	return min_cdclk;
>  }
> 
> --
> 2.43.2

RE: [PATCH 04/13] drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plane update

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 04/13] drm/i915/cdclk: Indicate whether CDCLK change happens
> during pre or post plane update
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we just get a plain "Changing CDCLK to ..." in the logs. It would actually
> be interesting to see whether we're doing the programming during the pre or post
> plane phase of the commit. Include that information in the debug message.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++++-------------
>  1 file changed, 6 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 99d2657f29a7..98546f384023 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2434,18 +2434,9 @@ static void intel_pcode_notify(struct
> drm_i915_private *i915,
>  			ret);
>  }
> 
> -/**
> - * intel_set_cdclk - Push the CDCLK configuration to the hardware
> - * @dev_priv: i915 device
> - * @cdclk_config: new CDCLK configuration
> - * @pipe: pipe with which to synchronize the update
> - *
> - * Program the hardware based on the passed in CDCLK state,
> - * if necessary.
> - */
>  static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>  			    const struct intel_cdclk_config *cdclk_config,
> -			    enum pipe pipe)
> +			    enum pipe pipe, const char *context)
>  {
>  	struct intel_encoder *encoder;
> 
> @@ -2455,7 +2446,7 @@ static void intel_set_cdclk(struct drm_i915_private
> *dev_priv,
>  	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv-
> >display.funcs.cdclk->set_cdclk))
>  		return;
> 
> -	intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
> +	intel_cdclk_dump_config(dev_priv, cdclk_config, context);
> 
>  	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -
> 2623,7 +2614,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state
> *state)
> 
>  	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
> -	intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe);
> +	intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe,
> +			"Pre changing CDCLK to");
>  }
> 
>  /**
> @@ -2651,7 +2643,8 @@ intel_set_cdclk_post_plane_update(struct
> intel_atomic_state *state)
> 
>  	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
> -	intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state-
> >pipe);
> +	intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe,
> +			"Post changing CDCLK to");
>  }
> 
>  static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> --
> 2.43.2

RE: [PATCH 05/13] drm/i915: Loop over all active pipes in intel_mbus_dbox_update

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 05/13] drm/i915: Loop over all active pipes in
> intel_mbus_dbox_update
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> We need to loop through all active pipes, not just the ones, that are in current
> state, because disabling and enabling even a particular pipe affects credits in
> another one.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index bc341abcab2f..f582992592c1 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3680,10 +3680,8 @@ void intel_mbus_dbox_update(struct
> intel_atomic_state *state)  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> -	const struct intel_crtc_state *new_crtc_state;
>  	const struct intel_crtc *crtc;
>  	u32 val = 0;
> -	int i;
> 
>  	if (DISPLAY_VER(i915) < 11)
>  		return;
> @@ -3727,12 +3725,9 @@ void intel_mbus_dbox_update(struct
> intel_atomic_state *state)
>  		val |= MBUS_DBOX_B_CREDIT(8);
>  	}
> 
> -	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,
> +new_dbuf_state->active_pipes) {
>  		u32 pipe_val = val;
> 
> -		if (!new_crtc_state->hw.active)
> -			continue;
> -
>  		if (DISPLAY_VER(i915) >= 14) {
>  			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
>  							      new_dbuf_state-
> >active_pipes))
> --
> 2.43.2

RE: [PATCH 06/13] drm/i915: Relocate intel_mbus_dbox_update()

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 06/13] drm/i915: Relocate intel_mbus_dbox_update()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_mbus_dbox_update() will become static soon. Relocate it into a place that
> avoids having to add a forward declaration for it.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 166 +++++++++----------
>  1 file changed, 83 insertions(+), 83 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index f582992592c1..6bd3fec0aa56 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3540,6 +3540,89 @@ int intel_dbuf_init(struct drm_i915_private *i915)
>  	return 0;
>  }
> 
> +static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8
> +active_pipes) {
> +	switch (pipe) {
> +	case PIPE_A:
> +		return !(active_pipes & BIT(PIPE_D));
> +	case PIPE_D:
> +		return !(active_pipes & BIT(PIPE_A));
> +	case PIPE_B:
> +		return !(active_pipes & BIT(PIPE_C));
> +	case PIPE_C:
> +		return !(active_pipes & BIT(PIPE_B));
> +	default: /* to suppress compiler warning */
> +		MISSING_CASE(pipe);
> +		break;
> +	}
> +
> +	return false;
> +}
> +
> +void intel_mbus_dbox_update(struct intel_atomic_state *state) {
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> +	const struct intel_crtc *crtc;
> +	u32 val = 0;
> +
> +	if (DISPLAY_VER(i915) < 11)
> +		return;
> +
> +	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> +	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> +	if (!new_dbuf_state ||
> +	    (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> +	     new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
> +		return;
> +
> +	if (DISPLAY_VER(i915) >= 14)
> +		val |= MBUS_DBOX_I_CREDIT(2);
> +
> +	if (DISPLAY_VER(i915) >= 12) {
> +		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> +		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> +		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> +	}
> +
> +	if (DISPLAY_VER(i915) >= 14)
> +		val |= new_dbuf_state->joined_mbus ?
> MBUS_DBOX_A_CREDIT(12) :
> +						     MBUS_DBOX_A_CREDIT(8);
> +	else if (IS_ALDERLAKE_P(i915))
> +		/* Wa_22010947358:adl-p */
> +		val |= new_dbuf_state->joined_mbus ?
> MBUS_DBOX_A_CREDIT(6) :
> +						     MBUS_DBOX_A_CREDIT(4);
> +	else
> +		val |= MBUS_DBOX_A_CREDIT(2);
> +
> +	if (DISPLAY_VER(i915) >= 14) {
> +		val |= MBUS_DBOX_B_CREDIT(0xA);
> +	} else if (IS_ALDERLAKE_P(i915)) {
> +		val |= MBUS_DBOX_BW_CREDIT(2);
> +		val |= MBUS_DBOX_B_CREDIT(8);
> +	} else if (DISPLAY_VER(i915) >= 12) {
> +		val |= MBUS_DBOX_BW_CREDIT(2);
> +		val |= MBUS_DBOX_B_CREDIT(12);
> +	} else {
> +		val |= MBUS_DBOX_BW_CREDIT(1);
> +		val |= MBUS_DBOX_B_CREDIT(8);
> +	}
> +
> +	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state-
> >active_pipes) {
> +		u32 pipe_val = val;
> +
> +		if (DISPLAY_VER(i915) >= 14) {
> +			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
> +							      new_dbuf_state-
> >active_pipes))
> +				pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
> +			else
> +				pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
> +		}
> +
> +		intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe),
> pipe_val);
> +	}
> +}
> +
>  int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
> ratio)  {
>  	struct intel_dbuf_state *dbuf_state;
> @@ -3657,89 +3740,6 @@ void intel_dbuf_post_plane_update(struct
> intel_atomic_state *state)
>  				new_dbuf_state->enabled_slices);
>  }
> 
> -static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8
> active_pipes) -{
> -	switch (pipe) {
> -	case PIPE_A:
> -		return !(active_pipes & BIT(PIPE_D));
> -	case PIPE_D:
> -		return !(active_pipes & BIT(PIPE_A));
> -	case PIPE_B:
> -		return !(active_pipes & BIT(PIPE_C));
> -	case PIPE_C:
> -		return !(active_pipes & BIT(PIPE_B));
> -	default: /* to suppress compiler warning */
> -		MISSING_CASE(pipe);
> -		break;
> -	}
> -
> -	return false;
> -}
> -
> -void intel_mbus_dbox_update(struct intel_atomic_state *state) -{
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> -	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> -	const struct intel_crtc *crtc;
> -	u32 val = 0;
> -
> -	if (DISPLAY_VER(i915) < 11)
> -		return;
> -
> -	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> -	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> -	if (!new_dbuf_state ||
> -	    (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> -	     new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
> -		return;
> -
> -	if (DISPLAY_VER(i915) >= 14)
> -		val |= MBUS_DBOX_I_CREDIT(2);
> -
> -	if (DISPLAY_VER(i915) >= 12) {
> -		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> -		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> -		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> -	}
> -
> -	if (DISPLAY_VER(i915) >= 14)
> -		val |= new_dbuf_state->joined_mbus ?
> MBUS_DBOX_A_CREDIT(12) :
> -						     MBUS_DBOX_A_CREDIT(8);
> -	else if (IS_ALDERLAKE_P(i915))
> -		/* Wa_22010947358:adl-p */
> -		val |= new_dbuf_state->joined_mbus ?
> MBUS_DBOX_A_CREDIT(6) :
> -						     MBUS_DBOX_A_CREDIT(4);
> -	else
> -		val |= MBUS_DBOX_A_CREDIT(2);
> -
> -	if (DISPLAY_VER(i915) >= 14) {
> -		val |= MBUS_DBOX_B_CREDIT(0xA);
> -	} else if (IS_ALDERLAKE_P(i915)) {
> -		val |= MBUS_DBOX_BW_CREDIT(2);
> -		val |= MBUS_DBOX_B_CREDIT(8);
> -	} else if (DISPLAY_VER(i915) >= 12) {
> -		val |= MBUS_DBOX_BW_CREDIT(2);
> -		val |= MBUS_DBOX_B_CREDIT(12);
> -	} else {
> -		val |= MBUS_DBOX_BW_CREDIT(1);
> -		val |= MBUS_DBOX_B_CREDIT(8);
> -	}
> -
> -	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state-
> >active_pipes) {
> -		u32 pipe_val = val;
> -
> -		if (DISPLAY_VER(i915) >= 14) {
> -			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
> -							      new_dbuf_state-
> >active_pipes))
> -				pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
> -			else
> -				pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
> -		}
> -
> -		intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe),
> pipe_val);
> -	}
> -}
> -
>  static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)  {
>  	struct drm_i915_private *i915 = m->private;
> --
> 2.43.2

RE: [PATCH 07/13] drm/i915: Extract intel_dbuf_mbus_join_update()

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 07/13] drm/i915: Extract intel_dbuf_mbus_join_update()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extact the stuff that writes the joining bits in MBUS_CTL into its own function.
> Will help with correctly sequencing the operations done during mbus
> programming.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 37 +++++++++++++-------
>  1 file changed, 25 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 6bd3fec0aa56..f7e03078bd43 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3653,21 +3653,12 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct
> drm_i915_private *i915, u8 ratio
>  			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));  }
> 
> -/*
> - * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
> before
> - * update the request state of all DBUS slices.
> - */
> -static void update_mbus_pre_enable(struct intel_atomic_state *state)
> +static void intel_dbuf_mbus_join_update(struct intel_atomic_state
> +*state)
>  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_dbuf_state *new_dbuf_state =
> +		intel_atomic_get_new_dbuf_state(state);
>  	u32 mbus_ctl;
> -	const struct intel_dbuf_state *old_dbuf_state =
> -		intel_atomic_get_old_dbuf_state(state);
> -	const struct intel_dbuf_state *new_dbuf_state =
> -		intel_atomic_get_new_dbuf_state(state);
> -
> -	if (!HAS_MBUS_JOINING(i915))
> -		return;
> 
>  	/*
>  	 * TODO: Implement vblank synchronized MBUS joining changes.
> @@ -3683,6 +3674,28 @@ static void update_mbus_pre_enable(struct
> intel_atomic_state *state)
>  	intel_de_rmw(i915, MBUS_CTL,
>  		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
>  		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
> +}
> +
> +/*
> + * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus
> +state before
> + * update the request state of all DBUS slices.
> + */
> +static void update_mbus_pre_enable(struct intel_atomic_state *state) {
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_dbuf_state *old_dbuf_state =
> +		intel_atomic_get_old_dbuf_state(state);
> +	const struct intel_dbuf_state *new_dbuf_state =
> +		intel_atomic_get_new_dbuf_state(state);
> +
> +	if (!HAS_MBUS_JOINING(i915))
> +		return;
> +
> +	/*
> +	 * TODO: Implement vblank synchronized MBUS joining changes.
> +	 * Must be properly coordinated with dbuf reprogramming.
> +	 */
> +	intel_dbuf_mbus_join_update(state);
> 
>  	if (DISPLAY_VER(i915) >= 20 &&
>  	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state-
> >mdclk_cdclk_ratio) {
> --
> 2.43.2

RE: [PATCH 08/13] drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 08/13] drm/i915: Extract
> intel_dbuf_mdclk_min_tracker_update()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extact the stuff that writes the dbuf/mbus ration stuff into its own function. Will

Nit: Typo in extract and ratio

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> help with correctly sequencing the operations done during mbus programming.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 43 ++++++++++++--------
>  1 file changed, 25 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index f7e03078bd43..7767c5eada36 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3653,6 +3653,30 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct
> drm_i915_private *i915, u8 ratio
>  			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));  }
> 
> +static void intel_dbuf_mdclk_min_tracker_update(struct
> +intel_atomic_state *state) {
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_dbuf_state *old_dbuf_state =
> +		intel_atomic_get_old_dbuf_state(state);
> +	const struct intel_dbuf_state *new_dbuf_state =
> +		intel_atomic_get_new_dbuf_state(state);
> +
> +	if (DISPLAY_VER(i915) >= 20 &&
> +	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state-
> >mdclk_cdclk_ratio) {
> +		/*
> +		 * For Xe2LPD and beyond, when there is a change in the ratio
> +		 * between MDCLK and CDCLK, updates to related registers need
> to
> +		 * happen at a specific point in the CDCLK change sequence. In
> +		 * that case, we defer to the call to
> +		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
> +		 */
> +		return;
> +	}
> +
> +	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state-
> >mdclk_cdclk_ratio,
> +					    new_dbuf_state->joined_mbus);
> +}
> +
>  static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev); @@ -3683,10
> +3707,6 @@ static void intel_dbuf_mbus_join_update(struct intel_atomic_state
> *state)  static void update_mbus_pre_enable(struct intel_atomic_state *state)  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
> -	const struct intel_dbuf_state *old_dbuf_state =
> -		intel_atomic_get_old_dbuf_state(state);
> -	const struct intel_dbuf_state *new_dbuf_state =
> -		intel_atomic_get_new_dbuf_state(state);
> 
>  	if (!HAS_MBUS_JOINING(i915))
>  		return;
> @@ -3697,20 +3717,7 @@ static void update_mbus_pre_enable(struct
> intel_atomic_state *state)
>  	 */
>  	intel_dbuf_mbus_join_update(state);
> 
> -	if (DISPLAY_VER(i915) >= 20 &&
> -	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state-
> >mdclk_cdclk_ratio) {
> -		/*
> -		 * For Xe2LPD and beyond, when there is a change in the ratio
> -		 * between MDCLK and CDCLK, updates to related registers need
> to
> -		 * happen at a specific point in the CDCLK change sequence. In
> -		 * that case, we defer to the call to
> -		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
> -		 */
> -		return;
> -	}
> -
> -	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state-
> >mdclk_cdclk_ratio,
> -					    new_dbuf_state->joined_mbus);
> +	intel_dbuf_mdclk_min_tracker_update(state);
>  }
> 
>  void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> --
> 2.43.2

RE: [PATCH 09/13] drm/i915: Add debugs for mbus joining and dbuf ratio programming

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 09/13] drm/i915: Add debugs for mbus joining and dbuf ratio
> programming

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add some debugs so that we can actually observe what is actually happening
> during the mbus/dbuf programming steps.
> We can just shove them into fairly low level functions as none of them are called
> during any critical sections/etc.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 7767c5eada36..a118ecf9e532 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3647,6 +3647,9 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct
> drm_i915_private *i915, u8 ratio
>  	if (joined_mbus)
>  		ratio *= 2;
> 
> +	drm_dbg_kms(&i915->drm, "Updating dbuf ratio to %d (mbus joined:
> %s)\n",
> +		    ratio, str_yes_no(joined_mbus));
> +
>  	for_each_dbuf_slice(i915, slice)
>  		intel_de_rmw(i915, DBUF_CTL_S(slice),
>  			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> @@ -3680,10 +3683,16 @@ static void
> intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state  static
> void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_dbuf_state *old_dbuf_state =
> +		intel_atomic_get_old_dbuf_state(state);
>  	const struct intel_dbuf_state *new_dbuf_state =
>  		intel_atomic_get_new_dbuf_state(state);
>  	u32 mbus_ctl;
> 
> +	drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s\n",
> +		    str_yes_no(old_dbuf_state->joined_mbus),
> +		    str_yes_no(new_dbuf_state->joined_mbus));
> +
>  	/*
>  	 * TODO: Implement vblank synchronized MBUS joining changes.
>  	 * Must be properly coordinated with dbuf reprogramming.
> --
> 2.43.2

RE: [PATCH 10/13] drm/i915: Use old mbus_join value when increasing CDCLK

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 10/13] drm/i915: Use old mbus_join value when increasing
> CDCLK
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> In order to make sure we are not breaking the proper sequence lets to updates

Nit: %s/lets to/lets do

> step by step and don't change MBUS join value during MDCLK/CDCLK
> programming stage.
> MBUS join programming would be taken care by pre/post ddb hooks.
> 
> v2: - Reworded comment about using old mbus_join value in
>       intel_set_cdclk(Ville Syrjälä)

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> [v3: vsyrjala: rebase on top of cdclk changes, reword a bit more]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 98546f384023..4024118a7ffb 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2612,6 +2612,12 @@ intel_set_cdclk_pre_plane_update(struct
> intel_atomic_state *state)
>  						 old_cdclk_state-
> >actual.voltage_level);
>  	}
> 
> +	/*
> +	 * mbus joining will be changed later by
> +	 * intel_dbuf_mbus_{pre,post}_ddb_update()
> +	 */
> +	cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
> +
>  	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
>  	intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe,
> --
> 2.43.2

Re: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active

[Ville Syrjälä]

On Thu, Mar 28, 2024 at 09:16:06AM +0000, Murthy, Arun R wrote:
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Wednesday, March 27, 2024 11:16 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when
> > pipes are active
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently we always reprogram CDCLK from the
> > intel_set_cdclk_pre_plane_update() when using squahs/crawl.
> Typo squashs->squash
> 
> > The code only works correctly for the cd2x update or full modeset cases, and it
> > was simply never updated to deal with squash/crawl.
> > 
> > If the CDCLK frequency is increasing we must reprogram it before we do
> > anything else that might depend on the new higher frequency, and conversely
> > we must not decrease the frequency until everything that might still depend on
> > the old higher frequency has been dealt with.
> > 
> > Since cdclk_state->pipe is only relevant when doing a cd2x update we can't use
> > it to determine the correct sequence during squash/crawl. To that end
> > introduce cdclk_state->disable_pipes which simply indicates that we must
> > perform the update while the pipes are disable (ie. during
> > intel_set_cdclk_pre_plane_update()). Otherwise we use the same old vs. new
> > CDCLK frequency comparsiong as for cd2x updates.
> > 
> > The only remaining problem case is when the voltage_level needs to increase
> > due to a DDI port, but the CDCLK frequency is decreasing (and not all pipes are
> > being disabled). The current approach will not bump the voltage level up until
> > after the port has already been enabled, which is too late.
> > But we'll take care of that case separately.
> > 
> > v2: Don't break the "must disable pipes case"
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++++++------
> > drivers/gpu/drm/i915/display/intel_cdclk.h |  3 +++
> >  2 files changed, 12 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 31aaa9780dfc..619529dba095 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2600,7 +2600,6 @@ intel_set_cdclk_pre_plane_update(struct
> > intel_atomic_state *state)
> >  		intel_atomic_get_old_cdclk_state(state);
> >  	const struct intel_cdclk_state *new_cdclk_state =
> >  		intel_atomic_get_new_cdclk_state(state);
> > -	enum pipe pipe = new_cdclk_state->pipe;
> Looks like this cdclk_state->pipe is not more used in the driver and can it be removed?

It is still used for its primary purpose (cd2x update pipe select).

The only thing changing here is that we no longer use it as a
canary to indicate whether we need to do the cdclk programming
with pipes off or not.

-- 
Ville Syrjälä
Intel

✓ Fi.CI.BAT: success for drm/i915: Implemnt vblank sycnhronized mbus joining changes

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5611 bytes --]

== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes
URL   : https://patchwork.freedesktop.org/series/131700/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14495 -> Patchwork_131700v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

Participating hosts (38 -> 36)
------------------------------

  Additional (1): fi-kbl-8809g 
  Missing    (3): bat-arls-4 fi-glk-j4005 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_131700v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_force_connector_basic@force-edid:
    - bat-dg2-8:          [PASS][1] -> [INCOMPLETE][2] ([i915#10419])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-dg2-8/igt@kms_force_connector_basic@force-edid.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-dg2-8/igt@kms_force_connector_basic@force-edid.html

  * igt@runner@aborted:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][3] ([i915#4991])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/fi-kbl-8809g/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@dmabuf@all-tests@dma_fence:
    - bat-arls-3:         [DMESG-FAIL][4] -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-arls-3/igt@dmabuf@all-tests@dma_fence.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-arls-3/igt@dmabuf@all-tests@dma_fence.html

  * igt@dmabuf@all-tests@sanitycheck:
    - bat-arls-3:         [ABORT][6] -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-arls-3/igt@dmabuf@all-tests@sanitycheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-arls-3/igt@dmabuf@all-tests@sanitycheck.html

  * igt@gem_lmem_swapping@basic@lmem0:
    - bat-dg2-14:         [FAIL][8] ([i915#10378]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-dg2-14/igt@gem_lmem_swapping@basic@lmem0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-dg2-14/igt@gem_lmem_swapping@basic@lmem0.html

  * igt@i915_pm_rpm@module-reload:
    - {bat-mtlp-9}:       [WARN][10] ([i915#10436]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@coherency:
    - bat-dg2-9:          [ABORT][12] ([i915#10366]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-dg2-9/igt@i915_selftest@live@coherency.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-dg2-9/igt@i915_selftest@live@coherency.html

  * igt@i915_selftest@live@hangcheck:
    - bat-mtlp-8:         [DMESG-FAIL][14] -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-mtlp-8/igt@i915_selftest@live@hangcheck.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-mtlp-8/igt@i915_selftest@live@hangcheck.html
    - bat-rpls-3:         [DMESG-WARN][16] ([i915#5591]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-rpls-3/igt@i915_selftest@live@hangcheck.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-rpls-3/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#10419]: https://gitlab.freedesktop.org/drm/intel/issues/10419
  [i915#10436]: https://gitlab.freedesktop.org/drm/intel/issues/10436
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591


Build changes
-------------

  * Linux: CI_DRM_14495 -> Patchwork_131700v1

  CI-20190529: 20190529
  CI_DRM_14495: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7786: 1e4a3cd0a4bb3419fb70ed3e01259485b056dcfd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_131700v1: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

45360b754e0c drm/i915: Optimize out redundant dbuf slice updates
5b77718cde22 drm/i915: Use a plain old int for the cdclk/mdclk ratio
20e24ebfb8f0 drm/i915: Implement vblank synchronized MBUS join changes
998a8d1a3fe6 drm/i915: Use old mbus_join value when increasing CDCLK
5bd07eef2032 drm/i915: Add debugs for mbus joining and dbuf ratio programming
ea274a22cf64 drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()
806549820e53 drm/i915: Extract intel_dbuf_mbus_join_update()
df2772cf89f6 drm/i915: Relocate intel_mbus_dbox_update()
fdf83bcfbeb5 drm/i915: Loop over all active pipes in intel_mbus_dbox_update
ab4df8dbc28e drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plane update
d2d2eca267fe drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks
b038835f4215 drm/i915/cdclk: Fix voltage_level programming edge case
8e9c9d764db5 drm/i915/cdclk: Fix CDCLK programming order when pipes are active

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

[-- Attachment #2: Type: text/html, Size: 6505 bytes --]

✓ Fi.CI.BAT: success for drm/i915: Implemnt vblank sycnhronized mbus joining changes

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5863 bytes --]

== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes
URL   : https://patchwork.freedesktop.org/series/131700/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14495 -> Patchwork_131700v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

Participating hosts (38 -> 36)
------------------------------

  Additional (1): fi-kbl-8809g 
  Missing    (3): bat-arls-4 fi-glk-j4005 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_131700v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_force_connector_basic@force-edid:
    - bat-dg2-8:          [PASS][1] -> [INCOMPLETE][2] ([i915#10419])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-dg2-8/igt@kms_force_connector_basic@force-edid.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-dg2-8/igt@kms_force_connector_basic@force-edid.html

  * igt@runner@aborted:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][3] ([i915#4991])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/fi-kbl-8809g/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@dmabuf@all-tests@dma_fence:
    - bat-arls-3:         [DMESG-FAIL][4] ([i915#10602]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-arls-3/igt@dmabuf@all-tests@dma_fence.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-arls-3/igt@dmabuf@all-tests@dma_fence.html

  * igt@dmabuf@all-tests@sanitycheck:
    - bat-arls-3:         [ABORT][6] ([i915#10601]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-arls-3/igt@dmabuf@all-tests@sanitycheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-arls-3/igt@dmabuf@all-tests@sanitycheck.html

  * igt@gem_lmem_swapping@basic@lmem0:
    - bat-dg2-14:         [FAIL][8] ([i915#10378]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-dg2-14/igt@gem_lmem_swapping@basic@lmem0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-dg2-14/igt@gem_lmem_swapping@basic@lmem0.html

  * igt@i915_pm_rpm@module-reload:
    - {bat-mtlp-9}:       [WARN][10] ([i915#10436]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@coherency:
    - bat-dg2-9:          [ABORT][12] ([i915#10366]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-dg2-9/igt@i915_selftest@live@coherency.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-dg2-9/igt@i915_selftest@live@coherency.html

  * igt@i915_selftest@live@hangcheck:
    - bat-mtlp-8:         [DMESG-FAIL][14] ([i915#9840]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-mtlp-8/igt@i915_selftest@live@hangcheck.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-mtlp-8/igt@i915_selftest@live@hangcheck.html
    - bat-rpls-3:         [DMESG-WARN][16] ([i915#5591]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/bat-rpls-3/igt@i915_selftest@live@hangcheck.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/bat-rpls-3/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#10419]: https://gitlab.freedesktop.org/drm/intel/issues/10419
  [i915#10436]: https://gitlab.freedesktop.org/drm/intel/issues/10436
  [i915#10601]: https://gitlab.freedesktop.org/drm/intel/issues/10601
  [i915#10602]: https://gitlab.freedesktop.org/drm/intel/issues/10602
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#9840]: https://gitlab.freedesktop.org/drm/intel/issues/9840


Build changes
-------------

  * Linux: CI_DRM_14495 -> Patchwork_131700v1

  CI-20190529: 20190529
  CI_DRM_14495: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7786: 1e4a3cd0a4bb3419fb70ed3e01259485b056dcfd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_131700v1: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

45360b754e0c drm/i915: Optimize out redundant dbuf slice updates
5b77718cde22 drm/i915: Use a plain old int for the cdclk/mdclk ratio
20e24ebfb8f0 drm/i915: Implement vblank synchronized MBUS join changes
998a8d1a3fe6 drm/i915: Use old mbus_join value when increasing CDCLK
5bd07eef2032 drm/i915: Add debugs for mbus joining and dbuf ratio programming
ea274a22cf64 drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()
806549820e53 drm/i915: Extract intel_dbuf_mbus_join_update()
df2772cf89f6 drm/i915: Relocate intel_mbus_dbox_update()
fdf83bcfbeb5 drm/i915: Loop over all active pipes in intel_mbus_dbox_update
ab4df8dbc28e drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plane update
d2d2eca267fe drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks
b038835f4215 drm/i915/cdclk: Fix voltage_level programming edge case
8e9c9d764db5 drm/i915/cdclk: Fix CDCLK programming order when pipes are active

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

[-- Attachment #2: Type: text/html, Size: 6746 bytes --]

RE: [PATCH 11/13] drm/i915: Implement vblank synchronized MBUS join changes

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH 11/13] drm/i915: Implement vblank synchronized MBUS join
> changes
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> Currently we can't change MBUS join status without doing a modeset, because
> we are lacking mechanism to synchronize those with vblank.
> However then this means that we can't do a fastset, if there is a need to change
> MBUS join state. Fix that by implementing such change.
> We already call correspondent check and update at pre_plane dbuf update, so the
> only thing left is to have a non-modeset version of that.
> If active pipes stay the same then fastset is possible and only MBUS join
> state/ddb allocation updates would be committed.
> 
> The full mbus/cdclk sequence will look as follows:
> 1. disable pipes
> 2. increase cdclk if necessary
>  2.1 reprogram cdclk
>  2.2 update dbuf tracker value
> 3. enable mbus joining if necessary
>  3.1 update mbus_ctl
>  3.2 update dbuf tracker value
> 4. reallocate dbuf for planes on active pipes 5. disable mbus joining if necessary
>  5.1 update dbuf tracker value
>  5.2 update mbus_ctl
> 6. enable pipes
> 7. decrease cdclk if necessary
>   7.1 update dbuf tracker value
>   7.2 reprogram cdclk
> 
> And in order to keep things in sync we need:
> Step 2:
> - mbus_join == old
> - mdclk/cdclk ratio == new
> Step 3:
> - mbus_join == new
> - mdclk/cdclk ratio == old when cdclk is changing in step 7
> - mdclk/cdclk ratio == new when cdclk is changing in step 2 Step 5:
> - mbus_join == new
> - mdclk/cdclk ratio == old when cdclk is changing in step 7
> - mdclk/cdclk ratio == new when cdclk is changing in step 2 Step 7:
> - mbus_join == new
> - mdclk/cdclk ratio == new
> 
> v2: - Removed redundant parentheses(Ville Syrjälä)
>     - Constified new_crtc_state in intel_mbus_joined_pipe(Ville Syrjälä)
>     - Removed pipe_select variable(Ville Syrjälä)
> [v3: vsyrjala: Correctly sequence vs. cdclk updates,
>                properly describe the full sequence,
> 	       shuffle code around to make the diff more legible,
> 	       streamline a few things]

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Co-developed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c   |  11 ++
>  drivers/gpu/drm/i915/display/intel_cdclk.h   |   1 +
>  drivers/gpu/drm/i915/display/intel_display.c |   5 +-
>  drivers/gpu/drm/i915/display/skl_watermark.c | 141 ++++++++++++-------
>  drivers/gpu/drm/i915/display/skl_watermark.h |   3 +-
>  5 files changed, 112 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4024118a7ffb..66c161d7b485 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2576,6 +2576,17 @@ static void intel_cdclk_pcode_post_notify(struct
> intel_atomic_state *state)
>  			   update_cdclk, update_pipe_count);  }
> 
> +bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
> +{
> +	const struct intel_cdclk_state *old_cdclk_state =
> +		intel_atomic_get_old_cdclk_state(state);
> +	const struct intel_cdclk_state *new_cdclk_state =
> +		intel_atomic_get_new_cdclk_state(state);
> +
> +	return new_cdclk_state && !new_cdclk_state->disable_pipes &&
> +		new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
> }
> +
>  /**
>   * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
>   * @state: intel atomic state
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 2843fc091086..5d4faf401774 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -69,6 +69,7 @@ bool intel_cdclk_clock_changed(const struct
> intel_cdclk_config *a,
>  			       const struct intel_cdclk_config *b);
>  u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>  			   const struct intel_cdclk_config *cdclk_config);
> +bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
>  void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);  void
> intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);  void
> intel_cdclk_dump_config(struct drm_i915_private *i915, diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4d6668a5f1ab..023cf4a77e6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6915,6 +6915,8 @@ static void skl_commit_modeset_enables(struct
> intel_atomic_state *state)
>  		intel_pre_update_crtc(state, crtc);
>  	}
> 
> +	intel_dbuf_mbus_pre_ddb_update(state);
> +
>  	while (update_pipes) {
>  		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  						    new_crtc_state, i) {
> @@ -6945,6 +6947,8 @@ static void skl_commit_modeset_enables(struct
> intel_atomic_state *state)
>  		}
>  	}
> 
> +	intel_dbuf_mbus_post_ddb_update(state);
> +
>  	update_pipes = modeset_pipes;
> 
>  	/*
> @@ -7191,7 +7195,6 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  	intel_encoders_update_prepare(state);
> 
>  	intel_dbuf_pre_plane_update(state);
> -	intel_mbus_dbox_update(state);
> 
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>  		if (new_crtc_state->do_async_flip)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index a118ecf9e532..ca0f1f89e6d9 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2636,13 +2636,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
>  		if (ret)
>  			return ret;
> 
> -		if (old_dbuf_state->joined_mbus != new_dbuf_state-
> >joined_mbus) {
> -			/* TODO: Implement vblank synchronized MBUS joining
> changes */
> -			ret = intel_modeset_all_pipes_late(state, "MBUS joining
> change");
> -			if (ret)
> -				return ret;
> -		}
> -
>  		drm_dbg_kms(&i915->drm,
>  			    "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices
> 0x%x), mbus joined? %s->%s\n",
>  			    old_dbuf_state->enabled_slices,
> @@ -3559,7 +3552,7 @@ static bool xelpdp_is_only_pipe_per_dbuf_bank(enum
> pipe pipe, u8 active_pipes)
>  	return false;
>  }
> 
> -void intel_mbus_dbox_update(struct intel_atomic_state *state)
> +static void intel_mbus_dbox_update(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; @@ -
> 3640,6 +3633,9 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct
> drm_i915_private *i915, u8 ratio  {
>  	enum dbuf_slice slice;
> 
> +	if (!HAS_MBUS_JOINING(i915))
> +		return;
> +
>  	if (DISPLAY_VER(i915) >= 20)
>  		intel_de_rmw(i915, MBUS_CTL,
> MBUS_TRANSLATION_THROTTLE_MIN_MASK,
>  			     MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
> @@ -3663,24 +3659,42 @@ static void
> intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
>  		intel_atomic_get_old_dbuf_state(state);
>  	const struct intel_dbuf_state *new_dbuf_state =
>  		intel_atomic_get_new_dbuf_state(state);
> +	int mdclk_cdclk_ratio;
> 
> -	if (DISPLAY_VER(i915) >= 20 &&
> -	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state-
> >mdclk_cdclk_ratio) {
> -		/*
> -		 * For Xe2LPD and beyond, when there is a change in the ratio
> -		 * between MDCLK and CDCLK, updates to related registers need
> to
> -		 * happen at a specific point in the CDCLK change sequence. In
> -		 * that case, we defer to the call to
> -		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
> -		 */
> -		return;
> +	if (intel_cdclk_is_decreasing_later(state)) {
> +		/* cdclk/mdclk will be changed later by
> intel_set_cdclk_post_plane_update() */
> +		mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio;
> +	} else {
> +		/* cdclk/mdclk already changed by
> intel_set_cdclk_pre_plane_update() */
> +		mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio;
>  	}
> 
> -	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state-
> >mdclk_cdclk_ratio,
> +	intel_dbuf_mdclk_cdclk_ratio_update(i915, mdclk_cdclk_ratio,
>  					    new_dbuf_state->joined_mbus);
>  }
> 
> -static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> +static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
> +					const struct intel_dbuf_state
> *dbuf_state) {
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	enum pipe pipe = ffs(dbuf_state->active_pipes) - 1;
> +	const struct intel_crtc_state *new_crtc_state;
> +	struct intel_crtc *crtc;
> +
> +	drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);
> +	drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state-
> >active_pipes));
> +
> +	crtc = intel_crtc_for_pipe(i915, pipe);
> +	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state))
> +		return pipe;
> +	else
> +		return INVALID_PIPE;
> +}
> +
> +static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state,
> +					enum pipe pipe)
>  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	const struct intel_dbuf_state *old_dbuf_state = @@ -3689,44 +3703,80
> @@ static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
>  		intel_atomic_get_new_dbuf_state(state);
>  	u32 mbus_ctl;
> 
> -	drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s\n",
> +	drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s (pipe:
> %c)\n",
>  		    str_yes_no(old_dbuf_state->joined_mbus),
> -		    str_yes_no(new_dbuf_state->joined_mbus));
> +		    str_yes_no(new_dbuf_state->joined_mbus),
> +		    pipe != INVALID_PIPE ? pipe_name(pipe) : '*');
> 
> -	/*
> -	 * TODO: Implement vblank synchronized MBUS joining changes.
> -	 * Must be properly coordinated with dbuf reprogramming.
> -	 */
>  	if (new_dbuf_state->joined_mbus)
> -		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> -			MBUS_JOIN_PIPE_SELECT_NONE;
> +		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN;
>  	else
> -		mbus_ctl = MBUS_HASHING_MODE_2x2 |
> -			MBUS_JOIN_PIPE_SELECT_NONE;
> +		mbus_ctl = MBUS_HASHING_MODE_2x2;
> +
> +	if (pipe != INVALID_PIPE)
> +		mbus_ctl |= MBUS_JOIN_PIPE_SELECT(pipe);
> +	else
> +		mbus_ctl |= MBUS_JOIN_PIPE_SELECT_NONE;
> 
>  	intel_de_rmw(i915, MBUS_CTL,
>  		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
>  		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);  }
> 
> -/*
> - * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
> before
> - * update the request state of all DBUS slices.
> - */
> -static void update_mbus_pre_enable(struct intel_atomic_state *state)
> +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state) {
> +	const struct intel_dbuf_state *new_dbuf_state =
> +		intel_atomic_get_new_dbuf_state(state);
> +	const struct intel_dbuf_state *old_dbuf_state =
> +		intel_atomic_get_old_dbuf_state(state);
> +
> +	if (!new_dbuf_state)
> +		return;
> +
> +	if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
> +		enum pipe pipe = intel_mbus_joined_pipe(state,
> new_dbuf_state);
> +
> +		WARN_ON(!new_dbuf_state->base.changed);
> +
> +		intel_dbuf_mbus_join_update(state, pipe);
> +		intel_mbus_dbox_update(state);
> +		intel_dbuf_mdclk_min_tracker_update(state);
> +	}
> +}
> +
> +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_dbuf_state *new_dbuf_state =
> +		intel_atomic_get_new_dbuf_state(state);
> +	const struct intel_dbuf_state *old_dbuf_state =
> +		intel_atomic_get_old_dbuf_state(state);
> 
> -	if (!HAS_MBUS_JOINING(i915))
> +	if (!new_dbuf_state)
>  		return;
> 
> -	/*
> -	 * TODO: Implement vblank synchronized MBUS joining changes.
> -	 * Must be properly coordinated with dbuf reprogramming.
> -	 */
> -	intel_dbuf_mbus_join_update(state);
> +	if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
> +		enum pipe pipe = intel_mbus_joined_pipe(state, old_dbuf_state);
> +
> +		WARN_ON(!new_dbuf_state->base.changed);
> +
> +		intel_dbuf_mdclk_min_tracker_update(state);
> +		intel_mbus_dbox_update(state);
> +		intel_dbuf_mbus_join_update(state, pipe);
> +
> +		if (pipe != INVALID_PIPE) {
> +			struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);
> +
> +			intel_crtc_wait_for_next_vblank(crtc);
> +		}
> +	} else if (old_dbuf_state->joined_mbus == new_dbuf_state->joined_mbus
> &&
> +		   old_dbuf_state->active_pipes != new_dbuf_state-
> >active_pipes) {
> +		WARN_ON(!new_dbuf_state->base.changed);
> +
> +		intel_dbuf_mdclk_min_tracker_update(state);
> +		intel_mbus_dbox_update(state);
> +	}
> 
> -	intel_dbuf_mdclk_min_tracker_update(state);
>  }
> 
>  void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) @@ -
> 3738,13 +3788,11 @@ void intel_dbuf_pre_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_old_dbuf_state(state);
> 
>  	if (!new_dbuf_state ||
> -	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices
> &&
> -	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> +	    new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
>  		return;
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> -	update_mbus_pre_enable(state);
>  	gen9_dbuf_slices_update(i915,
>  				old_dbuf_state->enabled_slices |
>  				new_dbuf_state->enabled_slices);
> @@ -3759,8 +3807,7 @@ void intel_dbuf_post_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_old_dbuf_state(state);
> 
>  	if (!new_dbuf_state ||
> -	    (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices
> &&
> -	     new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> +	    new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
>  		return;
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h
> b/drivers/gpu/drm/i915/display/skl_watermark.h
> index bf7516620ab6..3323a1d973f9 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -79,7 +79,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct
> intel_atomic_state *state, u8  void intel_dbuf_pre_plane_update(struct
> intel_atomic_state *state);  void intel_dbuf_post_plane_update(struct
> intel_atomic_state *state);  void intel_dbuf_mdclk_cdclk_ratio_update(struct
> drm_i915_private *i915, u8 ratio, bool joined_mbus); -void
> intel_mbus_dbox_update(struct intel_atomic_state *state);
> +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
> +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> 
>  #endif /* __SKL_WATERMARK_H__ */
> 
> --
> 2.43.2

RE: [PATCH 12/13] drm/i915: Use a plain old int for the cdclk/mdclk ratio

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 12/13] drm/i915: Use a plain old int for the cdclk/mdclk ratio
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> No point in throwing around u8 when we're dealing with just an integer. Use a
> plain old boring 'int'.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c   | 6 +++---
>  drivers/gpu/drm/i915/display/intel_cdclk.h   | 4 ++--
>  drivers/gpu/drm/i915/display/skl_watermark.c | 6 ++++--
> drivers/gpu/drm/i915/display/skl_watermark.h | 6 ++++--
>  4 files changed, 13 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 66c161d7b485..5cba0d08189b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1893,8 +1893,8 @@ static u32 xe2lpd_mdclk_source_sel(struct
> drm_i915_private *i915)
>  	return MDCLK_SOURCE_SEL_CD2XCLK;
>  }
> 
> -u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> -			   const struct intel_cdclk_config *cdclk_config)
> +int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +			    const struct intel_cdclk_config *cdclk_config)
>  {
>  	if (mdclk_source_is_cdclk_pll(i915))
>  		return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
> @@ -3321,7 +3321,7 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> 
>  	if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
>  	    intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
> -		u8 ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state-
> >actual);
> +		int ratio = intel_mdclk_cdclk_ratio(dev_priv,
> +&new_cdclk_state->actual);
> 
>  		ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
>  		if (ret)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 5d4faf401774..cfdcdec07a4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -67,8 +67,8 @@ void intel_update_cdclk(struct drm_i915_private
> *dev_priv);
>  u32 intel_read_rawclk(struct drm_i915_private *dev_priv);  bool
> intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
>  			       const struct intel_cdclk_config *b);
> -u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> -			   const struct intel_cdclk_config *cdclk_config);
> +int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +			    const struct intel_cdclk_config *cdclk_config);
>  bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);  void
> intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);  void
> intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); diff --git
> a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index ca0f1f89e6d9..1b48009efe2b 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3616,7 +3616,8 @@ static void intel_mbus_dbox_update(struct
> intel_atomic_state *state)
>  	}
>  }
> 
> -int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
> ratio)
> +int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
> +					   int ratio)
>  {
>  	struct intel_dbuf_state *dbuf_state;
> 
> @@ -3629,7 +3630,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct
> intel_atomic_state *state, u8
>  	return intel_atomic_lock_global_state(&dbuf_state->base);
>  }
> 
> -void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8
> ratio, bool joined_mbus)
> +void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
> +					 int ratio, bool joined_mbus)
>  {
>  	enum dbuf_slice slice;
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h
> b/drivers/gpu/drm/i915/display/skl_watermark.h
> index 3323a1d973f9..ef1a008466be 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -74,11 +74,13 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state
> *state);
>  	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state,
> &to_i915(state->base.dev)->display.dbuf.obj))
> 
>  int intel_dbuf_init(struct drm_i915_private *i915); -int
> intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
> ratio);
> +int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
> +					   int ratio);
> 
>  void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);  void
> intel_dbuf_post_plane_update(struct intel_atomic_state *state); -void
> intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio,
> bool joined_mbus);
> +void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
> +					 int ratio, bool joined_mbus);
>  void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);  void
> intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> 
> --
> 2.43.2

RE: [PATCH 13/13] drm/i915: Optimize out redundant dbuf slice updates

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 13/13] drm/i915: Optimize out redundant dbuf slice updates
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> if the new dbuf slices are a superset of the old dbuf slices then we don't have to
> do anything in intel_dbuf_post_plane_update(). Restructure the code to skip such
> redundant dbuf slice updates. The main benefit is slightly less confusing logs.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 27 +++++++++++++-------
>  1 file changed, 18 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1b48009efe2b..50ec51065118 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3788,16 +3788,20 @@ void intel_dbuf_pre_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_new_dbuf_state(state);
>  	const struct intel_dbuf_state *old_dbuf_state =
>  		intel_atomic_get_old_dbuf_state(state);
> +	u8 old_slices, new_slices;
> 
> -	if (!new_dbuf_state ||
> -	    new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
> +	if (!new_dbuf_state)
> +		return;
> +
> +	old_slices = old_dbuf_state->enabled_slices;
> +	new_slices = old_dbuf_state->enabled_slices |
> +new_dbuf_state->enabled_slices;
> +
> +	if (old_slices == new_slices)
>  		return;
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> -	gen9_dbuf_slices_update(i915,
> -				old_dbuf_state->enabled_slices |
> -				new_dbuf_state->enabled_slices);
> +	gen9_dbuf_slices_update(i915, new_slices);
>  }
> 
>  void intel_dbuf_post_plane_update(struct intel_atomic_state *state) @@ -
> 3807,15 +3811,20 @@ void intel_dbuf_post_plane_update(struct
> intel_atomic_state *state)
>  		intel_atomic_get_new_dbuf_state(state);
>  	const struct intel_dbuf_state *old_dbuf_state =
>  		intel_atomic_get_old_dbuf_state(state);
> +	u8 old_slices, new_slices;
> 
> -	if (!new_dbuf_state ||
> -	    new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
> +	if (!new_dbuf_state)
> +		return;
> +
> +	old_slices = old_dbuf_state->enabled_slices | new_dbuf_state-
> >enabled_slices;
> +	new_slices = new_dbuf_state->enabled_slices;
> +
> +	if (old_slices == new_slices)
>  		return;
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> -	gen9_dbuf_slices_update(i915,
> -				new_dbuf_state->enabled_slices);
> +	gen9_dbuf_slices_update(i915, new_slices);
>  }
> 
>  static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
> --
> 2.43.2

✓ Fi.CI.IGT: success for drm/i915: Implemnt vblank sycnhronized mbus joining changes

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1309 bytes --]

== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes
URL   : https://patchwork.freedesktop.org/series/131700/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14495_full -> Patchwork_131700v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

Participating hosts (9 -> 7)
------------------------------

  Additional (1): shard-snb-0 
  Missing    (3): shard-snb shard-dg2 shard-glk 


Changes
-------

  No changes found


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_14495 -> Patchwork_131700v1
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_14495: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7786: 1e4a3cd0a4bb3419fb70ed3e01259485b056dcfd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_131700v1: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

[-- Attachment #2: Type: text/html, Size: 1902 bytes --]

RE: [PATCH 00/13] drm/i915: Implemnt vblank sycnhronized mbus joining changes

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 00/13] drm/i915: Implemnt vblank sycnhronized mbus joining
> changes

Nit: Typo in implement and synchronized

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Get rid of the full modeset requirement for changing mbus joining. Things got
> quite a bit more complicated than originally envisioned due to the dynamic
> cdclk/mdclk ratio.
> Sadly we have to do a fairly careful dance between the dbuf and cdclk code to
> make sure everything is programmed in the correct sequence.
> 
> Stan did the grunt work, but the sequence vs. cdclk updates was still not right so I
> finished that part.
> I also reorganized the code quite a bit to make the resulting patches more legible.
> And I tossed in more debugs and whatnot so we can actually observe what it's
> doing.
> 
> Quickly smoke tested on tgl and adl, and things seem pretty decent.
> Unfortunately I don't have a LNL on me right now so I haven't fully tested the
> mdclk/cdclk ratio changes on real hw, but I did hack my adl to pretend that the
> ratio changes with cdclk and double checked that the logs look sensible for all the
> combinations of cdclk increase/decrease and mbus join enable/disable.
> So should work (tm) on real hw too.

Reviewed the series and it looks good to me.

This is ready for merge.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Regards,
Uma Shankar

> Stanislav Lisovskiy (3):
>   drm/i915: Loop over all active pipes in intel_mbus_dbox_update
>   drm/i915: Use old mbus_join value when increasing CDCLK
>   drm/i915: Implement vblank synchronized MBUS join changes
> 
> Ville Syrjälä (10):
>   drm/i915/cdclk: Fix CDCLK programming order when pipes are active
>   drm/i915/cdclk: Fix voltage_level programming edge case
>   drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks
>   drm/i915/cdclk: Indicate whether CDCLK change happens during pre or
>     post plane update
>   drm/i915: Relocate intel_mbus_dbox_update()
>   drm/i915: Extract intel_dbuf_mbus_join_update()
>   drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()
>   drm/i915: Add debugs for mbus joining and dbuf ratio programming
>   drm/i915: Use a plain old int for the cdclk/mdclk ratio
>   drm/i915: Optimize out redundant dbuf slice updates
> 
>  drivers/gpu/drm/i915/display/intel_cdclk.c   |  85 +++--
>  drivers/gpu/drm/i915/display/intel_cdclk.h   |   8 +-
>  drivers/gpu/drm/i915/display/intel_display.c |   5 +-
>  drivers/gpu/drm/i915/display/skl_watermark.c | 344 ++++++++++++-------
>  drivers/gpu/drm/i915/display/skl_watermark.h |   9 +-
>  5 files changed, 271 insertions(+), 180 deletions(-)
> 
> --
> 2.43.2

✓ Fi.CI.IGT: success for drm/i915: Implemnt vblank sycnhronized mbus joining changes

[Patchwork]

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== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes
URL   : https://patchwork.freedesktop.org/series/131700/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14495_full -> Patchwork_131700v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

Participating hosts (9 -> 10)
------------------------------

  Additional (1): shard-snb-0 

Known issues
------------

  Here are the changes found in Patchwork_131700v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_fdinfo@all-busy-check-all:
    - shard-mtlp:         NOTRUN -> [SKIP][1] ([i915#8414])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@drm_fdinfo@all-busy-check-all.html

  * igt@drm_fdinfo@virtual-busy-all:
    - shard-dg2:          NOTRUN -> [SKIP][2] ([i915#8414])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@drm_fdinfo@virtual-busy-all.html

  * igt@gem_ctx_persistence@heartbeat-close:
    - shard-dg2:          NOTRUN -> [SKIP][3] ([i915#8555])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_ctx_persistence@heartbeat-close.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-mtlp:         NOTRUN -> [SKIP][4] ([i915#280])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_eio@kms:
    - shard-tglu:         [PASS][5] -> [INCOMPLETE][6] ([i915#10513])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-5/igt@gem_eio@kms.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-9/igt@gem_eio@kms.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          NOTRUN -> [FAIL][7] ([i915#2846])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-tglu:         [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-9/igt@gem_exec_fair@basic-throttle@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-dg2:          NOTRUN -> [SKIP][11] ([i915#5107])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_lmem_swapping@heavy-multi@lmem0:
    - shard-dg2:          [PASS][12] -> [FAIL][13] ([i915#10378])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@gem_lmem_swapping@heavy-multi@lmem0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_lmem_swapping@heavy-multi@lmem0.html

  * igt@gem_lmem_swapping@verify-ccs@lmem0:
    - shard-dg2:          NOTRUN -> [FAIL][14] ([i915#10446])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_lmem_swapping@verify-ccs@lmem0.html

  * igt@gem_media_fill@media-fill:
    - shard-mtlp:         NOTRUN -> [SKIP][15] ([i915#8289])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@gem_media_fill@media-fill.html

  * igt@gem_mmap_gtt@basic-write-read-distinct:
    - shard-mtlp:         NOTRUN -> [SKIP][16] ([i915#4077]) +2 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@gem_mmap_gtt@basic-write-read-distinct.html

  * igt@gem_mmap_wc@read-write-distinct:
    - shard-mtlp:         NOTRUN -> [SKIP][17] ([i915#4083])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@gem_mmap_wc@read-write-distinct.html

  * igt@gem_mmap_wc@write:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#4083])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_mmap_wc@write.html

  * igt@gem_partial_pwrite_pread@write:
    - shard-mtlp:         NOTRUN -> [SKIP][19] ([i915#3282]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@gem_partial_pwrite_pread@write.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-glk:          NOTRUN -> [SKIP][20] +134 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk5/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-mtlp:         NOTRUN -> [SKIP][21] ([i915#4270])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_readwrite@write-bad-handle:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#3282])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_readwrite@write-bad-handle.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][23] ([i915#8428])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_render_copy@yf-tiled-ccs-to-linear:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#5190] / [i915#8428])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_render_copy@yf-tiled-ccs-to-linear.html

  * igt@gen7_exec_parse@cmd-crossing-page:
    - shard-mtlp:         NOTRUN -> [SKIP][25] +5 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@gen7_exec_parse@cmd-crossing-page.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          NOTRUN -> [ABORT][26] ([i915#5566])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk3/igt@gen9_exec_parse@allowed-single.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][27] -> [FAIL][28] ([i915#2521])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-8/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [PASS][29] -> [FAIL][30] ([i915#5138])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2:          NOTRUN -> [SKIP][31] ([i915#4538] / [i915#5190]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][32] ([i915#6095]) +7 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#10307] / [i915#6095]) +6 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#10307] / [i915#10434] / [i915#6095])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#7828])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][36] ([i915#7828]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-mtlp:         NOTRUN -> [SKIP][37] ([i915#3359])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21:
    - shard-mtlp:         NOTRUN -> [SKIP][38] ([i915#8814])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-onscreen-64x21.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-mtlp:         NOTRUN -> [SKIP][39] ([i915#9809])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#3637])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][41] ([i915#2672] / [i915#3555])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-mtlp:         NOTRUN -> [SKIP][42] ([i915#5274])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][43] ([i915#8708]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#5354]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][45] ([i915#1825]) +6 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-mtlp:         NOTRUN -> [SKIP][46] ([i915#10070])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][47] ([i915#7862]) +1 other test fail
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk5/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][48] ([i915#5235]) +2 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][49] ([i915#3555] / [i915#5235])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-edp-1.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-mtlp:         NOTRUN -> [SKIP][50] ([i915#9519])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_psr@fbc-psr-cursor-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#1072] / [i915#9732])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_psr@fbc-psr-cursor-mmap-cpu.html

  * igt@kms_psr@fbc-psr-primary-blt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][52] ([i915#9688]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_psr@fbc-psr-primary-blt@edp-1.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-mtlp:         NOTRUN -> [SKIP][53] ([i915#4235])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
    - shard-snb:          [PASS][54] -> [FAIL][55] ([i915#9196])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-snb5/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
    - shard-tglu:         [PASS][56] -> [FAIL][57] ([i915#9196]) +1 other test fail
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-mtlp:         NOTRUN -> [SKIP][58] ([i915#8808] / [i915#9906])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_vrr@flip-basic-fastset.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-mtlp:         NOTRUN -> [SKIP][59] ([i915#9917])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@sriov_basic@bind-unbind-vf.html

  * igt@syncobj_timeline@invalid-wait-zero-handles:
    - shard-glk:          NOTRUN -> [FAIL][60] ([i915#9781])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk5/igt@syncobj_timeline@invalid-wait-zero-handles.html

  * igt@syncobj_wait@invalid-wait-zero-handles:
    - shard-mtlp:         NOTRUN -> [FAIL][61] ([i915#9779])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@syncobj_wait@invalid-wait-zero-handles.html

  * igt@v3d/v3d_submit_cl@bad-multisync-out-sync:
    - shard-mtlp:         NOTRUN -> [SKIP][62] ([i915#2575]) +3 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@v3d/v3d_submit_cl@bad-multisync-out-sync.html

  * igt@vc4/vc4_label_bo@set-kernel-name:
    - shard-mtlp:         NOTRUN -> [SKIP][63] ([i915#7711]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@vc4/vc4_label_bo@set-kernel-name.html

  * igt@vc4/vc4_perfmon@destroy-invalid-perfmon:
    - shard-dg2:          NOTRUN -> [SKIP][64] ([i915#7711])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@vc4/vc4_perfmon@destroy-invalid-perfmon.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         [FAIL][65] ([i915#2842]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         [FAIL][67] ([i915#3743]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_color@legacy-gamma@pipe-c:
    - shard-mtlp:         [ABORT][69] -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-2/igt@kms_color@legacy-gamma@pipe-c.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_color@legacy-gamma@pipe-c.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1:
    - shard-tglu:         [FAIL][71] ([i915#9196]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html

  
  [i915#10070]: https://gitlab.freedesktop.org/drm/intel/issues/10070
  [i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
  [i915#10446]: https://gitlab.freedesktop.org/drm/intel/issues/10446
  [i915#10513]: https://gitlab.freedesktop.org/drm/intel/issues/10513
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7862]: https://gitlab.freedesktop.org/drm/intel/issues/7862
  [i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
  [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
  [i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9779]: https://gitlab.freedesktop.org/drm/intel/issues/9779
  [i915#9781]: https://gitlab.freedesktop.org/drm/intel/issues/9781
  [i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
  [i915#9906]: https://gitlab.freedesktop.org/drm/intel/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917


Build changes
-------------

  * Linux: CI_DRM_14495 -> Patchwork_131700v1
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_14495: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7786: 1e4a3cd0a4bb3419fb70ed3e01259485b056dcfd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_131700v1: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

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✗ Fi.CI.IGT: failure for drm/i915: Implemnt vblank sycnhronized mbus joining changes

[Patchwork]

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== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes
URL   : https://patchwork.freedesktop.org/series/131700/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14495_full -> Patchwork_131700v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_131700v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_131700v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_131700v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_eio@in-flight-suspend:
    - shard-dg2:          ([PASS][1], [PASS][2]) -> [INCOMPLETE][3]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-10/igt@gem_eio@in-flight-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-5/igt@gem_eio@in-flight-suspend.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-7/igt@gem_eio@in-flight-suspend.html

  * igt@kms_flip@dpms-off-confusion@d-hdmi-a3:
    - shard-dg2:          [PASS][4] -> [INCOMPLETE][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-6/igt@kms_flip@dpms-off-confusion@d-hdmi-a3.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-5/igt@kms_flip@dpms-off-confusion@d-hdmi-a3.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-a:
    - shard-mtlp:         [PASS][6] -> [ABORT][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-6/igt@kms_plane@pixel-format-source-clamping@pipe-a.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-5/igt@kms_plane@pixel-format-source-clamping@pipe-a.html

  
#### Warnings ####

  * igt@gem_workarounds@basic-read-context:
    - shard-dg2:          ([PASS][8], [TIMEOUT][9]) -> [TIMEOUT][10]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@gem_workarounds@basic-read-context.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-6/igt@gem_workarounds@basic-read-context.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-6/igt@gem_workarounds@basic-read-context.html

  * igt@kms_vrr@flipline:
    - shard-dg2:          ([TIMEOUT][11], [SKIP][12]) ([i915#3555]) -> [TIMEOUT][13]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-6/igt@kms_vrr@flipline.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@kms_vrr@flipline.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-6/igt@kms_vrr@flipline.html

  
Known issues
------------

  Here are the changes found in Patchwork_131700v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
    - shard-rkl:          [PASS][14] -> [FAIL][15] ([i915#7742])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-5/igt@drm_fdinfo@most-busy-check-all@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html

  * igt@drm_fdinfo@virtual-busy-all:
    - shard-dg2:          NOTRUN -> [SKIP][16] ([i915#8414])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@drm_fdinfo@virtual-busy-all.html

  * igt@drm_fdinfo@virtual-busy-idle:
    - shard-mtlp:         NOTRUN -> [SKIP][17] ([i915#8414])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@drm_fdinfo@virtual-busy-idle.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-dg1:          [PASS][18] -> [FAIL][19] ([i915#10086]) +2 other tests fail
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg1-18/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg1-16/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_ctx_persistence@heartbeat-close:
    - shard-dg2:          NOTRUN -> [SKIP][20] ([i915#8555])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_ctx_persistence@heartbeat-close.html

  * igt@gem_eio@kms:
    - shard-tglu:         ([PASS][21], [PASS][22]) -> [INCOMPLETE][23] ([i915#10513])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-5/igt@gem_eio@kms.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-8/igt@gem_eio@kms.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-9/igt@gem_eio@kms.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          NOTRUN -> [FAIL][24] ([i915#2846])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-rkl:          [PASS][25] -> [FAIL][26] ([i915#2842])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-tglu:         ([PASS][27], [PASS][28]) -> [FAIL][29] ([i915#2842]) +1 other test fail
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-7/igt@gem_exec_fair@basic-throttle@rcs0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-9/igt@gem_exec_fair@basic-throttle@rcs0.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#5107])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_fenced_exec_thrash@too-many-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][31] ([i915#4860])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@gem_fenced_exec_thrash@too-many-fences.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - shard-glk:          NOTRUN -> [SKIP][32] ([i915#4613]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk5/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-ccs@lmem0:
    - shard-dg2:          NOTRUN -> [FAIL][33] ([i915#10446])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_lmem_swapping@verify-ccs@lmem0.html

  * igt@gem_mmap_gtt@medium-copy-odd:
    - shard-mtlp:         NOTRUN -> [SKIP][34] ([i915#4077])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@gem_mmap_gtt@medium-copy-odd.html

  * igt@gem_mmap_wc@write:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4083])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_mmap_wc@write.html

  * igt@gem_pxp@display-protected-crc:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#4270])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@gem_pxp@display-protected-crc.html
    - shard-mtlp:         NOTRUN -> [SKIP][37] ([i915#4270])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@gem_pxp@display-protected-crc.html

  * igt@gem_readwrite@write-bad-handle:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#3282])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_readwrite@write-bad-handle.html

  * igt@gem_render_copy@yf-tiled-ccs-to-linear:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#5190] / [i915#8428])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_render_copy@yf-tiled-ccs-to-linear.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#8428])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          NOTRUN -> [ABORT][41] ([i915#5566])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk3/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@basic-rejected:
    - shard-mtlp:         NOTRUN -> [SKIP][42] ([i915#2856])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@gen9_exec_parse@basic-rejected.html
    - shard-rkl:          NOTRUN -> [SKIP][43] ([i915#2527])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@gen9_exec_parse@basic-rejected.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-glk:          NOTRUN -> [SKIP][44] +144 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk5/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-mtlp:         NOTRUN -> [SKIP][45] ([i915#6645])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
    - shard-tglu:         ([PASS][46], [PASS][47]) -> [FAIL][48] ([i915#2521])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-8/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#5286]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-mtlp:         NOTRUN -> [SKIP][50] ([i915#6187])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#4538] / [i915#5190]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][52]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][53] ([i915#6095]) +43 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-2/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#10307] / [i915#6095]) +73 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][55] ([i915#6095]) +23 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg1-13/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-8/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][57] ([i915#6095]) +3 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-c-edp-1.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#7828])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#7828]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_chamelium_hpd@vga-hpd-fast.html
    - shard-mtlp:         NOTRUN -> [SKIP][60] ([i915#7828]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_cursor_crc@cursor-random-64x21:
    - shard-mtlp:         NOTRUN -> [SKIP][61] ([i915#8814])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_cursor_crc@cursor-random-64x21.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          NOTRUN -> [SKIP][62] ([i915#4103])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
    - shard-mtlp:         NOTRUN -> [SKIP][63] ([i915#4213])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][64] ([i915#5354]) +3 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
    - shard-dg2:          ([PASS][65], [PASS][66]) -> [FAIL][67] ([i915#6880])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][68] +3 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html
    - shard-mtlp:         NOTRUN -> [SKIP][69] ([i915#8708]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite:
    - shard-mtlp:         NOTRUN -> [SKIP][70] ([i915#1825]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#3023]) +3 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][72] ([i915#1825]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          NOTRUN -> [SKIP][73] ([i915#6301])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#9423]) +11 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#5176] / [i915#9423]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][76] ([i915#5235]) +3 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [PASS][77] -> [SKIP][78] ([i915#9519])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-3/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@fbc-cursor-plane-update-sf@psr2-pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][79] ([i915#9808]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_psr2_sf@fbc-cursor-plane-update-sf@psr2-pipe-a-edp-1.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          NOTRUN -> [SKIP][80] ([i915#9683])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_psr2_su@page_flip-p010.html
    - shard-mtlp:         NOTRUN -> [SKIP][81] ([i915#4348])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-sprite-plane-move:
    - shard-rkl:          NOTRUN -> [SKIP][82] ([i915#1072] / [i915#9732]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_psr@fbc-pr-sprite-plane-move.html

  * igt@kms_psr@fbc-psr-cursor-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#1072] / [i915#9732])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@kms_psr@fbc-psr-cursor-mmap-cpu.html

  * igt@kms_psr@fbc-psr-primary-mmap-cpu@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#9688]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_psr@fbc-psr-primary-mmap-cpu@edp-1.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#3555]) +2 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([i915#5030]) +2 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1.html

  * igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][87] ([i915#5030] / [i915#9041])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
    - shard-snb:          ([PASS][88], [PASS][89]) -> [FAIL][90] ([i915#9196])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-snb5/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
    - shard-rkl:          NOTRUN -> [FAIL][91] ([i915#9196])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - shard-mtlp:         NOTRUN -> [SKIP][92] ([i915#9917])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@sriov_basic@enable-vfs-autoprobe-on.html
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#9917])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@v3d/v3d_perfmon@create-two-perfmon:
    - shard-mtlp:         NOTRUN -> [SKIP][94] ([i915#2575])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@v3d/v3d_perfmon@create-two-perfmon.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-deadline:
    - shard-rkl:          ([FAIL][95], [FAIL][96]) ([i915#2846]) -> [PASS][97]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-5/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         ([FAIL][98], [FAIL][99]) ([i915#2842]) -> [PASS][100]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg2:          ([FAIL][101], [PASS][102]) ([i915#10378]) -> [PASS][103]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@gem_mmap_offset@clear@smem0:
    - shard-mtlp:         ([PASS][104], [ABORT][105]) ([i915#10029]) -> [PASS][106]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-3/igt@gem_mmap_offset@clear@smem0.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-1/igt@gem_mmap_offset@clear@smem0.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@gem_mmap_offset@clear@smem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          ([INCOMPLETE][107], [INCOMPLETE][108]) ([i915#9820] / [i915#9849]) -> [PASS][109]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-2/igt@i915_module_load@reload-with-fault-injection.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
    - shard-mtlp:         [ABORT][110] ([i915#10131] / [i915#9820]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-4/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_power@sanity:
    - shard-mtlp:         ([SKIP][112], [PASS][113]) ([i915#7984]) -> [PASS][114]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-7/igt@i915_power@sanity.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-6/igt@i915_power@sanity.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-2/igt@i915_power@sanity.html

  * igt@i915_selftest@live@gt_pm:
    - shard-snb:          ([PASS][115], [ABORT][116]) -> [PASS][117]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-snb2/igt@i915_selftest@live@gt_pm.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-snb5/igt@i915_selftest@live@gt_pm.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-snb6/igt@i915_selftest@live@gt_pm.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         ([PASS][118], [FAIL][119]) ([i915#3743]) -> [PASS][120]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-9/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_color@legacy-gamma@pipe-c:
    - shard-mtlp:         ([PASS][121], [ABORT][122]) -> [PASS][123]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-7/igt@kms_color@legacy-gamma@pipe-c.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-2/igt@kms_color@legacy-gamma@pipe-c.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-8/igt@kms_color@legacy-gamma@pipe-c.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [FAIL][124] ([i915#2346]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-dg2:          ([FAIL][126], [PASS][127]) ([i915#6880]) -> [PASS][128]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          ([PASS][129], [SKIP][130]) ([i915#9519]) -> [PASS][131] +1 other test pass
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg2:          [FAIL][132] ([i915#8717]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-2/igt@kms_pm_rpm@i2c.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-11/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          ([SKIP][134], [SKIP][135]) ([i915#9519]) -> [PASS][136]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-11/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg2:          ([SKIP][137], [PASS][138]) ([i915#9519]) -> [PASS][139] +1 other test pass
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-6/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-6/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
    - shard-rkl:          [SKIP][140] ([i915#9519]) -> [PASS][141] +1 other test pass
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          [FAIL][142] ([IGT#2]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-2/igt@kms_sysfs_edid_timing.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-11/igt@kms_sysfs_edid_timing.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1:
    - shard-tglu:         ([FAIL][144], [FAIL][145]) ([i915#9196]) -> [PASS][146]
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4:
    - shard-dg1:          ([FAIL][147], [PASS][148]) ([i915#9196]) -> [PASS][149]
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg1-17/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg1-16/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg1-17/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4.html

  
#### Warnings ####

  * igt@gem_eio@reset-stress:
    - shard-dg2:          ([FAIL][150], [PASS][151]) ([i915#5784]) -> [FAIL][152] ([i915#5784])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-2/igt@gem_eio@reset-stress.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@gem_eio@reset-stress.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-2/igt@gem_eio@reset-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-tglu:         ([FAIL][153], [PASS][154]) ([i915#2842]) -> [FAIL][155] ([i915#2842])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-5/igt@gem_exec_fair@basic-none-share@rcs0.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-9/igt@gem_exec_fair@basic-none-share@rcs0.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-8/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-rkl:          ([FAIL][156], [PASS][157]) ([i915#2842]) -> [FAIL][158] ([i915#2842])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-2/igt@gem_exec_fair@basic-throttle@rcs0.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-3/igt@gem_exec_fair@basic-throttle@rcs0.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_lmem_swapping@heavy-multi@lmem0:
    - shard-dg1:          ([PASS][159], [FAIL][160]) ([i915#10378]) -> [FAIL][161] ([i915#10378])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg1-15/igt@gem_lmem_swapping@heavy-multi@lmem0.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg1-17/igt@gem_lmem_swapping@heavy-multi@lmem0.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg1-16/igt@gem_lmem_swapping@heavy-multi@lmem0.html
    - shard-dg2:          ([FAIL][162], [PASS][163]) ([i915#10378]) -> [FAIL][164] ([i915#10378])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-10/igt@gem_lmem_swapping@heavy-multi@lmem0.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@gem_lmem_swapping@heavy-multi@lmem0.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-10/igt@gem_lmem_swapping@heavy-multi@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
    - shard-dg2:          [FAIL][165] ([i915#10446]) -> [FAIL][166] ([i915#10378])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-8/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-3/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          ([WARN][167], [INCOMPLETE][168]) ([i915#7356] / [i915#9820] / [i915#9849]) -> [WARN][169] ([i915#7356])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         ([PASS][170], [FAIL][171]) ([i915#5138]) -> [FAIL][172] ([i915#5138])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         ([FAIL][173], [PASS][174]) ([i915#3743]) -> [FAIL][175] ([i915#3743])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          ([SKIP][176], [SKIP][177]) ([i915#9424] / [i915#9433]) -> [SKIP][178] ([i915#9424])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg1-13/igt@kms_content_protection@mei-interface.html
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg1-17/igt@kms_content_protection@mei-interface.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg1-17/igt@kms_content_protection@mei-interface.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2:          ([SKIP][179], [PASS][180]) ([i915#9519]) -> [SKIP][181] ([i915#9519]) +1 other test skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          ([PASS][182], [SKIP][183]) ([i915#9519]) -> [SKIP][184] ([i915#9519])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_psr@fbc-pr-cursor-mmap-gtt:
    - shard-dg2:          [SKIP][185] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][186] ([i915#1072] / [i915#9732]) +5 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-11/igt@kms_psr@fbc-pr-cursor-mmap-gtt.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-2/igt@kms_psr@fbc-pr-cursor-mmap-gtt.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-dg2:          ([SKIP][187], [SKIP][188]) ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][189] ([i915#1072] / [i915#9732]) +14 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-11/igt@kms_psr@fbc-psr-primary-page-flip.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-5/igt@kms_psr@fbc-psr-primary-page-flip.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-7/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_psr@fbc-psr2-sprite-mmap-gtt:
    - shard-dg2:          [SKIP][190] ([i915#1072] / [i915#9732]) -> [SKIP][191] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-dg2-2/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-dg2-11/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
    - shard-tglu:         ([PASS][192], [FAIL][193]) ([i915#9196]) -> [FAIL][194] ([i915#9196]) +1 other test fail
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14495/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html

  
  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [i915#10029]: https://gitlab.freedesktop.org/drm/intel/issues/10029
  [i915#10086]: https://gitlab.freedesktop.org/drm/intel/issues/10086
  [i915#10131]: https://gitlab.freedesktop.org/drm/intel/issues/10131
  [i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
  [i915#10446]: https://gitlab.freedesktop.org/drm/intel/issues/10446
  [i915#10513]: https://gitlab.freedesktop.org/drm/intel/issues/10513
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030
  [i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#7356]: https://gitlab.freedesktop.org/drm/intel/issues/7356
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8717]: https://gitlab.freedesktop.org/drm/intel/issues/8717
  [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
  [i915#9041]: https://gitlab.freedesktop.org/drm/intel/issues/9041
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
  [i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
  [i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
  [i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
  [i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917


Build changes
-------------

  * Linux: CI_DRM_14495 -> Patchwork_131700v1
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_14495: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7786: 1e4a3cd0a4bb3419fb70ed3e01259485b056dcfd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_131700v1: 07c774152cf8a034784b40978a77b5ee66e4779b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v1/index.html

[-- Attachment #2: Type: text/html, Size: 52597 bytes --]

✗ Fi.CI.SPARSE: warning for drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev2)
URL   : https://patchwork.freedesktop.org/series/131700/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ Fi.CI.BAT: success for drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10690 bytes --]

== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev2)
URL   : https://patchwork.freedesktop.org/series/131700/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14506 -> Patchwork_131700v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/index.html

Participating hosts (37 -> 35)
------------------------------

  Additional (2): fi-bsw-nick fi-kbl-8809g 
  Missing    (4): bat-mtlp-8 bat-kbl-2 bat-adlp-6 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_131700v2:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@basic-flip-vs-modeset@a-dp6:
    - {bat-mtlp-9}:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-mtlp-9/igt@kms_flip@basic-flip-vs-modeset@a-dp6.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-mtlp-9/igt@kms_flip@basic-flip-vs-modeset@a-dp6.html

  
Known issues
------------

  Here are the changes found in Patchwork_131700v2 that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - bat-arls-3:         [PASS][3] -> [FAIL][4] ([i915#10234])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-arls-3/boot.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-arls-3/boot.html
    - bat-jsl-1:          [PASS][5] -> [FAIL][6] ([i915#8293])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-jsl-1/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-jsl-1/boot.html

  
#### Possible fixes ####

  * boot:
    - bat-dg2-11:         [FAIL][7] ([i915#10491]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-dg2-11/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-bsw-nick:        NOTRUN -> [SKIP][9] +19 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/fi-bsw-nick/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_mmap@basic:
    - bat-dg2-11:         NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@gem_mmap@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg2-11:         NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg2-11:         NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg2-11:         NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@i915_pm_rps@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - bat-dg2-11:         NOTRUN -> [SKIP][14] ([i915#4212]) +7 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-11:         NOTRUN -> [SKIP][15] ([i915#5190])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-11:         NOTRUN -> [SKIP][16] ([i915#4215] / [i915#5190])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - bat-dg2-11:         NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
    - bat-dg2-11:         NOTRUN -> [SKIP][18] ([i915#3555] / [i915#3840])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-dg2-8:          [PASS][19] -> [ABORT][20] ([i915#10476])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-dg2-8/igt@kms_force_connector_basic@force-connector-state.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-8/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg2-11:         NOTRUN -> [SKIP][21]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-dg2-11:         NOTRUN -> [SKIP][22] ([i915#5274])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg2-11:         NOTRUN -> [SKIP][23] ([i915#5354])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - bat-dg2-11:         NOTRUN -> [SKIP][24] ([i915#1072] / [i915#9732]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg2-11:         NOTRUN -> [SKIP][25] ([i915#3555])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-11:         NOTRUN -> [SKIP][26] ([i915#3708])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg2-11:         NOTRUN -> [SKIP][27] ([i915#3708] / [i915#4077]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-read:
    - bat-dg2-11:         NOTRUN -> [SKIP][28] ([i915#3291] / [i915#3708]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-dg2-11/igt@prime_vgem@basic-read.html

  * igt@runner@aborted:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][29] ([i915#4991])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/fi-kbl-8809g/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
    - {bat-mtlp-9}:       [DMESG-WARN][30] -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/bat-mtlp-9/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/bat-mtlp-9/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10234]: https://gitlab.freedesktop.org/drm/intel/issues/10234
  [i915#10435]: https://gitlab.freedesktop.org/drm/intel/issues/10435
  [i915#10476]: https://gitlab.freedesktop.org/drm/intel/issues/10476
  [i915#10491]: https://gitlab.freedesktop.org/drm/intel/issues/10491
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732


Build changes
-------------

  * Linux: CI_DRM_14506 -> Patchwork_131700v2

  CI-20190529: 20190529
  CI_DRM_14506: 98f893b726e1ba5db2680da3f9f53ab2af9780be @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7790: 5ec1ff6da3535cf80fd4e1844867d75c481ef86a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_131700v2: 98f893b726e1ba5db2680da3f9f53ab2af9780be @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

bf4912029c08 drm/i915: Optimize out redundant dbuf slice updates
95e6dc5fc7e6 drm/i915: Use a plain old int for the cdclk/mdclk ratio
0df1fc1b3993 drm/i915: Implement vblank synchronized MBUS join changes
37cb8396237d drm/i915: Use old mbus_join value when increasing CDCLK
4e8fdf5736fc drm/i915: Add debugs for mbus joining and dbuf ratio programming
e105bebb90a8 drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()
24281f8b65c8 drm/i915: Extract intel_dbuf_mbus_join_update()
9153507d9ce7 drm/i915: Relocate intel_mbus_dbox_update()
91c1e49d5497 drm/i915: Loop over all active pipes in intel_mbus_dbox_update
cb8a77abdd7a drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plane update
73363f6705ef drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks
3d160c58d21f drm/i915/cdclk: Fix voltage_level programming edge case
f6e0184e202c drm/i915/cdclk: Fix CDCLK programming order when pipes are active

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/index.html

[-- Attachment #2: Type: text/html, Size: 12241 bytes --]

Re: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:32-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Currently we always reprogram CDCLK from the
>intel_set_cdclk_pre_plane_update() when using squahs/crawl.
>The code only works correctly for the cd2x update or full
>modeset cases, and it was simply never updated to deal with
>squash/crawl.
>
>If the CDCLK frequency is increasing we must reprogram it
>before we do anything else that might depend on the new
>higher frequency, and conversely we must not decrease
>the frequency until everything that might still depend
>on the old higher frequency has been dealt with.
>
>Since cdclk_state->pipe is only relevant when doing a cd2x
>update we can't use it to determine the correct sequence
>during squash/crawl. To that end introduce cdclk_state->disable_pipes
>which simply indicates that we must perform the update
>while the pipes are disable (ie. during
>intel_set_cdclk_pre_plane_update()). Otherwise we use the
>same old vs. new CDCLK frequency comparsiong as for cd2x
>updates.
>
>The only remaining problem case is when the voltage_level
>needs to increase due to a DDI port, but the CDCLK frequency
>is decreasing (and not all pipes are being disabled). The
>current approach will not bump the voltage level up until
>after the port has already been enabled, which is too late.
>But we'll take care of that case separately.

Yep. Maybe that's another reason to have that logic detached from the
cdclk sequence in the future?

Another one mentioned in an earlier discussion[1] would be the case
where voltage level changes without changes to CDCLK.

[1] https://lore.kernel.org/intel-gfx/Zc0dygncPPX_pqIi@intel.com/

>
>v2: Don't break the "must disable pipes case"
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++++++------
> drivers/gpu/drm/i915/display/intel_cdclk.h |  3 +++
> 2 files changed, 12 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 31aaa9780dfc..619529dba095 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2600,7 +2600,6 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>                 intel_atomic_get_old_cdclk_state(state);
>         const struct intel_cdclk_state *new_cdclk_state =
>                 intel_atomic_get_new_cdclk_state(state);
>-        enum pipe pipe = new_cdclk_state->pipe;
> 
>         if (!intel_cdclk_changed(&old_cdclk_state->actual,
>                                  &new_cdclk_state->actual))
>@@ -2609,11 +2608,12 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>         if (IS_DG2(i915))
>                 intel_cdclk_pcode_pre_notify(state);
> 
>-        if (pipe == INVALID_PIPE ||
>+        if (new_cdclk_state->disable_pipes ||
>             old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
>                 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
>-                intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
>+                intel_set_cdclk(i915, &new_cdclk_state->actual,
>+                                new_cdclk_state->pipe);
>         }
> }
> 
>@@ -2632,7 +2632,6 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>                 intel_atomic_get_old_cdclk_state(state);
>         const struct intel_cdclk_state *new_cdclk_state =
>                 intel_atomic_get_new_cdclk_state(state);
>-        enum pipe pipe = new_cdclk_state->pipe;
> 
>         if (!intel_cdclk_changed(&old_cdclk_state->actual,
>                                  &new_cdclk_state->actual))
>@@ -2641,11 +2640,12 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>         if (IS_DG2(i915))
>                 intel_cdclk_pcode_post_notify(state);
> 
>-        if (pipe != INVALID_PIPE &&
>+        if (!new_cdclk_state->disable_pipes &&
>             old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
>                 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
>-                intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
>+                intel_set_cdclk(i915, &new_cdclk_state->actual,
>+                                new_cdclk_state->pipe);
>         }
> }
> 
>@@ -3124,6 +3124,7 @@ static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_globa
>                 return NULL;
> 
>         cdclk_state->pipe = INVALID_PIPE;
>+        cdclk_state->disable_pipes = false;
> 
>         return &cdclk_state->base;
> }
>@@ -3316,6 +3317,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>                 if (ret)
>                         return ret;
> 
>+                new_cdclk_state->disable_pipes = true;
>+
>                 drm_dbg_kms(&dev_priv->drm,
>                             "Modeset required for cdclk change\n");
>         }
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
>index bc8f86e292d8..2843fc091086 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>@@ -53,6 +53,9 @@ struct intel_cdclk_state {
> 
>         /* bitmask of active pipes */
>         u8 active_pipes;
>+
>+        /* update cdclk with pipes disabled */
>+        bool disable_pipes;
> };
> 
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
>-- 
>2.43.2
>

Re: [PATCH 02/13] drm/i915/cdclk: Fix voltage_level programming edge case

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:33-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Currently we only consider the relationship of the
>old and new CDCLK frequencies when determining whether
>to do the repgramming from intel_set_cdclk_pre_plane_update()
>or intel_set_cdclk_post_plane_update().
>
>It is technically possible to have a situation where the
>CDCLK frequency is decreasing, but the voltage_level is
>increasing due a DDI port. In this case we should bump
>the voltage level already in intel_set_cdclk_pre_plane_update()
>(so that the voltage_level will have been increased by the
>time the port gets enabled), while leaving the CDCLK frequency
>unchanged (as active planes/etc. may still depend on it).
>We can then reduce the CDCLK frequency to its final value
>from intel_set_cdclk_post_plane_update().
>
>In order to handle that correctly we shall construct a
>suitable amalgam of the old and new cdclk states in
>intel_set_cdclk_pre_plane_update().
>
>And we can simply call intel_set_cdclk() unconditionally
>in both places as it will not do anything if nothing actually
>changes vs. the current hw state.
>
>v2: Handle cdclk_state->disable_pipes
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 27 +++++++++++++---------
> 1 file changed, 16 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 619529dba095..504c5cbbcfff 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2600,6 +2600,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>                 intel_atomic_get_old_cdclk_state(state);
>         const struct intel_cdclk_state *new_cdclk_state =
>                 intel_atomic_get_new_cdclk_state(state);
>+        struct intel_cdclk_config cdclk_config;
> 
>         if (!intel_cdclk_changed(&old_cdclk_state->actual,
>                                  &new_cdclk_state->actual))
>@@ -2608,13 +2609,21 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>         if (IS_DG2(i915))
>                 intel_cdclk_pcode_pre_notify(state);
> 
>-        if (new_cdclk_state->disable_pipes ||
>-            old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
>-                drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
>+        if (new_cdclk_state->disable_pipes) {
>+                cdclk_config = new_cdclk_state->actual;
>+        } else {
>+                if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk)
>+                        cdclk_config = new_cdclk_state->actual;
>+                else
>+                        cdclk_config = old_cdclk_state->actual;
> 
>-                intel_set_cdclk(i915, &new_cdclk_state->actual,
>-                                new_cdclk_state->pipe);
>+                cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
>+                                                 old_cdclk_state->actual.voltage_level);
>         }
>+
>+        drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
>+
>+        intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe);

Not sure if there could be unwanted side effects with passing
new_cdclk_state->pipe when using old_cdclk_state->actual. Because
voltage_level might have changed, parts of the cdclk change sequence end
up being exercised even when cdclk_config == old_cdclk_state->actual.

Well, even if those side effects might be harmless, I wonder if it would
be better if we used INVALID_PIPE when using old_cdclk_state->actual.

--
Gustavo Sousa

> }
> 
> /**
>@@ -2640,13 +2649,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>         if (IS_DG2(i915))
>                 intel_cdclk_pcode_post_notify(state);
> 
>-        if (!new_cdclk_state->disable_pipes &&
>-            old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
>-                drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
>+        drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
>-                intel_set_cdclk(i915, &new_cdclk_state->actual,
>-                                new_cdclk_state->pipe);
>-        }
>+        intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe);
> }
> 
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>-- 
>2.43.2
>

Re: [PATCH 04/13] drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plane update

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:35-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Currently we just get a plain "Changing CDCLK to ..." in the
>logs. It would actually be interesting to see whether we're
>doing the programming during the pre or post plane phase of
>the commit. Include that information in the debug message.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++++-------------
> 1 file changed, 6 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 99d2657f29a7..98546f384023 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2434,18 +2434,9 @@ static void intel_pcode_notify(struct drm_i915_private *i915,
>                         ret);
> }
> 
>-/**
>- * intel_set_cdclk - Push the CDCLK configuration to the hardware
>- * @dev_priv: i915 device
>- * @cdclk_config: new CDCLK configuration
>- * @pipe: pipe with which to synchronize the update
>- *
>- * Program the hardware based on the passed in CDCLK state,
>- * if necessary.
>- */
> static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>                             const struct intel_cdclk_config *cdclk_config,
>-                            enum pipe pipe)
>+                            enum pipe pipe, const char *context)
> {
>         struct intel_encoder *encoder;
> 
>@@ -2455,7 +2446,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>         if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
>                 return;
> 
>-        intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
>+        intel_cdclk_dump_config(dev_priv, cdclk_config, context);
> 
>         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>@@ -2623,7 +2614,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> 
>         drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
>-        intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe);
>+        intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe,
>+                        "Pre changing CDCLK to");
> }
> 
> /**
>@@ -2651,7 +2643,8 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> 
>         drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> 
>-        intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe);
>+        intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe,
>+                        "Post changing CDCLK to");
> }
> 
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>-- 
>2.43.2
>

Re: [PATCH 11/13] drm/i915: Implement vblank synchronized MBUS join changes

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:42-03:00)
>From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
>Currently we can't change MBUS join status without doing a modeset,
>because we are lacking mechanism to synchronize those with vblank.
>However then this means that we can't do a fastset, if there is a need
>to change MBUS join state. Fix that by implementing such change.
>We already call correspondent check and update at pre_plane dbuf update,
>so the only thing left is to have a non-modeset version of that.
>If active pipes stay the same then fastset is possible and only MBUS
>join state/ddb allocation updates would be committed.
>
>The full mbus/cdclk sequence will look as follows:
>1. disable pipes
>2. increase cdclk if necessary
> 2.1 reprogram cdclk
> 2.2 update dbuf tracker value
>3. enable mbus joining if necessary
> 3.1 update mbus_ctl
> 3.2 update dbuf tracker value
>4. reallocate dbuf for planes on active pipes
>5. disable mbus joining if necessary
> 5.1 update dbuf tracker value
> 5.2 update mbus_ctl
>6. enable pipes
>7. decrease cdclk if necessary
>  7.1 update dbuf tracker value
>  7.2 reprogram cdclk
>
>And in order to keep things in sync we need:
>Step 2:
>- mbus_join == old
>- mdclk/cdclk ratio == new
>Step 3:
>- mbus_join == new
>- mdclk/cdclk ratio == old when cdclk is changing in step 7
>- mdclk/cdclk ratio == new when cdclk is changing in step 2
>Step 5:
>- mbus_join == new
>- mdclk/cdclk ratio == old when cdclk is changing in step 7
>- mdclk/cdclk ratio == new when cdclk is changing in step 2
>Step 7:
>- mbus_join == new
>- mdclk/cdclk ratio == new
>
>v2: - Removed redundant parentheses(Ville Syrjälä)
>    - Constified new_crtc_state in intel_mbus_joined_pipe(Ville Syrjälä)
>    - Removed pipe_select variable(Ville Syrjälä)
>[v3: vsyrjala: Correctly sequence vs. cdclk updates,
>               properly describe the full sequence,
>               shuffle code around to make the diff more legible,
>               streamline a few things]
>
>Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>Co-developed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c   |  11 ++
> drivers/gpu/drm/i915/display/intel_cdclk.h   |   1 +
> drivers/gpu/drm/i915/display/intel_display.c |   5 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 141 ++++++++++++-------
> drivers/gpu/drm/i915/display/skl_watermark.h |   3 +-
> 5 files changed, 112 insertions(+), 49 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 4024118a7ffb..66c161d7b485 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2576,6 +2576,17 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>                            update_cdclk, update_pipe_count);
> }
> 
>+bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
>+{
>+        const struct intel_cdclk_state *old_cdclk_state =
>+                intel_atomic_get_old_cdclk_state(state);
>+        const struct intel_cdclk_state *new_cdclk_state =
>+                intel_atomic_get_new_cdclk_state(state);
>+
>+        return new_cdclk_state && !new_cdclk_state->disable_pipes &&
>+                new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
>+}
>+
> /**
>  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
>  * @state: intel atomic state
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
>index 2843fc091086..5d4faf401774 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>@@ -69,6 +69,7 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
>                                const struct intel_cdclk_config *b);
> u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>                            const struct intel_cdclk_config *cdclk_config);
>+bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> void intel_cdclk_dump_config(struct drm_i915_private *i915,
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 4d6668a5f1ab..023cf4a77e6f 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -6915,6 +6915,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>                 intel_pre_update_crtc(state, crtc);
>         }
> 
>+        intel_dbuf_mbus_pre_ddb_update(state);
>+
>         while (update_pipes) {
>                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>                                                     new_crtc_state, i) {
>@@ -6945,6 +6947,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>                 }
>         }
> 
>+        intel_dbuf_mbus_post_ddb_update(state);
>+
>         update_pipes = modeset_pipes;
> 
>         /*
>@@ -7191,7 +7195,6 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>         intel_encoders_update_prepare(state);
> 
>         intel_dbuf_pre_plane_update(state);
>-        intel_mbus_dbox_update(state);
> 
>         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>                 if (new_crtc_state->do_async_flip)
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>index a118ecf9e532..ca0f1f89e6d9 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -2636,13 +2636,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
>                 if (ret)
>                         return ret;
> 
>-                if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
>-                        /* TODO: Implement vblank synchronized MBUS joining changes */
>-                        ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
>-                        if (ret)
>-                                return ret;
>-                }
>-
>                 drm_dbg_kms(&i915->drm,
>                             "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
>                             old_dbuf_state->enabled_slices,
>@@ -3559,7 +3552,7 @@ static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
>         return false;
> }
> 
>-void intel_mbus_dbox_update(struct intel_atomic_state *state)
>+static void intel_mbus_dbox_update(struct intel_atomic_state *state)
> {
>         struct drm_i915_private *i915 = to_i915(state->base.dev);
>         const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
>@@ -3640,6 +3633,9 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
> {
>         enum dbuf_slice slice;
> 
>+        if (!HAS_MBUS_JOINING(i915))
>+                return;
>+
>         if (DISPLAY_VER(i915) >= 20)
>                 intel_de_rmw(i915, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
>                              MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
>@@ -3663,24 +3659,42 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
>                 intel_atomic_get_old_dbuf_state(state);
>         const struct intel_dbuf_state *new_dbuf_state =
>                 intel_atomic_get_new_dbuf_state(state);
>+        int mdclk_cdclk_ratio;
> 
>-        if (DISPLAY_VER(i915) >= 20 &&
>-            old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
>-                /*
>-                 * For Xe2LPD and beyond, when there is a change in the ratio
>-                 * between MDCLK and CDCLK, updates to related registers need to
>-                 * happen at a specific point in the CDCLK change sequence. In
>-                 * that case, we defer to the call to
>-                 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
>-                 */
>-                return;
>+        if (intel_cdclk_is_decreasing_later(state)) {
>+                /* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */
>+                mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio;
>+        } else {
>+                /* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */
>+                mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio;
>         }
> 
>-        intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
>+        intel_dbuf_mdclk_cdclk_ratio_update(i915, mdclk_cdclk_ratio,
>                                             new_dbuf_state->joined_mbus);

I get the feeling that this part actually belongs to the previous patch.

--
Gustavo Sousa

> }
> 
>-static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
>+static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
>+                                        const struct intel_dbuf_state *dbuf_state)
>+{
>+        struct drm_i915_private *i915 = to_i915(state->base.dev);
>+        enum pipe pipe = ffs(dbuf_state->active_pipes) - 1;
>+        const struct intel_crtc_state *new_crtc_state;
>+        struct intel_crtc *crtc;
>+
>+        drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);
>+        drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes));
>+
>+        crtc = intel_crtc_for_pipe(i915, pipe);
>+        new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>+
>+        if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state))
>+                return pipe;
>+        else
>+                return INVALID_PIPE;
>+}
>+
>+static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state,
>+                                        enum pipe pipe)
> {
>         struct drm_i915_private *i915 = to_i915(state->base.dev);
>         const struct intel_dbuf_state *old_dbuf_state =
>@@ -3689,44 +3703,80 @@ static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
>                 intel_atomic_get_new_dbuf_state(state);
>         u32 mbus_ctl;
> 
>-        drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s\n",
>+        drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n",
>                     str_yes_no(old_dbuf_state->joined_mbus),
>-                    str_yes_no(new_dbuf_state->joined_mbus));
>+                    str_yes_no(new_dbuf_state->joined_mbus),
>+                    pipe != INVALID_PIPE ? pipe_name(pipe) : '*');
> 
>-        /*
>-         * TODO: Implement vblank synchronized MBUS joining changes.
>-         * Must be properly coordinated with dbuf reprogramming.
>-         */
>         if (new_dbuf_state->joined_mbus)
>-                mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
>-                        MBUS_JOIN_PIPE_SELECT_NONE;
>+                mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN;
>         else
>-                mbus_ctl = MBUS_HASHING_MODE_2x2 |
>-                        MBUS_JOIN_PIPE_SELECT_NONE;
>+                mbus_ctl = MBUS_HASHING_MODE_2x2;
>+
>+        if (pipe != INVALID_PIPE)
>+                mbus_ctl |= MBUS_JOIN_PIPE_SELECT(pipe);
>+        else
>+                mbus_ctl |= MBUS_JOIN_PIPE_SELECT_NONE;
> 
>         intel_de_rmw(i915, MBUS_CTL,
>                      MBUS_HASHING_MODE_MASK | MBUS_JOIN |
>                      MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
> }
> 
>-/*
>- * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>- * update the request state of all DBUS slices.
>- */
>-static void update_mbus_pre_enable(struct intel_atomic_state *state)
>+void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state)
>+{
>+        const struct intel_dbuf_state *new_dbuf_state =
>+                intel_atomic_get_new_dbuf_state(state);
>+        const struct intel_dbuf_state *old_dbuf_state =
>+                intel_atomic_get_old_dbuf_state(state);
>+
>+        if (!new_dbuf_state)
>+                return;
>+
>+        if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
>+                enum pipe pipe = intel_mbus_joined_pipe(state, new_dbuf_state);
>+
>+                WARN_ON(!new_dbuf_state->base.changed);
>+
>+                intel_dbuf_mbus_join_update(state, pipe);
>+                intel_mbus_dbox_update(state);
>+                intel_dbuf_mdclk_min_tracker_update(state);
>+        }
>+}
>+
>+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
> {
>         struct drm_i915_private *i915 = to_i915(state->base.dev);
>+        const struct intel_dbuf_state *new_dbuf_state =
>+                intel_atomic_get_new_dbuf_state(state);
>+        const struct intel_dbuf_state *old_dbuf_state =
>+                intel_atomic_get_old_dbuf_state(state);
> 
>-        if (!HAS_MBUS_JOINING(i915))
>+        if (!new_dbuf_state)
>                 return;
> 
>-        /*
>-         * TODO: Implement vblank synchronized MBUS joining changes.
>-         * Must be properly coordinated with dbuf reprogramming.
>-         */
>-        intel_dbuf_mbus_join_update(state);
>+        if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
>+                enum pipe pipe = intel_mbus_joined_pipe(state, old_dbuf_state);
>+
>+                WARN_ON(!new_dbuf_state->base.changed);
>+
>+                intel_dbuf_mdclk_min_tracker_update(state);
>+                intel_mbus_dbox_update(state);
>+                intel_dbuf_mbus_join_update(state, pipe);
>+
>+                if (pipe != INVALID_PIPE) {
>+                        struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);
>+
>+                        intel_crtc_wait_for_next_vblank(crtc);
>+                }
>+        } else if (old_dbuf_state->joined_mbus == new_dbuf_state->joined_mbus &&
>+                   old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) {
>+                WARN_ON(!new_dbuf_state->base.changed);
>+
>+                intel_dbuf_mdclk_min_tracker_update(state);
>+                intel_mbus_dbox_update(state);
>+        }
> 
>-        intel_dbuf_mdclk_min_tracker_update(state);
> }
> 
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>@@ -3738,13 +3788,11 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>                 intel_atomic_get_old_dbuf_state(state);
> 
>         if (!new_dbuf_state ||
>-            (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
>-             new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
>+            new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
>                 return;
> 
>         WARN_ON(!new_dbuf_state->base.changed);
> 
>-        update_mbus_pre_enable(state);
>         gen9_dbuf_slices_update(i915,
>                                 old_dbuf_state->enabled_slices |
>                                 new_dbuf_state->enabled_slices);
>@@ -3759,8 +3807,7 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>                 intel_atomic_get_old_dbuf_state(state);
> 
>         if (!new_dbuf_state ||
>-            (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
>-             new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
>+            new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
>                 return;
> 
>         WARN_ON(!new_dbuf_state->base.changed);
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
>index bf7516620ab6..3323a1d973f9 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.h
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
>@@ -79,7 +79,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
> void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
>-void intel_mbus_dbox_update(struct intel_atomic_state *state);
>+void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
>+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> 
> #endif /* __SKL_WATERMARK_H__ */
> 
>-- 
>2.43.2
>

Re: [PATCH 12/13] drm/i915: Use a plain old int for the cdclk/mdclk ratio

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:43-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>No point in throwing around u8 when we're dealing with
>just an integer. Use a plain old boring 'int'.

Learned and noted :-)

Thanks for fixing that.

Should we also modify the member mdclk_cdclk_ratio of intel_dbuf_state?

In any case,

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c   | 6 +++---
> drivers/gpu/drm/i915/display/intel_cdclk.h   | 4 ++--
> drivers/gpu/drm/i915/display/skl_watermark.c | 6 ++++--
> drivers/gpu/drm/i915/display/skl_watermark.h | 6 ++++--
> 4 files changed, 13 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 66c161d7b485..5cba0d08189b 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -1893,8 +1893,8 @@ static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
>         return MDCLK_SOURCE_SEL_CD2XCLK;
> }
> 
>-u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>-                           const struct intel_cdclk_config *cdclk_config)
>+int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>+                            const struct intel_cdclk_config *cdclk_config)
> {
>         if (mdclk_source_is_cdclk_pll(i915))
>                 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
>@@ -3321,7 +3321,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> 
>         if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
>             intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
>-                u8 ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
>+                int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
> 
>                 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
>                 if (ret)
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
>index 5d4faf401774..cfdcdec07a4d 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>@@ -67,8 +67,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
>                                const struct intel_cdclk_config *b);
>-u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>-                           const struct intel_cdclk_config *cdclk_config);
>+int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>+                            const struct intel_cdclk_config *cdclk_config);
> bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>index ca0f1f89e6d9..1b48009efe2b 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3616,7 +3616,8 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state)
>         }
> }
> 
>-int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio)
>+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
>+                                           int ratio)
> {
>         struct intel_dbuf_state *dbuf_state;
> 
>@@ -3629,7 +3630,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
>         return intel_atomic_lock_global_state(&dbuf_state->base);
> }
> 
>-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus)
>+void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
>+                                         int ratio, bool joined_mbus)
> {
>         enum dbuf_slice slice;
> 
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
>index 3323a1d973f9..ef1a008466be 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.h
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
>@@ -74,11 +74,13 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
>         to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
> 
> int intel_dbuf_init(struct drm_i915_private *i915);
>-int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio);
>+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
>+                                           int ratio);
> 
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
>-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
>+void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
>+                                         int ratio, bool joined_mbus);
> void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
> void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> 
>-- 
>2.43.2
>

Re: [PATCH 06/13] drm/i915: Relocate intel_mbus_dbox_update()

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:37-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>intel_mbus_dbox_update() will become static soon. Relocate it
>into a place that avoids having to add a forward declaration
>for it.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 166 +++++++++----------
> 1 file changed, 83 insertions(+), 83 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>index f582992592c1..6bd3fec0aa56 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3540,6 +3540,89 @@ int intel_dbuf_init(struct drm_i915_private *i915)
>         return 0;
> }
> 
>+static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
>+{
>+        switch (pipe) {
>+        case PIPE_A:
>+                return !(active_pipes & BIT(PIPE_D));
>+        case PIPE_D:
>+                return !(active_pipes & BIT(PIPE_A));
>+        case PIPE_B:
>+                return !(active_pipes & BIT(PIPE_C));
>+        case PIPE_C:
>+                return !(active_pipes & BIT(PIPE_B));
>+        default: /* to suppress compiler warning */
>+                MISSING_CASE(pipe);
>+                break;
>+        }
>+
>+        return false;
>+}
>+
>+void intel_mbus_dbox_update(struct intel_atomic_state *state)
>+{
>+        struct drm_i915_private *i915 = to_i915(state->base.dev);
>+        const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
>+        const struct intel_crtc *crtc;
>+        u32 val = 0;
>+
>+        if (DISPLAY_VER(i915) < 11)
>+                return;
>+
>+        new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>+        old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
>+        if (!new_dbuf_state ||
>+            (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
>+             new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
>+                return;
>+
>+        if (DISPLAY_VER(i915) >= 14)
>+                val |= MBUS_DBOX_I_CREDIT(2);
>+
>+        if (DISPLAY_VER(i915) >= 12) {
>+                val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
>+                val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
>+                val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
>+        }
>+
>+        if (DISPLAY_VER(i915) >= 14)
>+                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
>+                                                     MBUS_DBOX_A_CREDIT(8);
>+        else if (IS_ALDERLAKE_P(i915))
>+                /* Wa_22010947358:adl-p */
>+                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
>+                                                     MBUS_DBOX_A_CREDIT(4);
>+        else
>+                val |= MBUS_DBOX_A_CREDIT(2);
>+
>+        if (DISPLAY_VER(i915) >= 14) {
>+                val |= MBUS_DBOX_B_CREDIT(0xA);
>+        } else if (IS_ALDERLAKE_P(i915)) {
>+                val |= MBUS_DBOX_BW_CREDIT(2);
>+                val |= MBUS_DBOX_B_CREDIT(8);
>+        } else if (DISPLAY_VER(i915) >= 12) {
>+                val |= MBUS_DBOX_BW_CREDIT(2);
>+                val |= MBUS_DBOX_B_CREDIT(12);
>+        } else {
>+                val |= MBUS_DBOX_BW_CREDIT(1);
>+                val |= MBUS_DBOX_B_CREDIT(8);
>+        }
>+
>+        for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
>+                u32 pipe_val = val;
>+
>+                if (DISPLAY_VER(i915) >= 14) {
>+                        if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
>+                                                              new_dbuf_state->active_pipes))
>+                                pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
>+                        else
>+                                pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
>+                }
>+
>+                intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
>+        }
>+}
>+
> int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio)
> {
>         struct intel_dbuf_state *dbuf_state;
>@@ -3657,89 +3740,6 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>                                 new_dbuf_state->enabled_slices);
> }
> 
>-static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
>-{
>-        switch (pipe) {
>-        case PIPE_A:
>-                return !(active_pipes & BIT(PIPE_D));
>-        case PIPE_D:
>-                return !(active_pipes & BIT(PIPE_A));
>-        case PIPE_B:
>-                return !(active_pipes & BIT(PIPE_C));
>-        case PIPE_C:
>-                return !(active_pipes & BIT(PIPE_B));
>-        default: /* to suppress compiler warning */
>-                MISSING_CASE(pipe);
>-                break;
>-        }
>-
>-        return false;
>-}
>-
>-void intel_mbus_dbox_update(struct intel_atomic_state *state)
>-{
>-        struct drm_i915_private *i915 = to_i915(state->base.dev);
>-        const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
>-        const struct intel_crtc *crtc;
>-        u32 val = 0;
>-
>-        if (DISPLAY_VER(i915) < 11)
>-                return;
>-
>-        new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>-        old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
>-        if (!new_dbuf_state ||
>-            (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
>-             new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
>-                return;
>-
>-        if (DISPLAY_VER(i915) >= 14)
>-                val |= MBUS_DBOX_I_CREDIT(2);
>-
>-        if (DISPLAY_VER(i915) >= 12) {
>-                val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
>-                val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
>-                val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
>-        }
>-
>-        if (DISPLAY_VER(i915) >= 14)
>-                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
>-                                                     MBUS_DBOX_A_CREDIT(8);
>-        else if (IS_ALDERLAKE_P(i915))
>-                /* Wa_22010947358:adl-p */
>-                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
>-                                                     MBUS_DBOX_A_CREDIT(4);
>-        else
>-                val |= MBUS_DBOX_A_CREDIT(2);
>-
>-        if (DISPLAY_VER(i915) >= 14) {
>-                val |= MBUS_DBOX_B_CREDIT(0xA);
>-        } else if (IS_ALDERLAKE_P(i915)) {
>-                val |= MBUS_DBOX_BW_CREDIT(2);
>-                val |= MBUS_DBOX_B_CREDIT(8);
>-        } else if (DISPLAY_VER(i915) >= 12) {
>-                val |= MBUS_DBOX_BW_CREDIT(2);
>-                val |= MBUS_DBOX_B_CREDIT(12);
>-        } else {
>-                val |= MBUS_DBOX_BW_CREDIT(1);
>-                val |= MBUS_DBOX_B_CREDIT(8);
>-        }
>-
>-        for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
>-                u32 pipe_val = val;
>-
>-                if (DISPLAY_VER(i915) >= 14) {
>-                        if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
>-                                                              new_dbuf_state->active_pipes))
>-                                pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
>-                        else
>-                                pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
>-                }
>-
>-                intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
>-        }
>-}
>-
> static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
> {
>         struct drm_i915_private *i915 = m->private;
>-- 
>2.43.2
>

Re: [PATCH 07/13] drm/i915: Extract intel_dbuf_mbus_join_update()

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:38-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Extact the stuff that writes the joining bits in MBUS_CTL
>into its own function. Will help with correctly sequencing
>the operations done during mbus programming.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 37 +++++++++++++-------
> 1 file changed, 25 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>index 6bd3fec0aa56..f7e03078bd43 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3653,21 +3653,12 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
>                              DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> }
> 
>-/*
>- * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>- * update the request state of all DBUS slices.
>- */
>-static void update_mbus_pre_enable(struct intel_atomic_state *state)
>+static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> {
>         struct drm_i915_private *i915 = to_i915(state->base.dev);
>+        const struct intel_dbuf_state *new_dbuf_state =
>+                intel_atomic_get_new_dbuf_state(state);
>         u32 mbus_ctl;
>-        const struct intel_dbuf_state *old_dbuf_state =
>-                intel_atomic_get_old_dbuf_state(state);
>-        const struct intel_dbuf_state *new_dbuf_state =
>-                intel_atomic_get_new_dbuf_state(state);
>-
>-        if (!HAS_MBUS_JOINING(i915))
>-                return;
> 
>         /*
>          * TODO: Implement vblank synchronized MBUS joining changes.
>@@ -3683,6 +3674,28 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
>         intel_de_rmw(i915, MBUS_CTL,
>                      MBUS_HASHING_MODE_MASK | MBUS_JOIN |
>                      MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
>+}
>+
>+/*
>+ * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>+ * update the request state of all DBUS slices.
>+ */
>+static void update_mbus_pre_enable(struct intel_atomic_state *state)
>+{
>+        struct drm_i915_private *i915 = to_i915(state->base.dev);
>+        const struct intel_dbuf_state *old_dbuf_state =
>+                intel_atomic_get_old_dbuf_state(state);
>+        const struct intel_dbuf_state *new_dbuf_state =
>+                intel_atomic_get_new_dbuf_state(state);
>+
>+        if (!HAS_MBUS_JOINING(i915))
>+                return;
>+
>+        /*
>+         * TODO: Implement vblank synchronized MBUS joining changes.
>+         * Must be properly coordinated with dbuf reprogramming.
>+         */
>+        intel_dbuf_mbus_join_update(state);
> 
>         if (DISPLAY_VER(i915) >= 20 &&
>             old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
>-- 
>2.43.2
>

Re: [PATCH 08/13] drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:39-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Extact the stuff that writes the dbuf/mbus ration stuff
>into its own function. Will help with correctly sequencing
>the operations done during mbus programming.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 43 ++++++++++++--------
> 1 file changed, 25 insertions(+), 18 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>index f7e03078bd43..7767c5eada36 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3653,6 +3653,30 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
>                              DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> }
> 
>+static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
>+{
>+        struct drm_i915_private *i915 = to_i915(state->base.dev);
>+        const struct intel_dbuf_state *old_dbuf_state =
>+                intel_atomic_get_old_dbuf_state(state);
>+        const struct intel_dbuf_state *new_dbuf_state =
>+                intel_atomic_get_new_dbuf_state(state);
>+
>+        if (DISPLAY_VER(i915) >= 20 &&
>+            old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
>+                /*
>+                 * For Xe2LPD and beyond, when there is a change in the ratio
>+                 * between MDCLK and CDCLK, updates to related registers need to
>+                 * happen at a specific point in the CDCLK change sequence. In
>+                 * that case, we defer to the call to
>+                 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
>+                 */
>+                return;
>+        }
>+
>+        intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
>+                                            new_dbuf_state->joined_mbus);
>+}
>+
> static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> {
>         struct drm_i915_private *i915 = to_i915(state->base.dev);
>@@ -3683,10 +3707,6 @@ static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> static void update_mbus_pre_enable(struct intel_atomic_state *state)
> {
>         struct drm_i915_private *i915 = to_i915(state->base.dev);
>-        const struct intel_dbuf_state *old_dbuf_state =
>-                intel_atomic_get_old_dbuf_state(state);
>-        const struct intel_dbuf_state *new_dbuf_state =
>-                intel_atomic_get_new_dbuf_state(state);
> 
>         if (!HAS_MBUS_JOINING(i915))
>                 return;
>@@ -3697,20 +3717,7 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
>          */
>         intel_dbuf_mbus_join_update(state);
> 
>-        if (DISPLAY_VER(i915) >= 20 &&
>-            old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
>-                /*
>-                 * For Xe2LPD and beyond, when there is a change in the ratio
>-                 * between MDCLK and CDCLK, updates to related registers need to
>-                 * happen at a specific point in the CDCLK change sequence. In
>-                 * that case, we defer to the call to
>-                 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
>-                 */
>-                return;
>-        }
>-
>-        intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
>-                                            new_dbuf_state->joined_mbus);
>+        intel_dbuf_mdclk_min_tracker_update(state);
> }
> 
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>-- 
>2.43.2
>

Re: [PATCH 09/13] drm/i915: Add debugs for mbus joining and dbuf ratio programming

[Gustavo Sousa]

Quoting Ville Syrjala (2024-03-27 14:45:40-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Add some debugs so that we can actually observe what is
>actually happening during the mbus/dbuf programming steps.
>We can just shove them into fairly low level functions as
>none of them are called during any critical sections/etc.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>index 7767c5eada36..a118ecf9e532 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3647,6 +3647,9 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
>         if (joined_mbus)
>                 ratio *= 2;
> 
>+        drm_dbg_kms(&i915->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n",
>+                    ratio, str_yes_no(joined_mbus));
>+
>         for_each_dbuf_slice(i915, slice)
>                 intel_de_rmw(i915, DBUF_CTL_S(slice),
>                              DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
>@@ -3680,10 +3683,16 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
> static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> {
>         struct drm_i915_private *i915 = to_i915(state->base.dev);
>+        const struct intel_dbuf_state *old_dbuf_state =
>+                intel_atomic_get_old_dbuf_state(state);
>         const struct intel_dbuf_state *new_dbuf_state =
>                 intel_atomic_get_new_dbuf_state(state);
>         u32 mbus_ctl;
> 
>+        drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s\n",
>+                    str_yes_no(old_dbuf_state->joined_mbus),
>+                    str_yes_no(new_dbuf_state->joined_mbus));
>+
>         /*
>          * TODO: Implement vblank synchronized MBUS joining changes.
>          * Must be properly coordinated with dbuf reprogramming.
>-- 
>2.43.2
>

✓ Fi.CI.IGT: success for drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 82796 bytes --]

== Series Details ==

Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev2)
URL   : https://patchwork.freedesktop.org/series/131700/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14506_full -> Patchwork_131700v2_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_131700v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-dg1:          NOTRUN -> [SKIP][1] ([i915#8411]) +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-rkl:          NOTRUN -> [SKIP][2] ([i915#8411])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-dg1:          NOTRUN -> [SKIP][3] ([i915#7701])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@device_reset@cold-reset-bound.html
    - shard-tglu:         NOTRUN -> [SKIP][4] ([i915#7701])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@device_reset@cold-reset-bound.html

  * igt@drm_fdinfo@busy@vcs1:
    - shard-dg1:          NOTRUN -> [SKIP][5] ([i915#8414]) +4 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@drm_fdinfo@busy@vcs1.html

  * igt@drm_fdinfo@virtual-busy:
    - shard-mtlp:         NOTRUN -> [SKIP][6] ([i915#8414])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@drm_fdinfo@virtual-busy.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-mtlp:         NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-dg1:          NOTRUN -> [SKIP][8] ([i915#9323])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-tglu:         NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-dg1:          NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-mtlp:         NOTRUN -> [SKIP][11] ([i915#9323])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-mtlp:         NOTRUN -> [SKIP][12] ([i915#6335])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@gem_create@create-ext-cpu-access-big.html
    - shard-dg2:          NOTRUN -> [ABORT][13] ([i915#9846])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_create@create-ext-set-pat:
    - shard-dg1:          NOTRUN -> [SKIP][14] ([i915#8562])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_create@create-ext-set-pat.html
    - shard-tglu:         NOTRUN -> [SKIP][15] ([i915#8562])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          NOTRUN -> [SKIP][16] ([i915#280])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-dg1:          NOTRUN -> [SKIP][17] ([i915#280])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-mtlp:         NOTRUN -> [SKIP][18] ([i915#280])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          NOTRUN -> [FAIL][19] ([i915#8898])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-snb7/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-rkl:          NOTRUN -> [SKIP][20] ([i915#4525])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_balancer@sliced:
    - shard-dg1:          NOTRUN -> [SKIP][21] ([i915#4812])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_exec_balancer@sliced.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#6334])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@many-4k-incremental:
    - shard-mtlp:         NOTRUN -> [FAIL][23] ([i915#9606]) +1 other test fail
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@gem_exec_capture@many-4k-incremental.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-tglu:         NOTRUN -> [FAIL][24] ([i915#2842])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none-solo:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#4473])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@gem_exec_fair@basic-none-solo.html

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][26] ([i915#2842]) +2 other tests fail
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-glk9/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-rkl:          [PASS][27] -> [FAIL][28] ([i915#2842]) +2 other tests fail
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-rkl-4/igt@gem_exec_fair@basic-none@vcs0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share:
    - shard-dg2:          NOTRUN -> [SKIP][29] ([i915#3539] / [i915#4852]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@gem_exec_fair@basic-pace-share.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglu:         [PASS][30] -> [FAIL][31] ([i915#2842])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-5/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][32] ([i915#2842])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_fence@submit67:
    - shard-mtlp:         NOTRUN -> [SKIP][33] ([i915#4812])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@gem_exec_fence@submit67.html

  * igt@gem_exec_reloc@basic-cpu-gtt-active:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#3281]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@gem_exec_reloc@basic-cpu-gtt-active.html

  * igt@gem_exec_reloc@basic-cpu-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][35] ([i915#3281]) +10 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@gem_exec_reloc@basic-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#3281]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_exec_reloc@basic-wc-read-noreloc:
    - shard-dg1:          NOTRUN -> [SKIP][37] ([i915#3281]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_exec_reloc@basic-wc-read-noreloc.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][38] ([i915#9275])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_fenced_exec_thrash@too-many-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][39] ([i915#4860])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@gem_fenced_exec_thrash@too-many-fences.html

  * igt@gem_gtt_cpu_tlb:
    - shard-dg1:          NOTRUN -> [SKIP][40] ([i915#4077]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_gtt_cpu_tlb.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-tglu:         NOTRUN -> [SKIP][41] ([i915#4613] / [i915#7582])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-multi@lmem0:
    - shard-dg1:          NOTRUN -> [FAIL][42] ([i915#10378])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_lmem_swapping@heavy-multi@lmem0.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-rkl:          NOTRUN -> [SKIP][43] ([i915#4613]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-random@lmem0:
    - shard-dg1:          [PASS][44] -> [FAIL][45] ([i915#10378])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg1-17/igt@gem_lmem_swapping@heavy-random@lmem0.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-16/igt@gem_lmem_swapping@heavy-random@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-mtlp:         NOTRUN -> [SKIP][46] ([i915#4613]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@random:
    - shard-glk:          NOTRUN -> [SKIP][47] ([i915#4613]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-glk1/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-tglu:         NOTRUN -> [SKIP][48] ([i915#4613])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_media_vme:
    - shard-tglu:         NOTRUN -> [SKIP][49] ([i915#284])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@gem_media_vme.html

  * igt@gem_mmap@basic:
    - shard-dg1:          NOTRUN -> [SKIP][50] ([i915#4083])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_mmap@basic.html

  * igt@gem_mmap_wc@write-read:
    - shard-mtlp:         NOTRUN -> [SKIP][51] ([i915#4083]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@gem_mmap_wc@write-read.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-rkl:          NOTRUN -> [SKIP][52] ([i915#3282])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_partial_pwrite_pread@reads-snoop:
    - shard-dg1:          NOTRUN -> [SKIP][53] ([i915#3282]) +4 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_partial_pwrite_pread@reads-snoop.html

  * igt@gem_pread@exhaustion:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#3282]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#4270])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-tglu:         NOTRUN -> [SKIP][56] ([i915#4270]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#4270]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
    - shard-mtlp:         NOTRUN -> [SKIP][58] ([i915#4270]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
    - shard-dg1:          NOTRUN -> [SKIP][59] ([i915#4270]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_pxp@verify-pxp-stale-ctx-execution.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#5190] / [i915#8428])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][61] ([i915#8428]) +4 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_render_tiled_blits@basic:
    - shard-mtlp:         NOTRUN -> [SKIP][62] ([i915#4079]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@gem_render_tiled_blits@basic.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg1:          NOTRUN -> [SKIP][63] ([i915#4079]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_softpin@evict-snoop:
    - shard-mtlp:         NOTRUN -> [SKIP][64] ([i915#4885])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@gem_softpin@evict-snoop.html

  * igt@gem_tiling_max_stride:
    - shard-mtlp:         NOTRUN -> [SKIP][65] ([i915#4077]) +14 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@gem_tiling_max_stride.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][66] ([i915#3297]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-glk:          NOTRUN -> [SKIP][67] ([i915#3323])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-glk1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate:
    - shard-mtlp:         NOTRUN -> [SKIP][68] ([i915#3297])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@gem_userptr_blits@map-fixed-invalidate.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-tglu:         NOTRUN -> [SKIP][69] ([i915#3297]) +2 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          NOTRUN -> [ABORT][70] ([i915#5566])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-glk5/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-mtlp:         NOTRUN -> [SKIP][71] ([i915#2856]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-dg1:          NOTRUN -> [SKIP][72] ([i915#2527])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-tglu:         NOTRUN -> [SKIP][73] ([i915#2527] / [i915#2856])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@gen9_exec_parse@bb-secure.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-rkl:          NOTRUN -> [SKIP][74] ([i915#2527])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_module_load@load:
    - shard-mtlp:         NOTRUN -> [SKIP][75] ([i915#6227])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@i915_module_load@load.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg1:          [PASS][76] -> [ABORT][77] ([i915#9820])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg1-16/igt@i915_module_load@reload-with-fault-injection.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-13/igt@i915_module_load@reload-with-fault-injection.html
    - shard-mtlp:         [PASS][78] -> [ABORT][79] ([i915#10131] / [i915#9820])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-mtlp-8/igt@i915_module_load@reload-with-fault-injection.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
    - shard-dg2:          [PASS][80] -> [INCOMPLETE][81] ([i915#9820] / [i915#9849])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-8/igt@i915_module_load@reload-with-fault-injection.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-reset:
    - shard-tglu:         NOTRUN -> [SKIP][82] ([i915#8399]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@i915_pm_freq_api@freq-reset.html

  * igt@i915_pm_rps@min-max-config-idle:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#6621])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@i915_pm_rps@min-max-config-idle.html
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#6621])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@i915_pm_rps@min-max-config-idle.html

  * igt@i915_pm_rps@thresholds-park@gt0:
    - shard-dg1:          NOTRUN -> [SKIP][85] ([i915#8925])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@i915_pm_rps@thresholds-park@gt0.html

  * igt@i915_pm_sseu@full-enable:
    - shard-dg2:          NOTRUN -> [SKIP][86] ([i915#4387])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-tglu:         NOTRUN -> [INCOMPLETE][87] ([i915#7443])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - shard-mtlp:         NOTRUN -> [SKIP][88] ([i915#4212]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-mtlp:         NOTRUN -> [SKIP][89] ([i915#3826])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-4-rc-ccs-cc:
    - shard-mtlp:         NOTRUN -> [SKIP][90] ([i915#8709]) +11 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-4-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#8709]) +11 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg1:          NOTRUN -> [SKIP][92] ([i915#9531])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#1769] / [i915#3555])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-tglu:         NOTRUN -> [SKIP][94] ([i915#5286]) +3 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][95] ([i915#5286]) +2 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][96] ([i915#4538] / [i915#5286]) +2 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][97] +19 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
    - shard-snb:          NOTRUN -> [SKIP][98] +116 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-snb7/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][99] ([i915#3638])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][100] ([i915#3638]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         [PASS][101] -> [FAIL][102] ([i915#3743])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][103] ([i915#4538]) +2 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][104] ([i915#4538] / [i915#5190]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][105] +245 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-glk5/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][106] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-10/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][107] ([i915#10278])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][108] ([i915#10278])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][109] ([i915#6095]) +31 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#6095]) +41 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][111] ([i915#6095]) +23 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#10307] / [i915#6095]) +155 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#6095]) +59 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html

  * igt@kms_cdclk@mode-transition@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#7213]) +3 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-a-dp-4.html

  * igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][115] ([i915#4087]) +3 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#7828]) +3 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-dg1:          NOTRUN -> [SKIP][117] ([i915#7828]) +2 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#7828]) +2 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
    - shard-mtlp:         NOTRUN -> [SKIP][119] ([i915#7828]) +8 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-tglu:         NOTRUN -> [SKIP][120] ([i915#7828]) +4 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][121] ([i915#7173])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][122] ([i915#3116] / [i915#3299])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][123] ([i915#6944] / [i915#9424])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-mtlp:         NOTRUN -> [SKIP][124] ([i915#8063] / [i915#9433])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-rkl:          NOTRUN -> [SKIP][125] ([i915#7118])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@uevent:
    - shard-mtlp:         NOTRUN -> [SKIP][126] ([i915#6944] / [i915#9424]) +1 other test skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-tglu:         NOTRUN -> [SKIP][127] ([i915#3359])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@kms_cursor_crc@cursor-offscreen-512x170.html
    - shard-dg1:          NOTRUN -> [SKIP][128] ([i915#3359]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#3359]) +1 other test skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-mtlp:         NOTRUN -> [SKIP][130] ([i915#3555] / [i915#8814]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-128x42:
    - shard-mtlp:         NOTRUN -> [SKIP][131] ([i915#8814]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][132] ([i915#3555]) +2 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-mtlp:         NOTRUN -> [SKIP][133] ([i915#3359])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][134] +16 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-mtlp:         NOTRUN -> [SKIP][135] ([i915#9809]) +4 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#4103])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-mtlp:         NOTRUN -> [SKIP][137] ([i915#9833])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#9227])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-mtlp:         NOTRUN -> [SKIP][139] ([i915#8588])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dp_aux_dev:
    - shard-tglu:         NOTRUN -> [SKIP][140] ([i915#1257])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_dp_aux_dev.html

  * igt@kms_draw_crc@draw-method-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][141] ([i915#8812])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_draw_crc@draw-method-mmap-gtt.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-dg1:          NOTRUN -> [SKIP][142] ([i915#3840])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_dsc@dsc-fractional-bpp.html
    - shard-tglu:         NOTRUN -> [SKIP][143] ([i915#3840])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-tglu:         NOTRUN -> [SKIP][144] ([i915#3555] / [i915#3840]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#3555] / [i915#3840])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#3469])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@display-2x:
    - shard-mtlp:         NOTRUN -> [SKIP][147] ([i915#1839])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@psr1:
    - shard-dg1:          NOTRUN -> [SKIP][148] ([i915#658])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][149] ([i915#8381])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-dg1:          NOTRUN -> [SKIP][150] ([i915#9934]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-mtlp:         NOTRUN -> [SKIP][151] ([i915#3637]) +6 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-dg2:          NOTRUN -> [SKIP][152] +4 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1:
    - shard-dg2:          [PASS][153] -> [FAIL][154] ([i915#2122])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-10/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][155] ([i915#2587] / [i915#2672]) +1 other test skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][156] ([i915#2587] / [i915#2672])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#2672]) +2 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][158] ([i915#2672]) +2 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][159] ([i915#8810]) +1 other test skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#2672])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][161] ([i915#2672] / [i915#3555])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-mtlp:         NOTRUN -> [SKIP][162] ([i915#5274])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][163] ([i915#8708]) +6 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-dg2:          [PASS][164] -> [FAIL][165] ([i915#6880]) +2 other tests fail
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][166] ([i915#8708]) +8 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#1825]) +17 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][168] +25 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render:
    - shard-mtlp:         NOTRUN -> [SKIP][169] ([i915#1825]) +26 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][170] ([i915#10055])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#3023]) +11 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
    - shard-dg2:          NOTRUN -> [SKIP][172] ([i915#5354]) +2 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-dg1:          NOTRUN -> [SKIP][173] ([i915#3458]) +10 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][174] ([i915#3458]) +4 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][175] ([i915#8708]) +2 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][176] +62 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][177] ([i915#3555] / [i915#8228])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-mtlp:         NOTRUN -> [SKIP][178] ([i915#3555] / [i915#8228])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][179] ([i915#6301])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][180] ([i915#4573]) +1 other test fail
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-glk1/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-mtlp:         NOTRUN -> [SKIP][181] ([i915#3555] / [i915#8821])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][182] ([i915#3555] / [i915#8806])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][183] ([i915#8292])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#9423]) +5 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#9423]) +11 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][186] ([i915#5176]) +11 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers@pipe-b-edp-1.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][187] ([i915#9423]) +3 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][188] ([i915#9423]) +7 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#5176] / [i915#9423]) +1 other test skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][190] ([i915#5235]) +1 other test skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][191] ([i915#5235]) +7 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][192] ([i915#5235]) +9 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][193] ([i915#3555] / [i915#5235]) +1 other test skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-edp-1.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][194] ([i915#5235] / [i915#9423]) +11 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][195] ([i915#5235]) +7 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-13/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-3.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][196] ([i915#5354])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-mtlp:         NOTRUN -> [SKIP][197] ([i915#8430])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [PASS][198] -> [SKIP][199] ([i915#9519])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-rkl-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][200] ([i915#9519])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg2:          [PASS][201] -> [SKIP][202] ([i915#9519]) +3 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp.html
    - shard-dg1:          NOTRUN -> [SKIP][203] ([i915#9519]) +1 other test skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-mtlp:         NOTRUN -> [SKIP][204] ([i915#9519])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          NOTRUN -> [SKIP][205] ([i915#9519])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-dg2:          NOTRUN -> [SKIP][206] ([i915#6524] / [i915#6805])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-dg1:          NOTRUN -> [SKIP][207] ([i915#6524])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_prime@d3hot.html
    - shard-tglu:         NOTRUN -> [SKIP][208] ([i915#6524])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-sf@psr2-pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][209] ([i915#9808]) +3 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-sf@psr2-pipe-a-edp-1.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-mtlp:         NOTRUN -> [SKIP][210] ([i915#4348])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          NOTRUN -> [SKIP][211] ([i915#9683])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-sprite-blt:
    - shard-rkl:          NOTRUN -> [SKIP][212] ([i915#1072] / [i915#9732]) +8 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@kms_psr@fbc-pr-sprite-blt.html

  * igt@kms_psr@fbc-psr-no-drrs:
    - shard-tglu:         NOTRUN -> [SKIP][213] ([i915#9732]) +12 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@kms_psr@fbc-psr-no-drrs.html

  * igt@kms_psr@fbc-psr2-basic:
    - shard-dg2:          NOTRUN -> [SKIP][214] ([i915#1072] / [i915#9673] / [i915#9732])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_psr@fbc-psr2-basic.html

  * igt@kms_psr@fbc-psr2-sprite-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][215] ([i915#1072] / [i915#9732]) +7 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html

  * igt@kms_psr@pr-primary-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][216] ([i915#9688]) +13 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@kms_psr@pr-primary-mmap-cpu.html

  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][217] ([i915#4077] / [i915#9688])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_psr@psr-primary-mmap-gtt@edp-1.html

  * igt@kms_psr@psr2-cursor-plane-move:
    - shard-dg2:          NOTRUN -> [SKIP][218] ([i915#1072] / [i915#9732]) +4 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_psr@psr2-cursor-plane-move.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-rkl:          NOTRUN -> [SKIP][219] ([i915#9685])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-mtlp:         NOTRUN -> [SKIP][220] ([i915#4235]) +2 other tests skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-rkl:          NOTRUN -> [SKIP][221] ([i915#5289])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][222] ([i915#4235] / [i915#5190])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-dg1:          NOTRUN -> [SKIP][223] ([i915#3555]) +5 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][224] ([i915#5030]) +2 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1.html

  * igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][225] ([i915#5030] / [i915#9041])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-mtlp:         NOTRUN -> [SKIP][226] ([i915#8623])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
    - shard-tglu:         [PASS][227] -> [FAIL][228] ([i915#9196]) +1 other test fail
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html

  * igt@kms_vrr@flip-suspend:
    - shard-mtlp:         NOTRUN -> [SKIP][229] ([i915#3555] / [i915#8808])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@max-min:
    - shard-dg1:          NOTRUN -> [SKIP][230] ([i915#9906]) +2 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@kms_vrr@max-min.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-tglu:         NOTRUN -> [SKIP][231] ([i915#9906]) +1 other test skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-10/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#2437] / [i915#9412])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-mtlp:         NOTRUN -> [SKIP][233] ([i915#2437] / [i915#9412]) +1 other test skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][234] ([i915#2436])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf@mi-rpc:
    - shard-dg1:          NOTRUN -> [SKIP][235] ([i915#2434])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@perf@mi-rpc.html

  * igt@perf@non-zero-reason@0-rcs0:
    - shard-dg2:          NOTRUN -> [FAIL][236] ([i915#9100])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@perf@non-zero-reason@0-rcs0.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          NOTRUN -> [FAIL][237] ([i915#4349]) +3 other tests fail
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-rkl:          NOTRUN -> [SKIP][238] ([i915#8850])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@perf_pmu@cpu-hotplug.html

  * igt@perf_pmu@event-wait@rcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][239] ([i915#3555] / [i915#8807])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@perf_pmu@event-wait@rcs0.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-tglu:         NOTRUN -> [SKIP][240] ([i915#8516])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@basic-fence-read:
    - shard-dg1:          NOTRUN -> [SKIP][241] ([i915#3708])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][242] ([i915#3708] / [i915#4077])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@fence-read-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][243] ([i915#3708]) +1 other test skip
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@prime_vgem@fence-read-hang.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-dg1:          NOTRUN -> [SKIP][244] ([i915#9917])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@sriov_basic@bind-unbind-vf.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-rkl:          NOTRUN -> [SKIP][245] ([i915#9917])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-mtlp:         NOTRUN -> [SKIP][246] ([i915#9917])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-5/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  * igt@syncobj_timeline@invalid-wait-zero-handles:
    - shard-snb:          NOTRUN -> [FAIL][247] ([i915#9781])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-snb6/igt@syncobj_timeline@invalid-wait-zero-handles.html
    - shard-tglu:         NOTRUN -> [FAIL][248] ([i915#9781])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-2/igt@syncobj_timeline@invalid-wait-zero-handles.html

  * igt@syncobj_wait@invalid-wait-zero-handles:
    - shard-mtlp:         NOTRUN -> [FAIL][249] ([i915#9779])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-4/igt@syncobj_wait@invalid-wait-zero-handles.html

  * igt@v3d/v3d_mmap@mmap-bo:
    - shard-mtlp:         NOTRUN -> [SKIP][250] ([i915#2575]) +11 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@v3d/v3d_mmap@mmap-bo.html

  * igt@v3d/v3d_submit_cl@bad-extension:
    - shard-dg1:          NOTRUN -> [SKIP][251] ([i915#2575]) +5 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@v3d/v3d_submit_cl@bad-extension.html

  * igt@v3d/v3d_submit_cl@bad-multisync-pad:
    - shard-tglu:         NOTRUN -> [SKIP][252] ([i915#2575]) +13 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-7/igt@v3d/v3d_submit_cl@bad-multisync-pad.html

  * igt@v3d/v3d_submit_csd@bad-pad:
    - shard-dg2:          NOTRUN -> [SKIP][253] ([i915#2575]) +1 other test skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@v3d/v3d_submit_csd@bad-pad.html

  * igt@vc4/vc4_perfmon@create-perfmon-exceed:
    - shard-dg2:          NOTRUN -> [SKIP][254] ([i915#7711]) +1 other test skip
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-2/igt@vc4/vc4_perfmon@create-perfmon-exceed.html

  * igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem:
    - shard-mtlp:         NOTRUN -> [SKIP][255] ([i915#7711]) +6 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-2/igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem.html

  * igt@vc4/vc4_tiling@set-get:
    - shard-rkl:          NOTRUN -> [SKIP][256] ([i915#7711]) +3 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-3/igt@vc4/vc4_tiling@set-get.html

  * igt@vc4/vc4_wait_bo@unused-bo-0ns:
    - shard-dg1:          NOTRUN -> [SKIP][257] ([i915#7711]) +4 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-18/igt@vc4/vc4_wait_bo@unused-bo-0ns.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
    - shard-rkl:          [FAIL][258] ([i915#7742]) -> [PASS][259]
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all@rcs0.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@drm_fdinfo@most-busy-check-all@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglu:         [FAIL][260] ([i915#2842]) -> [PASS][261]
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-tglu-7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_lmem_swapping@basic@lmem0:
    - shard-dg2:          [INCOMPLETE][262] -> [PASS][263]
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-6/igt@gem_lmem_swapping@basic@lmem0.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-random@lmem0:
    - shard-dg2:          [FAIL][264] ([i915#10378]) -> [PASS][265] +2 other tests pass
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [TIMEOUT][266] ([i915#5493]) -> [PASS][267]
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-8/igt@gem_lmem_swapping@smem-oom@lmem0.html
    - shard-dg1:          [TIMEOUT][268] ([i915#5493]) -> [PASS][269]
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_mmap_offset@clear@smem0:
    - shard-mtlp:         [ABORT][270] ([i915#10029]) -> [PASS][271]
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-mtlp-7/igt@gem_mmap_offset@clear@smem0.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-8/igt@gem_mmap_offset@clear@smem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          [INCOMPLETE][272] ([i915#9849]) -> [PASS][273]
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-snb1/igt@i915_module_load@reload-with-fault-injection.html
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][274] ([i915#2521]) -> [PASS][275]
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-tglu-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         [FAIL][276] ([i915#3743]) -> [PASS][277]
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-tglu-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1:
    - shard-snb:          [FAIL][278] ([i915#2122]) -> [PASS][279]
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-snb7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-snb5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-vga1-hdmi-a1:
    - shard-snb:          [ABORT][280] -> [PASS][281]
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-snb4/igt@kms_flip@2x-flip-vs-expired-vblank@ab-vga1-hdmi-a1.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-snb2/igt@kms_flip@2x-flip-vs-expired-vblank@ab-vga1-hdmi-a1.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@c-hdmi-a4:
    - shard-dg1:          [FAIL][282] -> [PASS][283]
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg1-18/igt@kms_flip@wf_vblank-ts-check-interruptible@c-hdmi-a4.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg1-17/igt@kms_flip@wf_vblank-ts-check-interruptible@c-hdmi-a4.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          [SKIP][284] ([i915#9519]) -> [PASS][285]
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
    - shard-mtlp:         [FAIL][286] ([i915#9196]) -> [PASS][287]
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-mtlp-8/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-mtlp-1/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1:
    - shard-tglu:         [FAIL][288] ([i915#9196]) -> [PASS][289] +1 other test pass
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html

  * igt@perf_pmu@most-busy-idle-check-all@rcs0:
    - shard-rkl:          [FAIL][290] ([i915#4349]) -> [PASS][291]
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-rkl-4/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-rkl-4/igt@perf_pmu@most-busy-idle-check-all@rcs0.html

  * igt@sysfs_timeslice_duration@duration@vecs1:
    - shard-dg2:          [INCOMPLETE][292] ([i915#9252]) -> [PASS][293]
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-5/igt@sysfs_timeslice_duration@duration@vecs1.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@sysfs_timeslice_duration@duration@vecs1.html

  
#### Warnings ####

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg2:          [FAIL][294] ([i915#10446]) -> [FAIL][295] ([i915#10378])
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@kms_psr@fbc-pr-suspend:
    - shard-dg2:          [SKIP][296] ([i915#1072] / [i915#9732]) -> [SKIP][297] ([i915#1072] / [i915#9673] / [i915#9732]) +18 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14506/shard-dg2-5/igt@kms_psr@fbc-pr-suspend.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/shard-dg2-11/igt@kms_psr@fbc-pr-suspend.html

  
  [i915#10029]: https://gitlab.freedesktop.org/drm/intel/issues/10029
  [i915#10055]: https://gitlab.freedesktop.org/drm/intel/issues/10055
  [i915#10131]: https://gitlab.freedesktop.org/drm/intel/issues/10131
  [i915#10278]: https://gitlab.freedesktop.org/drm/intel/issues/10278
  [i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
  [i915#10446]: https://gitlab.freedesktop.org/drm/intel/issues/10446
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
  [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#8063]: https://gitlab.freedesktop.org/drm/intel/issues/8063
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
  [i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
  [i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
  [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
  [i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
  [i915#8807]: https://gitlab.freedesktop.org/drm/intel/issues/8807
  [i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
  [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
  [i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
  [i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
  [i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
  [i915#9041]: https://gitlab.freedesktop.org/drm/intel/issues/9041
  [i915#9100]: https://gitlab.freedesktop.org/drm/intel/issues/9100
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
  [i915#9252]: https://gitlab.freedesktop.org/drm/intel/issues/9252
  [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
  [i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
  [i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/intel/issues/9531
  [i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9779]: https://gitlab.freedesktop.org/drm/intel/issues/9779
  [i915#9781]: https://gitlab.freedesktop.org/drm/intel/issues/9781
  [i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
  [i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
  [i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
  [i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833
  [i915#9846]: https://gitlab.freedesktop.org/drm/intel/issues/9846
  [i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
  [i915#9906]: https://gitlab.freedesktop.org/drm/intel/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/intel/issues/9934


Build changes
-------------

  * Linux: CI_DRM_14506 -> Patchwork_131700v2

  CI-20190529: 20190529
  CI_DRM_14506: 98f893b726e1ba5db2680da3f9f53ab2af9780be @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7790: 5ec1ff6da3535cf80fd4e1844867d75c481ef86a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_131700v2: 98f893b726e1ba5db2680da3f9f53ab2af9780be @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131700v2/index.html

[-- Attachment #2: Type: text/html, Size: 100115 bytes --]

Re: [PATCH 11/13] drm/i915: Implement vblank synchronized MBUS join changes

[Ville Syrjälä]

On Fri, Mar 29, 2024 at 03:15:02PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-27 14:45:42-03:00)
> >@@ -3663,24 +3659,42 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
> >                 intel_atomic_get_old_dbuf_state(state);
> >         const struct intel_dbuf_state *new_dbuf_state =
> >                 intel_atomic_get_new_dbuf_state(state);
> >+        int mdclk_cdclk_ratio;
> > 
> >-        if (DISPLAY_VER(i915) >= 20 &&
> >-            old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
> >-                /*
> >-                 * For Xe2LPD and beyond, when there is a change in the ratio
> >-                 * between MDCLK and CDCLK, updates to related registers need to
> >-                 * happen at a specific point in the CDCLK change sequence. In
> >-                 * that case, we defer to the call to
> >-                 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
> >-                 */
> >-                return;
> >+        if (intel_cdclk_is_decreasing_later(state)) {
> >+                /* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */
> >+                mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio;
> >+        } else {
> >+                /* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */
> >+                mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio;
> >         }
> > 
> >-        intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
> >+        intel_dbuf_mdclk_cdclk_ratio_update(i915, mdclk_cdclk_ratio,
> >                                             new_dbuf_state->joined_mbus);
> 
> I get the feeling that this part actually belongs to the previous patch.

Hmm, right. In fact I think it can just be its own patch.
I'll carve it out.

-- 
Ville Syrjälä
Intel

Re: [PATCH 12/13] drm/i915: Use a plain old int for the cdclk/mdclk ratio

[Ville Syrjälä]

On Fri, Mar 29, 2024 at 03:23:34PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-27 14:45:43-03:00)
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >No point in throwing around u8 when we're dealing with
> >just an integer. Use a plain old boring 'int'.
> 
> Learned and noted :-)
> 
> Thanks for fixing that.
> 
> Should we also modify the member mdclk_cdclk_ratio of intel_dbuf_state?

My rule of thumb is to prefer the smallest type when embedded
in structures. Whether that's a good idea I'm not really sure.
I suppose there is always some risk of forgeting to bump up the
type size when needed.

On the other hand we do have some absolutely massive structs
(looking at you intel_crtc_state!) where trying to keep things
small and optimally packed seems like a good idea. For the
dbuf state it probably doesn't make a lick of difference.

The other case is eg. big arrays/lists of structs where I
think generally it's a good idea to minimize the size as there
the overhead is potentially multiplied by the number of elements
Otherwise these just waste unswappable kernel memory.

I suppose one argument for using small types in all structures
is consistency. People tend to cargo cult what they see so
if existing code does it then new code should end up with the
same approach. Though I suppose it might also work against us
and trick people into also using the smaller types for function
arguments and on stack variables as well.

Apart from running out of bits, the main danger with the
smaller types is C's integer promotion and arithmetic
conversion rules. I feel most people don't generally know
how those work. Eg. people see a u8 and assume everything
to do with it is unsigned, and then they might get confused
whether negative values are possible or not as a result of
some artihmetic expression. So the safest type is pretty
much the plain old 'int', and that is in fact what u8 & co.
end up being due to the aforementioned language rules.

tldr I don't really have a great answer here :/

> 
> In any case,
> 
> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

Thanks.

> 
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_cdclk.c   | 6 +++---
> > drivers/gpu/drm/i915/display/intel_cdclk.h   | 4 ++--
> > drivers/gpu/drm/i915/display/skl_watermark.c | 6 ++++--
> > drivers/gpu/drm/i915/display/skl_watermark.h | 6 ++++--
> > 4 files changed, 13 insertions(+), 9 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >index 66c161d7b485..5cba0d08189b 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >@@ -1893,8 +1893,8 @@ static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
> >         return MDCLK_SOURCE_SEL_CD2XCLK;
> > }
> > 
> >-u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> >-                           const struct intel_cdclk_config *cdclk_config)
> >+int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> >+                            const struct intel_cdclk_config *cdclk_config)
> > {
> >         if (mdclk_source_is_cdclk_pll(i915))
> >                 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
> >@@ -3321,7 +3321,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> > 
> >         if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
> >             intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
> >-                u8 ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
> >+                int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
> > 
> >                 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
> >                 if (ret)
> >diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> >index 5d4faf401774..cfdcdec07a4d 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> >+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> >@@ -67,8 +67,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> > bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> >                                const struct intel_cdclk_config *b);
> >-u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> >-                           const struct intel_cdclk_config *cdclk_config);
> >+int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> >+                            const struct intel_cdclk_config *cdclk_config);
> > bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
> > void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> > void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> >diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> >index ca0f1f89e6d9..1b48009efe2b 100644
> >--- a/drivers/gpu/drm/i915/display/skl_watermark.c
> >+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> >@@ -3616,7 +3616,8 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state)
> >         }
> > }
> > 
> >-int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio)
> >+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
> >+                                           int ratio)
> > {
> >         struct intel_dbuf_state *dbuf_state;
> > 
> >@@ -3629,7 +3630,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
> >         return intel_atomic_lock_global_state(&dbuf_state->base);
> > }
> > 
> >-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus)
> >+void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
> >+                                         int ratio, bool joined_mbus)
> > {
> >         enum dbuf_slice slice;
> > 
> >diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> >index 3323a1d973f9..ef1a008466be 100644
> >--- a/drivers/gpu/drm/i915/display/skl_watermark.h
> >+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> >@@ -74,11 +74,13 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
> >         to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
> > 
> > int intel_dbuf_init(struct drm_i915_private *i915);
> >-int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio);
> >+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
> >+                                           int ratio);
> > 
> > void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> > void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
> >-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
> >+void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
> >+                                         int ratio, bool joined_mbus);
> > void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
> > void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> > 
> >-- 
> >2.43.2
> >

-- 
Ville Syrjälä
Intel

Re: [PATCH 02/13] drm/i915/cdclk: Fix voltage_level programming edge case

[Ville Syrjälä]

On Fri, Mar 29, 2024 at 02:04:55PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-27 14:45:33-03:00)
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Currently we only consider the relationship of the
> >old and new CDCLK frequencies when determining whether
> >to do the repgramming from intel_set_cdclk_pre_plane_update()
> >or intel_set_cdclk_post_plane_update().
> >
> >It is technically possible to have a situation where the
> >CDCLK frequency is decreasing, but the voltage_level is
> >increasing due a DDI port. In this case we should bump
> >the voltage level already in intel_set_cdclk_pre_plane_update()
> >(so that the voltage_level will have been increased by the
> >time the port gets enabled), while leaving the CDCLK frequency
> >unchanged (as active planes/etc. may still depend on it).
> >We can then reduce the CDCLK frequency to its final value
> >from intel_set_cdclk_post_plane_update().
> >
> >In order to handle that correctly we shall construct a
> >suitable amalgam of the old and new cdclk states in
> >intel_set_cdclk_pre_plane_update().
> >
> >And we can simply call intel_set_cdclk() unconditionally
> >in both places as it will not do anything if nothing actually
> >changes vs. the current hw state.
> >
> >v2: Handle cdclk_state->disable_pipes
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 27 +++++++++++++---------
> > 1 file changed, 16 insertions(+), 11 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >index 619529dba095..504c5cbbcfff 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >@@ -2600,6 +2600,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> >                 intel_atomic_get_old_cdclk_state(state);
> >         const struct intel_cdclk_state *new_cdclk_state =
> >                 intel_atomic_get_new_cdclk_state(state);
> >+        struct intel_cdclk_config cdclk_config;
> > 
> >         if (!intel_cdclk_changed(&old_cdclk_state->actual,
> >                                  &new_cdclk_state->actual))
> >@@ -2608,13 +2609,21 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> >         if (IS_DG2(i915))
> >                 intel_cdclk_pcode_pre_notify(state);
> > 
> >-        if (new_cdclk_state->disable_pipes ||
> >-            old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
> >-                drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> >+        if (new_cdclk_state->disable_pipes) {
> >+                cdclk_config = new_cdclk_state->actual;
> >+        } else {
> >+                if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk)
> >+                        cdclk_config = new_cdclk_state->actual;
> >+                else
> >+                        cdclk_config = old_cdclk_state->actual;
> > 
> >-                intel_set_cdclk(i915, &new_cdclk_state->actual,
> >-                                new_cdclk_state->pipe);
> >+                cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
> >+                                                 old_cdclk_state->actual.voltage_level);
> >         }
> >+
> >+        drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> >+
> >+        intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe);
> 
> Not sure if there could be unwanted side effects with passing
> new_cdclk_state->pipe when using old_cdclk_state->actual. Because
> voltage_level might have changed, parts of the cdclk change sequence end
> up being exercised even when cdclk_config == old_cdclk_state->actual.
> 
> Well, even if those side effects might be harmless, I wonder if it would
> be better if we used INVALID_PIPE when using old_cdclk_state->actual.

Yeah. I doubt there should be any really bad side effects, but
probably a good idea to sidestep the whole question by passing
in INVALID_PIPE.

-- 
Ville Syrjälä
Intel

Re: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active

[Ville Syrjälä]

On Fri, Mar 29, 2024 at 12:29:09PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-27 14:45:32-03:00)
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Currently we always reprogram CDCLK from the
> >intel_set_cdclk_pre_plane_update() when using squahs/crawl.
> >The code only works correctly for the cd2x update or full
> >modeset cases, and it was simply never updated to deal with
> >squash/crawl.
> >
> >If the CDCLK frequency is increasing we must reprogram it
> >before we do anything else that might depend on the new
> >higher frequency, and conversely we must not decrease
> >the frequency until everything that might still depend
> >on the old higher frequency has been dealt with.
> >
> >Since cdclk_state->pipe is only relevant when doing a cd2x
> >update we can't use it to determine the correct sequence
> >during squash/crawl. To that end introduce cdclk_state->disable_pipes
> >which simply indicates that we must perform the update
> >while the pipes are disable (ie. during
> >intel_set_cdclk_pre_plane_update()). Otherwise we use the
> >same old vs. new CDCLK frequency comparsiong as for cd2x
> >updates.
> >
> >The only remaining problem case is when the voltage_level
> >needs to increase due to a DDI port, but the CDCLK frequency
> >is decreasing (and not all pipes are being disabled). The
> >current approach will not bump the voltage level up until
> >after the port has already been enabled, which is too late.
> >But we'll take care of that case separately.
> 
> Yep. Maybe that's another reason to have that logic detached from the
> cdclk sequence in the future?

Perhaps.

The cdclk sequence is typically specified as
1. request max voltage
2. change cdclk
3. request final voltage
 
We don't actually know whether step 1 has any other side effects
beyond changing the voltage. Eg. it might also do some other magic
to prepare the hardware/firmware for the cdclk change, and so we
might not be able to decouple it from the cdclk sequence 100%.
One solution could be to bump the voltage to the max in the pre
plane voltage hook whenever cdclk is also changing.

We would definitely end up spreading the voltage requests further
out from the actual cdclk programming (they'd have to be the
outermost pre/post plane hooks), which may or may not have some
other side effects as well.

-- 
Ville Syrjälä
Intel