* drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id.
@ 2023-05-12 1:20 Zhang, Jesse(Jie)
2023-05-12 13:20 ` Alex Deucher
0 siblings, 1 reply; 2+ messages in thread
From: Zhang, Jesse(Jie) @ 2023-05-12 1:20 UTC (permalink / raw)
To: Deucher, Alexander, Quan, Evan, Wang, Chester; +Cc: amd-gfx
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[AMD Official Use Only - General]
drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id.
Due to the raven2 and raven/picasso maybe have the same GC_HWIP version.
So differentiate them by revision id.
Signed-off-by: shanshengwang <shansheng.wang@amd.com<mailto:shansheng.wang@amd.com>>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com<mailto:Jesse.Zhang@amd.com>>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index e093e83ae739..1f4edfb96636 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4000,30 +4000,27 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
clock = clock_lo | (clock_hi << 32ULL);
break;
case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
preempt_disable();
- clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
- clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
- hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
- /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
- * roughly every 42 seconds.
- */
- if (hi_check != clock_hi) {
+ if (adev->rev_id >= 0x8)
+ {
+ clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
+ clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
+ hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
+ }else{
+ clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
- clock_hi = hi_check;
+ hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
}
- preempt_enable();
- clock = clock_lo | (clock_hi << 32ULL);
- break;
- case IP_VERSION(9, 2, 2):
- preempt_disable();
- clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
- clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
- hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
- * roughly every 42 seconds.
- */
+ * roughly every 42 seconds.
+ */
if (hi_check != clock_hi) {
- clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
+ if (adev->rev_id >= 0x8) {
+ clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
+ }else{
+ clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
+ }
clock_hi = hi_check;
}
preempt_enable();
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id.
2023-05-12 1:20 drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id Zhang, Jesse(Jie)
@ 2023-05-12 13:20 ` Alex Deucher
0 siblings, 0 replies; 2+ messages in thread
From: Alex Deucher @ 2023-05-12 13:20 UTC (permalink / raw)
To: Zhang, Jesse(Jie); +Cc: Deucher, Alexander, Wang, Chester, Quan, Evan, amd-gfx
Acked-by: Alex Deucher <alexander.deucher@amd.com>
On Thu, May 11, 2023 at 9:20 PM Zhang, Jesse(Jie) <Jesse.Zhang@amd.com> wrote:
>
> [AMD Official Use Only - General]
>
>
> drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id.
>
>
>
> Due to the raven2 and raven/picasso maybe have the same GC_HWIP version.
>
> So differentiate them by revision id.
>
>
>
> Signed-off-by: shanshengwang <shansheng.wang@amd.com>
>
> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
>
>
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>
> index e093e83ae739..1f4edfb96636 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>
> @@ -4000,30 +4000,27 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>
> clock = clock_lo | (clock_hi << 32ULL);
>
> break;
>
> case IP_VERSION(9, 1, 0):
>
> + case IP_VERSION(9, 2, 2):
>
> preempt_disable();
>
> - clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
>
> - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
>
> - hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
>
> - /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
>
> - * roughly every 42 seconds.
>
> - */
>
> - if (hi_check != clock_hi) {
>
> + if (adev->rev_id >= 0x8)
>
> + {
>
> + clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
>
> + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
>
> + hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
>
> + }else{
>
> + clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
>
> clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
>
> - clock_hi = hi_check;
>
> + hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
>
> }
>
> - preempt_enable();
>
> - clock = clock_lo | (clock_hi << 32ULL);
>
> - break;
>
> - case IP_VERSION(9, 2, 2):
>
> - preempt_disable();
>
> - clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
>
> - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
>
> - hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
>
> /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
>
> - * roughly every 42 seconds.
>
> - */
>
> + * roughly every 42 seconds.
>
> + */
>
> if (hi_check != clock_hi) {
>
> - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
>
> + if (adev->rev_id >= 0x8) {
>
> + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
>
> + }else{
>
> + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
>
> + }
>
> clock_hi = hi_check;
>
> }
>
> preempt_enable();
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2023-05-12 13:20 UTC | newest]
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2023-05-12 13:20 ` Alex Deucher
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