From: "Liu, Zhan" <Zhan.Liu@amd.com>
To: "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>
Cc: "Liu, Charlene" <Charlene.Liu@amd.com>,
"Kotarac, Pavle" <Pavle.Kotarac@amd.com>,
Pierre-Loup Griffais <pgriffais@valvesoftware.com>,
"Gutierrez, Agustin" <Agustin.Gutierrez@amd.com>,
"Cornij, Nikola" <Nikola.Cornij@amd.com>
Subject: [PATCH] drm/amd/display: Shorten delay time to 1us while resetting FIFO
Date: Wed, 19 Jan 2022 22:18:56 +0000 [thread overview]
Message-ID: <DM4PR12MB521400998515602D0F8AA6EA9E599@DM4PR12MB5214.namprd12.prod.outlook.com> (raw)
[AMD Official Use Only]
[Why]
Current FIFO reset delay for dcn10 is 100us, which is too long
and will fail atomic flip. As a result, there will be no display
on boot.
[How]
Shorten delay time to 1us. This also aligns with FIFO reset delay
on other ASICs.
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index bf4436d7aaab..2077c22befa5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -909,7 +909,7 @@ void enc1_stream_encoder_reset_fifo(
/* set DIG_START to 0x1 to reset FIFO */
REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
- udelay(100);
+ udelay(1);
/* write 0 to take the FIFO out of reset */
REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
--
2.25.1
next reply other threads:[~2022-01-19 22:19 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-19 22:18 Liu, Zhan [this message]
2022-01-19 22:20 ` [PATCH] drm/amd/display: Shorten delay time to 1us while resetting FIFO Alex Deucher
2022-01-19 22:23 ` Liu, Zhan
2022-01-20 2:37 ` Liu, Zhan
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