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* [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
@ 2017-07-04 18:32 Shaoyun Liu
       [not found] ` <1499193166-23187-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 5+ messages in thread
From: Shaoyun Liu @ 2017-07-04 18:32 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Shaoyun Liu

nbio hdp flush routine are called within atomic context.
Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register
since this register has its own VF copy

Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c    | 2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c    | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15_common.h | 7 +++++++
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 1e272f7..61c0028 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -67,7 +67,7 @@ void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
 
 void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
 {
-	WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+	WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 }
 
 u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index aa04632..11b70d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -65,7 +65,7 @@ void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
 
 void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
 {
-	WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+	WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 }
 
 u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index e2d330e..7a8e4e28 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -77,6 +77,13 @@ struct nbio_pcie_index_data {
 		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
 		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
 
+#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
+	WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
+		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
+		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
+		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
+		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
+
 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
 	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
 		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
       [not found] ` <1499193166-23187-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
@ 2017-07-05 13:17   ` Deucher, Alexander
       [not found]     ` <CY4PR12MB1653A95F18F717BF6C3C8107F7D40-rpdhrqHFk06apTa93KjAaQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 5+ messages in thread
From: Deucher, Alexander @ 2017-07-05 13:17 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Liu, Shaoyun

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Shaoyun Liu
> Sent: Tuesday, July 04, 2017 2:33 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun
> Subject: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
> 
> nbio hdp flush routine are called within atomic context.
> Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL
> register
> since this register has its own VF copy
> 
> Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6
> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>

Please split this patch in two, one to add the new macro, the next to convert the nbio code.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c    | 2 +-
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c    | 2 +-
>  drivers/gpu/drm/amd/amdgpu/soc15_common.h | 7 +++++++
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 1e272f7..61c0028 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -67,7 +67,7 @@ void nbio_v6_1_mc_access_enable(struct
> amdgpu_device *adev, bool enable)
> 
>  void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
>  {
> -	WREG32_SOC15(NBIO, 0,
> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +	WREG32_SOC15_NO_KIQ(NBIO, 0,
> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>  }
> 
>  u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index aa04632..11b70d6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -65,7 +65,7 @@ void nbio_v7_0_mc_access_enable(struct
> amdgpu_device *adev, bool enable)
> 
>  void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
>  {
> -	WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL,
> 0);
> +	WREG32_SOC15_NO_KIQ(NBIO, 0,
> mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>  }
> 
>  u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index e2d330e..7a8e4e28 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -77,6 +77,13 @@ struct nbio_pcie_index_data {
>  		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 +
> reg : \
>  		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> 
> +#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
> +	WREG32_NO_KIQ( (0 == reg##_BASE_IDX ?
> ip##_BASE__INST##inst##_SEG0 + reg : \
> +		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 +
> reg : \
> +		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 +
> reg : \
> +		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 +
> reg : \
> +		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> +
>  #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
>  	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0
> + reg : \
>  		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 +
> reg : \
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
       [not found]     ` <CY4PR12MB1653A95F18F717BF6C3C8107F7D40-rpdhrqHFk06apTa93KjAaQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-07-05 15:04       ` Liu, Shaoyun
       [not found]         ` <DM5PR12MB1179438AC5B0EA81D83224EDF4D40-2J9CzHegvk8p/eksZXEfgQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 5+ messages in thread
From: Liu, Shaoyun @ 2017-07-05 15:04 UTC (permalink / raw)
  To: Deucher, Alexander, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Thanks . 
Split the change as suggested and pushed . 

Regards
Shaoyun.liu

-----Original Message-----
From: Deucher, Alexander 
Sent: Wednesday, July 05, 2017 9:17 AM
To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf 
> Of Shaoyun Liu
> Sent: Tuesday, July 04, 2017 2:33 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun
> Subject: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
> 
> nbio hdp flush routine are called within atomic context.
> Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register 
> since this register has its own VF copy
> 
> Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6
> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>

Please split this patch in two, one to add the new macro, the next to convert the nbio code.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c    | 2 +-
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c    | 2 +-
>  drivers/gpu/drm/amd/amdgpu/soc15_common.h | 7 +++++++
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 1e272f7..61c0028 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -67,7 +67,7 @@ void nbio_v6_1_mc_access_enable(struct amdgpu_device 
> *adev, bool enable)
> 
>  void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)  {
> -	WREG32_SOC15(NBIO, 0,
> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +	WREG32_SOC15_NO_KIQ(NBIO, 0,
> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);  }
> 
>  u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) diff --git 
> a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index aa04632..11b70d6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -65,7 +65,7 @@ void nbio_v7_0_mc_access_enable(struct amdgpu_device 
> *adev, bool enable)
> 
>  void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)  {
> -	WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL,
> 0);
> +	WREG32_SOC15_NO_KIQ(NBIO, 0,
> mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>  }
> 
>  u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) diff --git 
> a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index e2d330e..7a8e4e28 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -77,6 +77,13 @@ struct nbio_pcie_index_data {
>  		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
>  		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> 
> +#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
> +	WREG32_NO_KIQ( (0 == reg##_BASE_IDX ?
> ip##_BASE__INST##inst##_SEG0 + reg : \
> +		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 +
> reg : \
> +		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 +
> reg : \
> +		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 +
> reg : \
> +		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> +
>  #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
>  	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0
> + reg : \
>  		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
       [not found]         ` <DM5PR12MB1179438AC5B0EA81D83224EDF4D40-2J9CzHegvk8p/eksZXEfgQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-07-05 17:15           ` Alex Deucher
       [not found]             ` <CADnq5_PY3X3Z-YTSCN5uDV+v3Z6VxqnmUTBuJ_PiUyVPm=YUPA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
  0 siblings, 1 reply; 5+ messages in thread
From: Alex Deucher @ 2017-07-05 17:15 UTC (permalink / raw)
  To: Liu, Shaoyun; +Cc: Deucher, Alexander, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

On Wed, Jul 5, 2017 at 11:04 AM, Liu, Shaoyun <Shaoyun.Liu@amd.com> wrote:
> Thanks .
> Split the change as suggested and pushed .

Doesn't look like the second patch landed yet.  I don't see in queued
in gerrit either.

Alex

>
> Regards
> Shaoyun.liu
>
> -----Original Message-----
> From: Deucher, Alexander
> Sent: Wednesday, July 05, 2017 9:17 AM
> To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun
> Subject: RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
>
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
>> Of Shaoyun Liu
>> Sent: Tuesday, July 04, 2017 2:33 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Liu, Shaoyun
>> Subject: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
>>
>> nbio hdp flush routine are called within atomic context.
>> Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register
>> since this register has its own VF copy
>>
>> Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6
>> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
>
> Please split this patch in two, one to add the new macro, the next to convert the nbio code.  With that fixed:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c    | 2 +-
>>  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c    | 2 +-
>>  drivers/gpu/drm/amd/amdgpu/soc15_common.h | 7 +++++++
>>  3 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> index 1e272f7..61c0028 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> @@ -67,7 +67,7 @@ void nbio_v6_1_mc_access_enable(struct amdgpu_device
>> *adev, bool enable)
>>
>>  void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)  {
>> -     WREG32_SOC15(NBIO, 0,
>> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>> +     WREG32_SOC15_NO_KIQ(NBIO, 0,
>> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);  }
>>
>>  u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) diff --git
>> a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> index aa04632..11b70d6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> @@ -65,7 +65,7 @@ void nbio_v7_0_mc_access_enable(struct amdgpu_device
>> *adev, bool enable)
>>
>>  void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)  {
>> -     WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL,
>> 0);
>> +     WREG32_SOC15_NO_KIQ(NBIO, 0,
>> mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>>  }
>>
>>  u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) diff --git
>> a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> index e2d330e..7a8e4e28 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> @@ -77,6 +77,13 @@ struct nbio_pcie_index_data {
>>               (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
>>               (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
>>
>> +#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
>> +     WREG32_NO_KIQ( (0 == reg##_BASE_IDX ?
>> ip##_BASE__INST##inst##_SEG0 + reg : \
>> +             (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 +
>> reg : \
>> +             (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 +
>> reg : \
>> +             (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 +
>> reg : \
>> +             (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
>> +
>>  #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
>>       WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0
>> + reg : \
>>               (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
>> --
>> 1.9.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
       [not found]             ` <CADnq5_PY3X3Z-YTSCN5uDV+v3Z6VxqnmUTBuJ_PiUyVPm=YUPA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-07-05 17:28               ` Liu, Shaoyun
  0 siblings, 0 replies; 5+ messages in thread
From: Liu, Shaoyun @ 2017-07-05 17:28 UTC (permalink / raw)
  To: Alex Deucher; +Cc: Deucher, Alexander, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Let me  try  again.

Shaoyun.liu

-----Original Message-----
From: Alex Deucher [mailto:alexdeucher@gmail.com] 
Sent: Wednesday, July 05, 2017 1:15 PM
To: Liu, Shaoyun
Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine

On Wed, Jul 5, 2017 at 11:04 AM, Liu, Shaoyun <Shaoyun.Liu@amd.com> wrote:
> Thanks .
> Split the change as suggested and pushed .

Doesn't look like the second patch landed yet.  I don't see in queued in gerrit either.

Alex

>
> Regards
> Shaoyun.liu
>
> -----Original Message-----
> From: Deucher, Alexander
> Sent: Wednesday, July 05, 2017 9:17 AM
> To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun
> Subject: RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush 
> routine
>
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On 
>> Behalf Of Shaoyun Liu
>> Sent: Tuesday, July 04, 2017 2:33 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Liu, Shaoyun
>> Subject: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
>>
>> nbio hdp flush routine are called within atomic context.
>> Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register 
>> since this register has its own VF copy
>>
>> Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6
>> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
>
> Please split this patch in two, one to add the new macro, the next to convert the nbio code.  With that fixed:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c    | 2 +-
>>  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c    | 2 +-
>>  drivers/gpu/drm/amd/amdgpu/soc15_common.h | 7 +++++++
>>  3 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> index 1e272f7..61c0028 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> @@ -67,7 +67,7 @@ void nbio_v6_1_mc_access_enable(struct 
>> amdgpu_device *adev, bool enable)
>>
>>  void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)  {
>> -     WREG32_SOC15(NBIO, 0,
>> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>> +     WREG32_SOC15_NO_KIQ(NBIO, 0,
>> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);  }
>>
>>  u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) diff --git 
>> a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> index aa04632..11b70d6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> @@ -65,7 +65,7 @@ void nbio_v7_0_mc_access_enable(struct 
>> amdgpu_device *adev, bool enable)
>>
>>  void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)  {
>> -     WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL,
>> 0);
>> +     WREG32_SOC15_NO_KIQ(NBIO, 0,
>> mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>>  }
>>
>>  u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) diff --git 
>> a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> index e2d330e..7a8e4e28 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> @@ -77,6 +77,13 @@ struct nbio_pcie_index_data {
>>               (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
>>               (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
>>
>> +#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
>> +     WREG32_NO_KIQ( (0 == reg##_BASE_IDX ?
>> ip##_BASE__INST##inst##_SEG0 + reg : \
>> +             (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 +
>> reg : \
>> +             (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 +
>> reg : \
>> +             (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 +
>> reg : \
>> +             (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
>> +
>>  #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
>>       WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0
>> + reg : \
>>               (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + 
>> reg : \
>> --
>> 1.9.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-07-05 17:28 UTC | newest]

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-- links below jump to the message on this page --
2017-07-04 18:32 [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine Shaoyun Liu
     [not found] ` <1499193166-23187-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
2017-07-05 13:17   ` Deucher, Alexander
     [not found]     ` <CY4PR12MB1653A95F18F717BF6C3C8107F7D40-rpdhrqHFk06apTa93KjAaQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-07-05 15:04       ` Liu, Shaoyun
     [not found]         ` <DM5PR12MB1179438AC5B0EA81D83224EDF4D40-2J9CzHegvk8p/eksZXEfgQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-07-05 17:15           ` Alex Deucher
     [not found]             ` <CADnq5_PY3X3Z-YTSCN5uDV+v3Z6VxqnmUTBuJ_PiUyVPm=YUPA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-05 17:28               ` Liu, Shaoyun

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