* [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 6:47 ` Xiaojie Yuan 0 siblings, 0 replies; 26+ messages in thread From: Xiaojie Yuan @ 2019-11-20 6:47 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: gang.long-5C7GfCeVMHo, jack.xiao-5C7GfCeVMHo, Xiaojie Yuan, hawking.zhang-5C7GfCeVMHo This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 6:47 ` Xiaojie Yuan 0 siblings, 0 replies; 26+ messages in thread From: Xiaojie Yuan @ 2019-11-20 6:47 UTC (permalink / raw) To: amd-gfx; +Cc: gang.long, jack.xiao, Xiaojie Yuan, hawking.zhang This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
[parent not found: <20191120064701.2765-1-xiaojie.yuan-5C7GfCeVMHo@public.gmane.org>]
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:43 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 8:43 UTC (permalink / raw) To: Yuan, Xiaojie, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 14:47 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:43 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 8:43 UTC (permalink / raw) To: Yuan, Xiaojie, amd-gfx; +Cc: Long, Gang, Xiao, Jack Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 14:47 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
[parent not found: <DM5PR12MB1418A32EB8199ABFFCCAEC04FC4F0-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:45 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 8:45 UTC (permalink / raw) To: Zhang, Hawking, Yuan, Xiaojie, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack Or in another word, we are still not clear when the corruption actually happens, right? Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking Sent: 2019年11月20日 16:44 To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 14:47 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:45 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 8:45 UTC (permalink / raw) To: Zhang, Hawking, Yuan, Xiaojie, amd-gfx; +Cc: Long, Gang, Xiao, Jack Or in another word, we are still not clear when the corruption actually happens, right? Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking Sent: 2019年11月20日 16:44 To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 14:47 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
[parent not found: <DM5PR12MB14185B32B9CB4356233E5903FC4F0-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:47 ` Christian König 0 siblings, 0 replies; 26+ messages in thread From: Christian König @ 2019-11-20 8:47 UTC (permalink / raw) To: Zhang, Hawking, Yuan, Xiaojie, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); > @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:47 ` Christian König 0 siblings, 0 replies; 26+ messages in thread From: Christian König @ 2019-11-20 8:47 UTC (permalink / raw) To: Zhang, Hawking, Yuan, Xiaojie, amd-gfx; +Cc: Long, Gang, Xiao, Jack A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); > @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <01af7844-2fbe-fd1a-5662-c8a9ec5812f0-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:54 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 8:54 UTC (permalink / raw) To: Koenig, Christian, Yuan, Xiaojie, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); > @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) > { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:54 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 8:54 UTC (permalink / raw) To: Koenig, Christian, Yuan, Xiaojie, amd-gfx; +Cc: Long, Gang, Xiao, Jack I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); > @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) > { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <DM5PR12MB141866D265D123D18E289329FC4F0-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:57 ` Christian König 0 siblings, 0 replies; 26+ messages in thread From: Christian König @ 2019-11-20 8:57 UTC (permalink / raw) To: Zhang, Hawking, Koenig, Christian, Yuan, Xiaojie, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack While the GPU is locked up? Not a good idea at all, we need the SDMA for this and that would be rather unreliable. If the content of the BO is constant we should just re-initialize it after the reset. Regards, Christian. Am 20.11.19 um 09:54 schrieb Zhang, Hawking: > I think we should evict the bo and then move it back. > > Regards, > Hawking > > -----Original Message----- > From: Christian König <ckoenig.leichtzumerken@gmail.com> > Sent: 2019年11月20日 16:47 > To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. > > Christian. > > Am 20.11.19 um 09:45 schrieb Zhang, Hawking: >> Or in another word, we are still not clear when the corruption actually happens, right? >> >> Regards, >> Hawking >> -----Original Message----- >> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of >> Zhang, Hawking >> Sent: 2019年11月20日 16:44 >> To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; >> amd-gfx@lists.freedesktop.org >> Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> >> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer >> after gpu reset >> >> Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? >> >> Regards, >> Hawking >> -----Original Message----- >> From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> >> Sent: 2019年11月20日 14:47 >> To: amd-gfx@lists.freedesktop.org >> Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack >> <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie >> <Xiaojie.Yuan@amd.com> >> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after >> gpu reset >> >> This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. >> >> clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. >> >> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- >> 1 file changed, 37 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> index 9274bd4b6c68..8e24ea08ca39 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, >> WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } >> >> -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) >> +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) >> { >> + int r; >> + >> + if (adev->in_gpu_reset) { >> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); >> + if (r) >> + return r; >> + >> + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, >> + (void **)&adev->gfx.rlc.cs_ptr); >> + if (!r) { >> + adev->gfx.rlc.funcs->get_csb_buffer(adev, >> + adev->gfx.rlc.cs_ptr); >> + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); >> + } >> + >> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); >> + if (r) >> + return r; >> + } >> + >> /* csib */ >> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, >> adev->gfx.rlc.clear_state_gpu_addr >> 32); >> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, >> adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); >> WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, >> adev->gfx.rlc.clear_state_size); >> + >> + return 0; >> } >> >> -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) >> +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) >> { >> int i; >> + int r; >> >> - gfx_v10_0_init_csb(adev); >> + r = gfx_v10_0_init_csb(adev); >> + if (r) >> + return r; >> >> for (i = 0; i < adev->num_vmhubs; i++) >> amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); >> >> /* TODO: init power gating */ >> - return; >> + return 0; >> } >> >> void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) >> r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); >> if (r) >> return r; >> - gfx_v10_0_init_pg(adev); >> + >> + r = gfx_v10_0_init_pg(adev); >> + if (r) >> + return r; >> >> /* enable RLC SRM */ >> gfx_v10_0_rlc_enable_srm(adev); >> @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) >> return r; >> } >> >> - gfx_v10_0_init_pg(adev); >> + r = gfx_v10_0_init_pg(adev); >> + if (r) >> + return r; >> + >> adev->gfx.rlc.funcs->start(adev); >> >> if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) >> { >> -- >> 2.20.1 >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:57 ` Christian König 0 siblings, 0 replies; 26+ messages in thread From: Christian König @ 2019-11-20 8:57 UTC (permalink / raw) To: Zhang, Hawking, Koenig, Christian, Yuan, Xiaojie, amd-gfx Cc: Long, Gang, Xiao, Jack While the GPU is locked up? Not a good idea at all, we need the SDMA for this and that would be rather unreliable. If the content of the BO is constant we should just re-initialize it after the reset. Regards, Christian. Am 20.11.19 um 09:54 schrieb Zhang, Hawking: > I think we should evict the bo and then move it back. > > Regards, > Hawking > > -----Original Message----- > From: Christian König <ckoenig.leichtzumerken@gmail.com> > Sent: 2019年11月20日 16:47 > To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. > > Christian. > > Am 20.11.19 um 09:45 schrieb Zhang, Hawking: >> Or in another word, we are still not clear when the corruption actually happens, right? >> >> Regards, >> Hawking >> -----Original Message----- >> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of >> Zhang, Hawking >> Sent: 2019年11月20日 16:44 >> To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; >> amd-gfx@lists.freedesktop.org >> Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> >> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer >> after gpu reset >> >> Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? >> >> Regards, >> Hawking >> -----Original Message----- >> From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> >> Sent: 2019年11月20日 14:47 >> To: amd-gfx@lists.freedesktop.org >> Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack >> <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie >> <Xiaojie.Yuan@amd.com> >> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after >> gpu reset >> >> This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. >> >> clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. >> >> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- >> 1 file changed, 37 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> index 9274bd4b6c68..8e24ea08ca39 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, >> WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } >> >> -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) >> +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) >> { >> + int r; >> + >> + if (adev->in_gpu_reset) { >> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); >> + if (r) >> + return r; >> + >> + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, >> + (void **)&adev->gfx.rlc.cs_ptr); >> + if (!r) { >> + adev->gfx.rlc.funcs->get_csb_buffer(adev, >> + adev->gfx.rlc.cs_ptr); >> + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); >> + } >> + >> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); >> + if (r) >> + return r; >> + } >> + >> /* csib */ >> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, >> adev->gfx.rlc.clear_state_gpu_addr >> 32); >> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, >> adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); >> WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, >> adev->gfx.rlc.clear_state_size); >> + >> + return 0; >> } >> >> -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) >> +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) >> { >> int i; >> + int r; >> >> - gfx_v10_0_init_csb(adev); >> + r = gfx_v10_0_init_csb(adev); >> + if (r) >> + return r; >> >> for (i = 0; i < adev->num_vmhubs; i++) >> amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); >> >> /* TODO: init power gating */ >> - return; >> + return 0; >> } >> >> void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) >> r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); >> if (r) >> return r; >> - gfx_v10_0_init_pg(adev); >> + >> + r = gfx_v10_0_init_pg(adev); >> + if (r) >> + return r; >> >> /* enable RLC SRM */ >> gfx_v10_0_rlc_enable_srm(adev); >> @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) >> return r; >> } >> >> - gfx_v10_0_init_pg(adev); >> + r = gfx_v10_0_init_pg(adev); >> + if (r) >> + return r; >> + >> adev->gfx.rlc.funcs->start(adev); >> >> if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) >> { >> -- >> 2.20.1 >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 9:00 ` Yuan, Xiaojie 0 siblings, 0 replies; 26+ messages in thread From: Yuan, Xiaojie @ 2019-11-20 9:00 UTC (permalink / raw) To: Zhang, Hawking, Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack I can try this approach as well. This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:54 PM To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); > @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) > { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 9:00 ` Yuan, Xiaojie 0 siblings, 0 replies; 26+ messages in thread From: Yuan, Xiaojie @ 2019-11-20 9:00 UTC (permalink / raw) To: Zhang, Hawking, Koenig, Christian, amd-gfx; +Cc: Long, Gang, Xiao, Jack I can try this approach as well. This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:54 PM To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); > @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) > { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <MN2PR12MB3087E12C851C8A4B9BD1E6BA894F0-rweVpJHSKTpSqPH+ASrJYAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 9:04 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 9:04 UTC (permalink / raw) To: Yuan, Xiaojie, Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack, Ma, Le I'm okay with the re-initialize and it's more straightforward approach. Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 17:00 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I can try this approach as well. This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:54 PM To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ > static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == > AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 9:04 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 9:04 UTC (permalink / raw) To: Yuan, Xiaojie, Koenig, Christian, amd-gfx; +Cc: Long, Gang, Xiao, Jack, Ma, Le I'm okay with the re-initialize and it's more straightforward approach. Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 17:00 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I can try this approach as well. This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:54 PM To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ > static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == > AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <DM5PR12MB14182D46CB31725D29877954FC4F0-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 9:09 ` Yuan, Xiaojie 0 siblings, 0 replies; 26+ messages in thread From: Yuan, Xiaojie @ 2019-11-20 9:09 UTC (permalink / raw) To: Zhang, Hawking, Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack, Ma, Le Got it. Thanks Hawking and Chris for your attention. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 5:04 PM To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack; Ma, Le Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I'm okay with the re-initialize and it's more straightforward approach. Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 17:00 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I can try this approach as well. This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:54 PM To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ > static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == > AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 9:09 ` Yuan, Xiaojie 0 siblings, 0 replies; 26+ messages in thread From: Yuan, Xiaojie @ 2019-11-20 9:09 UTC (permalink / raw) To: Zhang, Hawking, Koenig, Christian, amd-gfx; +Cc: Long, Gang, Xiao, Jack, Ma, Le Got it. Thanks Hawking and Chris for your attention. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 5:04 PM To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack; Ma, Le Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I'm okay with the re-initialize and it's more straightforward approach. Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 17:00 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I can try this approach as well. This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:54 PM To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ > static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == > AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <MN2PR12MB3087B08DD3C6F496F4F37C52894F0-rweVpJHSKTpSqPH+ASrJYAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-21 1:28 ` Quan, Evan 0 siblings, 0 replies; 26+ messages in thread From: Quan, Evan @ 2019-11-21 1:28 UTC (permalink / raw) To: Yuan, Xiaojie, Zhang, Hawking, Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack, Ma, Le Hmm, this seems an old issue which was found on gfx v9. drm/amdgpu: pin the csb buffer on hw init v2 Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. v2: fit amdgpu_bo_pin change(take one less argument) Maybe we need to find out a solution suitable for all ASICs. Regards, Evan -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Yuan, Xiaojie Sent: Wednesday, November 20, 2019 5:10 PM To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Ma, Le <Le.Ma@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Got it. Thanks Hawking and Chris for your attention. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 5:04 PM To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack; Ma, Le Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I'm okay with the re-initialize and it's more straightforward approach. Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 17:00 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I can try this approach as well. This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:54 PM To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ > static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == > AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-21 1:28 ` Quan, Evan 0 siblings, 0 replies; 26+ messages in thread From: Quan, Evan @ 2019-11-21 1:28 UTC (permalink / raw) To: Yuan, Xiaojie, Zhang, Hawking, Koenig, Christian, amd-gfx Cc: Long, Gang, Xiao, Jack, Ma, Le Hmm, this seems an old issue which was found on gfx v9. drm/amdgpu: pin the csb buffer on hw init v2 Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. v2: fit amdgpu_bo_pin change(take one less argument) Maybe we need to find out a solution suitable for all ASICs. Regards, Evan -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Yuan, Xiaojie Sent: Wednesday, November 20, 2019 5:10 PM To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Ma, Le <Le.Ma@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Got it. Thanks Hawking and Chris for your attention. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 5:04 PM To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack; Ma, Le Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I'm okay with the re-initialize and it's more straightforward approach. Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 17:00 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I can try this approach as well. This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:54 PM To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Long, Gang; Xiao, Jack Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset I think we should evict the bo and then move it back. Regards, Hawking -----Original Message----- From: Christian König <ckoenig.leichtzumerken@gmail.com> Sent: 2019年11月20日 16:47 To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. Christian. Am 20.11.19 um 09:45 schrieb Zhang, Hawking: > Or in another word, we are still not clear when the corruption actually happens, right? > > Regards, > Hawking > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Zhang, Hawking > Sent: 2019年11月20日 16:44 > To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; > amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer > after gpu reset > > Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 14:47 > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack > <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie > <Xiaojie.Yuan@amd.com> > Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after > gpu reset > > This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. > > clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. > > Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 9274bd4b6c68..8e24ea08ca39 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } > > -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) > +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) > { > + int r; > + > + if (adev->in_gpu_reset) { > + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); > + if (r) > + return r; > + > + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, > + (void **)&adev->gfx.rlc.cs_ptr); > + if (!r) { > + adev->gfx.rlc.funcs->get_csb_buffer(adev, > + adev->gfx.rlc.cs_ptr); > + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); > + } > + > + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); > + if (r) > + return r; > + } > + > /* csib */ > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, > adev->gfx.rlc.clear_state_gpu_addr >> 32); > WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, > adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); > WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, > adev->gfx.rlc.clear_state_size); > + > + return 0; > } > > -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) > +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) > { > int i; > + int r; > > - gfx_v10_0_init_csb(adev); > + r = gfx_v10_0_init_csb(adev); > + if (r) > + return r; > > for (i = 0; i < adev->num_vmhubs; i++) > amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); > > /* TODO: init power gating */ > - return; > + return 0; > } > > void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); > if (r) > return r; > - gfx_v10_0_init_pg(adev); > + > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > > /* enable RLC SRM */ > gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ > static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) > return r; > } > > - gfx_v10_0_init_pg(adev); > + r = gfx_v10_0_init_pg(adev); > + if (r) > + return r; > + > adev->gfx.rlc.funcs->start(adev); > > if (adev->firmware.load_type == > AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <MN2PR12MB3344E669C43F9B6577D60AA8E44E0-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-21 2:26 ` Yuan, Xiaojie 0 siblings, 0 replies; 26+ messages in thread From: Yuan, Xiaojie @ 2019-11-21 2:26 UTC (permalink / raw) To: Quan, Evan Cc: Long, Gang, Xiao, Jack, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Ma, Le, Koenig, Christian, Zhang, Hawking Hi Evan, Yes, I know this commit, but the reason for csb corruption is different. The fix you mentioned is for suspend code path when bo is not unpinned at fini time. Then it is not evicted (resides in vram) and corrupts because of vram power down. For gpu reset code path, bos are not evicted, so we need to re-init csb. BR, Xiaojie > On Nov 21, 2019, at 9:28 AM, Quan, Evan <Evan.Quan@amd.com> wrote: > > Hmm, this seems an old issue which was found on gfx v9. > > drm/amdgpu: pin the csb buffer on hw init v2 > > Without this pin, the csb buffer will be filled with inconsistent > data after S3 resume. And that will causes gfx hang on gfxoff > exit since this csb will be executed then. > > v2: fit amdgpu_bo_pin change(take one less argument) > > Maybe we need to find out a solution suitable for all ASICs. > > Regards, > Evan > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Yuan, Xiaojie > Sent: Wednesday, November 20, 2019 5:10 PM > To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Ma, Le <Le.Ma@amd.com> > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > Got it. > Thanks Hawking and Chris for your attention. > > BR, > Xiaojie > > ________________________________________ > From: Zhang, Hawking <Hawking.Zhang@amd.com> > Sent: Wednesday, November 20, 2019 5:04 PM > To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org > Cc: Long, Gang; Xiao, Jack; Ma, Le > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > I'm okay with the re-initialize and it's more straightforward approach. > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 17:00 > To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > I can try this approach as well. > This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. > > BR, > Xiaojie > > ________________________________________ > From: Zhang, Hawking <Hawking.Zhang@amd.com> > Sent: Wednesday, November 20, 2019 4:54 PM > To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org > Cc: Long, Gang; Xiao, Jack > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > I think we should evict the bo and then move it back. > > Regards, > Hawking > > -----Original Message----- > From: Christian König <ckoenig.leichtzumerken@gmail.com> > Sent: 2019年11月20日 16:47 > To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. > > Christian. > >> Am 20.11.19 um 09:45 schrieb Zhang, Hawking: >> Or in another word, we are still not clear when the corruption actually happens, right? >> >> Regards, >> Hawking >> -----Original Message----- >> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of >> Zhang, Hawking >> Sent: 2019年11月20日 16:44 >> To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; >> amd-gfx@lists.freedesktop.org >> Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> >> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer >> after gpu reset >> >> Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? >> >> Regards, >> Hawking >> -----Original Message----- >> From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> >> Sent: 2019年11月20日 14:47 >> To: amd-gfx@lists.freedesktop.org >> Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack >> <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie >> <Xiaojie.Yuan@amd.com> >> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after >> gpu reset >> >> This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. >> >> clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. >> >> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- >> 1 file changed, 37 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> index 9274bd4b6c68..8e24ea08ca39 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, >> WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } >> >> -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) >> +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) >> { >> + int r; >> + >> + if (adev->in_gpu_reset) { >> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); >> + if (r) >> + return r; >> + >> + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, >> + (void **)&adev->gfx.rlc.cs_ptr); >> + if (!r) { >> + adev->gfx.rlc.funcs->get_csb_buffer(adev, >> + adev->gfx.rlc.cs_ptr); >> + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); >> + } >> + >> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); >> + if (r) >> + return r; >> + } >> + >> /* csib */ >> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, >> adev->gfx.rlc.clear_state_gpu_addr >> 32); >> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, >> adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); >> WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, >> adev->gfx.rlc.clear_state_size); >> + >> + return 0; >> } >> >> -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) >> +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) >> { >> int i; >> + int r; >> >> - gfx_v10_0_init_csb(adev); >> + r = gfx_v10_0_init_csb(adev); >> + if (r) >> + return r; >> >> for (i = 0; i < adev->num_vmhubs; i++) >> amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); >> >> /* TODO: init power gating */ >> - return; >> + return 0; >> } >> >> void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) >> r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); >> if (r) >> return r; >> - gfx_v10_0_init_pg(adev); >> + >> + r = gfx_v10_0_init_pg(adev); >> + if (r) >> + return r; >> >> /* enable RLC SRM */ >> gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ >> static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) >> return r; >> } >> >> - gfx_v10_0_init_pg(adev); >> + r = gfx_v10_0_init_pg(adev); >> + if (r) >> + return r; >> + >> adev->gfx.rlc.funcs->start(adev); >> >> if (adev->firmware.load_type == >> AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { >> -- >> 2.20.1 >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-21 2:26 ` Yuan, Xiaojie 0 siblings, 0 replies; 26+ messages in thread From: Yuan, Xiaojie @ 2019-11-21 2:26 UTC (permalink / raw) To: Quan, Evan Cc: Long, Gang, Xiao, Jack, amd-gfx, Ma, Le, Koenig, Christian, Zhang, Hawking Hi Evan, Yes, I know this commit, but the reason for csb corruption is different. The fix you mentioned is for suspend code path when bo is not unpinned at fini time. Then it is not evicted (resides in vram) and corrupts because of vram power down. For gpu reset code path, bos are not evicted, so we need to re-init csb. BR, Xiaojie > On Nov 21, 2019, at 9:28 AM, Quan, Evan <Evan.Quan@amd.com> wrote: > > Hmm, this seems an old issue which was found on gfx v9. > > drm/amdgpu: pin the csb buffer on hw init v2 > > Without this pin, the csb buffer will be filled with inconsistent > data after S3 resume. And that will causes gfx hang on gfxoff > exit since this csb will be executed then. > > v2: fit amdgpu_bo_pin change(take one less argument) > > Maybe we need to find out a solution suitable for all ASICs. > > Regards, > Evan > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Yuan, Xiaojie > Sent: Wednesday, November 20, 2019 5:10 PM > To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Ma, Le <Le.Ma@amd.com> > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > Got it. > Thanks Hawking and Chris for your attention. > > BR, > Xiaojie > > ________________________________________ > From: Zhang, Hawking <Hawking.Zhang@amd.com> > Sent: Wednesday, November 20, 2019 5:04 PM > To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org > Cc: Long, Gang; Xiao, Jack; Ma, Le > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > I'm okay with the re-initialize and it's more straightforward approach. > > Regards, > Hawking > -----Original Message----- > From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> > Sent: 2019年11月20日 17:00 > To: Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > I can try this approach as well. > This csb is similar to the kiq mqd which are allocated in vram and might corrupt after baco reset. > > BR, > Xiaojie > > ________________________________________ > From: Zhang, Hawking <Hawking.Zhang@amd.com> > Sent: Wednesday, November 20, 2019 4:54 PM > To: Koenig, Christian; Yuan, Xiaojie; amd-gfx@lists.freedesktop.org > Cc: Long, Gang; Xiao, Jack > Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > I think we should evict the bo and then move it back. > > Regards, > Hawking > > -----Original Message----- > From: Christian König <ckoenig.leichtzumerken@gmail.com> > Sent: 2019年11月20日 16:47 > To: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> > Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset > > A baco reset also resets the MC, doesn't it? n this case it would be expected that the content of VRAM is corrupted. > > Christian. > >> Am 20.11.19 um 09:45 schrieb Zhang, Hawking: >> Or in another word, we are still not clear when the corruption actually happens, right? >> >> Regards, >> Hawking >> -----Original Message----- >> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of >> Zhang, Hawking >> Sent: 2019年11月20日 16:44 >> To: Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; >> amd-gfx@lists.freedesktop.org >> Cc: Long, Gang <Gang.Long@amd.com>; Xiao, Jack <Jack.Xiao@amd.com> >> Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer >> after gpu reset >> >> Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? >> >> Regards, >> Hawking >> -----Original Message----- >> From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> >> Sent: 2019年11月20日 14:47 >> To: amd-gfx@lists.freedesktop.org >> Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack >> <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie >> <Xiaojie.Yuan@amd.com> >> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after >> gpu reset >> >> This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. >> >> clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. >> >> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- >> 1 file changed, 37 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> index 9274bd4b6c68..8e24ea08ca39 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c >> @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, >> WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } >> >> -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) >> +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) >> { >> + int r; >> + >> + if (adev->in_gpu_reset) { >> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); >> + if (r) >> + return r; >> + >> + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, >> + (void **)&adev->gfx.rlc.cs_ptr); >> + if (!r) { >> + adev->gfx.rlc.funcs->get_csb_buffer(adev, >> + adev->gfx.rlc.cs_ptr); >> + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); >> + } >> + >> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); >> + if (r) >> + return r; >> + } >> + >> /* csib */ >> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, >> adev->gfx.rlc.clear_state_gpu_addr >> 32); >> WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, >> adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); >> WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, >> adev->gfx.rlc.clear_state_size); >> + >> + return 0; >> } >> >> -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) >> +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) >> { >> int i; >> + int r; >> >> - gfx_v10_0_init_csb(adev); >> + r = gfx_v10_0_init_csb(adev); >> + if (r) >> + return r; >> >> for (i = 0; i < adev->num_vmhubs; i++) >> amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); >> >> /* TODO: init power gating */ >> - return; >> + return 0; >> } >> >> void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) >> r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); >> if (r) >> return r; >> - gfx_v10_0_init_pg(adev); >> + >> + r = gfx_v10_0_init_pg(adev); >> + if (r) >> + return r; >> >> /* enable RLC SRM */ >> gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ >> static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) >> return r; >> } >> >> - gfx_v10_0_init_pg(adev); >> + r = gfx_v10_0_init_pg(adev); >> + if (r) >> + return r; >> + >> adev->gfx.rlc.funcs->start(adev); >> >> if (adev->firmware.load_type == >> AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { >> -- >> 2.20.1 >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:56 ` Yuan, Xiaojie 0 siblings, 0 replies; 26+ messages in thread From: Yuan, Xiaojie @ 2019-11-20 8:56 UTC (permalink / raw) To: Zhang, Hawking, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack Hi Hawking, This is a formal fix I think. As you suggested, I tried to dump csb in various locations in gpu reset sequence: 1. after gfx_v10_0_hw_fini() completes - csb still contains correct data | v baco reset | v 2. right after gmc resume - csb contains corrupted data In this small time window, no firmware touches csb and it should prove that vram lost causes csb corrupt. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:43 PM To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Xiao, Jack; Long, Gang Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 14:47 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 8:56 ` Yuan, Xiaojie 0 siblings, 0 replies; 26+ messages in thread From: Yuan, Xiaojie @ 2019-11-20 8:56 UTC (permalink / raw) To: Zhang, Hawking, amd-gfx; +Cc: Long, Gang, Xiao, Jack Hi Hawking, This is a formal fix I think. As you suggested, I tried to dump csb in various locations in gpu reset sequence: 1. after gfx_v10_0_hw_fini() completes - csb still contains correct data | v baco reset | v 2. right after gmc resume - csb contains corrupted data In this small time window, no firmware touches csb and it should prove that vram lost causes csb corrupt. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:43 PM To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Xiao, Jack; Long, Gang Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 14:47 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
[parent not found: <MN2PR12MB308747C45983374E17E1BD17894F0-rweVpJHSKTpSqPH+ASrJYAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 9:03 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 9:03 UTC (permalink / raw) To: Yuan, Xiaojie, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Long, Gang, Xiao, Jack I see. Thanks for the clarifying. The patch is Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 16:56 To: Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org Cc: Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Hi Hawking, This is a formal fix I think. As you suggested, I tried to dump csb in various locations in gpu reset sequence: 1. after gfx_v10_0_hw_fini() completes - csb still contains correct data | v baco reset | v 2. right after gmc resume - csb contains corrupted data In this small time window, no firmware touches csb and it should prove that vram lost causes csb corrupt. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:43 PM To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Xiao, Jack; Long, Gang Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 14:47 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset @ 2019-11-20 9:03 ` Zhang, Hawking 0 siblings, 0 replies; 26+ messages in thread From: Zhang, Hawking @ 2019-11-20 9:03 UTC (permalink / raw) To: Yuan, Xiaojie, amd-gfx; +Cc: Long, Gang, Xiao, Jack I see. Thanks for the clarifying. The patch is Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 16:56 To: Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org Cc: Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com> Subject: Re: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Hi Hawking, This is a formal fix I think. As you suggested, I tried to dump csb in various locations in gpu reset sequence: 1. after gfx_v10_0_hw_fini() completes - csb still contains correct data | v baco reset | v 2. right after gmc resume - csb contains corrupted data In this small time window, no firmware touches csb and it should prove that vram lost causes csb corrupt. BR, Xiaojie ________________________________________ From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Wednesday, November 20, 2019 4:43 PM To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org Cc: Xiao, Jack; Long, Gang Subject: RE: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Just make sure I understand you correctly. So until fw team root cause the reason of csb corruption, we keep the workaround in driver, correct? Regards, Hawking -----Original Message----- From: Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Sent: 2019年11月20日 14:47 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Long, Gang <Gang.Long@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com> Subject: [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 9274bd4b6c68..8e24ea08ca39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } -static void gfx_v10_0_init_csb(struct amdgpu_device *adev) +static int gfx_v10_0_init_csb(struct amdgpu_device *adev) { + int r; + + if (adev->in_gpu_reset) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (r) + return r; + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, + (void **)&adev->gfx.rlc.cs_ptr); + if (!r) { + adev->gfx.rlc.funcs->get_csb_buffer(adev, + adev->gfx.rlc.cs_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + } + + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + if (r) + return r; + } + /* csib */ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, adev->gfx.rlc.clear_state_gpu_addr >> 32); WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; } -static void gfx_v10_0_init_pg(struct amdgpu_device *adev) +static int gfx_v10_0_init_pg(struct amdgpu_device *adev) { int i; + int r; - gfx_v10_0_init_csb(adev); + r = gfx_v10_0_init_csb(adev); + if (r) + return r; for (i = 0; i < adev->num_vmhubs; i++) amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); /* TODO: init power gating */ - return; + return 0; } void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) @@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); if (r) return r; - gfx_v10_0_init_pg(adev); + + r = gfx_v10_0_init_pg(adev); + if (r) + return r; /* enable RLC SRM */ gfx_v10_0_rlc_enable_srm(adev); @@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) return r; } - gfx_v10_0_init_pg(adev); + r = gfx_v10_0_init_pg(adev); + if (r) + return r; + adev->gfx.rlc.funcs->start(adev); if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
end of thread, other threads:[~2019-11-21 2:26 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
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2019-11-20 6:47 [PATCH] drm/amdgpu/gfx10: re-init clear state buffer after gpu reset Xiaojie Yuan
2019-11-20 6:47 ` Xiaojie Yuan
[not found] ` <20191120064701.2765-1-xiaojie.yuan-5C7GfCeVMHo@public.gmane.org>
2019-11-20 8:43 ` Zhang, Hawking
2019-11-20 8:43 ` Zhang, Hawking
[not found] ` <DM5PR12MB1418A32EB8199ABFFCCAEC04FC4F0-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-20 8:45 ` Zhang, Hawking
2019-11-20 8:45 ` Zhang, Hawking
[not found] ` <DM5PR12MB14185B32B9CB4356233E5903FC4F0-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-20 8:47 ` Christian König
2019-11-20 8:47 ` Christian König
[not found] ` <01af7844-2fbe-fd1a-5662-c8a9ec5812f0-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-11-20 8:54 ` Zhang, Hawking
2019-11-20 8:54 ` Zhang, Hawking
[not found] ` <DM5PR12MB141866D265D123D18E289329FC4F0-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-20 8:57 ` Christian König
2019-11-20 8:57 ` Christian König
2019-11-20 9:00 ` Yuan, Xiaojie
2019-11-20 9:00 ` Yuan, Xiaojie
[not found] ` <MN2PR12MB3087E12C851C8A4B9BD1E6BA894F0-rweVpJHSKTpSqPH+ASrJYAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-20 9:04 ` Zhang, Hawking
2019-11-20 9:04 ` Zhang, Hawking
[not found] ` <DM5PR12MB14182D46CB31725D29877954FC4F0-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-20 9:09 ` Yuan, Xiaojie
2019-11-20 9:09 ` Yuan, Xiaojie
[not found] ` <MN2PR12MB3087B08DD3C6F496F4F37C52894F0-rweVpJHSKTpSqPH+ASrJYAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-21 1:28 ` Quan, Evan
2019-11-21 1:28 ` Quan, Evan
[not found] ` <MN2PR12MB3344E669C43F9B6577D60AA8E44E0-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-21 2:26 ` Yuan, Xiaojie
2019-11-21 2:26 ` Yuan, Xiaojie
2019-11-20 8:56 ` Yuan, Xiaojie
2019-11-20 8:56 ` Yuan, Xiaojie
[not found] ` <MN2PR12MB308747C45983374E17E1BD17894F0-rweVpJHSKTpSqPH+ASrJYAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-20 9:03 ` Zhang, Hawking
2019-11-20 9:03 ` Zhang, Hawking
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