[PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Cui, Flora]

1. skip test if there's no desired ring
2. clear shader buffer
3. update command buffer for gfx9

Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36
Signed-off-by: Flora Cui <flora.cui@amd.com>
---
 tests/amdgpu/basic_tests.c | 36 ++++++++++++++++++++++++++++--------
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 2d47269..8fa7088 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -329,14 +329,15 @@ static const uint32_t preamblecache_gfx9[] = {
 	0xc0016900, 0x2d5, 0x10000, 0xc0016900,  0x2dc, 0x0,
 	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
 	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
-	0xc0026900, 0x311,  0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
+	0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20,
 	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
 	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
 	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
 	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
 	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
 	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
-	0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
+	0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
+	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
 	0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0,
 	0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0,
 	0xc0017900, 0x24b, 0x0
@@ -450,7 +451,7 @@ static const uint32_t cached_cmd_gfx9[] = {
 	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
 	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
 	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
-	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
+	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x1a,
 	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
 	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
 	0xc0026900, 0x292, 0x20, 0x60201b8,
@@ -2094,10 +2095,7 @@ static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t ip_type)
 	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
 	ptr[i++] = 0x204;
 	i += 3;
-	/* clear mmCOMPUTE_RESOURCE_LIMITS */
-	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
-	ptr[i++] = 0x215;
-	ptr[i++] = 0;
+
 	/* clear mmCOMPUTE_TMPRING_SIZE */
 	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
 	ptr[i++] = 0x218;
@@ -2184,6 +2182,7 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
 					&bo_shader, &ptr_shader,
 					&mc_address_shader, &va_shader);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_shader, 0, bo_shader_size);
 
 	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
 	CU_ASSERT_EQUAL(r, 0);
@@ -2220,6 +2219,11 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
 	ptr_cmd[i++] = 0x22222222;
 	ptr_cmd[i++] = 0x22222222;
 
+	/* clear mmCOMPUTE_RESOURCE_LIMITS */
+	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+	ptr_cmd[i++] = 0x215;
+	ptr_cmd[i++] = 0;
+
 	/* dispatch direct command */
 	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
 	ptr_cmd[i++] = 0x10;
@@ -2321,6 +2325,7 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
 					&bo_shader, &ptr_shader,
 					&mc_address_shader, &va_shader);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_shader, 0, bo_shader_size);
 
 	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
 	CU_ASSERT_EQUAL(r, 0);
@@ -2365,6 +2370,11 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
 	ptr_cmd[i++] = 0x400;
 	ptr_cmd[i++] = 0x74fac;
 
+	/* clear mmCOMPUTE_RESOURCE_LIMITS */
+	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+	ptr_cmd[i++] = 0x215;
+	ptr_cmd[i++] = 0;
+
 	/* dispatch direct command */
 	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
 	ptr_cmd[i++] = 0x10;
@@ -2438,6 +2448,8 @@ static void amdgpu_dispatch_test(void)
 
 	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info);
 	CU_ASSERT_EQUAL(r, 0);
+	if (!info.available_rings)
+		printf("SKIP ... as there's no compute ring\n");
 
 	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
 		amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
@@ -2446,6 +2458,8 @@ static void amdgpu_dispatch_test(void)
 
 	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
 	CU_ASSERT_EQUAL(r, 0);
+	if (!info.available_rings)
+		printf("SKIP ... as there's no graphics ring\n");
 
 	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
 		amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
@@ -2901,12 +2915,14 @@ static void amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
 					&bo_shader_ps, &ptr_shader_ps,
 					&mc_address_shader_ps, &va_shader_ps);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_shader_ps, 0, bo_shader_size);
 
 	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
 					AMDGPU_GEM_DOMAIN_VRAM, 0,
 					&bo_shader_vs, &ptr_shader_vs,
 					&mc_address_shader_vs, &va_shader_vs);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_shader_vs, 0, bo_shader_size);
 
 	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
 	CU_ASSERT_EQUAL(r, 0);
@@ -2996,7 +3012,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
 	ptr_cmd[i++] = 0x92;
 	i += 3;
 
-	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 1);
+	ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
 	ptr_cmd[i++] = 0x191;
 	ptr_cmd[i++] = 0;
 
@@ -3074,12 +3090,14 @@ static void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t
 					&bo_shader_ps, &ptr_shader_ps,
 					&mc_address_shader_ps, &va_shader_ps);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_shader_ps, 0, bo_shader_size);
 
 	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
 					AMDGPU_GEM_DOMAIN_VRAM, 0,
 					&bo_shader_vs, &ptr_shader_vs,
 					&mc_address_shader_vs, &va_shader_vs);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_shader_vs, 0, bo_shader_size);
 
 	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX);
 	CU_ASSERT_EQUAL(r, 0);
@@ -3105,6 +3123,8 @@ static void amdgpu_draw_test(void)
 
 	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
 	CU_ASSERT_EQUAL(r, 0);
+	if (!info.available_rings)
+		printf("SKIP ... as there's no graphics ring\n");
 
 	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
 		amdgpu_memset_draw_test(device_handle, ring_id);
-- 
2.7.4

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[PATCH libdrm 2/2] tests/amdgpu: add gpu reset test

[Cui, Flora]

1. perform gpu reset
2. perform dispatch test to verify gpu reset to a good state

Change-Id: I4bba0d1b829288bba7b6885d7e68c8f69ef8f4b5
Signed-off-by: Flora Cui <flora.cui@amd.com>
---
 tests/amdgpu/amdgpu_test.c |  5 +++++
 tests/amdgpu/basic_tests.c | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 73403fb..0c9364a 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -472,6 +472,11 @@ static void amdgpu_disable_suites()
 	if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
 		if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test", CU_FALSE))
 			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
+
+	/* This test was ran on GFX9 only */
+	if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
+		if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", CU_FALSE))
+			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
 }
 
 /* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 8fa7088..c04df8b 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -24,6 +24,9 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
 #ifdef HAVE_ALLOCA_H
 # include <alloca.h>
 #endif
@@ -51,6 +54,7 @@ static void amdgpu_sync_dependency_test(void);
 static void amdgpu_bo_eviction_test(void);
 static void amdgpu_dispatch_test(void);
 static void amdgpu_draw_test(void);
+static void amdgpu_gpu_reset_test(void);
 
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
 static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -74,6 +78,7 @@ CU_TestInfo basic_tests[] = {
 	{ "Sync dependency Test",  amdgpu_sync_dependency_test },
 	{ "Dispatch Test",  amdgpu_dispatch_test },
 	{ "Draw Test",  amdgpu_draw_test },
+	{ "GPU reset Test", amdgpu_gpu_reset_test },
 	CU_TEST_INFO_NULL,
 };
 #define BUFFER_SIZE (8 * 1024)
@@ -3131,3 +3136,36 @@ static void amdgpu_draw_test(void)
 		amdgpu_memcpy_draw_test(device_handle, ring_id);
 	}
 }
+
+static void amdgpu_gpu_reset_test(void)
+{
+	int r;
+	char debugfs_path[256], tmp[10];
+	int fd;
+	struct stat sbuf;
+	amdgpu_context_handle context_handle;
+	uint32_t hang_state, hangs;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = fstat(drm_amdgpu[0], &sbuf);
+	CU_ASSERT_EQUAL(r, 0);
+
+	sprintf(debugfs_path, "/sys/kernel/debug/dri/%d/amdgpu_gpu_recover", minor(sbuf.st_rdev));
+	fd = open(debugfs_path, O_RDONLY);
+	CU_ASSERT(fd >= 0);
+
+	r = read(fd, tmp, sizeof(tmp)/sizeof(char));
+	CU_ASSERT(r > 0);
+
+	r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET);
+
+	close(fd);
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	amdgpu_dispatch_test();
+}
-- 
2.7.4

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RE: [PATCH libdrm 2/2] tests/amdgpu: add gpu reset test

[Zhang, Hawking]

Series is:

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Cui, Flora
Sent: 2019年7月18日 16:11
To: amd-gfx@lists.freedesktop.org
Cc: Cui, Flora <Flora.Cui@amd.com>
Subject: [PATCH libdrm 2/2] tests/amdgpu: add gpu reset test

1. perform gpu reset
2. perform dispatch test to verify gpu reset to a good state

Change-Id: I4bba0d1b829288bba7b6885d7e68c8f69ef8f4b5
Signed-off-by: Flora Cui <flora.cui@amd.com>
---
 tests/amdgpu/amdgpu_test.c |  5 +++++
 tests/amdgpu/basic_tests.c | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 73403fb..0c9364a 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -472,6 +472,11 @@ static void amdgpu_disable_suites()
 	if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
 		if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test", CU_FALSE))
 			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
+
+	/* This test was ran on GFX9 only */
+	if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
+		if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", CU_FALSE))
+			fprintf(stderr, "test deactivation failed - %s\n", 
+CU_get_error_msg());
 }
 
 /* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 8fa7088..c04df8b 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -24,6 +24,9 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
 #ifdef HAVE_ALLOCA_H
 # include <alloca.h>
 #endif
@@ -51,6 +54,7 @@ static void amdgpu_sync_dependency_test(void);
 static void amdgpu_bo_eviction_test(void);  static void amdgpu_dispatch_test(void);  static void amdgpu_draw_test(void);
+static void amdgpu_gpu_reset_test(void);
 
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);  static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); @@ -74,6 +78,7 @@ CU_TestInfo basic_tests[] = {
 	{ "Sync dependency Test",  amdgpu_sync_dependency_test },
 	{ "Dispatch Test",  amdgpu_dispatch_test },
 	{ "Draw Test",  amdgpu_draw_test },
+	{ "GPU reset Test", amdgpu_gpu_reset_test },
 	CU_TEST_INFO_NULL,
 };
 #define BUFFER_SIZE (8 * 1024)
@@ -3131,3 +3136,36 @@ static void amdgpu_draw_test(void)
 		amdgpu_memcpy_draw_test(device_handle, ring_id);
 	}
 }
+
+static void amdgpu_gpu_reset_test(void) {
+	int r;
+	char debugfs_path[256], tmp[10];
+	int fd;
+	struct stat sbuf;
+	amdgpu_context_handle context_handle;
+	uint32_t hang_state, hangs;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = fstat(drm_amdgpu[0], &sbuf);
+	CU_ASSERT_EQUAL(r, 0);
+
+	sprintf(debugfs_path, "/sys/kernel/debug/dri/%d/amdgpu_gpu_recover", minor(sbuf.st_rdev));
+	fd = open(debugfs_path, O_RDONLY);
+	CU_ASSERT(fd >= 0);
+
+	r = read(fd, tmp, sizeof(tmp)/sizeof(char));
+	CU_ASSERT(r > 0);
+
+	r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET);
+
+	close(fd);
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	amdgpu_dispatch_test();
+}
--
2.7.4

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Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Christian König]

Am 18.07.19 um 10:10 schrieb Cui, Flora:
> 1. skip test if there's no desired ring
> 2. clear shader buffer
> 3. update command buffer for gfx9
>
> Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36
> Signed-off-by: Flora Cui <flora.cui@amd.com>

Acked-by: Christian König <christian.koenig@amd.com>

> ---
>   tests/amdgpu/basic_tests.c | 36 ++++++++++++++++++++++++++++--------
>   1 file changed, 28 insertions(+), 8 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index 2d47269..8fa7088 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -329,14 +329,15 @@ static const uint32_t preamblecache_gfx9[] = {
>   	0xc0016900, 0x2d5, 0x10000, 0xc0016900,  0x2dc, 0x0,
>   	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
>   	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
> -	0xc0026900, 0x311,  0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
> +	0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20,
>   	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
>   	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
>   	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
>   	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
>   	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
>   	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
> -	0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
> +	0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
> +	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
>   	0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0,
>   	0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0,
>   	0xc0017900, 0x24b, 0x0
> @@ -450,7 +451,7 @@ static const uint32_t cached_cmd_gfx9[] = {
>   	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
>   	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
>   	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
> -	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
> +	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x1a,
>   	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
>   	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
>   	0xc0026900, 0x292, 0x20, 0x60201b8,
> @@ -2094,10 +2095,7 @@ static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t ip_type)
>   	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
>   	ptr[i++] = 0x204;
>   	i += 3;
> -	/* clear mmCOMPUTE_RESOURCE_LIMITS */
> -	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
> -	ptr[i++] = 0x215;
> -	ptr[i++] = 0;
> +
>   	/* clear mmCOMPUTE_TMPRING_SIZE */
>   	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>   	ptr[i++] = 0x218;
> @@ -2184,6 +2182,7 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>   					&bo_shader, &ptr_shader,
>   					&mc_address_shader, &va_shader);
>   	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader, 0, bo_shader_size);
>   
>   	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
>   	CU_ASSERT_EQUAL(r, 0);
> @@ -2220,6 +2219,11 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>   	ptr_cmd[i++] = 0x22222222;
>   	ptr_cmd[i++] = 0x22222222;
>   
> +	/* clear mmCOMPUTE_RESOURCE_LIMITS */
> +	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
> +	ptr_cmd[i++] = 0x215;
> +	ptr_cmd[i++] = 0;
> +
>   	/* dispatch direct command */
>   	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>   	ptr_cmd[i++] = 0x10;
> @@ -2321,6 +2325,7 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>   					&bo_shader, &ptr_shader,
>   					&mc_address_shader, &va_shader);
>   	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader, 0, bo_shader_size);
>   
>   	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
>   	CU_ASSERT_EQUAL(r, 0);
> @@ -2365,6 +2370,11 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>   	ptr_cmd[i++] = 0x400;
>   	ptr_cmd[i++] = 0x74fac;
>   
> +	/* clear mmCOMPUTE_RESOURCE_LIMITS */
> +	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
> +	ptr_cmd[i++] = 0x215;
> +	ptr_cmd[i++] = 0;
> +
>   	/* dispatch direct command */
>   	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>   	ptr_cmd[i++] = 0x10;
> @@ -2438,6 +2448,8 @@ static void amdgpu_dispatch_test(void)
>   
>   	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info);
>   	CU_ASSERT_EQUAL(r, 0);
> +	if (!info.available_rings)
> +		printf("SKIP ... as there's no compute ring\n");
>   
>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>   		amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
> @@ -2446,6 +2458,8 @@ static void amdgpu_dispatch_test(void)
>   
>   	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
>   	CU_ASSERT_EQUAL(r, 0);
> +	if (!info.available_rings)
> +		printf("SKIP ... as there's no graphics ring\n");
>   
>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>   		amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
> @@ -2901,12 +2915,14 @@ static void amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
>   					&bo_shader_ps, &ptr_shader_ps,
>   					&mc_address_shader_ps, &va_shader_ps);
>   	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader_ps, 0, bo_shader_size);
>   
>   	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
>   					AMDGPU_GEM_DOMAIN_VRAM, 0,
>   					&bo_shader_vs, &ptr_shader_vs,
>   					&mc_address_shader_vs, &va_shader_vs);
>   	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader_vs, 0, bo_shader_size);
>   
>   	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
>   	CU_ASSERT_EQUAL(r, 0);
> @@ -2996,7 +3012,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
>   	ptr_cmd[i++] = 0x92;
>   	i += 3;
>   
> -	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 1);
> +	ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
>   	ptr_cmd[i++] = 0x191;
>   	ptr_cmd[i++] = 0;
>   
> @@ -3074,12 +3090,14 @@ static void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t
>   					&bo_shader_ps, &ptr_shader_ps,
>   					&mc_address_shader_ps, &va_shader_ps);
>   	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader_ps, 0, bo_shader_size);
>   
>   	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
>   					AMDGPU_GEM_DOMAIN_VRAM, 0,
>   					&bo_shader_vs, &ptr_shader_vs,
>   					&mc_address_shader_vs, &va_shader_vs);
>   	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader_vs, 0, bo_shader_size);
>   
>   	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX);
>   	CU_ASSERT_EQUAL(r, 0);
> @@ -3105,6 +3123,8 @@ static void amdgpu_draw_test(void)
>   
>   	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
>   	CU_ASSERT_EQUAL(r, 0);
> +	if (!info.available_rings)
> +		printf("SKIP ... as there's no graphics ring\n");
>   
>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>   		amdgpu_memset_draw_test(device_handle, ring_id);

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Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Cui, Flora]

Hi Michel,

These 2 commits is pushed to https://gitlab.freedesktop.org/fcui/drm. 
Could you help to merge to mesa/drm?

BR,

Flora

在 7/18/2019 5:31 PM, Christian König 写道:
> Am 18.07.19 um 10:10 schrieb Cui, Flora:
>> 1. skip test if there's no desired ring
>> 2. clear shader buffer
>> 3. update command buffer for gfx9
>>
>> Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36
>> Signed-off-by: Flora Cui <flora.cui@amd.com>
>
> Acked-by: Christian König <christian.koenig@amd.com>
>
>> ---
>>   tests/amdgpu/basic_tests.c | 36 ++++++++++++++++++++++++++++--------
>>   1 file changed, 28 insertions(+), 8 deletions(-)
>>
>> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
>> index 2d47269..8fa7088 100644
>> --- a/tests/amdgpu/basic_tests.c
>> +++ b/tests/amdgpu/basic_tests.c
>> @@ -329,14 +329,15 @@ static const uint32_t preamblecache_gfx9[] = {
>>       0xc0016900, 0x2d5, 0x10000, 0xc0016900,  0x2dc, 0x0,
>>       0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 
>> 0x2e5, 0x0, 0x0,
>>       0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 
>> 0x3f800000,
>> -    0xc0026900, 0x311,  0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
>> +    0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20,
>>       0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 
>> 0x367, 0x0,
>>       0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 
>> 0x19, 0x0,
>>       0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
>>       0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
>>       0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 
>> 0x0, 0x0,
>>       0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
>> -    0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
>> +    0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
>> +    0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
>>       0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 
>> 0x20000243, 0x0,
>>       0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 
>> 0xc0017900, 0x24a, 0x0,
>>       0xc0017900, 0x24b, 0x0
>> @@ -450,7 +451,7 @@ static const uint32_t cached_cmd_gfx9[] = {
>>       0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
>>       0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
>>       0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
>> -    0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
>> +    0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x1a,
>>       0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
>>       0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
>>       0xc0026900, 0x292, 0x20, 0x60201b8,
>> @@ -2094,10 +2095,7 @@ static int amdgpu_dispatch_init(uint32_t *ptr, 
>> uint32_t ip_type)
>>       ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
>>       ptr[i++] = 0x204;
>>       i += 3;
>> -    /* clear mmCOMPUTE_RESOURCE_LIMITS */
>> -    ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> -    ptr[i++] = 0x215;
>> -    ptr[i++] = 0;
>> +
>>       /* clear mmCOMPUTE_TMPRING_SIZE */
>>       ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>>       ptr[i++] = 0x218;
>> @@ -2184,6 +2182,7 @@ static void 
>> amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>>                       &bo_shader, &ptr_shader,
>>                       &mc_address_shader, &va_shader);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    memset(ptr_shader, 0, bo_shader_size);
>>         r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
>>       CU_ASSERT_EQUAL(r, 0);
>> @@ -2220,6 +2219,11 @@ static void 
>> amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>>       ptr_cmd[i++] = 0x22222222;
>>       ptr_cmd[i++] = 0x22222222;
>>   +    /* clear mmCOMPUTE_RESOURCE_LIMITS */
>> +    ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> +    ptr_cmd[i++] = 0x215;
>> +    ptr_cmd[i++] = 0;
>> +
>>       /* dispatch direct command */
>>       ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>>       ptr_cmd[i++] = 0x10;
>> @@ -2321,6 +2325,7 @@ static void 
>> amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>>                       &bo_shader, &ptr_shader,
>>                       &mc_address_shader, &va_shader);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    memset(ptr_shader, 0, bo_shader_size);
>>         r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
>>       CU_ASSERT_EQUAL(r, 0);
>> @@ -2365,6 +2370,11 @@ static void 
>> amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>>       ptr_cmd[i++] = 0x400;
>>       ptr_cmd[i++] = 0x74fac;
>>   +    /* clear mmCOMPUTE_RESOURCE_LIMITS */
>> +    ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> +    ptr_cmd[i++] = 0x215;
>> +    ptr_cmd[i++] = 0;
>> +
>>       /* dispatch direct command */
>>       ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>>       ptr_cmd[i++] = 0x10;
>> @@ -2438,6 +2448,8 @@ static void amdgpu_dispatch_test(void)
>>         r = amdgpu_query_hw_ip_info(device_handle, 
>> AMDGPU_HW_IP_COMPUTE, 0, &info);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    if (!info.available_rings)
>> +        printf("SKIP ... as there's no compute ring\n");
>>         for (ring_id = 0; (1 << ring_id) & info.available_rings; 
>> ring_id++) {
>>           amdgpu_memset_dispatch_test(device_handle, 
>> AMDGPU_HW_IP_COMPUTE, ring_id);
>> @@ -2446,6 +2458,8 @@ static void amdgpu_dispatch_test(void)
>>         r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 
>> 0, &info);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    if (!info.available_rings)
>> +        printf("SKIP ... as there's no graphics ring\n");
>>         for (ring_id = 0; (1 << ring_id) & info.available_rings; 
>> ring_id++) {
>>           amdgpu_memset_dispatch_test(device_handle, 
>> AMDGPU_HW_IP_GFX, ring_id);
>> @@ -2901,12 +2915,14 @@ static void 
>> amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
>>                       &bo_shader_ps, &ptr_shader_ps,
>>                       &mc_address_shader_ps, &va_shader_ps);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    memset(ptr_shader_ps, 0, bo_shader_size);
>>         r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
>>                       AMDGPU_GEM_DOMAIN_VRAM, 0,
>>                       &bo_shader_vs, &ptr_shader_vs,
>>                       &mc_address_shader_vs, &va_shader_vs);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    memset(ptr_shader_vs, 0, bo_shader_size);
>>         r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
>>       CU_ASSERT_EQUAL(r, 0);
>> @@ -2996,7 +3012,7 @@ static void 
>> amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
>>       ptr_cmd[i++] = 0x92;
>>       i += 3;
>>   -    ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 1);
>> +    ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
>>       ptr_cmd[i++] = 0x191;
>>       ptr_cmd[i++] = 0;
>>   @@ -3074,12 +3090,14 @@ static void 
>> amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t
>>                       &bo_shader_ps, &ptr_shader_ps,
>>                       &mc_address_shader_ps, &va_shader_ps);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    memset(ptr_shader_ps, 0, bo_shader_size);
>>         r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
>>                       AMDGPU_GEM_DOMAIN_VRAM, 0,
>>                       &bo_shader_vs, &ptr_shader_vs,
>>                       &mc_address_shader_vs, &va_shader_vs);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    memset(ptr_shader_vs, 0, bo_shader_size);
>>         r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX);
>>       CU_ASSERT_EQUAL(r, 0);
>> @@ -3105,6 +3123,8 @@ static void amdgpu_draw_test(void)
>>         r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 
>> 0, &info);
>>       CU_ASSERT_EQUAL(r, 0);
>> +    if (!info.available_rings)
>> +        printf("SKIP ... as there's no graphics ring\n");
>>         for (ring_id = 0; (1 << ring_id) & info.available_rings; 
>> ring_id++) {
>>           amdgpu_memset_draw_test(device_handle, ring_id);
>
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Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Michel Dänzer]

On 2019-07-19 8:00 a.m., Cui, Flora wrote:
> Hi Michel,
> 
> These 2 commits is pushed to https://gitlab.freedesktop.org/fcui/drm. 
> Could you help to merge to mesa/drm?

Please remove the Change-Id tags.


P.S. When a commit log lists multiple separate changes, it's a good
indication that the change should be split up.

P.P.S. We'll need to figure out a better way to handle merging libdrm
changes. My personal preference would be to enable GitLab merge requests
for it.

-- 
Earthling Michel Dänzer               |              https://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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RE: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Huang, Ray]

Thanks Flora, can we have these tests, and try on our new APUs as well? 😊

Thanks,
Ray

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Cui,
> Flora
> Sent: Thursday, July 18, 2019 4:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Cui, Flora <Flora.Cui@amd.com>
> Subject: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test
> 
> 1. skip test if there's no desired ring
> 2. clear shader buffer
> 3. update command buffer for gfx9
> 
> Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36
> Signed-off-by: Flora Cui <flora.cui@amd.com>
> ---
>  tests/amdgpu/basic_tests.c | 36 ++++++++++++++++++++++++++++--------
>  1 file changed, 28 insertions(+), 8 deletions(-)
> 
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index
> 2d47269..8fa7088 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -329,14 +329,15 @@ static const uint32_t preamblecache_gfx9[] = {
>  	0xc0016900, 0x2d5, 0x10000, 0xc0016900,  0x2dc, 0x0,
>  	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5,
> 0x0, 0x0,
>  	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000,
> 0x3f800000,
> -	0xc0026900, 0x311,  0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
> +	0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e,
> 0x20,
>  	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900,
> 0x367, 0x0,
>  	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19,
> 0x0,
>  	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
>  	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
>  	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0,
> 0x0,
>  	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
> -	0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
> +	0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210,
> 0,
> +	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
>  	0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900,
> 0x20000243, 0x0,
>  	0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900,
> 0x24a, 0x0,
>  	0xc0017900, 0x24b, 0x0
> @@ -450,7 +451,7 @@ static const uint32_t cached_cmd_gfx9[] = {
>  	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
>  	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
>  	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
> -	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
> +	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x1a,
>  	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
>  	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
>  	0xc0026900, 0x292, 0x20, 0x60201b8,
> @@ -2094,10 +2095,7 @@ static int amdgpu_dispatch_init(uint32_t *ptr,
> uint32_t ip_type)
>  	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
>  	ptr[i++] = 0x204;
>  	i += 3;
> -	/* clear mmCOMPUTE_RESOURCE_LIMITS */
> -	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
> -	ptr[i++] = 0x215;
> -	ptr[i++] = 0;
> +
>  	/* clear mmCOMPUTE_TMPRING_SIZE */
>  	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>  	ptr[i++] = 0x218;
> @@ -2184,6 +2182,7 @@ static void
> amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>  					&bo_shader, &ptr_shader,
>  					&mc_address_shader, &va_shader);
>  	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader, 0, bo_shader_size);
> 
>  	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
>  	CU_ASSERT_EQUAL(r, 0);
> @@ -2220,6 +2219,11 @@ static void
> amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>  	ptr_cmd[i++] = 0x22222222;
>  	ptr_cmd[i++] = 0x22222222;
> 
> +	/* clear mmCOMPUTE_RESOURCE_LIMITS */
> +	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
> +	ptr_cmd[i++] = 0x215;
> +	ptr_cmd[i++] = 0;
> +
>  	/* dispatch direct command */
>  	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>  	ptr_cmd[i++] = 0x10;
> @@ -2321,6 +2325,7 @@ static void
> amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>  					&bo_shader, &ptr_shader,
>  					&mc_address_shader, &va_shader);
>  	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader, 0, bo_shader_size);
> 
>  	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
>  	CU_ASSERT_EQUAL(r, 0);
> @@ -2365,6 +2370,11 @@ static void
> amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>  	ptr_cmd[i++] = 0x400;
>  	ptr_cmd[i++] = 0x74fac;
> 
> +	/* clear mmCOMPUTE_RESOURCE_LIMITS */
> +	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
> +	ptr_cmd[i++] = 0x215;
> +	ptr_cmd[i++] = 0;
> +
>  	/* dispatch direct command */
>  	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>  	ptr_cmd[i++] = 0x10;
> @@ -2438,6 +2448,8 @@ static void amdgpu_dispatch_test(void)
> 
>  	r = amdgpu_query_hw_ip_info(device_handle,
> AMDGPU_HW_IP_COMPUTE, 0, &info);
>  	CU_ASSERT_EQUAL(r, 0);
> +	if (!info.available_rings)
> +		printf("SKIP ... as there's no compute ring\n");
> 
>  	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>  		amdgpu_memset_dispatch_test(device_handle,
> AMDGPU_HW_IP_COMPUTE, ring_id); @@ -2446,6 +2458,8 @@ static void
> amdgpu_dispatch_test(void)
> 
>  	r = amdgpu_query_hw_ip_info(device_handle,
> AMDGPU_HW_IP_GFX, 0, &info);
>  	CU_ASSERT_EQUAL(r, 0);
> +	if (!info.available_rings)
> +		printf("SKIP ... as there's no graphics ring\n");
> 
>  	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>  		amdgpu_memset_dispatch_test(device_handle,
> AMDGPU_HW_IP_GFX, ring_id); @@ -2901,12 +2915,14 @@ static void
> amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
>  					&bo_shader_ps, &ptr_shader_ps,
>  					&mc_address_shader_ps,
> &va_shader_ps);
>  	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader_ps, 0, bo_shader_size);
> 
>  	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size,
> 4096,
>  					AMDGPU_GEM_DOMAIN_VRAM, 0,
>  					&bo_shader_vs, &ptr_shader_vs,
>  					&mc_address_shader_vs,
> &va_shader_vs);
>  	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader_vs, 0, bo_shader_size);
> 
>  	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
>  	CU_ASSERT_EQUAL(r, 0);
> @@ -2996,7 +3012,7 @@ static void
> amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
>  	ptr_cmd[i++] = 0x92;
>  	i += 3;
> 
> -	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 1);
> +	ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
>  	ptr_cmd[i++] = 0x191;
>  	ptr_cmd[i++] = 0;
> 
> @@ -3074,12 +3090,14 @@ static void
> amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle,
> uint32_t
>  					&bo_shader_ps, &ptr_shader_ps,
>  					&mc_address_shader_ps,
> &va_shader_ps);
>  	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader_ps, 0, bo_shader_size);
> 
>  	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size,
> 4096,
>  					AMDGPU_GEM_DOMAIN_VRAM, 0,
>  					&bo_shader_vs, &ptr_shader_vs,
>  					&mc_address_shader_vs,
> &va_shader_vs);
>  	CU_ASSERT_EQUAL(r, 0);
> +	memset(ptr_shader_vs, 0, bo_shader_size);
> 
>  	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX);
>  	CU_ASSERT_EQUAL(r, 0);
> @@ -3105,6 +3123,8 @@ static void amdgpu_draw_test(void)
> 
>  	r = amdgpu_query_hw_ip_info(device_handle,
> AMDGPU_HW_IP_GFX, 0, &info);
>  	CU_ASSERT_EQUAL(r, 0);
> +	if (!info.available_rings)
> +		printf("SKIP ... as there's no graphics ring\n");
> 
>  	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>  		amdgpu_memset_draw_test(device_handle, ring_id);
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Cui, Flora]

the Change-Id tags are added automatically. do you know how to get rid of it?

在 7/19/2019 3:40 PM, Michel Dänzer 写道:
> On 2019-07-19 8:00 a.m., Cui, Flora wrote:
>> Hi Michel,
>>
>> These 2 commits is pushed to https://gitlab.freedesktop.org/fcui/drm.
>> Could you help to merge to mesa/drm?
> Please remove the Change-Id tags.
>
>
> P.S. When a commit log lists multiple separate changes, it's a good
> indication that the change should be split up.
>
> P.P.S. We'll need to figure out a better way to handle merging libdrm
> changes. My personal preference would be to enable GitLab merge requests
> for it.
>
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Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Michel Dänzer]

On 2019-07-19 10:34 a.m., Cui, Flora wrote:
> the Change-Id tags are added automatically. do you know how to get rid of it?

They're only magic to Gerrit, not to Git itself. You can remove them
with any Git commit log editing tool, e.g.

 git commit --amend


-- 
Earthling Michel Dänzer               |              https://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Cui, Flora]

I'm not sure. Could you have a try?

在 7/19/2019 3:48 PM, Huang, Ray 写道:
> Thanks Flora, can we have these tests, and try on our new APUs as well? 😊
>
> Thanks,
> Ray
>
>> -----Original Message-----
>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Cui,
>> Flora
>> Sent: Thursday, July 18, 2019 4:11 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Cui, Flora <Flora.Cui@amd.com>
>> Subject: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test
>>
>> 1. skip test if there's no desired ring
>> 2. clear shader buffer
>> 3. update command buffer for gfx9
>>
>> Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36
>> Signed-off-by: Flora Cui <flora.cui@amd.com>
>> ---
>>   tests/amdgpu/basic_tests.c | 36 ++++++++++++++++++++++++++++--------
>>   1 file changed, 28 insertions(+), 8 deletions(-)
>>
>> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index
>> 2d47269..8fa7088 100644
>> --- a/tests/amdgpu/basic_tests.c
>> +++ b/tests/amdgpu/basic_tests.c
>> @@ -329,14 +329,15 @@ static const uint32_t preamblecache_gfx9[] = {
>>   	0xc0016900, 0x2d5, 0x10000, 0xc0016900,  0x2dc, 0x0,
>>   	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5,
>> 0x0, 0x0,
>>   	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000,
>> 0x3f800000,
>> -	0xc0026900, 0x311,  0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
>> +	0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e,
>> 0x20,
>>   	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900,
>> 0x367, 0x0,
>>   	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19,
>> 0x0,
>>   	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
>>   	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
>>   	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0,
>> 0x0,
>>   	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
>> -	0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
>> +	0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210,
>> 0,
>> +	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
>>   	0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900,
>> 0x20000243, 0x0,
>>   	0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900,
>> 0x24a, 0x0,
>>   	0xc0017900, 0x24b, 0x0
>> @@ -450,7 +451,7 @@ static const uint32_t cached_cmd_gfx9[] = {
>>   	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
>>   	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
>>   	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
>> -	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
>> +	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x1a,
>>   	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
>>   	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
>>   	0xc0026900, 0x292, 0x20, 0x60201b8,
>> @@ -2094,10 +2095,7 @@ static int amdgpu_dispatch_init(uint32_t *ptr,
>> uint32_t ip_type)
>>   	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
>>   	ptr[i++] = 0x204;
>>   	i += 3;
>> -	/* clear mmCOMPUTE_RESOURCE_LIMITS */
>> -	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> -	ptr[i++] = 0x215;
>> -	ptr[i++] = 0;
>> +
>>   	/* clear mmCOMPUTE_TMPRING_SIZE */
>>   	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>>   	ptr[i++] = 0x218;
>> @@ -2184,6 +2182,7 @@ static void
>> amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>>   					&bo_shader, &ptr_shader,
>>   					&mc_address_shader, &va_shader);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader, 0, bo_shader_size);
>>
>>   	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
>>   	CU_ASSERT_EQUAL(r, 0);
>> @@ -2220,6 +2219,11 @@ static void
>> amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>>   	ptr_cmd[i++] = 0x22222222;
>>   	ptr_cmd[i++] = 0x22222222;
>>
>> +	/* clear mmCOMPUTE_RESOURCE_LIMITS */
>> +	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> +	ptr_cmd[i++] = 0x215;
>> +	ptr_cmd[i++] = 0;
>> +
>>   	/* dispatch direct command */
>>   	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>>   	ptr_cmd[i++] = 0x10;
>> @@ -2321,6 +2325,7 @@ static void
>> amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>>   					&bo_shader, &ptr_shader,
>>   					&mc_address_shader, &va_shader);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader, 0, bo_shader_size);
>>
>>   	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
>>   	CU_ASSERT_EQUAL(r, 0);
>> @@ -2365,6 +2370,11 @@ static void
>> amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>>   	ptr_cmd[i++] = 0x400;
>>   	ptr_cmd[i++] = 0x74fac;
>>
>> +	/* clear mmCOMPUTE_RESOURCE_LIMITS */
>> +	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> +	ptr_cmd[i++] = 0x215;
>> +	ptr_cmd[i++] = 0;
>> +
>>   	/* dispatch direct command */
>>   	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>>   	ptr_cmd[i++] = 0x10;
>> @@ -2438,6 +2448,8 @@ static void amdgpu_dispatch_test(void)
>>
>>   	r = amdgpu_query_hw_ip_info(device_handle,
>> AMDGPU_HW_IP_COMPUTE, 0, &info);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	if (!info.available_rings)
>> +		printf("SKIP ... as there's no compute ring\n");
>>
>>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>>   		amdgpu_memset_dispatch_test(device_handle,
>> AMDGPU_HW_IP_COMPUTE, ring_id); @@ -2446,6 +2458,8 @@ static void
>> amdgpu_dispatch_test(void)
>>
>>   	r = amdgpu_query_hw_ip_info(device_handle,
>> AMDGPU_HW_IP_GFX, 0, &info);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	if (!info.available_rings)
>> +		printf("SKIP ... as there's no graphics ring\n");
>>
>>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>>   		amdgpu_memset_dispatch_test(device_handle,
>> AMDGPU_HW_IP_GFX, ring_id); @@ -2901,12 +2915,14 @@ static void
>> amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
>>   					&bo_shader_ps, &ptr_shader_ps,
>>   					&mc_address_shader_ps,
>> &va_shader_ps);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader_ps, 0, bo_shader_size);
>>
>>   	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size,
>> 4096,
>>   					AMDGPU_GEM_DOMAIN_VRAM, 0,
>>   					&bo_shader_vs, &ptr_shader_vs,
>>   					&mc_address_shader_vs,
>> &va_shader_vs);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader_vs, 0, bo_shader_size);
>>
>>   	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
>>   	CU_ASSERT_EQUAL(r, 0);
>> @@ -2996,7 +3012,7 @@ static void
>> amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
>>   	ptr_cmd[i++] = 0x92;
>>   	i += 3;
>>
>> -	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 1);
>> +	ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
>>   	ptr_cmd[i++] = 0x191;
>>   	ptr_cmd[i++] = 0;
>>
>> @@ -3074,12 +3090,14 @@ static void
>> amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle,
>> uint32_t
>>   					&bo_shader_ps, &ptr_shader_ps,
>>   					&mc_address_shader_ps,
>> &va_shader_ps);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader_ps, 0, bo_shader_size);
>>
>>   	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size,
>> 4096,
>>   					AMDGPU_GEM_DOMAIN_VRAM, 0,
>>   					&bo_shader_vs, &ptr_shader_vs,
>>   					&mc_address_shader_vs,
>> &va_shader_vs);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader_vs, 0, bo_shader_size);
>>
>>   	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX);
>>   	CU_ASSERT_EQUAL(r, 0);
>> @@ -3105,6 +3123,8 @@ static void amdgpu_draw_test(void)
>>
>>   	r = amdgpu_query_hw_ip_info(device_handle,
>> AMDGPU_HW_IP_GFX, 0, &info);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	if (!info.available_rings)
>> +		printf("SKIP ... as there's no graphics ring\n");
>>
>>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>>   		amdgpu_memset_draw_test(device_handle, ring_id);
>> --
>> 2.7.4
>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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